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Fix mtcrf/mfcr
[qemu/mini2440.git] / target-ppc / translate.c
blob8e0b2e04ed1d9ac8b768b963e468142f7be248a6
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define DO_SINGLE_STEP
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DISAS(...) do { } while (0)
49 #endif
50 /*****************************************************************************/
51 /* Code translation helpers */
52
53 /* global register indexes */
54 static TCGv_ptr cpu_env;
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 #if !defined(TARGET_PPC64)
57 + 10*4 + 22*5 /* SPE GPRh */
58 #endif
59 + 10*4 + 22*5 /* FPR */
60 + 2*(10*6 + 22*7) /* AVRh, AVRl */
61 + 8*5 /* CRF */];
62 static TCGv cpu_gpr[32];
63 #if !defined(TARGET_PPC64)
64 static TCGv cpu_gprh[32];
65 #endif
66 static TCGv_i64 cpu_fpr[32];
67 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
68 static TCGv_i32 cpu_crf[8];
69 static TCGv cpu_nip;
70 static TCGv cpu_msr;
71 static TCGv cpu_ctr;
72 static TCGv cpu_lr;
73 static TCGv cpu_xer;
74 static TCGv cpu_reserve;
75 static TCGv_i32 cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 static int done_init = 0;
85
86 if (done_init)
87 return;
88
89 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
90
91 p = cpu_reg_names;
92
93 for (i = 0; i < 8; i++) {
94 sprintf(p, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUState, crf[i]), p);
97 p += 5;
98 }
99
100 for (i = 0; i < 32; i++) {
101 sprintf(p, "r%d", i);
102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
103 offsetof(CPUState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 sprintf(p, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 #endif
111
112 sprintf(p, "fp%d", i);
113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUState, fpr[i]), p);
115 p += (i < 10) ? 4 : 5;
116
117 sprintf(p, "avr%dH", i);
118 #ifdef WORDS_BIGENDIAN
119 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
120 offsetof(CPUState, avr[i].u64[0]), p);
121 #else
122 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
123 offsetof(CPUState, avr[i].u64[1]), p);
124 #endif
125 p += (i < 10) ? 6 : 7;
126
127 sprintf(p, "avr%dL", i);
128 #ifdef WORDS_BIGENDIAN
129 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
130 offsetof(CPUState, avr[i].u64[1]), p);
131 #else
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUState, avr[i].u64[0]), p);
134 #endif
135 p += (i < 10) ? 6 : 7;
136 }
137
138 cpu_nip = tcg_global_mem_new(TCG_AREG0,
139 offsetof(CPUState, nip), "nip");
140
141 cpu_msr = tcg_global_mem_new(TCG_AREG0,
142 offsetof(CPUState, msr), "msr");
143
144 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
145 offsetof(CPUState, ctr), "ctr");
146
147 cpu_lr = tcg_global_mem_new(TCG_AREG0,
148 offsetof(CPUState, lr), "lr");
149
150 cpu_xer = tcg_global_mem_new(TCG_AREG0,
151 offsetof(CPUState, xer), "xer");
152
153 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
154 offsetof(CPUState, reserve), "reserve");
155
156 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
157 offsetof(CPUState, fpscr), "fpscr");
158
159 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
160 offsetof(CPUState, access_type), "access_type");
161
162 /* register helpers */
163 #define GEN_HELPER 2
164 #include "helper.h"
165
166 done_init = 1;
167 }
168
169 /* internal defines */
170 typedef struct DisasContext {
171 struct TranslationBlock *tb;
172 target_ulong nip;
173 uint32_t opcode;
174 uint32_t exception;
175 /* Routine used to access memory */
176 int mem_idx;
177 int access_type;
178 /* Translation flags */
179 int le_mode;
180 #if defined(TARGET_PPC64)
181 int sf_mode;
182 #endif
183 int fpu_enabled;
184 int altivec_enabled;
185 int spe_enabled;
186 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
187 int singlestep_enabled;
188 } DisasContext;
189
190 struct opc_handler_t {
191 /* invalid bits */
192 uint32_t inval;
193 /* instruction type */
194 uint64_t type;
195 /* handler */
196 void (*handler)(DisasContext *ctx);
197 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
198 const char *oname;
199 #endif
200 #if defined(DO_PPC_STATISTICS)
201 uint64_t count;
202 #endif
203 };
204
205 static always_inline void gen_reset_fpstatus (void)
206 {
207 #ifdef CONFIG_SOFTFLOAT
208 gen_helper_reset_fpstatus();
209 #endif
210 }
211
212 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
213 {
214 TCGv_i32 t0 = tcg_temp_new_i32();
215
216 if (set_fprf != 0) {
217 /* This case might be optimized later */
218 tcg_gen_movi_i32(t0, 1);
219 gen_helper_compute_fprf(t0, arg, t0);
220 if (unlikely(set_rc)) {
221 tcg_gen_mov_i32(cpu_crf[1], t0);
222 }
223 gen_helper_float_check_status();
224 } else if (unlikely(set_rc)) {
225 /* We always need to compute fpcc */
226 tcg_gen_movi_i32(t0, 0);
227 gen_helper_compute_fprf(t0, arg, t0);
228 tcg_gen_mov_i32(cpu_crf[1], t0);
229 }
230
231 tcg_temp_free_i32(t0);
232 }
233
234 static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
235 {
236 if (ctx->access_type != access_type) {
237 tcg_gen_movi_i32(cpu_access_type, access_type);
238 ctx->access_type = access_type;
239 }
240 }
241
242 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
243 {
244 #if defined(TARGET_PPC64)
245 if (ctx->sf_mode)
246 tcg_gen_movi_tl(cpu_nip, nip);
247 else
248 #endif
249 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
250 }
251
252 static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
253 {
254 TCGv_i32 t0, t1;
255 if (ctx->exception == POWERPC_EXCP_NONE) {
256 gen_update_nip(ctx, ctx->nip);
257 }
258 t0 = tcg_const_i32(excp);
259 t1 = tcg_const_i32(error);
260 gen_helper_raise_exception_err(t0, t1);
261 tcg_temp_free_i32(t0);
262 tcg_temp_free_i32(t1);
263 ctx->exception = (excp);
264 }
265
266 static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
267 {
268 TCGv_i32 t0;
269 if (ctx->exception == POWERPC_EXCP_NONE) {
270 gen_update_nip(ctx, ctx->nip);
271 }
272 t0 = tcg_const_i32(excp);
273 gen_helper_raise_exception(t0);
274 tcg_temp_free_i32(t0);
275 ctx->exception = (excp);
276 }
277
278 static always_inline void gen_debug_exception (DisasContext *ctx)
279 {
280 TCGv_i32 t0;
281
282 if (ctx->exception != POWERPC_EXCP_BRANCH)
283 gen_update_nip(ctx, ctx->nip);
284 t0 = tcg_const_i32(EXCP_DEBUG);
285 gen_helper_raise_exception(t0);
286 tcg_temp_free_i32(t0);
287 }
288
289 static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
290 {
291 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
292 }
293
294 /* Stop translation */
295 static always_inline void gen_stop_exception (DisasContext *ctx)
296 {
297 gen_update_nip(ctx, ctx->nip);
298 ctx->exception = POWERPC_EXCP_STOP;
299 }
300
301 /* No need to update nip here, as execution flow will change */
302 static always_inline void gen_sync_exception (DisasContext *ctx)
303 {
304 ctx->exception = POWERPC_EXCP_SYNC;
305 }
306
307 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
308 static void gen_##name (DisasContext *ctx); \
309 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
310 static void gen_##name (DisasContext *ctx)
311
312 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
313 static void gen_##name (DisasContext *ctx); \
314 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
315 static void gen_##name (DisasContext *ctx)
316
317 typedef struct opcode_t {
318 unsigned char opc1, opc2, opc3;
319 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
320 unsigned char pad[5];
321 #else
322 unsigned char pad[1];
323 #endif
324 opc_handler_t handler;
325 const char *oname;
326 } opcode_t;
327
328 /*****************************************************************************/
329 /*** Instruction decoding ***/
330 #define EXTRACT_HELPER(name, shift, nb) \
331 static always_inline uint32_t name (uint32_t opcode) \
332 { \
333 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
334 }
335
336 #define EXTRACT_SHELPER(name, shift, nb) \
337 static always_inline int32_t name (uint32_t opcode) \
338 { \
339 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
340 }
341
342 /* Opcode part 1 */
343 EXTRACT_HELPER(opc1, 26, 6);
344 /* Opcode part 2 */
345 EXTRACT_HELPER(opc2, 1, 5);
346 /* Opcode part 3 */
347 EXTRACT_HELPER(opc3, 6, 5);
348 /* Update Cr0 flags */
349 EXTRACT_HELPER(Rc, 0, 1);
350 /* Destination */
351 EXTRACT_HELPER(rD, 21, 5);
352 /* Source */
353 EXTRACT_HELPER(rS, 21, 5);
354 /* First operand */
355 EXTRACT_HELPER(rA, 16, 5);
356 /* Second operand */
357 EXTRACT_HELPER(rB, 11, 5);
358 /* Third operand */
359 EXTRACT_HELPER(rC, 6, 5);
360 /*** Get CRn ***/
361 EXTRACT_HELPER(crfD, 23, 3);
362 EXTRACT_HELPER(crfS, 18, 3);
363 EXTRACT_HELPER(crbD, 21, 5);
364 EXTRACT_HELPER(crbA, 16, 5);
365 EXTRACT_HELPER(crbB, 11, 5);
366 /* SPR / TBL */
367 EXTRACT_HELPER(_SPR, 11, 10);
368 static always_inline uint32_t SPR (uint32_t opcode)
369 {
370 uint32_t sprn = _SPR(opcode);
371
372 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
373 }
374 /*** Get constants ***/
375 EXTRACT_HELPER(IMM, 12, 8);
376 /* 16 bits signed immediate value */
377 EXTRACT_SHELPER(SIMM, 0, 16);
378 /* 16 bits unsigned immediate value */
379 EXTRACT_HELPER(UIMM, 0, 16);
380 /* 5 bits signed immediate value */
381 EXTRACT_HELPER(SIMM5, 16, 5);
382 /* 5 bits signed immediate value */
383 EXTRACT_HELPER(UIMM5, 16, 5);
384 /* Bit count */
385 EXTRACT_HELPER(NB, 11, 5);
386 /* Shift count */
387 EXTRACT_HELPER(SH, 11, 5);
388 /* Vector shift count */
389 EXTRACT_HELPER(VSH, 6, 4);
390 /* Mask start */
391 EXTRACT_HELPER(MB, 6, 5);
392 /* Mask end */
393 EXTRACT_HELPER(ME, 1, 5);
394 /* Trap operand */
395 EXTRACT_HELPER(TO, 21, 5);
396
397 EXTRACT_HELPER(CRM, 12, 8);
398 EXTRACT_HELPER(FM, 17, 8);
399 EXTRACT_HELPER(SR, 16, 4);
400 EXTRACT_HELPER(FPIMM, 12, 4);
401
402 /*** Jump target decoding ***/
403 /* Displacement */
404 EXTRACT_SHELPER(d, 0, 16);
405 /* Immediate address */
406 static always_inline target_ulong LI (uint32_t opcode)
407 {
408 return (opcode >> 0) & 0x03FFFFFC;
409 }
410
411 static always_inline uint32_t BD (uint32_t opcode)
412 {
413 return (opcode >> 0) & 0xFFFC;
414 }
415
416 EXTRACT_HELPER(BO, 21, 5);
417 EXTRACT_HELPER(BI, 16, 5);
418 /* Absolute/relative address */
419 EXTRACT_HELPER(AA, 1, 1);
420 /* Link */
421 EXTRACT_HELPER(LK, 0, 1);
422
423 /* Create a mask between <start> and <end> bits */
424 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
425 {
426 target_ulong ret;
427
428 #if defined(TARGET_PPC64)
429 if (likely(start == 0)) {
430 ret = UINT64_MAX << (63 - end);
431 } else if (likely(end == 63)) {
432 ret = UINT64_MAX >> start;
433 }
434 #else
435 if (likely(start == 0)) {
436 ret = UINT32_MAX << (31 - end);
437 } else if (likely(end == 31)) {
438 ret = UINT32_MAX >> start;
439 }
440 #endif
441 else {
442 ret = (((target_ulong)(-1ULL)) >> (start)) ^
443 (((target_ulong)(-1ULL) >> (end)) >> 1);
444 if (unlikely(start > end))
445 return ~ret;
446 }
447
448 return ret;
449 }
450
451 /*****************************************************************************/
452 /* PowerPC Instructions types definitions */
453 enum {
454 PPC_NONE = 0x0000000000000000ULL,
455 /* PowerPC base instructions set */
456 PPC_INSNS_BASE = 0x0000000000000001ULL,
457 /* integer operations instructions */
458 #define PPC_INTEGER PPC_INSNS_BASE
459 /* flow control instructions */
460 #define PPC_FLOW PPC_INSNS_BASE
461 /* virtual memory instructions */
462 #define PPC_MEM PPC_INSNS_BASE
463 /* ld/st with reservation instructions */
464 #define PPC_RES PPC_INSNS_BASE
465 /* spr/msr access instructions */
466 #define PPC_MISC PPC_INSNS_BASE
467 /* Deprecated instruction sets */
468 /* Original POWER instruction set */
469 PPC_POWER = 0x0000000000000002ULL,
470 /* POWER2 instruction set extension */
471 PPC_POWER2 = 0x0000000000000004ULL,
472 /* Power RTC support */
473 PPC_POWER_RTC = 0x0000000000000008ULL,
474 /* Power-to-PowerPC bridge (601) */
475 PPC_POWER_BR = 0x0000000000000010ULL,
476 /* 64 bits PowerPC instruction set */
477 PPC_64B = 0x0000000000000020ULL,
478 /* New 64 bits extensions (PowerPC 2.0x) */
479 PPC_64BX = 0x0000000000000040ULL,
480 /* 64 bits hypervisor extensions */
481 PPC_64H = 0x0000000000000080ULL,
482 /* New wait instruction (PowerPC 2.0x) */
483 PPC_WAIT = 0x0000000000000100ULL,
484 /* Time base mftb instruction */
485 PPC_MFTB = 0x0000000000000200ULL,
486
487 /* Fixed-point unit extensions */
488 /* PowerPC 602 specific */
489 PPC_602_SPEC = 0x0000000000000400ULL,
490 /* isel instruction */
491 PPC_ISEL = 0x0000000000000800ULL,
492 /* popcntb instruction */
493 PPC_POPCNTB = 0x0000000000001000ULL,
494 /* string load / store */
495 PPC_STRING = 0x0000000000002000ULL,
496
497 /* Floating-point unit extensions */
498 /* Optional floating point instructions */
499 PPC_FLOAT = 0x0000000000010000ULL,
500 /* New floating-point extensions (PowerPC 2.0x) */
501 PPC_FLOAT_EXT = 0x0000000000020000ULL,
502 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
503 PPC_FLOAT_FRES = 0x0000000000080000ULL,
504 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
505 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
506 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
507 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
508
509 /* Vector/SIMD extensions */
510 /* Altivec support */
511 PPC_ALTIVEC = 0x0000000001000000ULL,
512 /* PowerPC 2.03 SPE extension */
513 PPC_SPE = 0x0000000002000000ULL,
514 /* PowerPC 2.03 SPE single-precision floating-point extension */
515 PPC_SPE_SINGLE = 0x0000000004000000ULL,
516 /* PowerPC 2.03 SPE double-precision floating-point extension */
517 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
518
519 /* Optional memory control instructions */
520 PPC_MEM_TLBIA = 0x0000000010000000ULL,
521 PPC_MEM_TLBIE = 0x0000000020000000ULL,
522 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
523 /* sync instruction */
524 PPC_MEM_SYNC = 0x0000000080000000ULL,
525 /* eieio instruction */
526 PPC_MEM_EIEIO = 0x0000000100000000ULL,
527
528 /* Cache control instructions */
529 PPC_CACHE = 0x0000000200000000ULL,
530 /* icbi instruction */
531 PPC_CACHE_ICBI = 0x0000000400000000ULL,
532 /* dcbz instruction with fixed cache line size */
533 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
534 /* dcbz instruction with tunable cache line size */
535 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
536 /* dcba instruction */
537 PPC_CACHE_DCBA = 0x0000002000000000ULL,
538 /* Freescale cache locking instructions */
539 PPC_CACHE_LOCK = 0x0000004000000000ULL,
540
541 /* MMU related extensions */
542 /* external control instructions */
543 PPC_EXTERN = 0x0000010000000000ULL,
544 /* segment register access instructions */
545 PPC_SEGMENT = 0x0000020000000000ULL,
546 /* PowerPC 6xx TLB management instructions */
547 PPC_6xx_TLB = 0x0000040000000000ULL,
548 /* PowerPC 74xx TLB management instructions */
549 PPC_74xx_TLB = 0x0000080000000000ULL,
550 /* PowerPC 40x TLB management instructions */
551 PPC_40x_TLB = 0x0000100000000000ULL,
552 /* segment register access instructions for PowerPC 64 "bridge" */
553 PPC_SEGMENT_64B = 0x0000200000000000ULL,
554 /* SLB management */
555 PPC_SLBI = 0x0000400000000000ULL,
556
557 /* Embedded PowerPC dedicated instructions */
558 PPC_WRTEE = 0x0001000000000000ULL,
559 /* PowerPC 40x exception model */
560 PPC_40x_EXCP = 0x0002000000000000ULL,
561 /* PowerPC 405 Mac instructions */
562 PPC_405_MAC = 0x0004000000000000ULL,
563 /* PowerPC 440 specific instructions */
564 PPC_440_SPEC = 0x0008000000000000ULL,
565 /* BookE (embedded) PowerPC specification */
566 PPC_BOOKE = 0x0010000000000000ULL,
567 /* mfapidi instruction */
568 PPC_MFAPIDI = 0x0020000000000000ULL,
569 /* tlbiva instruction */
570 PPC_TLBIVA = 0x0040000000000000ULL,
571 /* tlbivax instruction */
572 PPC_TLBIVAX = 0x0080000000000000ULL,
573 /* PowerPC 4xx dedicated instructions */
574 PPC_4xx_COMMON = 0x0100000000000000ULL,
575 /* PowerPC 40x ibct instructions */
576 PPC_40x_ICBT = 0x0200000000000000ULL,
577 /* rfmci is not implemented in all BookE PowerPC */
578 PPC_RFMCI = 0x0400000000000000ULL,
579 /* rfdi instruction */
580 PPC_RFDI = 0x0800000000000000ULL,
581 /* DCR accesses */
582 PPC_DCR = 0x1000000000000000ULL,
583 /* DCR extended accesse */
584 PPC_DCRX = 0x2000000000000000ULL,
585 /* user-mode DCR access, implemented in PowerPC 460 */
586 PPC_DCRUX = 0x4000000000000000ULL,
587 };
588
589 /*****************************************************************************/
590 /* PowerPC instructions table */
591 #if HOST_LONG_BITS == 64
592 #define OPC_ALIGN 8
593 #else
594 #define OPC_ALIGN 4
595 #endif
596 #if defined(__APPLE__)
597 #define OPCODES_SECTION \
598 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
599 #else
600 #define OPCODES_SECTION \
601 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
602 #endif
603
604 #if defined(DO_PPC_STATISTICS)
605 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
606 OPCODES_SECTION opcode_t opc_##name = { \
607 .opc1 = op1, \
608 .opc2 = op2, \
609 .opc3 = op3, \
610 .pad = { 0, }, \
611 .handler = { \
612 .inval = invl, \
613 .type = _typ, \
614 .handler = &gen_##name, \
615 .oname = stringify(name), \
616 }, \
617 .oname = stringify(name), \
618 }
619 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
620 OPCODES_SECTION opcode_t opc_##name = { \
621 .opc1 = op1, \
622 .opc2 = op2, \
623 .opc3 = op3, \
624 .pad = { 0, }, \
625 .handler = { \
626 .inval = invl, \
627 .type = _typ, \
628 .handler = &gen_##name, \
629 .oname = onam, \
630 }, \
631 .oname = onam, \
632 }
633 #else
634 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
635 OPCODES_SECTION opcode_t opc_##name = { \
636 .opc1 = op1, \
637 .opc2 = op2, \
638 .opc3 = op3, \
639 .pad = { 0, }, \
640 .handler = { \
641 .inval = invl, \
642 .type = _typ, \
643 .handler = &gen_##name, \
644 }, \
645 .oname = stringify(name), \
646 }
647 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
648 OPCODES_SECTION opcode_t opc_##name = { \
649 .opc1 = op1, \
650 .opc2 = op2, \
651 .opc3 = op3, \
652 .pad = { 0, }, \
653 .handler = { \
654 .inval = invl, \
655 .type = _typ, \
656 .handler = &gen_##name, \
657 }, \
658 .oname = onam, \
659 }
660 #endif
661
662 #define GEN_OPCODE_MARK(name) \
663 OPCODES_SECTION opcode_t opc_##name = { \
664 .opc1 = 0xFF, \
665 .opc2 = 0xFF, \
666 .opc3 = 0xFF, \
667 .pad = { 0, }, \
668 .handler = { \
669 .inval = 0x00000000, \
670 .type = 0x00, \
671 .handler = NULL, \
672 }, \
673 .oname = stringify(name), \
674 }
675
676 /* SPR load/store helpers */
677 static always_inline void gen_load_spr(TCGv t, int reg)
678 {
679 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
680 }
681
682 static always_inline void gen_store_spr(int reg, TCGv t)
683 {
684 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
685 }
686
687 /* Start opcode list */
688 GEN_OPCODE_MARK(start);
689
690 /* Invalid instruction */
691 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
692 {
693 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
694 }
695
696 static opc_handler_t invalid_handler = {
697 .inval = 0xFFFFFFFF,
698 .type = PPC_NONE,
699 .handler = gen_invalid,
700 };
701
702 /*** Integer comparison ***/
703
704 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
705 {
706 int l1, l2, l3;
707
708 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
709 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
710 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
711
712 l1 = gen_new_label();
713 l2 = gen_new_label();
714 l3 = gen_new_label();
715 if (s) {
716 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
717 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
718 } else {
719 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
720 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
721 }
722 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
723 tcg_gen_br(l3);
724 gen_set_label(l1);
725 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
726 tcg_gen_br(l3);
727 gen_set_label(l2);
728 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
729 gen_set_label(l3);
730 }
731
732 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
733 {
734 TCGv t0 = tcg_const_local_tl(arg1);
735 gen_op_cmp(arg0, t0, s, crf);
736 tcg_temp_free(t0);
737 }
738
739 #if defined(TARGET_PPC64)
740 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
741 {
742 TCGv t0, t1;
743 t0 = tcg_temp_local_new();
744 t1 = tcg_temp_local_new();
745 if (s) {
746 tcg_gen_ext32s_tl(t0, arg0);
747 tcg_gen_ext32s_tl(t1, arg1);
748 } else {
749 tcg_gen_ext32u_tl(t0, arg0);
750 tcg_gen_ext32u_tl(t1, arg1);
751 }
752 gen_op_cmp(t0, t1, s, crf);
753 tcg_temp_free(t1);
754 tcg_temp_free(t0);
755 }
756
757 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
758 {
759 TCGv t0 = tcg_const_local_tl(arg1);
760 gen_op_cmp32(arg0, t0, s, crf);
761 tcg_temp_free(t0);
762 }
763 #endif
764
765 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
766 {
767 #if defined(TARGET_PPC64)
768 if (!(ctx->sf_mode))
769 gen_op_cmpi32(reg, 0, 1, 0);
770 else
771 #endif
772 gen_op_cmpi(reg, 0, 1, 0);
773 }
774
775 /* cmp */
776 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
777 {
778 #if defined(TARGET_PPC64)
779 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
780 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
781 1, crfD(ctx->opcode));
782 else
783 #endif
784 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
785 1, crfD(ctx->opcode));
786 }
787
788 /* cmpi */
789 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
790 {
791 #if defined(TARGET_PPC64)
792 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
793 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
794 1, crfD(ctx->opcode));
795 else
796 #endif
797 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
798 1, crfD(ctx->opcode));
799 }
800
801 /* cmpl */
802 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
803 {
804 #if defined(TARGET_PPC64)
805 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
806 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
807 0, crfD(ctx->opcode));
808 else
809 #endif
810 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
811 0, crfD(ctx->opcode));
812 }
813
814 /* cmpli */
815 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
816 {
817 #if defined(TARGET_PPC64)
818 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
819 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
820 0, crfD(ctx->opcode));
821 else
822 #endif
823 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
824 0, crfD(ctx->opcode));
825 }
826
827 /* isel (PowerPC 2.03 specification) */
828 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
829 {
830 int l1, l2;
831 uint32_t bi = rC(ctx->opcode);
832 uint32_t mask;
833 TCGv_i32 t0;
834
835 l1 = gen_new_label();
836 l2 = gen_new_label();
837
838 mask = 1 << (3 - (bi & 0x03));
839 t0 = tcg_temp_new_i32();
840 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
841 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
842 if (rA(ctx->opcode) == 0)
843 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
844 else
845 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
846 tcg_gen_br(l2);
847 gen_set_label(l1);
848 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
849 gen_set_label(l2);
850 tcg_temp_free_i32(t0);
851 }
852
853 /*** Integer arithmetic ***/
854
855 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
856 {
857 int l1;
858 TCGv t0;
859
860 l1 = gen_new_label();
861 /* Start with XER OV disabled, the most likely case */
862 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
863 t0 = tcg_temp_local_new();
864 tcg_gen_xor_tl(t0, arg0, arg1);
865 #if defined(TARGET_PPC64)
866 if (!ctx->sf_mode)
867 tcg_gen_ext32s_tl(t0, t0);
868 #endif
869 if (sub)
870 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
871 else
872 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
873 tcg_gen_xor_tl(t0, arg1, arg2);
874 #if defined(TARGET_PPC64)
875 if (!ctx->sf_mode)
876 tcg_gen_ext32s_tl(t0, t0);
877 #endif
878 if (sub)
879 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
880 else
881 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
882 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
883 gen_set_label(l1);
884 tcg_temp_free(t0);
885 }
886
887 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
888 {
889 int l1 = gen_new_label();
890
891 #if defined(TARGET_PPC64)
892 if (!(ctx->sf_mode)) {
893 TCGv t0, t1;
894 t0 = tcg_temp_new();
895 t1 = tcg_temp_new();
896
897 tcg_gen_ext32u_tl(t0, arg1);
898 tcg_gen_ext32u_tl(t1, arg2);
899 if (sub) {
900 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
901 } else {
902 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
903 }
904 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
905 gen_set_label(l1);
906 tcg_temp_free(t0);
907 tcg_temp_free(t1);
908 } else
909 #endif
910 {
911 if (sub) {
912 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
913 } else {
914 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
915 }
916 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
917 gen_set_label(l1);
918 }
919 }
920
921 /* Common add function */
922 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
923 int add_ca, int compute_ca, int compute_ov)
924 {
925 TCGv t0, t1;
926
927 if ((!compute_ca && !compute_ov) ||
928 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
929 t0 = ret;
930 } else {
931 t0 = tcg_temp_local_new();
932 }
933
934 if (add_ca) {
935 t1 = tcg_temp_local_new();
936 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
937 tcg_gen_shri_tl(t1, t1, XER_CA);
938 }
939
940 if (compute_ca && compute_ov) {
941 /* Start with XER CA and OV disabled, the most likely case */
942 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
943 } else if (compute_ca) {
944 /* Start with XER CA disabled, the most likely case */
945 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
946 } else if (compute_ov) {
947 /* Start with XER OV disabled, the most likely case */
948 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
949 }
950
951 tcg_gen_add_tl(t0, arg1, arg2);
952
953 if (compute_ca) {
954 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
955 }
956 if (add_ca) {
957 tcg_gen_add_tl(t0, t0, t1);
958 gen_op_arith_compute_ca(ctx, t0, t1, 0);
959 tcg_temp_free(t1);
960 }
961 if (compute_ov) {
962 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
963 }
964
965 if (unlikely(Rc(ctx->opcode) != 0))
966 gen_set_Rc0(ctx, t0);
967
968 if (!TCGV_EQUAL(t0, ret)) {
969 tcg_gen_mov_tl(ret, t0);
970 tcg_temp_free(t0);
971 }
972 }
973 /* Add functions with two operands */
974 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
975 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
976 { \
977 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
978 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
979 add_ca, compute_ca, compute_ov); \
980 }
981 /* Add functions with one operand and one immediate */
982 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
983 add_ca, compute_ca, compute_ov) \
984 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
985 { \
986 TCGv t0 = tcg_const_local_tl(const_val); \
987 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
988 cpu_gpr[rA(ctx->opcode)], t0, \
989 add_ca, compute_ca, compute_ov); \
990 tcg_temp_free(t0); \
991 }
992
993 /* add add. addo addo. */
994 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
995 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
996 /* addc addc. addco addco. */
997 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
998 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
999 /* adde adde. addeo addeo. */
1000 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1001 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1002 /* addme addme. addmeo addmeo. */
1003 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1004 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1005 /* addze addze. addzeo addzeo.*/
1006 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1007 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1008 /* addi */
1009 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1010 {
1011 target_long simm = SIMM(ctx->opcode);
1012
1013 if (rA(ctx->opcode) == 0) {
1014 /* li case */
1015 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1016 } else {
1017 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1018 }
1019 }
1020 /* addic addic.*/
1021 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1022 int compute_Rc0)
1023 {
1024 target_long simm = SIMM(ctx->opcode);
1025
1026 /* Start with XER CA and OV disabled, the most likely case */
1027 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1028
1029 if (likely(simm != 0)) {
1030 TCGv t0 = tcg_temp_local_new();
1031 tcg_gen_addi_tl(t0, arg1, simm);
1032 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1033 tcg_gen_mov_tl(ret, t0);
1034 tcg_temp_free(t0);
1035 } else {
1036 tcg_gen_mov_tl(ret, arg1);
1037 }
1038 if (compute_Rc0) {
1039 gen_set_Rc0(ctx, ret);
1040 }
1041 }
1042 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1043 {
1044 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1045 }
1046 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1047 {
1048 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1049 }
1050 /* addis */
1051 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1052 {
1053 target_long simm = SIMM(ctx->opcode);
1054
1055 if (rA(ctx->opcode) == 0) {
1056 /* lis case */
1057 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1058 } else {
1059 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1060 }
1061 }
1062
1063 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1064 int sign, int compute_ov)
1065 {
1066 int l1 = gen_new_label();
1067 int l2 = gen_new_label();
1068 TCGv_i32 t0 = tcg_temp_local_new_i32();
1069 TCGv_i32 t1 = tcg_temp_local_new_i32();
1070
1071 tcg_gen_trunc_tl_i32(t0, arg1);
1072 tcg_gen_trunc_tl_i32(t1, arg2);
1073 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1074 if (sign) {
1075 int l3 = gen_new_label();
1076 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1077 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1078 gen_set_label(l3);
1079 tcg_gen_div_i32(t0, t0, t1);
1080 } else {
1081 tcg_gen_divu_i32(t0, t0, t1);
1082 }
1083 if (compute_ov) {
1084 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1085 }
1086 tcg_gen_br(l2);
1087 gen_set_label(l1);
1088 if (sign) {
1089 tcg_gen_sari_i32(t0, t0, 31);
1090 } else {
1091 tcg_gen_movi_i32(t0, 0);
1092 }
1093 if (compute_ov) {
1094 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1095 }
1096 gen_set_label(l2);
1097 tcg_gen_extu_i32_tl(ret, t0);
1098 tcg_temp_free_i32(t0);
1099 tcg_temp_free_i32(t1);
1100 if (unlikely(Rc(ctx->opcode) != 0))
1101 gen_set_Rc0(ctx, ret);
1102 }
1103 /* Div functions */
1104 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1105 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1106 { \
1107 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1108 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1109 sign, compute_ov); \
1110 }
1111 /* divwu divwu. divwuo divwuo. */
1112 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1113 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1114 /* divw divw. divwo divwo. */
1115 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1116 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1117 #if defined(TARGET_PPC64)
1118 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1119 int sign, int compute_ov)
1120 {
1121 int l1 = gen_new_label();
1122 int l2 = gen_new_label();
1123
1124 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1125 if (sign) {
1126 int l3 = gen_new_label();
1127 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1128 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1129 gen_set_label(l3);
1130 tcg_gen_div_i64(ret, arg1, arg2);
1131 } else {
1132 tcg_gen_divu_i64(ret, arg1, arg2);
1133 }
1134 if (compute_ov) {
1135 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1136 }
1137 tcg_gen_br(l2);
1138 gen_set_label(l1);
1139 if (sign) {
1140 tcg_gen_sari_i64(ret, arg1, 63);
1141 } else {
1142 tcg_gen_movi_i64(ret, 0);
1143 }
1144 if (compute_ov) {
1145 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1146 }
1147 gen_set_label(l2);
1148 if (unlikely(Rc(ctx->opcode) != 0))
1149 gen_set_Rc0(ctx, ret);
1150 }
1151 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1152 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1153 { \
1154 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1155 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1156 sign, compute_ov); \
1157 }
1158 /* divwu divwu. divwuo divwuo. */
1159 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1160 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1161 /* divw divw. divwo divwo. */
1162 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1163 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1164 #endif
1165
1166 /* mulhw mulhw. */
1167 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1168 {
1169 TCGv_i64 t0, t1;
1170
1171 t0 = tcg_temp_new_i64();
1172 t1 = tcg_temp_new_i64();
1173 #if defined(TARGET_PPC64)
1174 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1175 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1176 tcg_gen_mul_i64(t0, t0, t1);
1177 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1178 #else
1179 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1180 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1181 tcg_gen_mul_i64(t0, t0, t1);
1182 tcg_gen_shri_i64(t0, t0, 32);
1183 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1184 #endif
1185 tcg_temp_free_i64(t0);
1186 tcg_temp_free_i64(t1);
1187 if (unlikely(Rc(ctx->opcode) != 0))
1188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1189 }
1190 /* mulhwu mulhwu. */
1191 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1192 {
1193 TCGv_i64 t0, t1;
1194
1195 t0 = tcg_temp_new_i64();
1196 t1 = tcg_temp_new_i64();
1197 #if defined(TARGET_PPC64)
1198 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1199 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1200 tcg_gen_mul_i64(t0, t0, t1);
1201 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1202 #else
1203 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1204 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1205 tcg_gen_mul_i64(t0, t0, t1);
1206 tcg_gen_shri_i64(t0, t0, 32);
1207 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1208 #endif
1209 tcg_temp_free_i64(t0);
1210 tcg_temp_free_i64(t1);
1211 if (unlikely(Rc(ctx->opcode) != 0))
1212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1213 }
1214 /* mullw mullw. */
1215 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1216 {
1217 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1218 cpu_gpr[rB(ctx->opcode)]);
1219 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1220 if (unlikely(Rc(ctx->opcode) != 0))
1221 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1222 }
1223 /* mullwo mullwo. */
1224 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1225 {
1226 int l1;
1227 TCGv_i64 t0, t1;
1228
1229 t0 = tcg_temp_new_i64();
1230 t1 = tcg_temp_new_i64();
1231 l1 = gen_new_label();
1232 /* Start with XER OV disabled, the most likely case */
1233 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1234 #if defined(TARGET_PPC64)
1235 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1236 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1237 #else
1238 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1239 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1240 #endif
1241 tcg_gen_mul_i64(t0, t0, t1);
1242 #if defined(TARGET_PPC64)
1243 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1244 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1245 #else
1246 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1247 tcg_gen_ext32s_i64(t1, t0);
1248 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1249 #endif
1250 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1251 gen_set_label(l1);
1252 tcg_temp_free_i64(t0);
1253 tcg_temp_free_i64(t1);
1254 if (unlikely(Rc(ctx->opcode) != 0))
1255 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1256 }
1257 /* mulli */
1258 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1259 {
1260 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1261 SIMM(ctx->opcode));
1262 }
1263 #if defined(TARGET_PPC64)
1264 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1265 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1266 { \
1267 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1268 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1269 if (unlikely(Rc(ctx->opcode) != 0)) \
1270 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1271 }
1272 /* mulhd mulhd. */
1273 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1274 /* mulhdu mulhdu. */
1275 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1276 /* mulld mulld. */
1277 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1278 {
1279 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1280 cpu_gpr[rB(ctx->opcode)]);
1281 if (unlikely(Rc(ctx->opcode) != 0))
1282 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1283 }
1284 /* mulldo mulldo. */
1285 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1286 #endif
1287
1288 /* neg neg. nego nego. */
1289 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1290 {
1291 int l1 = gen_new_label();
1292 int l2 = gen_new_label();
1293 TCGv t0 = tcg_temp_local_new();
1294 #if defined(TARGET_PPC64)
1295 if (ctx->sf_mode) {
1296 tcg_gen_mov_tl(t0, arg1);
1297 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1298 } else
1299 #endif
1300 {
1301 tcg_gen_ext32s_tl(t0, arg1);
1302 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1303 }
1304 tcg_gen_neg_tl(ret, arg1);
1305 if (ov_check) {
1306 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1307 }
1308 tcg_gen_br(l2);
1309 gen_set_label(l1);
1310 tcg_gen_mov_tl(ret, t0);
1311 if (ov_check) {
1312 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1313 }
1314 gen_set_label(l2);
1315 tcg_temp_free(t0);
1316 if (unlikely(Rc(ctx->opcode) != 0))
1317 gen_set_Rc0(ctx, ret);
1318 }
1319 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1320 {
1321 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1322 }
1323 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1324 {
1325 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1326 }
1327
1328 /* Common subf function */
1329 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1330 int add_ca, int compute_ca, int compute_ov)
1331 {
1332 TCGv t0, t1;
1333
1334 if ((!compute_ca && !compute_ov) ||
1335 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1336 t0 = ret;
1337 } else {
1338 t0 = tcg_temp_local_new();
1339 }
1340
1341 if (add_ca) {
1342 t1 = tcg_temp_local_new();
1343 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1344 tcg_gen_shri_tl(t1, t1, XER_CA);
1345 }
1346
1347 if (compute_ca && compute_ov) {
1348 /* Start with XER CA and OV disabled, the most likely case */
1349 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1350 } else if (compute_ca) {
1351 /* Start with XER CA disabled, the most likely case */
1352 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1353 } else if (compute_ov) {
1354 /* Start with XER OV disabled, the most likely case */
1355 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1356 }
1357
1358 if (add_ca) {
1359 tcg_gen_not_tl(t0, arg1);
1360 tcg_gen_add_tl(t0, t0, arg2);
1361 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1362 tcg_gen_add_tl(t0, t0, t1);
1363 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1364 tcg_temp_free(t1);
1365 } else {
1366 tcg_gen_sub_tl(t0, arg2, arg1);
1367 if (compute_ca) {
1368 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1369 }
1370 }
1371 if (compute_ov) {
1372 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1373 }
1374
1375 if (unlikely(Rc(ctx->opcode) != 0))
1376 gen_set_Rc0(ctx, t0);
1377
1378 if (!TCGV_EQUAL(t0, ret)) {
1379 tcg_gen_mov_tl(ret, t0);
1380 tcg_temp_free(t0);
1381 }
1382 }
1383 /* Sub functions with Two operands functions */
1384 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1385 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1386 { \
1387 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1388 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1389 add_ca, compute_ca, compute_ov); \
1390 }
1391 /* Sub functions with one operand and one immediate */
1392 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1393 add_ca, compute_ca, compute_ov) \
1394 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1395 { \
1396 TCGv t0 = tcg_const_local_tl(const_val); \
1397 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1398 cpu_gpr[rA(ctx->opcode)], t0, \
1399 add_ca, compute_ca, compute_ov); \
1400 tcg_temp_free(t0); \
1401 }
1402 /* subf subf. subfo subfo. */
1403 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1404 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1405 /* subfc subfc. subfco subfco. */
1406 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1407 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1408 /* subfe subfe. subfeo subfo. */
1409 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1410 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1411 /* subfme subfme. subfmeo subfmeo. */
1412 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1413 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1414 /* subfze subfze. subfzeo subfzeo.*/
1415 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1416 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1417 /* subfic */
1418 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1419 {
1420 /* Start with XER CA and OV disabled, the most likely case */
1421 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1422 TCGv t0 = tcg_temp_local_new();
1423 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1424 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1425 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1426 tcg_temp_free(t1);
1427 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1428 tcg_temp_free(t0);
1429 }
1430
1431 /*** Integer logical ***/
1432 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1433 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1434 { \
1435 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1436 cpu_gpr[rB(ctx->opcode)]); \
1437 if (unlikely(Rc(ctx->opcode) != 0)) \
1438 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1439 }
1440
1441 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1442 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1443 { \
1444 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1445 if (unlikely(Rc(ctx->opcode) != 0)) \
1446 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1447 }
1448
1449 /* and & and. */
1450 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1451 /* andc & andc. */
1452 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1453 /* andi. */
1454 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1455 {
1456 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1457 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1458 }
1459 /* andis. */
1460 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1461 {
1462 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1463 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1464 }
1465 /* cntlzw */
1466 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1467 {
1468 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1469 if (unlikely(Rc(ctx->opcode) != 0))
1470 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1471 }
1472 /* eqv & eqv. */
1473 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1474 /* extsb & extsb. */
1475 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1476 /* extsh & extsh. */
1477 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1478 /* nand & nand. */
1479 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1480 /* nor & nor. */
1481 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1482 /* or & or. */
1483 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1484 {
1485 int rs, ra, rb;
1486
1487 rs = rS(ctx->opcode);
1488 ra = rA(ctx->opcode);
1489 rb = rB(ctx->opcode);
1490 /* Optimisation for mr. ri case */
1491 if (rs != ra || rs != rb) {
1492 if (rs != rb)
1493 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1494 else
1495 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1496 if (unlikely(Rc(ctx->opcode) != 0))
1497 gen_set_Rc0(ctx, cpu_gpr[ra]);
1498 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1499 gen_set_Rc0(ctx, cpu_gpr[rs]);
1500 #if defined(TARGET_PPC64)
1501 } else {
1502 int prio = 0;
1503
1504 switch (rs) {
1505 case 1:
1506 /* Set process priority to low */
1507 prio = 2;
1508 break;
1509 case 6:
1510 /* Set process priority to medium-low */
1511 prio = 3;
1512 break;
1513 case 2:
1514 /* Set process priority to normal */
1515 prio = 4;
1516 break;
1517 #if !defined(CONFIG_USER_ONLY)
1518 case 31:
1519 if (ctx->mem_idx > 0) {
1520 /* Set process priority to very low */
1521 prio = 1;
1522 }
1523 break;
1524 case 5:
1525 if (ctx->mem_idx > 0) {
1526 /* Set process priority to medium-hight */
1527 prio = 5;
1528 }
1529 break;
1530 case 3:
1531 if (ctx->mem_idx > 0) {
1532 /* Set process priority to high */
1533 prio = 6;
1534 }
1535 break;
1536 case 7:
1537 if (ctx->mem_idx > 1) {
1538 /* Set process priority to very high */
1539 prio = 7;
1540 }
1541 break;
1542 #endif
1543 default:
1544 /* nop */
1545 break;
1546 }
1547 if (prio) {
1548 TCGv t0 = tcg_temp_new();
1549 gen_load_spr(t0, SPR_PPR);
1550 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1551 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1552 gen_store_spr(SPR_PPR, t0);
1553 tcg_temp_free(t0);
1554 }
1555 #endif
1556 }
1557 }
1558 /* orc & orc. */
1559 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1560 /* xor & xor. */
1561 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1562 {
1563 /* Optimisation for "set to zero" case */
1564 if (rS(ctx->opcode) != rB(ctx->opcode))
1565 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1566 else
1567 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1568 if (unlikely(Rc(ctx->opcode) != 0))
1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1570 }
1571 /* ori */
1572 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1573 {
1574 target_ulong uimm = UIMM(ctx->opcode);
1575
1576 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1577 /* NOP */
1578 /* XXX: should handle special NOPs for POWER series */
1579 return;
1580 }
1581 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1582 }
1583 /* oris */
1584 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1585 {
1586 target_ulong uimm = UIMM(ctx->opcode);
1587
1588 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1589 /* NOP */
1590 return;
1591 }
1592 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1593 }
1594 /* xori */
1595 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1596 {
1597 target_ulong uimm = UIMM(ctx->opcode);
1598
1599 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1600 /* NOP */
1601 return;
1602 }
1603 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1604 }
1605 /* xoris */
1606 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1607 {
1608 target_ulong uimm = UIMM(ctx->opcode);
1609
1610 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1611 /* NOP */
1612 return;
1613 }
1614 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1615 }
1616 /* popcntb : PowerPC 2.03 specification */
1617 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1618 {
1619 #if defined(TARGET_PPC64)
1620 if (ctx->sf_mode)
1621 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1622 else
1623 #endif
1624 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1625 }
1626
1627 #if defined(TARGET_PPC64)
1628 /* extsw & extsw. */
1629 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1630 /* cntlzd */
1631 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1632 {
1633 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1634 if (unlikely(Rc(ctx->opcode) != 0))
1635 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1636 }
1637 #endif
1638
1639 /*** Integer rotate ***/
1640 /* rlwimi & rlwimi. */
1641 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1642 {
1643 uint32_t mb, me, sh;
1644
1645 mb = MB(ctx->opcode);
1646 me = ME(ctx->opcode);
1647 sh = SH(ctx->opcode);
1648 if (likely(sh == 0 && mb == 0 && me == 31)) {
1649 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1650 } else {
1651 target_ulong mask;
1652 TCGv t1;
1653 TCGv t0 = tcg_temp_new();
1654 #if defined(TARGET_PPC64)
1655 TCGv_i32 t2 = tcg_temp_new_i32();
1656 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1657 tcg_gen_rotli_i32(t2, t2, sh);
1658 tcg_gen_extu_i32_i64(t0, t2);
1659 tcg_temp_free_i32(t2);
1660 #else
1661 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1662 #endif
1663 #if defined(TARGET_PPC64)
1664 mb += 32;
1665 me += 32;
1666 #endif
1667 mask = MASK(mb, me);
1668 t1 = tcg_temp_new();
1669 tcg_gen_andi_tl(t0, t0, mask);
1670 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1671 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1672 tcg_temp_free(t0);
1673 tcg_temp_free(t1);
1674 }
1675 if (unlikely(Rc(ctx->opcode) != 0))
1676 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1677 }
1678 /* rlwinm & rlwinm. */
1679 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1680 {
1681 uint32_t mb, me, sh;
1682
1683 sh = SH(ctx->opcode);
1684 mb = MB(ctx->opcode);
1685 me = ME(ctx->opcode);
1686
1687 if (likely(mb == 0 && me == (31 - sh))) {
1688 if (likely(sh == 0)) {
1689 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1690 } else {
1691 TCGv t0 = tcg_temp_new();
1692 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1693 tcg_gen_shli_tl(t0, t0, sh);
1694 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1695 tcg_temp_free(t0);
1696 }
1697 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1698 TCGv t0 = tcg_temp_new();
1699 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1700 tcg_gen_shri_tl(t0, t0, mb);
1701 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1702 tcg_temp_free(t0);
1703 } else {
1704 TCGv t0 = tcg_temp_new();
1705 #if defined(TARGET_PPC64)
1706 TCGv_i32 t1 = tcg_temp_new_i32();
1707 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1708 tcg_gen_rotli_i32(t1, t1, sh);
1709 tcg_gen_extu_i32_i64(t0, t1);
1710 tcg_temp_free_i32(t1);
1711 #else
1712 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1713 #endif
1714 #if defined(TARGET_PPC64)
1715 mb += 32;
1716 me += 32;
1717 #endif
1718 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1719 tcg_temp_free(t0);
1720 }
1721 if (unlikely(Rc(ctx->opcode) != 0))
1722 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1723 }
1724 /* rlwnm & rlwnm. */
1725 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1726 {
1727 uint32_t mb, me;
1728 TCGv t0;
1729 #if defined(TARGET_PPC64)
1730 TCGv_i32 t1, t2;
1731 #endif
1732
1733 mb = MB(ctx->opcode);
1734 me = ME(ctx->opcode);
1735 t0 = tcg_temp_new();
1736 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1737 #if defined(TARGET_PPC64)
1738 t1 = tcg_temp_new_i32();
1739 t2 = tcg_temp_new_i32();
1740 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1741 tcg_gen_trunc_i64_i32(t2, t0);
1742 tcg_gen_rotl_i32(t1, t1, t2);
1743 tcg_gen_extu_i32_i64(t0, t1);
1744 tcg_temp_free_i32(t1);
1745 tcg_temp_free_i32(t2);
1746 #else
1747 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1748 #endif
1749 if (unlikely(mb != 0 || me != 31)) {
1750 #if defined(TARGET_PPC64)
1751 mb += 32;
1752 me += 32;
1753 #endif
1754 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1755 } else {
1756 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1757 }
1758 tcg_temp_free(t0);
1759 if (unlikely(Rc(ctx->opcode) != 0))
1760 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1761 }
1762
1763 #if defined(TARGET_PPC64)
1764 #define GEN_PPC64_R2(name, opc1, opc2) \
1765 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1766 { \
1767 gen_##name(ctx, 0); \
1768 } \
1769 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1770 PPC_64B) \
1771 { \
1772 gen_##name(ctx, 1); \
1773 }
1774 #define GEN_PPC64_R4(name, opc1, opc2) \
1775 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1776 { \
1777 gen_##name(ctx, 0, 0); \
1778 } \
1779 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1780 PPC_64B) \
1781 { \
1782 gen_##name(ctx, 0, 1); \
1783 } \
1784 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1785 PPC_64B) \
1786 { \
1787 gen_##name(ctx, 1, 0); \
1788 } \
1789 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1790 PPC_64B) \
1791 { \
1792 gen_##name(ctx, 1, 1); \
1793 }
1794
1795 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1796 uint32_t me, uint32_t sh)
1797 {
1798 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1799 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1800 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1801 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1802 } else {
1803 TCGv t0 = tcg_temp_new();
1804 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1805 if (likely(mb == 0 && me == 63)) {
1806 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1807 } else {
1808 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1809 }
1810 tcg_temp_free(t0);
1811 }
1812 if (unlikely(Rc(ctx->opcode) != 0))
1813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1814 }
1815 /* rldicl - rldicl. */
1816 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1817 {
1818 uint32_t sh, mb;
1819
1820 sh = SH(ctx->opcode) | (shn << 5);
1821 mb = MB(ctx->opcode) | (mbn << 5);
1822 gen_rldinm(ctx, mb, 63, sh);
1823 }
1824 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1825 /* rldicr - rldicr. */
1826 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1827 {
1828 uint32_t sh, me;
1829
1830 sh = SH(ctx->opcode) | (shn << 5);
1831 me = MB(ctx->opcode) | (men << 5);
1832 gen_rldinm(ctx, 0, me, sh);
1833 }
1834 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1835 /* rldic - rldic. */
1836 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1837 {
1838 uint32_t sh, mb;
1839
1840 sh = SH(ctx->opcode) | (shn << 5);
1841 mb = MB(ctx->opcode) | (mbn << 5);
1842 gen_rldinm(ctx, mb, 63 - sh, sh);
1843 }
1844 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1845
1846 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1847 uint32_t me)
1848 {
1849 TCGv t0;
1850
1851 mb = MB(ctx->opcode);
1852 me = ME(ctx->opcode);
1853 t0 = tcg_temp_new();
1854 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1855 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1856 if (unlikely(mb != 0 || me != 63)) {
1857 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1858 } else {
1859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1860 }
1861 tcg_temp_free(t0);
1862 if (unlikely(Rc(ctx->opcode) != 0))
1863 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1864 }
1865
1866 /* rldcl - rldcl. */
1867 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1868 {
1869 uint32_t mb;
1870
1871 mb = MB(ctx->opcode) | (mbn << 5);
1872 gen_rldnm(ctx, mb, 63);
1873 }
1874 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1875 /* rldcr - rldcr. */
1876 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1877 {
1878 uint32_t me;
1879
1880 me = MB(ctx->opcode) | (men << 5);
1881 gen_rldnm(ctx, 0, me);
1882 }
1883 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1884 /* rldimi - rldimi. */
1885 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1886 {
1887 uint32_t sh, mb, me;
1888
1889 sh = SH(ctx->opcode) | (shn << 5);
1890 mb = MB(ctx->opcode) | (mbn << 5);
1891 me = 63 - sh;
1892 if (unlikely(sh == 0 && mb == 0)) {
1893 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1894 } else {
1895 TCGv t0, t1;
1896 target_ulong mask;
1897
1898 t0 = tcg_temp_new();
1899 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1900 t1 = tcg_temp_new();
1901 mask = MASK(mb, me);
1902 tcg_gen_andi_tl(t0, t0, mask);
1903 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1904 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1905 tcg_temp_free(t0);
1906 tcg_temp_free(t1);
1907 }
1908 if (unlikely(Rc(ctx->opcode) != 0))
1909 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1910 }
1911 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1912 #endif
1913
1914 /*** Integer shift ***/
1915 /* slw & slw. */
1916 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1917 {
1918 TCGv t0;
1919 int l1, l2;
1920 l1 = gen_new_label();
1921 l2 = gen_new_label();
1922
1923 t0 = tcg_temp_local_new();
1924 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1925 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1926 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1927 tcg_gen_br(l2);
1928 gen_set_label(l1);
1929 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1930 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1931 gen_set_label(l2);
1932 tcg_temp_free(t0);
1933 if (unlikely(Rc(ctx->opcode) != 0))
1934 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1935 }
1936 /* sraw & sraw. */
1937 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1938 {
1939 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1940 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1941 if (unlikely(Rc(ctx->opcode) != 0))
1942 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1943 }
1944 /* srawi & srawi. */
1945 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1946 {
1947 int sh = SH(ctx->opcode);
1948 if (sh != 0) {
1949 int l1, l2;
1950 TCGv t0;
1951 l1 = gen_new_label();
1952 l2 = gen_new_label();
1953 t0 = tcg_temp_local_new();
1954 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1955 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1956 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1957 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1958 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1959 tcg_gen_br(l2);
1960 gen_set_label(l1);
1961 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1962 gen_set_label(l2);
1963 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1964 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1965 tcg_temp_free(t0);
1966 } else {
1967 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1968 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1969 }
1970 if (unlikely(Rc(ctx->opcode) != 0))
1971 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1972 }
1973 /* srw & srw. */
1974 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1975 {
1976 TCGv t0, t1;
1977 int l1, l2;
1978 l1 = gen_new_label();
1979 l2 = gen_new_label();
1980
1981 t0 = tcg_temp_local_new();
1982 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1983 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1984 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1985 tcg_gen_br(l2);
1986 gen_set_label(l1);
1987 t1 = tcg_temp_new();
1988 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1989 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1990 tcg_temp_free(t1);
1991 gen_set_label(l2);
1992 tcg_temp_free(t0);
1993 if (unlikely(Rc(ctx->opcode) != 0))
1994 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1995 }
1996 #if defined(TARGET_PPC64)
1997 /* sld & sld. */
1998 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1999 {
2000 TCGv t0;
2001 int l1, l2;
2002 l1 = gen_new_label();
2003 l2 = gen_new_label();
2004
2005 t0 = tcg_temp_local_new();
2006 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2007 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2008 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2009 tcg_gen_br(l2);
2010 gen_set_label(l1);
2011 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2012 gen_set_label(l2);
2013 tcg_temp_free(t0);
2014 if (unlikely(Rc(ctx->opcode) != 0))
2015 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2016 }
2017 /* srad & srad. */
2018 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2019 {
2020 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2021 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2022 if (unlikely(Rc(ctx->opcode) != 0))
2023 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2024 }
2025 /* sradi & sradi. */
2026 static always_inline void gen_sradi (DisasContext *ctx, int n)
2027 {
2028 int sh = SH(ctx->opcode) + (n << 5);
2029 if (sh != 0) {
2030 int l1, l2;
2031 TCGv t0;
2032 l1 = gen_new_label();
2033 l2 = gen_new_label();
2034 t0 = tcg_temp_local_new();
2035 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2036 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2037 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2038 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2039 tcg_gen_br(l2);
2040 gen_set_label(l1);
2041 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2042 gen_set_label(l2);
2043 tcg_temp_free(t0);
2044 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2045 } else {
2046 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2047 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2048 }
2049 if (unlikely(Rc(ctx->opcode) != 0))
2050 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2051 }
2052 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2053 {
2054 gen_sradi(ctx, 0);
2055 }
2056 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2057 {
2058 gen_sradi(ctx, 1);
2059 }
2060 /* srd & srd. */
2061 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2062 {
2063 TCGv t0;
2064 int l1, l2;
2065 l1 = gen_new_label();
2066 l2 = gen_new_label();
2067
2068 t0 = tcg_temp_local_new();
2069 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2070 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2071 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2072 tcg_gen_br(l2);
2073 gen_set_label(l1);
2074 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2075 gen_set_label(l2);
2076 tcg_temp_free(t0);
2077 if (unlikely(Rc(ctx->opcode) != 0))
2078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2079 }
2080 #endif
2081
2082 /*** Floating-Point arithmetic ***/
2083 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2084 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2085 { \
2086 if (unlikely(!ctx->fpu_enabled)) { \
2087 gen_exception(ctx, POWERPC_EXCP_FPU); \
2088 return; \
2089 } \
2090 /* NIP cannot be restored if the memory exception comes from an helper */ \
2091 gen_update_nip(ctx, ctx->nip - 4); \
2092 gen_reset_fpstatus(); \
2093 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2094 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2095 if (isfloat) { \
2096 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2097 } \
2098 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2099 Rc(ctx->opcode) != 0); \
2100 }
2101
2102 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2103 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2104 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2105
2106 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2107 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2108 { \
2109 if (unlikely(!ctx->fpu_enabled)) { \
2110 gen_exception(ctx, POWERPC_EXCP_FPU); \
2111 return; \
2112 } \
2113 /* NIP cannot be restored if the memory exception comes from an helper */ \
2114 gen_update_nip(ctx, ctx->nip - 4); \
2115 gen_reset_fpstatus(); \
2116 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2117 cpu_fpr[rB(ctx->opcode)]); \
2118 if (isfloat) { \
2119 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2120 } \
2121 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2122 set_fprf, Rc(ctx->opcode) != 0); \
2123 }
2124 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2125 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2126 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2127
2128 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2129 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2130 { \
2131 if (unlikely(!ctx->fpu_enabled)) { \
2132 gen_exception(ctx, POWERPC_EXCP_FPU); \
2133 return; \
2134 } \
2135 /* NIP cannot be restored if the memory exception comes from an helper */ \
2136 gen_update_nip(ctx, ctx->nip - 4); \
2137 gen_reset_fpstatus(); \
2138 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2139 cpu_fpr[rC(ctx->opcode)]); \
2140 if (isfloat) { \
2141 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2142 } \
2143 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2144 set_fprf, Rc(ctx->opcode) != 0); \
2145 }
2146 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2147 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2148 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2149
2150 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2151 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2152 { \
2153 if (unlikely(!ctx->fpu_enabled)) { \
2154 gen_exception(ctx, POWERPC_EXCP_FPU); \
2155 return; \
2156 } \
2157 /* NIP cannot be restored if the memory exception comes from an helper */ \
2158 gen_update_nip(ctx, ctx->nip - 4); \
2159 gen_reset_fpstatus(); \
2160 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2161 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2162 set_fprf, Rc(ctx->opcode) != 0); \
2163 }
2164
2165 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2166 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2167 { \
2168 if (unlikely(!ctx->fpu_enabled)) { \
2169 gen_exception(ctx, POWERPC_EXCP_FPU); \
2170 return; \
2171 } \
2172 /* NIP cannot be restored if the memory exception comes from an helper */ \
2173 gen_update_nip(ctx, ctx->nip - 4); \
2174 gen_reset_fpstatus(); \
2175 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2176 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2177 set_fprf, Rc(ctx->opcode) != 0); \
2178 }
2179
2180 /* fadd - fadds */
2181 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2182 /* fdiv - fdivs */
2183 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2184 /* fmul - fmuls */
2185 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2186
2187 /* fre */
2188 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2189
2190 /* fres */
2191 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2192
2193 /* frsqrte */
2194 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2195
2196 /* frsqrtes */
2197 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2198 {
2199 if (unlikely(!ctx->fpu_enabled)) {
2200 gen_exception(ctx, POWERPC_EXCP_FPU);
2201 return;
2202 }
2203 /* NIP cannot be restored if the memory exception comes from an helper */
2204 gen_update_nip(ctx, ctx->nip - 4);
2205 gen_reset_fpstatus();
2206 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2207 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2208 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2209 }
2210
2211 /* fsel */
2212 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2213 /* fsub - fsubs */
2214 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2215 /* Optional: */
2216 /* fsqrt */
2217 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2218 {
2219 if (unlikely(!ctx->fpu_enabled)) {
2220 gen_exception(ctx, POWERPC_EXCP_FPU);
2221 return;
2222 }
2223 /* NIP cannot be restored if the memory exception comes from an helper */
2224 gen_update_nip(ctx, ctx->nip - 4);
2225 gen_reset_fpstatus();
2226 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2227 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2228 }
2229
2230 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2231 {
2232 if (unlikely(!ctx->fpu_enabled)) {
2233 gen_exception(ctx, POWERPC_EXCP_FPU);
2234 return;
2235 }
2236 /* NIP cannot be restored if the memory exception comes from an helper */
2237 gen_update_nip(ctx, ctx->nip - 4);
2238 gen_reset_fpstatus();
2239 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2240 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2241 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2242 }
2243
2244 /*** Floating-Point multiply-and-add ***/
2245 /* fmadd - fmadds */
2246 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2247 /* fmsub - fmsubs */
2248 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2249 /* fnmadd - fnmadds */
2250 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2251 /* fnmsub - fnmsubs */
2252 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2253
2254 /*** Floating-Point round & convert ***/
2255 /* fctiw */
2256 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2257 /* fctiwz */
2258 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2259 /* frsp */
2260 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2261 #if defined(TARGET_PPC64)
2262 /* fcfid */
2263 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2264 /* fctid */
2265 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2266 /* fctidz */
2267 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2268 #endif
2269
2270 /* frin */
2271 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2272 /* friz */
2273 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2274 /* frip */
2275 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2276 /* frim */
2277 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2278
2279 /*** Floating-Point compare ***/
2280 /* fcmpo */
2281 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2282 {
2283 TCGv_i32 crf;
2284 if (unlikely(!ctx->fpu_enabled)) {
2285 gen_exception(ctx, POWERPC_EXCP_FPU);
2286 return;
2287 }
2288 /* NIP cannot be restored if the memory exception comes from an helper */
2289 gen_update_nip(ctx, ctx->nip - 4);
2290 gen_reset_fpstatus();
2291 crf = tcg_const_i32(crfD(ctx->opcode));
2292 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2293 tcg_temp_free_i32(crf);
2294 gen_helper_float_check_status();
2295 }
2296
2297 /* fcmpu */
2298 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2299 {
2300 TCGv_i32 crf;
2301 if (unlikely(!ctx->fpu_enabled)) {
2302 gen_exception(ctx, POWERPC_EXCP_FPU);
2303 return;
2304 }
2305 /* NIP cannot be restored if the memory exception comes from an helper */
2306 gen_update_nip(ctx, ctx->nip - 4);
2307 gen_reset_fpstatus();
2308 crf = tcg_const_i32(crfD(ctx->opcode));
2309 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2310 tcg_temp_free_i32(crf);
2311 gen_helper_float_check_status();
2312 }
2313
2314 /*** Floating-point move ***/
2315 /* fabs */
2316 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2317 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2318
2319 /* fmr - fmr. */
2320 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2321 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2322 {
2323 if (unlikely(!ctx->fpu_enabled)) {
2324 gen_exception(ctx, POWERPC_EXCP_FPU);
2325 return;
2326 }
2327 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2328 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2329 }
2330
2331 /* fnabs */
2332 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2333 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2334 /* fneg */
2335 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2336 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2337
2338 /*** Floating-Point status & ctrl register ***/
2339 /* mcrfs */
2340 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2341 {
2342 int bfa;
2343
2344 if (unlikely(!ctx->fpu_enabled)) {
2345 gen_exception(ctx, POWERPC_EXCP_FPU);
2346 return;
2347 }
2348 bfa = 4 * (7 - crfS(ctx->opcode));
2349 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2350 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2351 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2352 }
2353
2354 /* mffs */
2355 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2356 {
2357 if (unlikely(!ctx->fpu_enabled)) {
2358 gen_exception(ctx, POWERPC_EXCP_FPU);
2359 return;
2360 }
2361 gen_reset_fpstatus();
2362 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2363 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2364 }
2365
2366 /* mtfsb0 */
2367 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2368 {
2369 uint8_t crb;
2370
2371 if (unlikely(!ctx->fpu_enabled)) {
2372 gen_exception(ctx, POWERPC_EXCP_FPU);
2373 return;
2374 }
2375 crb = 31 - crbD(ctx->opcode);
2376 gen_reset_fpstatus();
2377 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2378 TCGv_i32 t0;
2379 /* NIP cannot be restored if the memory exception comes from an helper */
2380 gen_update_nip(ctx, ctx->nip - 4);
2381 t0 = tcg_const_i32(crb);
2382 gen_helper_fpscr_clrbit(t0);
2383 tcg_temp_free_i32(t0);
2384 }
2385 if (unlikely(Rc(ctx->opcode) != 0)) {
2386 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2387 }
2388 }
2389
2390 /* mtfsb1 */
2391 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2392 {
2393 uint8_t crb;
2394
2395 if (unlikely(!ctx->fpu_enabled)) {
2396 gen_exception(ctx, POWERPC_EXCP_FPU);
2397 return;
2398 }
2399 crb = 31 - crbD(ctx->opcode);
2400 gen_reset_fpstatus();
2401 /* XXX: we pretend we can only do IEEE floating-point computations */
2402 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2403 TCGv_i32 t0;
2404 /* NIP cannot be restored if the memory exception comes from an helper */
2405 gen_update_nip(ctx, ctx->nip - 4);
2406 t0 = tcg_const_i32(crb);
2407 gen_helper_fpscr_setbit(t0);
2408 tcg_temp_free_i32(t0);
2409 }
2410 if (unlikely(Rc(ctx->opcode) != 0)) {
2411 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2412 }
2413 /* We can raise a differed exception */
2414 gen_helper_float_check_status();
2415 }
2416
2417 /* mtfsf */
2418 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2419 {
2420 TCGv_i32 t0;
2421
2422 if (unlikely(!ctx->fpu_enabled)) {
2423 gen_exception(ctx, POWERPC_EXCP_FPU);
2424 return;
2425 }
2426 /* NIP cannot be restored if the memory exception comes from an helper */
2427 gen_update_nip(ctx, ctx->nip - 4);
2428 gen_reset_fpstatus();
2429 t0 = tcg_const_i32(FM(ctx->opcode));
2430 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2431 tcg_temp_free_i32(t0);
2432 if (unlikely(Rc(ctx->opcode) != 0)) {
2433 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2434 }
2435 /* We can raise a differed exception */
2436 gen_helper_float_check_status();
2437 }
2438
2439 /* mtfsfi */
2440 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2441 {
2442 int bf, sh;
2443 TCGv_i64 t0;
2444 TCGv_i32 t1;
2445
2446 if (unlikely(!ctx->fpu_enabled)) {
2447 gen_exception(ctx, POWERPC_EXCP_FPU);
2448 return;
2449 }
2450 bf = crbD(ctx->opcode) >> 2;
2451 sh = 7 - bf;
2452 /* NIP cannot be restored if the memory exception comes from an helper */
2453 gen_update_nip(ctx, ctx->nip - 4);
2454 gen_reset_fpstatus();
2455 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2456 t1 = tcg_const_i32(1 << sh);
2457 gen_helper_store_fpscr(t0, t1);
2458 tcg_temp_free_i64(t0);
2459 tcg_temp_free_i32(t1);
2460 if (unlikely(Rc(ctx->opcode) != 0)) {
2461 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2462 }
2463 /* We can raise a differed exception */
2464 gen_helper_float_check_status();
2465 }
2466
2467 /*** Addressing modes ***/
2468 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2469 static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2470 {
2471 target_long simm = SIMM(ctx->opcode);
2472
2473 simm &= ~maskl;
2474 if (rA(ctx->opcode) == 0) {
2475 #if defined(TARGET_PPC64)
2476 if (!ctx->sf_mode) {
2477 tcg_gen_movi_tl(EA, (uint32_t)simm);
2478 } else
2479 #endif
2480 tcg_gen_movi_tl(EA, simm);
2481 } else if (likely(simm != 0)) {
2482 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2483 #if defined(TARGET_PPC64)
2484 if (!ctx->sf_mode) {
2485 tcg_gen_ext32u_tl(EA, EA);
2486 }
2487 #endif
2488 } else {
2489 #if defined(TARGET_PPC64)
2490 if (!ctx->sf_mode) {
2491 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2492 } else
2493 #endif
2494 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2495 }
2496 }
2497
2498 static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2499 {
2500 if (rA(ctx->opcode) == 0) {
2501 #if defined(TARGET_PPC64)
2502 if (!ctx->sf_mode) {
2503 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2504 } else
2505 #endif
2506 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2507 } else {
2508 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2509 #if defined(TARGET_PPC64)
2510 if (!ctx->sf_mode) {
2511 tcg_gen_ext32u_tl(EA, EA);
2512 }
2513 #endif
2514 }
2515 }
2516
2517 static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2518 {
2519 if (rA(ctx->opcode) == 0) {
2520 tcg_gen_movi_tl(EA, 0);
2521 } else {
2522 #if defined(TARGET_PPC64)
2523 if (!ctx->sf_mode) {
2524 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2525 } else
2526 #endif
2527 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2528 }
2529 }
2530
2531 static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2532 {
2533 tcg_gen_addi_tl(ret, arg1, val);
2534 #if defined(TARGET_PPC64)
2535 if (!ctx->sf_mode) {
2536 tcg_gen_ext32u_tl(ret, ret);
2537 }
2538 #endif
2539 }
2540
2541 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2542 {
2543 int l1 = gen_new_label();
2544 TCGv t0 = tcg_temp_new();
2545 TCGv_i32 t1, t2;
2546 /* NIP cannot be restored if the memory exception comes from an helper */
2547 gen_update_nip(ctx, ctx->nip - 4);
2548 tcg_gen_andi_tl(t0, EA, mask);
2549 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2550 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2551 t2 = tcg_const_i32(0);
2552 gen_helper_raise_exception_err(t1, t2);
2553 tcg_temp_free_i32(t1);
2554 tcg_temp_free_i32(t2);
2555 gen_set_label(l1);
2556 tcg_temp_free(t0);
2557 }
2558
2559 /*** Integer load ***/
2560 static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2561 {
2562 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2563 }
2564
2565 static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2566 {
2567 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2568 }
2569
2570 static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2571 {
2572 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2573 if (unlikely(ctx->le_mode)) {
2574 #if defined(TARGET_PPC64)
2575 TCGv_i32 t0 = tcg_temp_new_i32();
2576 tcg_gen_trunc_tl_i32(t0, arg1);
2577 tcg_gen_bswap16_i32(t0, t0);
2578 tcg_gen_extu_i32_tl(arg1, t0);
2579 tcg_temp_free_i32(t0);
2580 #else
2581 tcg_gen_bswap16_i32(arg1, arg1);
2582 #endif
2583 }
2584 }
2585
2586 static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2587 {
2588 if (unlikely(ctx->le_mode)) {
2589 #if defined(TARGET_PPC64)
2590 TCGv_i32 t0;
2591 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2592 t0 = tcg_temp_new_i32();
2593 tcg_gen_trunc_tl_i32(t0, arg1);
2594 tcg_gen_bswap16_i32(t0, t0);
2595 tcg_gen_extu_i32_tl(arg1, t0);
2596 tcg_gen_ext16s_tl(arg1, arg1);
2597 tcg_temp_free_i32(t0);
2598 #else
2599 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2600 tcg_gen_bswap16_i32(arg1, arg1);
2601 tcg_gen_ext16s_i32(arg1, arg1);
2602 #endif
2603 } else {
2604 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2605 }
2606 }
2607
2608 static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2609 {
2610 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2611 if (unlikely(ctx->le_mode)) {
2612 #if defined(TARGET_PPC64)
2613 TCGv_i32 t0 = tcg_temp_new_i32();
2614 tcg_gen_trunc_tl_i32(t0, arg1);
2615 tcg_gen_bswap_i32(t0, t0);
2616 tcg_gen_extu_i32_tl(arg1, t0);
2617 tcg_temp_free_i32(t0);
2618 #else
2619 tcg_gen_bswap_i32(arg1, arg1);
2620 #endif
2621 }
2622 }
2623
2624 #if defined(TARGET_PPC64)
2625 static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2626 {
2627 if (unlikely(ctx->le_mode)) {
2628 TCGv_i32 t0;
2629 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2630 t0 = tcg_temp_new_i32();
2631 tcg_gen_trunc_tl_i32(t0, arg1);
2632 tcg_gen_bswap_i32(t0, t0);
2633 tcg_gen_ext_i32_tl(arg1, t0);
2634 tcg_temp_free_i32(t0);
2635 } else
2636 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2637 }
2638 #endif
2639
2640 static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2641 {
2642 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2643 if (unlikely(ctx->le_mode)) {
2644 tcg_gen_bswap_i64(arg1, arg1);
2645 }
2646 }
2647
2648 static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2649 {
2650 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2651 }
2652
2653 static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2654 {
2655 if (unlikely(ctx->le_mode)) {
2656 #if defined(TARGET_PPC64)
2657 TCGv_i32 t0;
2658 TCGv t1;
2659 t0 = tcg_temp_new_i32();
2660 tcg_gen_trunc_tl_i32(t0, arg1);
2661 tcg_gen_ext16u_i32(t0, t0);
2662 tcg_gen_bswap16_i32(t0, t0);
2663 t1 = tcg_temp_new();
2664 tcg_gen_extu_i32_tl(t1, t0);
2665 tcg_temp_free_i32(t0);
2666 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2667 tcg_temp_free(t1);
2668 #else
2669 TCGv t0 = tcg_temp_new();
2670 tcg_gen_ext16u_tl(t0, arg1);
2671 tcg_gen_bswap16_i32(t0, t0);
2672 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2673 tcg_temp_free(t0);
2674 #endif
2675 } else {
2676 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2677 }
2678 }
2679
2680 static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2681 {
2682 if (unlikely(ctx->le_mode)) {
2683 #if defined(TARGET_PPC64)
2684 TCGv_i32 t0;
2685 TCGv t1;
2686 t0 = tcg_temp_new_i32();
2687 tcg_gen_trunc_tl_i32(t0, arg1);
2688 tcg_gen_bswap_i32(t0, t0);
2689 t1 = tcg_temp_new();
2690 tcg_gen_extu_i32_tl(t1, t0);
2691 tcg_temp_free_i32(t0);
2692 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2693 tcg_temp_free(t1);
2694 #else
2695 TCGv t0 = tcg_temp_new_i32();
2696 tcg_gen_bswap_i32(t0, arg1);
2697 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2698 tcg_temp_free(t0);
2699 #endif
2700 } else {
2701 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2702 }
2703 }
2704
2705 static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2706 {
2707 if (unlikely(ctx->le_mode)) {
2708 TCGv_i64 t0 = tcg_temp_new_i64();
2709 tcg_gen_bswap_i64(t0, arg1);
2710 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2711 tcg_temp_free_i64(t0);
2712 } else
2713 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2714 }
2715
2716 #define GEN_LD(name, ldop, opc, type) \
2717 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2718 { \
2719 TCGv EA; \
2720 gen_set_access_type(ctx, ACCESS_INT); \
2721 EA = tcg_temp_new(); \
2722 gen_addr_imm_index(ctx, EA, 0); \
2723 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2724 tcg_temp_free(EA); \
2725 }
2726
2727 #define GEN_LDU(name, ldop, opc, type) \
2728 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2729 { \
2730 TCGv EA; \
2731 if (unlikely(rA(ctx->opcode) == 0 || \
2732 rA(ctx->opcode) == rD(ctx->opcode))) { \
2733 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2734 return; \
2735 } \
2736 gen_set_access_type(ctx, ACCESS_INT); \
2737 EA = tcg_temp_new(); \
2738 if (type == PPC_64B) \
2739 gen_addr_imm_index(ctx, EA, 0x03); \
2740 else \
2741 gen_addr_imm_index(ctx, EA, 0); \
2742 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2744 tcg_temp_free(EA); \
2745 }
2746
2747 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2748 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2749 { \
2750 TCGv EA; \
2751 if (unlikely(rA(ctx->opcode) == 0 || \
2752 rA(ctx->opcode) == rD(ctx->opcode))) { \
2753 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2754 return; \
2755 } \
2756 gen_set_access_type(ctx, ACCESS_INT); \
2757 EA = tcg_temp_new(); \
2758 gen_addr_reg_index(ctx, EA); \
2759 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2761 tcg_temp_free(EA); \
2762 }
2763
2764 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2765 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2766 { \
2767 TCGv EA; \
2768 gen_set_access_type(ctx, ACCESS_INT); \
2769 EA = tcg_temp_new(); \
2770 gen_addr_reg_index(ctx, EA); \
2771 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2772 tcg_temp_free(EA); \
2773 }
2774
2775 #define GEN_LDS(name, ldop, op, type) \
2776 GEN_LD(name, ldop, op | 0x20, type); \
2777 GEN_LDU(name, ldop, op | 0x21, type); \
2778 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2779 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2780
2781 /* lbz lbzu lbzux lbzx */
2782 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2783 /* lha lhau lhaux lhax */
2784 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2785 /* lhz lhzu lhzux lhzx */
2786 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2787 /* lwz lwzu lwzux lwzx */
2788 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2789 #if defined(TARGET_PPC64)
2790 /* lwaux */
2791 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2792 /* lwax */
2793 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2794 /* ldux */
2795 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2796 /* ldx */
2797 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2798 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2799 {
2800 TCGv EA;
2801 if (Rc(ctx->opcode)) {
2802 if (unlikely(rA(ctx->opcode) == 0 ||
2803 rA(ctx->opcode) == rD(ctx->opcode))) {
2804 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2805 return;
2806 }
2807 }
2808 gen_set_access_type(ctx, ACCESS_INT);
2809 EA = tcg_temp_new();
2810 gen_addr_imm_index(ctx, EA, 0x03);
2811 if (ctx->opcode & 0x02) {
2812 /* lwa (lwau is undefined) */
2813 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2814 } else {
2815 /* ld - ldu */
2816 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2817 }
2818 if (Rc(ctx->opcode))
2819 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2820 tcg_temp_free(EA);
2821 }
2822 /* lq */
2823 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2824 {
2825 #if defined(CONFIG_USER_ONLY)
2826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2827 #else
2828 int ra, rd;
2829 TCGv EA;
2830
2831 /* Restore CPU state */
2832 if (unlikely(ctx->mem_idx == 0)) {
2833 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2834 return;
2835 }
2836 ra = rA(ctx->opcode);
2837 rd = rD(ctx->opcode);
2838 if (unlikely((rd & 1) || rd == ra)) {
2839 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2840 return;
2841 }
2842 if (unlikely(ctx->le_mode)) {
2843 /* Little-endian mode is not handled */
2844 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2845 return;
2846 }
2847 gen_set_access_type(ctx, ACCESS_INT);
2848 EA = tcg_temp_new();
2849 gen_addr_imm_index(ctx, EA, 0x0F);
2850 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2851 gen_addr_add(ctx, EA, EA, 8);
2852 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2853 tcg_temp_free(EA);
2854 #endif
2855 }
2856 #endif
2857
2858 /*** Integer store ***/
2859 #define GEN_ST(name, stop, opc, type) \
2860 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2861 { \
2862 TCGv EA; \
2863 gen_set_access_type(ctx, ACCESS_INT); \
2864 EA = tcg_temp_new(); \
2865 gen_addr_imm_index(ctx, EA, 0); \
2866 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2867 tcg_temp_free(EA); \
2868 }
2869
2870 #define GEN_STU(name, stop, opc, type) \
2871 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2872 { \
2873 TCGv EA; \
2874 if (unlikely(rA(ctx->opcode) == 0)) { \
2875 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2876 return; \
2877 } \
2878 gen_set_access_type(ctx, ACCESS_INT); \
2879 EA = tcg_temp_new(); \
2880 if (type == PPC_64B) \
2881 gen_addr_imm_index(ctx, EA, 0x03); \
2882 else \
2883 gen_addr_imm_index(ctx, EA, 0); \
2884 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2885 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2886 tcg_temp_free(EA); \
2887 }
2888
2889 #define GEN_STUX(name, stop, opc2, opc3, type) \
2890 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2891 { \
2892 TCGv EA; \
2893 if (unlikely(rA(ctx->opcode) == 0)) { \
2894 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2895 return; \
2896 } \
2897 gen_set_access_type(ctx, ACCESS_INT); \
2898 EA = tcg_temp_new(); \
2899 gen_addr_reg_index(ctx, EA); \
2900 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2901 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2902 tcg_temp_free(EA); \
2903 }
2904
2905 #define GEN_STX(name, stop, opc2, opc3, type) \
2906 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2907 { \
2908 TCGv EA; \
2909 gen_set_access_type(ctx, ACCESS_INT); \
2910 EA = tcg_temp_new(); \
2911 gen_addr_reg_index(ctx, EA); \
2912 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2913 tcg_temp_free(EA); \
2914 }
2915
2916 #define GEN_STS(name, stop, op, type) \
2917 GEN_ST(name, stop, op | 0x20, type); \
2918 GEN_STU(name, stop, op | 0x21, type); \
2919 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2920 GEN_STX(name, stop, 0x17, op | 0x00, type)
2921
2922 /* stb stbu stbux stbx */
2923 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2924 /* sth sthu sthux sthx */
2925 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2926 /* stw stwu stwux stwx */
2927 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2928 #if defined(TARGET_PPC64)
2929 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2930 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2931 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2932 {
2933 int rs;
2934 TCGv EA;
2935
2936 rs = rS(ctx->opcode);
2937 if ((ctx->opcode & 0x3) == 0x2) {
2938 #if defined(CONFIG_USER_ONLY)
2939 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2940 #else
2941 /* stq */
2942 if (unlikely(ctx->mem_idx == 0)) {
2943 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2944 return;
2945 }
2946 if (unlikely(rs & 1)) {
2947 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2948 return;
2949 }
2950 if (unlikely(ctx->le_mode)) {
2951 /* Little-endian mode is not handled */
2952 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2953 return;
2954 }
2955 gen_set_access_type(ctx, ACCESS_INT);
2956 EA = tcg_temp_new();
2957 gen_addr_imm_index(ctx, EA, 0x03);
2958 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2959 gen_addr_add(ctx, EA, EA, 8);
2960 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2961 tcg_temp_free(EA);
2962 #endif
2963 } else {
2964 /* std / stdu */
2965 if (Rc(ctx->opcode)) {
2966 if (unlikely(rA(ctx->opcode) == 0)) {
2967 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2968 return;
2969 }
2970 }
2971 gen_set_access_type(ctx, ACCESS_INT);
2972 EA = tcg_temp_new();
2973 gen_addr_imm_index(ctx, EA, 0x03);
2974 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2975 if (Rc(ctx->opcode))
2976 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2977 tcg_temp_free(EA);
2978 }
2979 }
2980 #endif
2981 /*** Integer load and store with byte reverse ***/
2982 /* lhbrx */
2983 static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2984 {
2985 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2986 if (likely(!ctx->le_mode)) {
2987 #if defined(TARGET_PPC64)
2988 TCGv_i32 t0 = tcg_temp_new_i32();
2989 tcg_gen_trunc_tl_i32(t0, arg1);
2990 tcg_gen_bswap16_i32(t0, t0);
2991 tcg_gen_extu_i32_tl(arg1, t0);
2992 tcg_temp_free_i32(t0);
2993 #else
2994 tcg_gen_bswap16_i32(arg1, arg1);
2995 #endif
2996 }
2997 }
2998 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2999
3000 /* lwbrx */
3001 static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3002 {
3003 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3004 if (likely(!ctx->le_mode)) {
3005 #if defined(TARGET_PPC64)
3006 TCGv_i32 t0 = tcg_temp_new_i32();
3007 tcg_gen_trunc_tl_i32(t0, arg1);
3008 tcg_gen_bswap_i32(t0, t0);
3009 tcg_gen_extu_i32_tl(arg1, t0);
3010 tcg_temp_free_i32(t0);
3011 #else
3012 tcg_gen_bswap_i32(arg1, arg1);
3013 #endif
3014 }
3015 }
3016 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3017
3018 /* sthbrx */
3019 static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3020 {
3021 if (likely(!ctx->le_mode)) {
3022 #if defined(TARGET_PPC64)
3023 TCGv_i32 t0;
3024 TCGv t1;
3025 t0 = tcg_temp_new_i32();
3026 tcg_gen_trunc_tl_i32(t0, arg1);
3027 tcg_gen_ext16u_i32(t0, t0);
3028 tcg_gen_bswap16_i32(t0, t0);
3029 t1 = tcg_temp_new();
3030 tcg_gen_extu_i32_tl(t1, t0);
3031 tcg_temp_free_i32(t0);
3032 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3033 tcg_temp_free(t1);
3034 #else
3035 TCGv t0 = tcg_temp_new();
3036 tcg_gen_ext16u_tl(t0, arg1);
3037 tcg_gen_bswap16_i32(t0, t0);
3038 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3039 tcg_temp_free(t0);
3040 #endif
3041 } else {
3042 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3043 }
3044 }
3045 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3046
3047 /* stwbrx */
3048 static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3049 {
3050 if (likely(!ctx->le_mode)) {
3051 #if defined(TARGET_PPC64)
3052 TCGv_i32 t0;
3053 TCGv t1;
3054 t0 = tcg_temp_new_i32();
3055 tcg_gen_trunc_tl_i32(t0, arg1);
3056 tcg_gen_bswap_i32(t0, t0);
3057 t1 = tcg_temp_new();
3058 tcg_gen_extu_i32_tl(t1, t0);
3059 tcg_temp_free_i32(t0);
3060 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3061 tcg_temp_free(t1);
3062 #else
3063 TCGv t0 = tcg_temp_new_i32();
3064 tcg_gen_bswap_i32(t0, arg1);
3065 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3066 tcg_temp_free(t0);
3067 #endif
3068 } else {
3069 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3070 }
3071 }
3072 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3073
3074 /*** Integer load and store multiple ***/
3075 /* lmw */
3076 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3077 {
3078 TCGv t0;
3079 TCGv_i32 t1;
3080 gen_set_access_type(ctx, ACCESS_INT);
3081 /* NIP cannot be restored if the memory exception comes from an helper */
3082 gen_update_nip(ctx, ctx->nip - 4);
3083 t0 = tcg_temp_new();
3084 t1 = tcg_const_i32(rD(ctx->opcode));
3085 gen_addr_imm_index(ctx, t0, 0);
3086 gen_helper_lmw(t0, t1);
3087 tcg_temp_free(t0);
3088 tcg_temp_free_i32(t1);
3089 }
3090
3091 /* stmw */
3092 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3093 {
3094 TCGv t0;
3095 TCGv_i32 t1;
3096 gen_set_access_type(ctx, ACCESS_INT);
3097 /* NIP cannot be restored if the memory exception comes from an helper */
3098 gen_update_nip(ctx, ctx->nip - 4);
3099 t0 = tcg_temp_new();
3100 t1 = tcg_const_i32(rS(ctx->opcode));
3101 gen_addr_imm_index(ctx, t0, 0);
3102 gen_helper_stmw(t0, t1);
3103 tcg_temp_free(t0);
3104 tcg_temp_free_i32(t1);
3105 }
3106
3107 /*** Integer load and store strings ***/
3108 /* lswi */
3109 /* PowerPC32 specification says we must generate an exception if
3110 * rA is in the range of registers to be loaded.
3111 * In an other hand, IBM says this is valid, but rA won't be loaded.
3112 * For now, I'll follow the spec...
3113 */
3114 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3115 {
3116 TCGv t0;
3117 TCGv_i32 t1, t2;
3118 int nb = NB(ctx->opcode);
3119 int start = rD(ctx->opcode);
3120 int ra = rA(ctx->opcode);
3121 int nr;
3122
3123 if (nb == 0)
3124 nb = 32;
3125 nr = nb / 4;
3126 if (unlikely(((start + nr) > 32 &&
3127 start <= ra && (start + nr - 32) > ra) ||
3128 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3129 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3130 return;
3131 }
3132 gen_set_access_type(ctx, ACCESS_INT);
3133 /* NIP cannot be restored if the memory exception comes from an helper */
3134 gen_update_nip(ctx, ctx->nip - 4);
3135 t0 = tcg_temp_new();
3136 gen_addr_register(ctx, t0);
3137 t1 = tcg_const_i32(nb);
3138 t2 = tcg_const_i32(start);
3139 gen_helper_lsw(t0, t1, t2);
3140 tcg_temp_free(t0);
3141 tcg_temp_free_i32(t1);
3142 tcg_temp_free_i32(t2);
3143 }
3144
3145 /* lswx */
3146 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3147 {
3148 TCGv t0;
3149 TCGv_i32 t1, t2, t3;
3150 gen_set_access_type(ctx, ACCESS_INT);
3151 /* NIP cannot be restored if the memory exception comes from an helper */
3152 gen_update_nip(ctx, ctx->nip - 4);
3153 t0 = tcg_temp_new();
3154 gen_addr_reg_index(ctx, t0);
3155 t1 = tcg_const_i32(rD(ctx->opcode));
3156 t2 = tcg_const_i32(rA(ctx->opcode));
3157 t3 = tcg_const_i32(rB(ctx->opcode));
3158 gen_helper_lswx(t0, t1, t2, t3);
3159 tcg_temp_free(t0);
3160 tcg_temp_free_i32(t1);
3161 tcg_temp_free_i32(t2);
3162 tcg_temp_free_i32(t3);
3163 }
3164
3165 /* stswi */
3166 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3167 {
3168 TCGv t0;
3169 TCGv_i32 t1, t2;
3170 int nb = NB(ctx->opcode);
3171 gen_set_access_type(ctx, ACCESS_INT);
3172 /* NIP cannot be restored if the memory exception comes from an helper */
3173 gen_update_nip(ctx, ctx->nip - 4);
3174 t0 = tcg_temp_new();
3175 gen_addr_register(ctx, t0);
3176 if (nb == 0)
3177 nb = 32;
3178 t1 = tcg_const_i32(nb);
3179 t2 = tcg_const_i32(rS(ctx->opcode));
3180 gen_helper_stsw(t0, t1, t2);
3181 tcg_temp_free(t0);
3182 tcg_temp_free_i32(t1);
3183 tcg_temp_free_i32(t2);
3184 }
3185
3186 /* stswx */
3187 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3188 {
3189 TCGv t0;
3190 TCGv_i32 t1, t2;
3191 gen_set_access_type(ctx, ACCESS_INT);
3192 /* NIP cannot be restored if the memory exception comes from an helper */
3193 gen_update_nip(ctx, ctx->nip - 4);
3194 t0 = tcg_temp_new();
3195 gen_addr_reg_index(ctx, t0);
3196 t1 = tcg_temp_new_i32();
3197 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3198 tcg_gen_andi_i32(t1, t1, 0x7F);
3199 t2 = tcg_const_i32(rS(ctx->opcode));
3200 gen_helper_stsw(t0, t1, t2);
3201 tcg_temp_free(t0);
3202 tcg_temp_free_i32(t1);
3203 tcg_temp_free_i32(t2);
3204 }
3205
3206 /*** Memory synchronisation ***/
3207 /* eieio */
3208 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3209 {
3210 }
3211
3212 /* isync */
3213 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3214 {
3215 gen_stop_exception(ctx);
3216 }
3217
3218 /* lwarx */
3219 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3220 {
3221 TCGv t0;
3222 gen_set_access_type(ctx, ACCESS_RES);
3223 t0 = tcg_temp_local_new();
3224 gen_addr_reg_index(ctx, t0);
3225 gen_check_align(ctx, t0, 0x03);
3226 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3227 tcg_gen_mov_tl(cpu_reserve, t0);
3228 tcg_temp_free(t0);
3229 }
3230
3231 /* stwcx. */
3232 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3233 {
3234 int l1;
3235 TCGv t0;
3236 gen_set_access_type(ctx, ACCESS_RES);
3237 t0 = tcg_temp_local_new();
3238 gen_addr_reg_index(ctx, t0);
3239 gen_check_align(ctx, t0, 0x03);
3240 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3241 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3242 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3243 l1 = gen_new_label();
3244 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3245 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3246 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3247 gen_set_label(l1);
3248 tcg_gen_movi_tl(cpu_reserve, -1);
3249 tcg_temp_free(t0);
3250 }
3251
3252 #if defined(TARGET_PPC64)
3253 /* ldarx */
3254 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3255 {
3256 TCGv t0;
3257 gen_set_access_type(ctx, ACCESS_RES);
3258 t0 = tcg_temp_local_new();
3259 gen_addr_reg_index(ctx, t0);
3260 gen_check_align(ctx, t0, 0x07);
3261 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3262 tcg_gen_mov_tl(cpu_reserve, t0);
3263 tcg_temp_free(t0);
3264 }
3265
3266 /* stdcx. */
3267 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3268 {
3269 int l1;
3270 TCGv t0;
3271 gen_set_access_type(ctx, ACCESS_RES);
3272 t0 = tcg_temp_local_new();
3273 gen_addr_reg_index(ctx, t0);
3274 gen_check_align(ctx, t0, 0x07);
3275 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3276 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3277 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3278 l1 = gen_new_label();
3279 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3280 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3281 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3282 gen_set_label(l1);
3283 tcg_gen_movi_tl(cpu_reserve, -1);
3284 tcg_temp_free(t0);
3285 }
3286 #endif /* defined(TARGET_PPC64) */
3287
3288 /* sync */
3289 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3290 {
3291 }
3292
3293 /* wait */
3294 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3295 {
3296 TCGv_i32 t0 = tcg_temp_new_i32();
3297 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3298 tcg_temp_free_i32(t0);
3299 /* Stop translation, as the CPU is supposed to sleep from now */
3300 gen_exception_err(ctx, EXCP_HLT, 1);
3301 }
3302
3303 /*** Floating-point load ***/
3304 #define GEN_LDF(name, ldop, opc, type) \
3305 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3306 { \
3307 TCGv EA; \
3308 if (unlikely(!ctx->fpu_enabled)) { \
3309 gen_exception(ctx, POWERPC_EXCP_FPU); \
3310 return; \
3311 } \
3312 gen_set_access_type(ctx, ACCESS_FLOAT); \
3313 EA = tcg_temp_new(); \
3314 gen_addr_imm_index(ctx, EA, 0); \
3315 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3316 tcg_temp_free(EA); \
3317 }
3318
3319 #define GEN_LDUF(name, ldop, opc, type) \
3320 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3321 { \
3322 TCGv EA; \
3323 if (unlikely(!ctx->fpu_enabled)) { \
3324 gen_exception(ctx, POWERPC_EXCP_FPU); \
3325 return; \
3326 } \
3327 if (unlikely(rA(ctx->opcode) == 0)) { \
3328 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3329 return; \
3330 } \
3331 gen_set_access_type(ctx, ACCESS_FLOAT); \
3332 EA = tcg_temp_new(); \
3333 gen_addr_imm_index(ctx, EA, 0); \
3334 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3335 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3336 tcg_temp_free(EA); \
3337 }
3338
3339 #define GEN_LDUXF(name, ldop, opc, type) \
3340 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3341 { \
3342 TCGv EA; \
3343 if (unlikely(!ctx->fpu_enabled)) { \
3344 gen_exception(ctx, POWERPC_EXCP_FPU); \
3345 return; \
3346 } \
3347 if (unlikely(rA(ctx->opcode) == 0)) { \
3348 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3349 return; \
3350 } \
3351 gen_set_access_type(ctx, ACCESS_FLOAT); \
3352 EA = tcg_temp_new(); \
3353 gen_addr_reg_index(ctx, EA); \
3354 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3355 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3356 tcg_temp_free(EA); \
3357 }
3358
3359 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3360 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3361 { \
3362 TCGv EA; \
3363 if (unlikely(!ctx->fpu_enabled)) { \
3364 gen_exception(ctx, POWERPC_EXCP_FPU); \
3365 return; \
3366 } \
3367 gen_set_access_type(ctx, ACCESS_FLOAT); \
3368 EA = tcg_temp_new(); \
3369 gen_addr_reg_index(ctx, EA); \
3370 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3371 tcg_temp_free(EA); \
3372 }
3373
3374 #define GEN_LDFS(name, ldop, op, type) \
3375 GEN_LDF(name, ldop, op | 0x20, type); \
3376 GEN_LDUF(name, ldop, op | 0x21, type); \
3377 GEN_LDUXF(name, ldop, op | 0x01, type); \
3378 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3379
3380 static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3381 {
3382 TCGv t0 = tcg_temp_new();
3383 TCGv_i32 t1 = tcg_temp_new_i32();
3384 gen_qemu_ld32u(ctx, t0, arg2);
3385 tcg_gen_trunc_tl_i32(t1, t0);
3386 tcg_temp_free(t0);
3387 gen_helper_float32_to_float64(arg1, t1);
3388 tcg_temp_free_i32(t1);
3389 }
3390
3391 /* lfd lfdu lfdux lfdx */
3392 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3393 /* lfs lfsu lfsux lfsx */
3394 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3395
3396 /*** Floating-point store ***/
3397 #define GEN_STF(name, stop, opc, type) \
3398 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3399 { \
3400 TCGv EA; \
3401 if (unlikely(!ctx->fpu_enabled)) { \
3402 gen_exception(ctx, POWERPC_EXCP_FPU); \
3403 return; \
3404 } \
3405 gen_set_access_type(ctx, ACCESS_FLOAT); \
3406 EA = tcg_temp_new(); \
3407 gen_addr_imm_index(ctx, EA, 0); \
3408 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3409 tcg_temp_free(EA); \
3410 }
3411
3412 #define GEN_STUF(name, stop, opc, type) \
3413 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3414 { \
3415 TCGv EA; \
3416 if (unlikely(!ctx->fpu_enabled)) { \
3417 gen_exception(ctx, POWERPC_EXCP_FPU); \
3418 return; \
3419 } \
3420 if (unlikely(rA(ctx->opcode) == 0)) { \
3421 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3422 return; \
3423 } \
3424 gen_set_access_type(ctx, ACCESS_FLOAT); \
3425 EA = tcg_temp_new(); \
3426 gen_addr_imm_index(ctx, EA, 0); \
3427 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3428 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3429 tcg_temp_free(EA); \
3430 }
3431
3432 #define GEN_STUXF(name, stop, opc, type) \
3433 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3434 { \
3435 TCGv EA; \
3436 if (unlikely(!ctx->fpu_enabled)) { \
3437 gen_exception(ctx, POWERPC_EXCP_FPU); \
3438 return; \
3439 } \
3440 if (unlikely(rA(ctx->opcode) == 0)) { \
3441 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3442 return; \
3443 } \
3444 gen_set_access_type(ctx, ACCESS_FLOAT); \
3445 EA = tcg_temp_new(); \
3446 gen_addr_reg_index(ctx, EA); \
3447 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3448 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3449 tcg_temp_free(EA); \
3450 }
3451
3452 #define GEN_STXF(name, stop, opc2, opc3, type) \
3453 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3454 { \
3455 TCGv EA; \
3456 if (unlikely(!ctx->fpu_enabled)) { \
3457 gen_exception(ctx, POWERPC_EXCP_FPU); \
3458 return; \
3459 } \
3460 gen_set_access_type(ctx, ACCESS_FLOAT); \
3461 EA = tcg_temp_new(); \
3462 gen_addr_reg_index(ctx, EA); \
3463 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3464 tcg_temp_free(EA); \
3465 }
3466
3467 #define GEN_STFS(name, stop, op, type) \
3468 GEN_STF(name, stop, op | 0x20, type); \
3469 GEN_STUF(name, stop, op | 0x21, type); \
3470 GEN_STUXF(name, stop, op | 0x01, type); \
3471 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3472
3473 static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3474 {
3475 TCGv_i32 t0 = tcg_temp_new_i32();
3476 TCGv t1 = tcg_temp_new();
3477 gen_helper_float64_to_float32(t0, arg1);
3478 tcg_gen_extu_i32_tl(t1, t0);
3479 tcg_temp_free_i32(t0);
3480 gen_qemu_st32(ctx, t1, arg2);
3481 tcg_temp_free(t1);
3482 }
3483
3484 /* stfd stfdu stfdux stfdx */
3485 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3486 /* stfs stfsu stfsux stfsx */
3487 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3488
3489 /* Optional: */
3490 static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3491 {
3492 TCGv t0 = tcg_temp_new();
3493 tcg_gen_trunc_i64_tl(t0, arg1),
3494 gen_qemu_st32(ctx, t0, arg2);
3495 tcg_temp_free(t0);
3496 }
3497 /* stfiwx */
3498 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3499
3500 /*** Branch ***/
3501 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3502 target_ulong dest)
3503 {
3504 TranslationBlock *tb;
3505 tb = ctx->tb;
3506 #if defined(TARGET_PPC64)
3507 if (!ctx->sf_mode)
3508 dest = (uint32_t) dest;
3509 #endif
3510 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3511 likely(!ctx->singlestep_enabled)) {
3512 tcg_gen_goto_tb(n);
3513 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3514 tcg_gen_exit_tb((long)tb + n);
3515 } else {
3516 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3517 if (unlikely(ctx->singlestep_enabled)) {
3518 if ((ctx->singlestep_enabled &
3519 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3520 ctx->exception == POWERPC_EXCP_BRANCH) {
3521 target_ulong tmp = ctx->nip;
3522 ctx->nip = dest;
3523 gen_exception(ctx, POWERPC_EXCP_TRACE);
3524 ctx->nip = tmp;
3525 }
3526 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3527 gen_debug_exception(ctx);
3528 }
3529 }
3530 tcg_gen_exit_tb(0);
3531 }
3532 }
3533
3534 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3535 {
3536 #if defined(TARGET_PPC64)
3537 if (ctx->sf_mode == 0)
3538 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3539 else
3540 #endif
3541 tcg_gen_movi_tl(cpu_lr, nip);
3542 }
3543
3544 /* b ba bl bla */
3545 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3546 {
3547 target_ulong li, target;
3548
3549 ctx->exception = POWERPC_EXCP_BRANCH;
3550 /* sign extend LI */
3551 #if defined(TARGET_PPC64)
3552 if (ctx->sf_mode)
3553 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3554 else
3555 #endif
3556 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3557 if (likely(AA(ctx->opcode) == 0))
3558 target = ctx->nip + li - 4;
3559 else
3560 target = li;
3561 if (LK(ctx->opcode))
3562 gen_setlr(ctx, ctx->nip);
3563 gen_goto_tb(ctx, 0, target);
3564 }
3565
3566 #define BCOND_IM 0
3567 #define BCOND_LR 1
3568 #define BCOND_CTR 2
3569
3570 static always_inline void gen_bcond (DisasContext *ctx, int type)
3571 {
3572 uint32_t bo = BO(ctx->opcode);
3573 int l1 = gen_new_label();
3574 TCGv target;
3575
3576 ctx->exception = POWERPC_EXCP_BRANCH;
3577 if (type == BCOND_LR || type == BCOND_CTR) {
3578 target = tcg_temp_local_new();
3579 if (type == BCOND_CTR)
3580 tcg_gen_mov_tl(target, cpu_ctr);
3581 else
3582 tcg_gen_mov_tl(target, cpu_lr);
3583 }
3584 if (LK(ctx->opcode))
3585 gen_setlr(ctx, ctx->nip);
3586 l1 = gen_new_label();
3587 if ((bo & 0x4) == 0) {
3588 /* Decrement and test CTR */
3589 TCGv temp = tcg_temp_new();
3590 if (unlikely(type == BCOND_CTR)) {
3591 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3592 return;
3593 }
3594 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3595 #if defined(TARGET_PPC64)
3596 if (!ctx->sf_mode)
3597 tcg_gen_ext32u_tl(temp, cpu_ctr);
3598 else
3599 #endif
3600 tcg_gen_mov_tl(temp, cpu_ctr);
3601 if (bo & 0x2) {
3602 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3603 } else {
3604 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3605 }
3606 tcg_temp_free(temp);
3607 }
3608 if ((bo & 0x10) == 0) {
3609 /* Test CR */
3610 uint32_t bi = BI(ctx->opcode);
3611 uint32_t mask = 1 << (3 - (bi & 0x03));
3612 TCGv_i32 temp = tcg_temp_new_i32();
3613
3614 if (bo & 0x8) {
3615 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3616 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3617 } else {
3618 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3619 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3620 }
3621 tcg_temp_free_i32(temp);
3622 }
3623 if (type == BCOND_IM) {
3624 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3625 if (likely(AA(ctx->opcode) == 0)) {
3626 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3627 } else {
3628 gen_goto_tb(ctx, 0, li);
3629 }
3630 gen_set_label(l1);
3631 gen_goto_tb(ctx, 1, ctx->nip);
3632 } else {
3633 #if defined(TARGET_PPC64)
3634 if (!(ctx->sf_mode))
3635 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3636 else
3637 #endif
3638 tcg_gen_andi_tl(cpu_nip, target, ~3);
3639 tcg_gen_exit_tb(0);
3640 gen_set_label(l1);
3641 #if defined(TARGET_PPC64)
3642 if (!(ctx->sf_mode))
3643 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3644 else
3645 #endif
3646 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3647 tcg_gen_exit_tb(0);
3648 }
3649 }
3650
3651 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3652 {
3653 gen_bcond(ctx, BCOND_IM);
3654 }
3655
3656 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3657 {
3658 gen_bcond(ctx, BCOND_CTR);
3659 }
3660
3661 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3662 {
3663 gen_bcond(ctx, BCOND_LR);
3664 }
3665
3666 /*** Condition register logical ***/
3667 #define GEN_CRLOGIC(name, tcg_op, opc) \
3668 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3669 { \
3670 uint8_t bitmask; \
3671 int sh; \
3672 TCGv_i32 t0, t1; \
3673 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3674 t0 = tcg_temp_new_i32(); \
3675 if (sh > 0) \
3676 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3677 else if (sh < 0) \
3678 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3679 else \
3680 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3681 t1 = tcg_temp_new_i32(); \
3682 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3683 if (sh > 0) \
3684 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3685 else if (sh < 0) \
3686 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3687 else \
3688 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3689 tcg_op(t0, t0, t1); \
3690 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3691 tcg_gen_andi_i32(t0, t0, bitmask); \
3692 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3693 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3694 tcg_temp_free_i32(t0); \
3695 tcg_temp_free_i32(t1); \
3696 }
3697
3698 /* crand */
3699 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3700 /* crandc */
3701 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3702 /* creqv */
3703 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3704 /* crnand */
3705 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3706 /* crnor */
3707 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3708 /* cror */
3709 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3710 /* crorc */
3711 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3712 /* crxor */
3713 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3714 /* mcrf */
3715 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3716 {
3717 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3718 }
3719
3720 /*** System linkage ***/
3721 /* rfi (mem_idx only) */
3722 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3723 {
3724 #if defined(CONFIG_USER_ONLY)
3725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3726 #else
3727 /* Restore CPU state */
3728 if (unlikely(!ctx->mem_idx)) {
3729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3730 return;
3731 }
3732 gen_helper_rfi();
3733 gen_sync_exception(ctx);
3734 #endif
3735 }
3736
3737 #if defined(TARGET_PPC64)
3738 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3739 {
3740 #if defined(CONFIG_USER_ONLY)
3741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3742 #else
3743 /* Restore CPU state */
3744 if (unlikely(!ctx->mem_idx)) {
3745 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3746 return;
3747 }
3748 gen_helper_rfid();
3749 gen_sync_exception(ctx);
3750 #endif
3751 }
3752
3753 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3754 {
3755 #if defined(CONFIG_USER_ONLY)
3756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3757 #else
3758 /* Restore CPU state */
3759 if (unlikely(ctx->mem_idx <= 1)) {
3760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3761 return;
3762 }
3763 gen_helper_hrfid();
3764 gen_sync_exception(ctx);
3765 #endif
3766 }
3767 #endif
3768
3769 /* sc */
3770 #if defined(CONFIG_USER_ONLY)
3771 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3772 #else
3773 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3774 #endif
3775 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3776 {
3777 uint32_t lev;
3778
3779 lev = (ctx->opcode >> 5) & 0x7F;
3780 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3781 }
3782
3783 /*** Trap ***/
3784 /* tw */
3785 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3786 {
3787 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3788 /* Update the nip since this might generate a trap exception */
3789 gen_update_nip(ctx, ctx->nip);
3790 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3791 tcg_temp_free_i32(t0);
3792 }
3793
3794 /* twi */
3795 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3796 {
3797 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3798 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3799 /* Update the nip since this might generate a trap exception */
3800 gen_update_nip(ctx, ctx->nip);
3801 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3802 tcg_temp_free(t0);
3803 tcg_temp_free_i32(t1);
3804 }
3805
3806 #if defined(TARGET_PPC64)
3807 /* td */
3808 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3809 {
3810 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3811 /* Update the nip since this might generate a trap exception */
3812 gen_update_nip(ctx, ctx->nip);
3813 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3814 tcg_temp_free_i32(t0);
3815 }
3816
3817 /* tdi */
3818 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3819 {
3820 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3821 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3822 /* Update the nip since this might generate a trap exception */
3823 gen_update_nip(ctx, ctx->nip);
3824 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3825 tcg_temp_free(t0);
3826 tcg_temp_free_i32(t1);
3827 }
3828 #endif
3829
3830 /*** Processor control ***/
3831 /* mcrxr */
3832 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3833 {
3834 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3835 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3836 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3837 }
3838
3839 /* mfcr */
3840 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3841 {
3842 uint32_t crm, crn;
3843
3844 if (likely(ctx->opcode & 0x00100000)) {
3845 crm = CRM(ctx->opcode);
3846 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3847 crn = ffs (crm) - 1;
3848 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3849 tcg_gen_shli_i32(cpu_gpr[rD(ctx->opcode)],
3850 cpu_gpr[rD(ctx->opcode)], crn * 4);
3851 }
3852 } else {
3853 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3854 }
3855 }
3856
3857 /* mfmsr */
3858 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3859 {
3860 #if defined(CONFIG_USER_ONLY)
3861 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3862 #else
3863 if (unlikely(!ctx->mem_idx)) {
3864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3865 return;
3866 }
3867 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3868 #endif
3869 }
3870
3871 #if 1
3872 #define SPR_NOACCESS ((void *)(-1UL))
3873 #else
3874 static void spr_noaccess (void *opaque, int sprn)
3875 {
3876 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3877 printf("ERROR: try to access SPR %d !\n", sprn);
3878 }
3879 #define SPR_NOACCESS (&spr_noaccess)
3880 #endif
3881
3882 /* mfspr */
3883 static always_inline void gen_op_mfspr (DisasContext *ctx)
3884 {
3885 void (*read_cb)(void *opaque, int gprn, int sprn);
3886 uint32_t sprn = SPR(ctx->opcode);
3887
3888 #if !defined(CONFIG_USER_ONLY)
3889 if (ctx->mem_idx == 2)
3890 read_cb = ctx->spr_cb[sprn].hea_read;
3891 else if (ctx->mem_idx)
3892 read_cb = ctx->spr_cb[sprn].oea_read;
3893 else
3894 #endif
3895 read_cb = ctx->spr_cb[sprn].uea_read;
3896 if (likely(read_cb != NULL)) {
3897 if (likely(read_cb != SPR_NOACCESS)) {
3898 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3899 } else {
3900 /* Privilege exception */
3901 /* This is a hack to avoid warnings when running Linux:
3902 * this OS breaks the PowerPC virtualisation model,
3903 * allowing userland application to read the PVR
3904 */
3905 if (sprn != SPR_PVR) {
3906 qemu_log("Trying to read privileged spr %d %03x at "
3907 ADDRX "\n", sprn, sprn, ctx->nip);
3908 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3909 sprn, sprn, ctx->nip);
3910 }
3911 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3912 }
3913 } else {
3914 /* Not defined */
3915 qemu_log("Trying to read invalid spr %d %03x at "
3916 ADDRX "\n", sprn, sprn, ctx->nip);
3917 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3918 sprn, sprn, ctx->nip);
3919 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3920 }
3921 }
3922
3923 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3924 {
3925 gen_op_mfspr(ctx);
3926 }
3927
3928 /* mftb */
3929 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3930 {
3931 gen_op_mfspr(ctx);
3932 }
3933
3934 /* mtcrf */
3935 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3936 {
3937 uint32_t crm, crn;
3938
3939 crm = CRM(ctx->opcode);
3940 if (likely((ctx->opcode & 0x00100000))) {
3941 if (crm && ((crm & (crm - 1)) == 0)) {
3942 TCGv_i32 temp = tcg_temp_new_i32();
3943 crn = ffs (crm) - 1;
3944 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3945 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3946 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3947 tcg_temp_free_i32(temp);
3948 }
3949 } else {
3950 TCGv_i32 temp = tcg_const_i32(crm);
3951 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3952 tcg_temp_free_i32(temp);
3953 }
3954 }
3955
3956 /* mtmsr */
3957 #if defined(TARGET_PPC64)
3958 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3959 {
3960 #if defined(CONFIG_USER_ONLY)
3961 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3962 #else
3963 if (unlikely(!ctx->mem_idx)) {
3964 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3965 return;
3966 }
3967 if (ctx->opcode & 0x00010000) {
3968 /* Special form that does not need any synchronisation */
3969 TCGv t0 = tcg_temp_new();
3970 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3971 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3972 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3973 tcg_temp_free(t0);
3974 } else {
3975 /* XXX: we need to update nip before the store
3976 * if we enter power saving mode, we will exit the loop
3977 * directly from ppc_store_msr
3978 */
3979 gen_update_nip(ctx, ctx->nip);
3980 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3981 /* Must stop the translation as machine state (may have) changed */
3982 /* Note that mtmsr is not always defined as context-synchronizing */
3983 gen_stop_exception(ctx);
3984 }
3985 #endif
3986 }
3987 #endif
3988
3989 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3990 {
3991 #if defined(CONFIG_USER_ONLY)
3992 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3993 #else
3994 if (unlikely(!ctx->mem_idx)) {
3995 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3996 return;
3997 }
3998 if (ctx->opcode & 0x00010000) {
3999 /* Special form that does not need any synchronisation */
4000 TCGv t0 = tcg_temp_new();
4001 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4002 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4003 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4004 tcg_temp_free(t0);
4005 } else {
4006 /* XXX: we need to update nip before the store
4007 * if we enter power saving mode, we will exit the loop
4008 * directly from ppc_store_msr
4009 */
4010 gen_update_nip(ctx, ctx->nip);
4011 #if defined(TARGET_PPC64)
4012 if (!ctx->sf_mode) {
4013 TCGv t0 = tcg_temp_new();
4014 TCGv t1 = tcg_temp_new();
4015 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4016 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4017 tcg_gen_or_tl(t0, t0, t1);
4018 tcg_temp_free(t1);
4019 gen_helper_store_msr(t0);
4020 tcg_temp_free(t0);
4021 } else
4022 #endif
4023 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
4024 /* Must stop the translation as machine state (may have) changed */
4025 /* Note that mtmsr is not always defined as context-synchronizing */
4026 gen_stop_exception(ctx);
4027 }
4028 #endif
4029 }
4030
4031 /* mtspr */
4032 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4033 {
4034 void (*write_cb)(void *opaque, int sprn, int gprn);
4035 uint32_t sprn = SPR(ctx->opcode);
4036
4037 #if !defined(CONFIG_USER_ONLY)
4038 if (ctx->mem_idx == 2)
4039 write_cb = ctx->spr_cb[sprn].hea_write;
4040 else if (ctx->mem_idx)
4041 write_cb = ctx->spr_cb[sprn].oea_write;
4042 else
4043 #endif
4044 write_cb = ctx->spr_cb[sprn].uea_write;
4045 if (likely(write_cb != NULL)) {
4046 if (likely(write_cb != SPR_NOACCESS)) {
4047 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4048 } else {
4049 /* Privilege exception */
4050 qemu_log("Trying to write privileged spr %d %03x at "
4051 ADDRX "\n", sprn, sprn, ctx->nip);
4052 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4053 sprn, sprn, ctx->nip);
4054 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4055 }
4056 } else {
4057 /* Not defined */
4058 qemu_log("Trying to write invalid spr %d %03x at "
4059 ADDRX "\n", sprn, sprn, ctx->nip);
4060 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4061 sprn, sprn, ctx->nip);
4062 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4063 }
4064 }
4065
4066 /*** Cache management ***/
4067 /* dcbf */
4068 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4069 {
4070 /* XXX: specification says this is treated as a load by the MMU */
4071 TCGv t0;
4072 gen_set_access_type(ctx, ACCESS_CACHE);
4073 t0 = tcg_temp_new();
4074 gen_addr_reg_index(ctx, t0);
4075 gen_qemu_ld8u(ctx, t0, t0);
4076 tcg_temp_free(t0);
4077 }
4078
4079 /* dcbi (Supervisor only) */
4080 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4081 {
4082 #if defined(CONFIG_USER_ONLY)
4083 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4084 #else
4085 TCGv EA, val;
4086 if (unlikely(!ctx->mem_idx)) {
4087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4088 return;
4089 }
4090 EA = tcg_temp_new();
4091 gen_set_access_type(ctx, ACCESS_CACHE);
4092 gen_addr_reg_index(ctx, EA);
4093 val = tcg_temp_new();
4094 /* XXX: specification says this should be treated as a store by the MMU */
4095 gen_qemu_ld8u(ctx, val, EA);
4096 gen_qemu_st8(ctx, val, EA);
4097 tcg_temp_free(val);
4098 tcg_temp_free(EA);
4099 #endif
4100 }
4101
4102 /* dcdst */
4103 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4104 {
4105 /* XXX: specification say this is treated as a load by the MMU */
4106 TCGv t0;
4107 gen_set_access_type(ctx, ACCESS_CACHE);
4108 t0 = tcg_temp_new();
4109 gen_addr_reg_index(ctx, t0);
4110 gen_qemu_ld8u(ctx, t0, t0);
4111 tcg_temp_free(t0);
4112 }
4113
4114 /* dcbt */
4115 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4116 {
4117 /* interpreted as no-op */
4118 /* XXX: specification say this is treated as a load by the MMU
4119 * but does not generate any exception
4120 */
4121 }
4122
4123 /* dcbtst */
4124 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4125 {
4126 /* interpreted as no-op */
4127 /* XXX: specification say this is treated as a load by the MMU
4128 * but does not generate any exception
4129 */
4130 }
4131
4132 /* dcbz */
4133 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4134 {
4135 TCGv t0;
4136 gen_set_access_type(ctx, ACCESS_CACHE);
4137 /* NIP cannot be restored if the memory exception comes from an helper */
4138 gen_update_nip(ctx, ctx->nip - 4);
4139 t0 = tcg_temp_new();
4140 gen_addr_reg_index(ctx, t0);
4141 gen_helper_dcbz(t0);
4142 tcg_temp_free(t0);
4143 }
4144
4145 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4146 {
4147 TCGv t0;
4148 gen_set_access_type(ctx, ACCESS_CACHE);
4149 /* NIP cannot be restored if the memory exception comes from an helper */
4150 gen_update_nip(ctx, ctx->nip - 4);
4151 t0 = tcg_temp_new();
4152 gen_addr_reg_index(ctx, t0);
4153 if (ctx->opcode & 0x00200000)
4154 gen_helper_dcbz(t0);
4155 else
4156 gen_helper_dcbz_970(t0);
4157 tcg_temp_free(t0);
4158 }
4159
4160 /* dst / dstt */
4161 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4162 {
4163 if (rA(ctx->opcode) == 0) {
4164 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4165 } else {
4166 /* interpreted as no-op */
4167 }
4168 }
4169
4170 /* dstst /dststt */
4171 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4172 {
4173 if (rA(ctx->opcode) == 0) {
4174 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4175 } else {
4176 /* interpreted as no-op */
4177 }
4178
4179 }
4180
4181 /* dss / dssall */
4182 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4183 {
4184 /* interpreted as no-op */
4185 }
4186
4187 /* icbi */
4188 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4189 {
4190 TCGv t0;
4191 gen_set_access_type(ctx, ACCESS_CACHE);
4192 /* NIP cannot be restored if the memory exception comes from an helper */
4193 gen_update_nip(ctx, ctx->nip - 4);
4194 t0 = tcg_temp_new();
4195 gen_addr_reg_index(ctx, t0);
4196 gen_helper_icbi(t0);
4197 tcg_temp_free(t0);
4198 }
4199
4200 /* Optional: */
4201 /* dcba */
4202 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4203 {
4204 /* interpreted as no-op */
4205 /* XXX: specification say this is treated as a store by the MMU
4206 * but does not generate any exception
4207 */
4208 }
4209
4210 /*** Segment register manipulation ***/
4211 /* Supervisor only: */
4212 /* mfsr */
4213 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4214 {
4215 #if defined(CONFIG_USER_ONLY)
4216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4217 #else
4218 TCGv t0;
4219 if (unlikely(!ctx->mem_idx)) {
4220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4221 return;
4222 }
4223 t0 = tcg_const_tl(SR(ctx->opcode));
4224 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4225 tcg_temp_free(t0);
4226 #endif
4227 }
4228
4229 /* mfsrin */
4230 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4231 {
4232 #if defined(CONFIG_USER_ONLY)
4233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4234 #else
4235 TCGv t0;
4236 if (unlikely(!ctx->mem_idx)) {
4237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4238 return;
4239 }
4240 t0 = tcg_temp_new();
4241 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4242 tcg_gen_andi_tl(t0, t0, 0xF);
4243 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4244 tcg_temp_free(t0);
4245 #endif
4246 }
4247
4248 /* mtsr */
4249 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4250 {
4251 #if defined(CONFIG_USER_ONLY)
4252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4253 #else
4254 TCGv t0;
4255 if (unlikely(!ctx->mem_idx)) {
4256 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4257 return;
4258 }
4259 t0 = tcg_const_tl(SR(ctx->opcode));
4260 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4261 tcg_temp_free(t0);
4262 #endif
4263 }
4264
4265 /* mtsrin */
4266 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4267 {
4268 #if defined(CONFIG_USER_ONLY)
4269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4270 #else
4271 TCGv t0;
4272 if (unlikely(!ctx->mem_idx)) {
4273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4274 return;
4275 }
4276 t0 = tcg_temp_new();
4277 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4278 tcg_gen_andi_tl(t0, t0, 0xF);
4279 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4280 tcg_temp_free(t0);
4281 #endif
4282 }
4283
4284 #if defined(TARGET_PPC64)
4285 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4286 /* mfsr */
4287 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4288 {
4289 #if defined(CONFIG_USER_ONLY)
4290 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4291 #else
4292 TCGv t0;
4293 if (unlikely(!ctx->mem_idx)) {
4294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4295 return;
4296 }
4297 t0 = tcg_const_tl(SR(ctx->opcode));
4298 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4299 tcg_temp_free(t0);
4300 #endif
4301 }
4302
4303 /* mfsrin */
4304 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4305 PPC_SEGMENT_64B)
4306 {
4307 #if defined(CONFIG_USER_ONLY)
4308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4309 #else
4310 TCGv t0;
4311 if (unlikely(!ctx->mem_idx)) {
4312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4313 return;
4314 }
4315 t0 = tcg_temp_new();
4316 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4317 tcg_gen_andi_tl(t0, t0, 0xF);
4318 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4319 tcg_temp_free(t0);
4320 #endif
4321 }
4322
4323 /* mtsr */
4324 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4325 {
4326 #if defined(CONFIG_USER_ONLY)
4327 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4328 #else
4329 TCGv t0;
4330 if (unlikely(!ctx->mem_idx)) {
4331 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4332 return;
4333 }
4334 t0 = tcg_const_tl(SR(ctx->opcode));
4335 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4336 tcg_temp_free(t0);
4337 #endif
4338 }
4339
4340 /* mtsrin */
4341 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4342 PPC_SEGMENT_64B)
4343 {
4344 #if defined(CONFIG_USER_ONLY)
4345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4346 #else
4347 TCGv t0;
4348 if (unlikely(!ctx->mem_idx)) {
4349 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4350 return;
4351 }
4352 t0 = tcg_temp_new();
4353 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4354 tcg_gen_andi_tl(t0, t0, 0xF);
4355 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4356 tcg_temp_free(t0);
4357 #endif
4358 }
4359 #endif /* defined(TARGET_PPC64) */
4360
4361 /*** Lookaside buffer management ***/
4362 /* Optional & mem_idx only: */
4363 /* tlbia */
4364 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4365 {
4366 #if defined(CONFIG_USER_ONLY)
4367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4368 #else
4369 if (unlikely(!ctx->mem_idx)) {
4370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4371 return;
4372 }
4373 gen_helper_tlbia();
4374 #endif
4375 }
4376
4377 /* tlbie */
4378 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4379 {
4380 #if defined(CONFIG_USER_ONLY)
4381 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4382 #else
4383 if (unlikely(!ctx->mem_idx)) {
4384 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4385 return;
4386 }
4387 #if defined(TARGET_PPC64)
4388 if (!ctx->sf_mode) {
4389 TCGv t0 = tcg_temp_new();
4390 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4391 gen_helper_tlbie(t0);
4392 tcg_temp_free(t0);
4393 } else
4394 #endif
4395 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4396 #endif
4397 }
4398
4399 /* tlbsync */
4400 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4401 {
4402 #if defined(CONFIG_USER_ONLY)
4403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4404 #else
4405 if (unlikely(!ctx->mem_idx)) {
4406 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4407 return;
4408 }
4409 /* This has no effect: it should ensure that all previous
4410 * tlbie have completed
4411 */
4412 gen_stop_exception(ctx);
4413 #endif
4414 }
4415
4416 #if defined(TARGET_PPC64)
4417 /* slbia */
4418 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4419 {
4420 #if defined(CONFIG_USER_ONLY)
4421 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4422 #else
4423 if (unlikely(!ctx->mem_idx)) {
4424 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4425 return;
4426 }
4427 gen_helper_slbia();
4428 #endif
4429 }
4430
4431 /* slbie */
4432 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4433 {
4434 #if defined(CONFIG_USER_ONLY)
4435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4436 #else
4437 if (unlikely(!ctx->mem_idx)) {
4438 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4439 return;
4440 }
4441 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4442 #endif
4443 }
4444 #endif
4445
4446 /*** External control ***/
4447 /* Optional: */
4448 /* eciwx */
4449 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4450 {
4451 TCGv t0;
4452 /* Should check EAR[E] ! */
4453 gen_set_access_type(ctx, ACCESS_EXT);
4454 t0 = tcg_temp_new();
4455 gen_addr_reg_index(ctx, t0);
4456 gen_check_align(ctx, t0, 0x03);
4457 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4458 tcg_temp_free(t0);
4459 }
4460
4461 /* ecowx */
4462 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4463 {
4464 TCGv t0;
4465 /* Should check EAR[E] ! */
4466 gen_set_access_type(ctx, ACCESS_EXT);
4467 t0 = tcg_temp_new();
4468 gen_addr_reg_index(ctx, t0);
4469 gen_check_align(ctx, t0, 0x03);
4470 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4471 tcg_temp_free(t0);
4472 }
4473
4474 /* PowerPC 601 specific instructions */
4475 /* abs - abs. */
4476 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4477 {
4478 int l1 = gen_new_label();
4479 int l2 = gen_new_label();
4480 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4481 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4482 tcg_gen_br(l2);
4483 gen_set_label(l1);
4484 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4485 gen_set_label(l2);
4486 if (unlikely(Rc(ctx->opcode) != 0))
4487 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4488 }
4489
4490 /* abso - abso. */
4491 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4492 {
4493 int l1 = gen_new_label();
4494 int l2 = gen_new_label();
4495 int l3 = gen_new_label();
4496 /* Start with XER OV disabled, the most likely case */
4497 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4498 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4499 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4500 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4501 tcg_gen_br(l2);
4502 gen_set_label(l1);
4503 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4504 tcg_gen_br(l3);
4505 gen_set_label(l2);
4506 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4507 gen_set_label(l3);
4508 if (unlikely(Rc(ctx->opcode) != 0))
4509 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4510 }
4511
4512 /* clcs */
4513 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4514 {
4515 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4516 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4517 tcg_temp_free_i32(t0);
4518 /* Rc=1 sets CR0 to an undefined state */
4519 }
4520
4521 /* div - div. */
4522 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4523 {
4524 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4525 if (unlikely(Rc(ctx->opcode) != 0))
4526 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4527 }
4528
4529 /* divo - divo. */
4530 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4531 {
4532 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4533 if (unlikely(Rc(ctx->opcode) != 0))
4534 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4535 }
4536
4537 /* divs - divs. */
4538 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4539 {
4540 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4541 if (unlikely(Rc(ctx->opcode) != 0))
4542 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4543 }
4544
4545 /* divso - divso. */
4546 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4547 {
4548 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4549 if (unlikely(Rc(ctx->opcode) != 0))
4550 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4551 }
4552
4553 /* doz - doz. */
4554 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4555 {
4556 int l1 = gen_new_label();
4557 int l2 = gen_new_label();
4558 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4559 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4560 tcg_gen_br(l2);
4561 gen_set_label(l1);
4562 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4563 gen_set_label(l2);
4564 if (unlikely(Rc(ctx->opcode) != 0))
4565 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4566 }
4567
4568 /* dozo - dozo. */
4569 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4570 {
4571 int l1 = gen_new_label();
4572 int l2 = gen_new_label();
4573 TCGv t0 = tcg_temp_new();
4574 TCGv t1 = tcg_temp_new();
4575 TCGv t2 = tcg_temp_new();
4576 /* Start with XER OV disabled, the most likely case */
4577 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4578 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4579 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4580 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4581 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4582 tcg_gen_andc_tl(t1, t1, t2);
4583 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4584 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4585 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4586 tcg_gen_br(l2);
4587 gen_set_label(l1);
4588 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4589 gen_set_label(l2);
4590 tcg_temp_free(t0);
4591 tcg_temp_free(t1);
4592 tcg_temp_free(t2);
4593 if (unlikely(Rc(ctx->opcode) != 0))
4594 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4595 }
4596
4597 /* dozi */
4598 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4599 {
4600 target_long simm = SIMM(ctx->opcode);
4601 int l1 = gen_new_label();
4602 int l2 = gen_new_label();
4603 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4604 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4605 tcg_gen_br(l2);
4606 gen_set_label(l1);
4607 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4608 gen_set_label(l2);
4609 if (unlikely(Rc(ctx->opcode) != 0))
4610 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4611 }
4612
4613 /* lscbx - lscbx. */
4614 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4615 {
4616 TCGv t0 = tcg_temp_new();
4617 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4618 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4619 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4620
4621 gen_addr_reg_index(ctx, t0);
4622 /* NIP cannot be restored if the memory exception comes from an helper */
4623 gen_update_nip(ctx, ctx->nip - 4);
4624 gen_helper_lscbx(t0, t0, t1, t2, t3);
4625 tcg_temp_free_i32(t1);
4626 tcg_temp_free_i32(t2);
4627 tcg_temp_free_i32(t3);
4628 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4629 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4630 if (unlikely(Rc(ctx->opcode) != 0))
4631 gen_set_Rc0(ctx, t0);
4632 tcg_temp_free(t0);
4633 }
4634
4635 /* maskg - maskg. */
4636 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4637 {
4638 int l1 = gen_new_label();
4639 TCGv t0 = tcg_temp_new();
4640 TCGv t1 = tcg_temp_new();
4641 TCGv t2 = tcg_temp_new();
4642 TCGv t3 = tcg_temp_new();
4643 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4644 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4645 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4646 tcg_gen_addi_tl(t2, t0, 1);
4647 tcg_gen_shr_tl(t2, t3, t2);
4648 tcg_gen_shr_tl(t3, t3, t1);
4649 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4650 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4651 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4652 gen_set_label(l1);
4653 tcg_temp_free(t0);
4654 tcg_temp_free(t1);
4655 tcg_temp_free(t2);
4656 tcg_temp_free(t3);
4657 if (unlikely(Rc(ctx->opcode) != 0))
4658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4659 }
4660
4661 /* maskir - maskir. */
4662 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4663 {
4664 TCGv t0 = tcg_temp_new();
4665 TCGv t1 = tcg_temp_new();
4666 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4667 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4668 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4669 tcg_temp_free(t0);
4670 tcg_temp_free(t1);
4671 if (unlikely(Rc(ctx->opcode) != 0))
4672 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4673 }
4674
4675 /* mul - mul. */
4676 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4677 {
4678 TCGv_i64 t0 = tcg_temp_new_i64();
4679 TCGv_i64 t1 = tcg_temp_new_i64();
4680 TCGv t2 = tcg_temp_new();
4681 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4682 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4683 tcg_gen_mul_i64(t0, t0, t1);
4684 tcg_gen_trunc_i64_tl(t2, t0);
4685 gen_store_spr(SPR_MQ, t2);
4686 tcg_gen_shri_i64(t1, t0, 32);
4687 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4688 tcg_temp_free_i64(t0);
4689 tcg_temp_free_i64(t1);
4690 tcg_temp_free(t2);
4691 if (unlikely(Rc(ctx->opcode) != 0))
4692 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4693 }
4694
4695 /* mulo - mulo. */
4696 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4697 {
4698 int l1 = gen_new_label();
4699 TCGv_i64 t0 = tcg_temp_new_i64();
4700 TCGv_i64 t1 = tcg_temp_new_i64();
4701 TCGv t2 = tcg_temp_new();
4702 /* Start with XER OV disabled, the most likely case */
4703 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4704 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4705 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4706 tcg_gen_mul_i64(t0, t0, t1);
4707 tcg_gen_trunc_i64_tl(t2, t0);
4708 gen_store_spr(SPR_MQ, t2);
4709 tcg_gen_shri_i64(t1, t0, 32);
4710 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4711 tcg_gen_ext32s_i64(t1, t0);
4712 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4713 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4714 gen_set_label(l1);
4715 tcg_temp_free_i64(t0);
4716 tcg_temp_free_i64(t1);
4717 tcg_temp_free(t2);
4718 if (unlikely(Rc(ctx->opcode) != 0))
4719 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4720 }
4721
4722 /* nabs - nabs. */
4723 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4724 {
4725 int l1 = gen_new_label();
4726 int l2 = gen_new_label();
4727 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4728 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4729 tcg_gen_br(l2);
4730 gen_set_label(l1);
4731 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4732 gen_set_label(l2);
4733 if (unlikely(Rc(ctx->opcode) != 0))
4734 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4735 }
4736
4737 /* nabso - nabso. */
4738 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4739 {
4740 int l1 = gen_new_label();
4741 int l2 = gen_new_label();
4742 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4743 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4744 tcg_gen_br(l2);
4745 gen_set_label(l1);
4746 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4747 gen_set_label(l2);
4748 /* nabs never overflows */
4749 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4750 if (unlikely(Rc(ctx->opcode) != 0))
4751 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4752 }
4753
4754 /* rlmi - rlmi. */
4755 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4756 {
4757 uint32_t mb = MB(ctx->opcode);
4758 uint32_t me = ME(ctx->opcode);
4759 TCGv t0 = tcg_temp_new();
4760 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4761 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4762 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4763 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4764 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4765 tcg_temp_free(t0);
4766 if (unlikely(Rc(ctx->opcode) != 0))
4767 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4768 }
4769
4770 /* rrib - rrib. */
4771 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4772 {
4773 TCGv t0 = tcg_temp_new();
4774 TCGv t1 = tcg_temp_new();
4775 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4776 tcg_gen_movi_tl(t1, 0x80000000);
4777 tcg_gen_shr_tl(t1, t1, t0);
4778 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4779 tcg_gen_and_tl(t0, t0, t1);
4780 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4781 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4782 tcg_temp_free(t0);
4783 tcg_temp_free(t1);
4784 if (unlikely(Rc(ctx->opcode) != 0))
4785 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4786 }
4787
4788 /* sle - sle. */
4789 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4790 {
4791 TCGv t0 = tcg_temp_new();
4792 TCGv t1 = tcg_temp_new();
4793 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4794 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4795 tcg_gen_subfi_tl(t1, 32, t1);
4796 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4797 tcg_gen_or_tl(t1, t0, t1);
4798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4799 gen_store_spr(SPR_MQ, t1);
4800 tcg_temp_free(t0);
4801 tcg_temp_free(t1);
4802 if (unlikely(Rc(ctx->opcode) != 0))
4803 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4804 }
4805
4806 /* sleq - sleq. */
4807 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4808 {
4809 TCGv t0 = tcg_temp_new();
4810 TCGv t1 = tcg_temp_new();
4811 TCGv t2 = tcg_temp_new();
4812 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4813 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4814 tcg_gen_shl_tl(t2, t2, t0);
4815 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4816 gen_load_spr(t1, SPR_MQ);
4817 gen_store_spr(SPR_MQ, t0);
4818 tcg_gen_and_tl(t0, t0, t2);
4819 tcg_gen_andc_tl(t1, t1, t2);
4820 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4821 tcg_temp_free(t0);
4822 tcg_temp_free(t1);
4823 tcg_temp_free(t2);
4824 if (unlikely(Rc(ctx->opcode) != 0))
4825 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4826 }
4827
4828 /* sliq - sliq. */
4829 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4830 {
4831 int sh = SH(ctx->opcode);
4832 TCGv t0 = tcg_temp_new();
4833 TCGv t1 = tcg_temp_new();
4834 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4835 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4836 tcg_gen_or_tl(t1, t0, t1);
4837 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4838 gen_store_spr(SPR_MQ, t1);
4839 tcg_temp_free(t0);
4840 tcg_temp_free(t1);
4841 if (unlikely(Rc(ctx->opcode) != 0))
4842 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4843 }
4844
4845 /* slliq - slliq. */
4846 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4847 {
4848 int sh = SH(ctx->opcode);
4849 TCGv t0 = tcg_temp_new();
4850 TCGv t1 = tcg_temp_new();
4851 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4852 gen_load_spr(t1, SPR_MQ);
4853 gen_store_spr(SPR_MQ, t0);
4854 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4855 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4856 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4857 tcg_temp_free(t0);
4858 tcg_temp_free(t1);
4859 if (unlikely(Rc(ctx->opcode) != 0))
4860 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4861 }
4862
4863 /* sllq - sllq. */
4864 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4865 {
4866 int l1 = gen_new_label();
4867 int l2 = gen_new_label();
4868 TCGv t0 = tcg_temp_local_new();
4869 TCGv t1 = tcg_temp_local_new();
4870 TCGv t2 = tcg_temp_local_new();
4871 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4872 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4873 tcg_gen_shl_tl(t1, t1, t2);
4874 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4875 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4876 gen_load_spr(t0, SPR_MQ);
4877 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4878 tcg_gen_br(l2);
4879 gen_set_label(l1);
4880 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4881 gen_load_spr(t2, SPR_MQ);
4882 tcg_gen_andc_tl(t1, t2, t1);
4883 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4884 gen_set_label(l2);
4885 tcg_temp_free(t0);
4886 tcg_temp_free(t1);
4887 tcg_temp_free(t2);
4888 if (unlikely(Rc(ctx->opcode) != 0))
4889 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4890 }
4891
4892 /* slq - slq. */
4893 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4894 {
4895 int l1 = gen_new_label();
4896 TCGv t0 = tcg_temp_new();
4897 TCGv t1 = tcg_temp_new();
4898 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4899 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4900 tcg_gen_subfi_tl(t1, 32, t1);
4901 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4902 tcg_gen_or_tl(t1, t0, t1);
4903 gen_store_spr(SPR_MQ, t1);
4904 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4905 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4906 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4907 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4908 gen_set_label(l1);
4909 tcg_temp_free(t0);
4910 tcg_temp_free(t1);
4911 if (unlikely(Rc(ctx->opcode) != 0))
4912 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4913 }
4914
4915 /* sraiq - sraiq. */
4916 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4917 {
4918 int sh = SH(ctx->opcode);
4919 int l1 = gen_new_label();
4920 TCGv t0 = tcg_temp_new();
4921 TCGv t1 = tcg_temp_new();
4922 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4923 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4924 tcg_gen_or_tl(t0, t0, t1);
4925 gen_store_spr(SPR_MQ, t0);
4926 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4927 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4928 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4929 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4930 gen_set_label(l1);
4931 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4932 tcg_temp_free(t0);
4933 tcg_temp_free(t1);
4934 if (unlikely(Rc(ctx->opcode) != 0))
4935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4936 }
4937
4938 /* sraq - sraq. */
4939 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4940 {
4941 int l1 = gen_new_label();
4942 int l2 = gen_new_label();
4943 TCGv t0 = tcg_temp_new();
4944 TCGv t1 = tcg_temp_local_new();
4945 TCGv t2 = tcg_temp_local_new();
4946 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4947 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4948 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4949 tcg_gen_subfi_tl(t2, 32, t2);
4950 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4951 tcg_gen_or_tl(t0, t0, t2);
4952 gen_store_spr(SPR_MQ, t0);
4953 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4954 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4955 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4956 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4957 gen_set_label(l1);
4958 tcg_temp_free(t0);
4959 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4960 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4961 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4962 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4963 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4964 gen_set_label(l2);
4965 tcg_temp_free(t1);
4966 tcg_temp_free(t2);
4967 if (unlikely(Rc(ctx->opcode) != 0))
4968 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4969 }
4970
4971 /* sre - sre. */
4972 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4973 {
4974 TCGv t0 = tcg_temp_new();
4975 TCGv t1 = tcg_temp_new();
4976 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4977 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4978 tcg_gen_subfi_tl(t1, 32, t1);
4979 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4980 tcg_gen_or_tl(t1, t0, t1);
4981 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4982 gen_store_spr(SPR_MQ, t1);
4983 tcg_temp_free(t0);
4984 tcg_temp_free(t1);
4985 if (unlikely(Rc(ctx->opcode) != 0))
4986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4987 }
4988
4989 /* srea - srea. */
4990 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4991 {
4992 TCGv t0 = tcg_temp_new();
4993 TCGv t1 = tcg_temp_new();
4994 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4995 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4996 gen_store_spr(SPR_MQ, t0);
4997 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4998 tcg_temp_free(t0);
4999 tcg_temp_free(t1);
5000 if (unlikely(Rc(ctx->opcode) != 0))
5001 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5002 }
5003
5004 /* sreq */
5005 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
5006 {
5007 TCGv t0 = tcg_temp_new();
5008 TCGv t1 = tcg_temp_new();
5009 TCGv t2 = tcg_temp_new();
5010 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5011 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5012 tcg_gen_shr_tl(t1, t1, t0);
5013 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5014 gen_load_spr(t2, SPR_MQ);
5015 gen_store_spr(SPR_MQ, t0);
5016 tcg_gen_and_tl(t0, t0, t1);
5017 tcg_gen_andc_tl(t2, t2, t1);
5018 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5019 tcg_temp_free(t0);
5020 tcg_temp_free(t1);
5021 tcg_temp_free(t2);
5022 if (unlikely(Rc(ctx->opcode) != 0))
5023 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5024 }
5025
5026 /* sriq */
5027 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
5028 {
5029 int sh = SH(ctx->opcode);
5030 TCGv t0 = tcg_temp_new();
5031 TCGv t1 = tcg_temp_new();
5032 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5033 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5034 tcg_gen_or_tl(t1, t0, t1);
5035 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5036 gen_store_spr(SPR_MQ, t1);
5037 tcg_temp_free(t0);
5038 tcg_temp_free(t1);
5039 if (unlikely(Rc(ctx->opcode) != 0))
5040 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5041 }
5042
5043 /* srliq */
5044 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5045 {
5046 int sh = SH(ctx->opcode);
5047 TCGv t0 = tcg_temp_new();
5048 TCGv t1 = tcg_temp_new();
5049 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5050 gen_load_spr(t1, SPR_MQ);
5051 gen_store_spr(SPR_MQ, t0);
5052 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5053 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5054 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5055 tcg_temp_free(t0);
5056 tcg_temp_free(t1);
5057 if (unlikely(Rc(ctx->opcode) != 0))
5058 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5059 }
5060
5061 /* srlq */
5062 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5063 {
5064 int l1 = gen_new_label();
5065 int l2 = gen_new_label();
5066 TCGv t0 = tcg_temp_local_new();
5067 TCGv t1 = tcg_temp_local_new();
5068 TCGv t2 = tcg_temp_local_new();
5069 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5070 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5071 tcg_gen_shr_tl(t2, t1, t2);
5072 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5073 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5074 gen_load_spr(t0, SPR_MQ);
5075 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5076 tcg_gen_br(l2);
5077 gen_set_label(l1);
5078 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5079 tcg_gen_and_tl(t0, t0, t2);
5080 gen_load_spr(t1, SPR_MQ);
5081 tcg_gen_andc_tl(t1, t1, t2);
5082 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5083 gen_set_label(l2);
5084 tcg_temp_free(t0);
5085 tcg_temp_free(t1);
5086 tcg_temp_free(t2);
5087 if (unlikely(Rc(ctx->opcode) != 0))
5088 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5089 }
5090
5091 /* srq */
5092 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5093 {
5094 int l1 = gen_new_label();
5095 TCGv t0 = tcg_temp_new();
5096 TCGv t1 = tcg_temp_new();
5097 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5098 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5099 tcg_gen_subfi_tl(t1, 32, t1);
5100 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5101 tcg_gen_or_tl(t1, t0, t1);
5102 gen_store_spr(SPR_MQ, t1);
5103 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5104 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5105 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5106 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5107 gen_set_label(l1);
5108 tcg_temp_free(t0);
5109 tcg_temp_free(t1);
5110 if (unlikely(Rc(ctx->opcode) != 0))
5111 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5112 }
5113
5114 /* PowerPC 602 specific instructions */
5115 /* dsa */
5116 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5117 {
5118 /* XXX: TODO */
5119 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5120 }
5121
5122 /* esa */
5123 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5124 {
5125 /* XXX: TODO */
5126 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5127 }
5128
5129 /* mfrom */
5130 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5131 {
5132 #if defined(CONFIG_USER_ONLY)
5133 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5134 #else
5135 if (unlikely(!ctx->mem_idx)) {
5136 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5137 return;
5138 }
5139 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5140 #endif
5141 }
5142
5143 /* 602 - 603 - G2 TLB management */
5144 /* tlbld */
5145 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5146 {
5147 #if defined(CONFIG_USER_ONLY)
5148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5149 #else
5150 if (unlikely(!ctx->mem_idx)) {
5151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5152 return;
5153 }
5154 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5155 #endif
5156 }
5157
5158 /* tlbli */
5159 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5160 {
5161 #if defined(CONFIG_USER_ONLY)
5162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5163 #else
5164 if (unlikely(!ctx->mem_idx)) {
5165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5166 return;
5167 }
5168 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5169 #endif
5170 }
5171
5172 /* 74xx TLB management */
5173 /* tlbld */
5174 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5175 {
5176 #if defined(CONFIG_USER_ONLY)
5177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5178 #else
5179 if (unlikely(!ctx->mem_idx)) {
5180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5181 return;
5182 }
5183 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5184 #endif
5185 }
5186
5187 /* tlbli */
5188 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5189 {
5190 #if defined(CONFIG_USER_ONLY)
5191 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5192 #else
5193 if (unlikely(!ctx->mem_idx)) {
5194 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5195 return;
5196 }
5197 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5198 #endif
5199 }
5200
5201 /* POWER instructions not in PowerPC 601 */
5202 /* clf */
5203 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5204 {
5205 /* Cache line flush: implemented as no-op */
5206 }
5207
5208 /* cli */
5209 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5210 {
5211 /* Cache line invalidate: privileged and treated as no-op */
5212 #if defined(CONFIG_USER_ONLY)
5213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5214 #else
5215 if (unlikely(!ctx->mem_idx)) {
5216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5217 return;
5218 }
5219 #endif
5220 }
5221
5222 /* dclst */
5223 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5224 {
5225 /* Data cache line store: treated as no-op */
5226 }
5227
5228 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5229 {
5230 #if defined(CONFIG_USER_ONLY)
5231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5232 #else
5233 int ra = rA(ctx->opcode);
5234 int rd = rD(ctx->opcode);
5235 TCGv t0;
5236 if (unlikely(!ctx->mem_idx)) {
5237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5238 return;
5239 }
5240 t0 = tcg_temp_new();
5241 gen_addr_reg_index(ctx, t0);
5242 tcg_gen_shri_tl(t0, t0, 28);
5243 tcg_gen_andi_tl(t0, t0, 0xF);
5244 gen_helper_load_sr(cpu_gpr[rd], t0);
5245 tcg_temp_free(t0);
5246 if (ra != 0 && ra != rd)
5247 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5248 #endif
5249 }
5250
5251 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5252 {
5253 #if defined(CONFIG_USER_ONLY)
5254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5255 #else
5256 TCGv t0;
5257 if (unlikely(!ctx->mem_idx)) {
5258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5259 return;
5260 }
5261 t0 = tcg_temp_new();
5262 gen_addr_reg_index(ctx, t0);
5263 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5264 tcg_temp_free(t0);
5265 #endif
5266 }
5267
5268 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5269 {
5270 #if defined(CONFIG_USER_ONLY)
5271 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5272 #else
5273 if (unlikely(!ctx->mem_idx)) {
5274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5275 return;
5276 }
5277 gen_helper_rfsvc();
5278 gen_sync_exception(ctx);
5279 #endif
5280 }
5281
5282 /* svc is not implemented for now */
5283
5284 /* POWER2 specific instructions */
5285 /* Quad manipulation (load/store two floats at a time) */
5286
5287 /* lfq */
5288 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5289 {
5290 int rd = rD(ctx->opcode);
5291 TCGv t0;
5292 gen_set_access_type(ctx, ACCESS_FLOAT);
5293 t0 = tcg_temp_new();
5294 gen_addr_imm_index(ctx, t0, 0);
5295 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5296 gen_addr_add(ctx, t0, t0, 8);
5297 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5298 tcg_temp_free(t0);
5299 }
5300
5301 /* lfqu */
5302 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5303 {
5304 int ra = rA(ctx->opcode);
5305 int rd = rD(ctx->opcode);
5306 TCGv t0, t1;
5307 gen_set_access_type(ctx, ACCESS_FLOAT);
5308 t0 = tcg_temp_new();
5309 t1 = tcg_temp_new();
5310 gen_addr_imm_index(ctx, t0, 0);
5311 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5312 gen_addr_add(ctx, t1, t0, 8);
5313 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5314 if (ra != 0)
5315 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5316 tcg_temp_free(t0);
5317 tcg_temp_free(t1);
5318 }
5319
5320 /* lfqux */
5321 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5322 {
5323 int ra = rA(ctx->opcode);
5324 int rd = rD(ctx->opcode);
5325 gen_set_access_type(ctx, ACCESS_FLOAT);
5326 TCGv t0, t1;
5327 t0 = tcg_temp_new();
5328 gen_addr_reg_index(ctx, t0);
5329 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5330 t1 = tcg_temp_new();
5331 gen_addr_add(ctx, t1, t0, 8);
5332 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5333 tcg_temp_free(t1);
5334 if (ra != 0)
5335 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5336 tcg_temp_free(t0);
5337 }
5338
5339 /* lfqx */
5340 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5341 {
5342 int rd = rD(ctx->opcode);
5343 TCGv t0;
5344 gen_set_access_type(ctx, ACCESS_FLOAT);
5345 t0 = tcg_temp_new();
5346 gen_addr_reg_index(ctx, t0);
5347 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5348 gen_addr_add(ctx, t0, t0, 8);
5349 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5350 tcg_temp_free(t0);
5351 }
5352
5353 /* stfq */
5354 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5355 {
5356 int rd = rD(ctx->opcode);
5357 TCGv t0;
5358 gen_set_access_type(ctx, ACCESS_FLOAT);
5359 t0 = tcg_temp_new();
5360 gen_addr_imm_index(ctx, t0, 0);
5361 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5362 gen_addr_add(ctx, t0, t0, 8);
5363 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5364 tcg_temp_free(t0);
5365 }
5366
5367 /* stfqu */
5368 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5369 {
5370 int ra = rA(ctx->opcode);
5371 int rd = rD(ctx->opcode);
5372 TCGv t0, t1;
5373 gen_set_access_type(ctx, ACCESS_FLOAT);
5374 t0 = tcg_temp_new();
5375 gen_addr_imm_index(ctx, t0, 0);
5376 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5377 t1 = tcg_temp_new();
5378 gen_addr_add(ctx, t1, t0, 8);
5379 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5380 tcg_temp_free(t1);
5381 if (ra != 0)
5382 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5383 tcg_temp_free(t0);
5384 }
5385
5386 /* stfqux */
5387 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5388 {
5389 int ra = rA(ctx->opcode);
5390 int rd = rD(ctx->opcode);
5391 TCGv t0, t1;
5392 gen_set_access_type(ctx, ACCESS_FLOAT);
5393 t0 = tcg_temp_new();
5394 gen_addr_reg_index(ctx, t0);
5395 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5396 t1 = tcg_temp_new();
5397 gen_addr_add(ctx, t1, t0, 8);
5398 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5399 tcg_temp_free(t1);
5400 if (ra != 0)
5401 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5402 tcg_temp_free(t0);
5403 }
5404
5405 /* stfqx */
5406 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5407 {
5408 int rd = rD(ctx->opcode);
5409 TCGv t0;
5410 gen_set_access_type(ctx, ACCESS_FLOAT);
5411 t0 = tcg_temp_new();
5412 gen_addr_reg_index(ctx, t0);
5413 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5414 gen_addr_add(ctx, t0, t0, 8);
5415 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5416 tcg_temp_free(t0);
5417 }
5418
5419 /* BookE specific instructions */
5420 /* XXX: not implemented on 440 ? */
5421 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5422 {
5423 /* XXX: TODO */
5424 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5425 }
5426
5427 /* XXX: not implemented on 440 ? */
5428 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5429 {
5430 #if defined(CONFIG_USER_ONLY)
5431 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5432 #else
5433 TCGv t0;
5434 if (unlikely(!ctx->mem_idx)) {
5435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5436 return;
5437 }
5438 t0 = tcg_temp_new();
5439 gen_addr_reg_index(ctx, t0);
5440 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5441 tcg_temp_free(t0);
5442 #endif
5443 }
5444
5445 /* All 405 MAC instructions are translated here */
5446 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5447 int opc2, int opc3,
5448 int ra, int rb, int rt, int Rc)
5449 {
5450 TCGv t0, t1;
5451
5452 t0 = tcg_temp_local_new();
5453 t1 = tcg_temp_local_new();
5454
5455 switch (opc3 & 0x0D) {
5456 case 0x05:
5457 /* macchw - macchw. - macchwo - macchwo. */
5458 /* macchws - macchws. - macchwso - macchwso. */
5459 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5460 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5461 /* mulchw - mulchw. */
5462 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5463 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5464 tcg_gen_ext16s_tl(t1, t1);
5465 break;
5466 case 0x04:
5467 /* macchwu - macchwu. - macchwuo - macchwuo. */
5468 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5469 /* mulchwu - mulchwu. */
5470 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5471 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5472 tcg_gen_ext16u_tl(t1, t1);
5473 break;
5474 case 0x01:
5475 /* machhw - machhw. - machhwo - machhwo. */
5476 /* machhws - machhws. - machhwso - machhwso. */
5477 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5478 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5479 /* mulhhw - mulhhw. */
5480 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5481 tcg_gen_ext16s_tl(t0, t0);
5482 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5483 tcg_gen_ext16s_tl(t1, t1);
5484 break;
5485 case 0x00:
5486 /* machhwu - machhwu. - machhwuo - machhwuo. */
5487 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5488 /* mulhhwu - mulhhwu. */
5489 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5490 tcg_gen_ext16u_tl(t0, t0);
5491 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5492 tcg_gen_ext16u_tl(t1, t1);
5493 break;
5494 case 0x0D:
5495 /* maclhw - maclhw. - maclhwo - maclhwo. */
5496 /* maclhws - maclhws. - maclhwso - maclhwso. */
5497 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5498 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5499 /* mullhw - mullhw. */
5500 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5501 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5502 break;
5503 case 0x0C:
5504 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5505 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5506 /* mullhwu - mullhwu. */
5507 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5508 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5509 break;
5510 }
5511 if (opc2 & 0x04) {
5512 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5513 tcg_gen_mul_tl(t1, t0, t1);
5514 if (opc2 & 0x02) {
5515 /* nmultiply-and-accumulate (0x0E) */
5516 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5517 } else {
5518 /* multiply-and-accumulate (0x0C) */
5519 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5520 }
5521
5522 if (opc3 & 0x12) {
5523 /* Check overflow and/or saturate */
5524 int l1 = gen_new_label();
5525
5526 if (opc3 & 0x10) {
5527 /* Start with XER OV disabled, the most likely case */
5528 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5529 }
5530 if (opc3 & 0x01) {
5531 /* Signed */
5532 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5533 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5534 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5535 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5536 if (opc3 & 0x02) {
5537 /* Saturate */
5538 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5539 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5540 }
5541 } else {
5542 /* Unsigned */
5543 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5544 if (opc3 & 0x02) {
5545 /* Saturate */
5546 tcg_gen_movi_tl(t0, UINT32_MAX);
5547 }
5548 }
5549 if (opc3 & 0x10) {
5550 /* Check overflow */
5551 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5552 }
5553 gen_set_label(l1);
5554 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5555 }
5556 } else {
5557 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5558 }
5559 tcg_temp_free(t0);
5560 tcg_temp_free(t1);
5561 if (unlikely(Rc) != 0) {
5562 /* Update Rc0 */
5563 gen_set_Rc0(ctx, cpu_gpr[rt]);
5564 }
5565 }
5566
5567 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5568 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5569 { \
5570 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5571 rD(ctx->opcode), Rc(ctx->opcode)); \
5572 }
5573
5574 /* macchw - macchw. */
5575 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5576 /* macchwo - macchwo. */
5577 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5578 /* macchws - macchws. */
5579 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5580 /* macchwso - macchwso. */
5581 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5582 /* macchwsu - macchwsu. */
5583 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5584 /* macchwsuo - macchwsuo. */
5585 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5586 /* macchwu - macchwu. */
5587 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5588 /* macchwuo - macchwuo. */
5589 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5590 /* machhw - machhw. */
5591 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5592 /* machhwo - machhwo. */
5593 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5594 /* machhws - machhws. */
5595 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5596 /* machhwso - machhwso. */
5597 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5598 /* machhwsu - machhwsu. */
5599 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5600 /* machhwsuo - machhwsuo. */
5601 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5602 /* machhwu - machhwu. */
5603 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5604 /* machhwuo - machhwuo. */
5605 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5606 /* maclhw - maclhw. */
5607 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5608 /* maclhwo - maclhwo. */
5609 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5610 /* maclhws - maclhws. */
5611 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5612 /* maclhwso - maclhwso. */
5613 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5614 /* maclhwu - maclhwu. */
5615 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5616 /* maclhwuo - maclhwuo. */
5617 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5618 /* maclhwsu - maclhwsu. */
5619 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5620 /* maclhwsuo - maclhwsuo. */
5621 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5622 /* nmacchw - nmacchw. */
5623 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5624 /* nmacchwo - nmacchwo. */
5625 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5626 /* nmacchws - nmacchws. */
5627 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5628 /* nmacchwso - nmacchwso. */
5629 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5630 /* nmachhw - nmachhw. */
5631 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5632 /* nmachhwo - nmachhwo. */
5633 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5634 /* nmachhws - nmachhws. */
5635 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5636 /* nmachhwso - nmachhwso. */
5637 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5638 /* nmaclhw - nmaclhw. */
5639 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5640 /* nmaclhwo - nmaclhwo. */
5641 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5642 /* nmaclhws - nmaclhws. */
5643 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5644 /* nmaclhwso - nmaclhwso. */
5645 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5646
5647 /* mulchw - mulchw. */
5648 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5649 /* mulchwu - mulchwu. */
5650 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5651 /* mulhhw - mulhhw. */
5652 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5653 /* mulhhwu - mulhhwu. */
5654 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5655 /* mullhw - mullhw. */
5656 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5657 /* mullhwu - mullhwu. */
5658 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5659
5660 /* mfdcr */
5661 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5662 {
5663 #if defined(CONFIG_USER_ONLY)
5664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5665 #else
5666 TCGv dcrn;
5667 if (unlikely(!ctx->mem_idx)) {
5668 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5669 return;
5670 }
5671 /* NIP cannot be restored if the memory exception comes from an helper */
5672 gen_update_nip(ctx, ctx->nip - 4);
5673 dcrn = tcg_const_tl(SPR(ctx->opcode));
5674 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5675 tcg_temp_free(dcrn);
5676 #endif
5677 }
5678
5679 /* mtdcr */
5680 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5681 {
5682 #if defined(CONFIG_USER_ONLY)
5683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5684 #else
5685 TCGv dcrn;
5686 if (unlikely(!ctx->mem_idx)) {
5687 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5688 return;
5689 }
5690 /* NIP cannot be restored if the memory exception comes from an helper */
5691 gen_update_nip(ctx, ctx->nip - 4);
5692 dcrn = tcg_const_tl(SPR(ctx->opcode));
5693 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5694 tcg_temp_free(dcrn);
5695 #endif
5696 }
5697
5698 /* mfdcrx */
5699 /* XXX: not implemented on 440 ? */
5700 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5701 {
5702 #if defined(CONFIG_USER_ONLY)
5703 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5704 #else
5705 if (unlikely(!ctx->mem_idx)) {
5706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5707 return;
5708 }
5709 /* NIP cannot be restored if the memory exception comes from an helper */
5710 gen_update_nip(ctx, ctx->nip - 4);
5711 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5712 /* Note: Rc update flag set leads to undefined state of Rc0 */
5713 #endif
5714 }
5715
5716 /* mtdcrx */
5717 /* XXX: not implemented on 440 ? */
5718 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5719 {
5720 #if defined(CONFIG_USER_ONLY)
5721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5722 #else
5723 if (unlikely(!ctx->mem_idx)) {
5724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5725 return;
5726 }
5727 /* NIP cannot be restored if the memory exception comes from an helper */
5728 gen_update_nip(ctx, ctx->nip - 4);
5729 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5730 /* Note: Rc update flag set leads to undefined state of Rc0 */
5731 #endif
5732 }
5733
5734 /* mfdcrux (PPC 460) : user-mode access to DCR */
5735 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5736 {
5737 /* NIP cannot be restored if the memory exception comes from an helper */
5738 gen_update_nip(ctx, ctx->nip - 4);
5739 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5740 /* Note: Rc update flag set leads to undefined state of Rc0 */
5741 }
5742
5743 /* mtdcrux (PPC 460) : user-mode access to DCR */
5744 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5745 {
5746 /* NIP cannot be restored if the memory exception comes from an helper */
5747 gen_update_nip(ctx, ctx->nip - 4);
5748 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5749 /* Note: Rc update flag set leads to undefined state of Rc0 */
5750 }
5751
5752 /* dccci */
5753 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5754 {
5755 #if defined(CONFIG_USER_ONLY)
5756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5757 #else
5758 if (unlikely(!ctx->mem_idx)) {
5759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5760 return;
5761 }
5762 /* interpreted as no-op */
5763 #endif
5764 }
5765
5766 /* dcread */
5767 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5768 {
5769 #if defined(CONFIG_USER_ONLY)
5770 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5771 #else
5772 TCGv EA, val;
5773 if (unlikely(!ctx->mem_idx)) {
5774 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5775 return;
5776 }
5777 gen_set_access_type(ctx, ACCESS_CACHE);
5778 EA = tcg_temp_new();
5779 gen_addr_reg_index(ctx, EA);
5780 val = tcg_temp_new();
5781 gen_qemu_ld32u(ctx, val, EA);
5782 tcg_temp_free(val);
5783 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5784 tcg_temp_free(EA);
5785 #endif
5786 }
5787
5788 /* icbt */
5789 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5790 {
5791 /* interpreted as no-op */
5792 /* XXX: specification say this is treated as a load by the MMU
5793 * but does not generate any exception
5794 */
5795 }
5796
5797 /* iccci */
5798 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5799 {
5800 #if defined(CONFIG_USER_ONLY)
5801 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5802 #else
5803 if (unlikely(!ctx->mem_idx)) {
5804 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5805 return;
5806 }
5807 /* interpreted as no-op */
5808 #endif
5809 }
5810
5811 /* icread */
5812 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5813 {
5814 #if defined(CONFIG_USER_ONLY)
5815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5816 #else
5817 if (unlikely(!ctx->mem_idx)) {
5818 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5819 return;
5820 }
5821 /* interpreted as no-op */
5822 #endif
5823 }
5824
5825 /* rfci (mem_idx only) */
5826 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5827 {
5828 #if defined(CONFIG_USER_ONLY)
5829 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5830 #else
5831 if (unlikely(!ctx->mem_idx)) {
5832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5833 return;
5834 }
5835 /* Restore CPU state */
5836 gen_helper_40x_rfci();
5837 gen_sync_exception(ctx);
5838 #endif
5839 }
5840
5841 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5842 {
5843 #if defined(CONFIG_USER_ONLY)
5844 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5845 #else
5846 if (unlikely(!ctx->mem_idx)) {
5847 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5848 return;
5849 }
5850 /* Restore CPU state */
5851 gen_helper_rfci();
5852 gen_sync_exception(ctx);
5853 #endif
5854 }
5855
5856 /* BookE specific */
5857 /* XXX: not implemented on 440 ? */
5858 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5859 {
5860 #if defined(CONFIG_USER_ONLY)
5861 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5862 #else
5863 if (unlikely(!ctx->mem_idx)) {
5864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5865 return;
5866 }
5867 /* Restore CPU state */
5868 gen_helper_rfdi();
5869 gen_sync_exception(ctx);
5870 #endif
5871 }
5872
5873 /* XXX: not implemented on 440 ? */
5874 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5875 {
5876 #if defined(CONFIG_USER_ONLY)
5877 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5878 #else
5879 if (unlikely(!ctx->mem_idx)) {
5880 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5881 return;
5882 }
5883 /* Restore CPU state */
5884 gen_helper_rfmci();
5885 gen_sync_exception(ctx);
5886 #endif
5887 }
5888
5889 /* TLB management - PowerPC 405 implementation */
5890 /* tlbre */
5891 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5892 {
5893 #if defined(CONFIG_USER_ONLY)
5894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5895 #else
5896 if (unlikely(!ctx->mem_idx)) {
5897 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5898 return;
5899 }
5900 switch (rB(ctx->opcode)) {
5901 case 0:
5902 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5903 break;
5904 case 1:
5905 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5906 break;
5907 default:
5908 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5909 break;
5910 }
5911 #endif
5912 }
5913
5914 /* tlbsx - tlbsx. */
5915 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5916 {
5917 #if defined(CONFIG_USER_ONLY)
5918 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5919 #else
5920 TCGv t0;
5921 if (unlikely(!ctx->mem_idx)) {
5922 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5923 return;
5924 }
5925 t0 = tcg_temp_new();
5926 gen_addr_reg_index(ctx, t0);
5927 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5928 tcg_temp_free(t0);
5929 if (Rc(ctx->opcode)) {
5930 int l1 = gen_new_label();
5931 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5932 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5933 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5934 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5935 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5936 gen_set_label(l1);
5937 }
5938 #endif
5939 }
5940
5941 /* tlbwe */
5942 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5943 {
5944 #if defined(CONFIG_USER_ONLY)
5945 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5946 #else
5947 if (unlikely(!ctx->mem_idx)) {
5948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5949 return;
5950 }
5951 switch (rB(ctx->opcode)) {
5952 case 0:
5953 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5954 break;
5955 case 1:
5956 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5957 break;
5958 default:
5959 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5960 break;
5961 }
5962 #endif
5963 }
5964
5965 /* TLB management - PowerPC 440 implementation */
5966 /* tlbre */
5967 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5968 {
5969 #if defined(CONFIG_USER_ONLY)
5970 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5971 #else
5972 if (unlikely(!ctx->mem_idx)) {
5973 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5974 return;
5975 }
5976 switch (rB(ctx->opcode)) {
5977 case 0:
5978 case 1:
5979 case 2:
5980 {
5981 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5982 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5983 tcg_temp_free_i32(t0);
5984 }
5985 break;
5986 default:
5987 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5988 break;
5989 }
5990 #endif
5991 }
5992
5993 /* tlbsx - tlbsx. */
5994 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5995 {
5996 #if defined(CONFIG_USER_ONLY)
5997 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5998 #else
5999 TCGv t0;
6000 if (unlikely(!ctx->mem_idx)) {
6001 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6002 return;
6003 }
6004 t0 = tcg_temp_new();
6005 gen_addr_reg_index(ctx, t0);
6006 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
6007 tcg_temp_free(t0);
6008 if (Rc(ctx->opcode)) {
6009 int l1 = gen_new_label();
6010 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6011 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6012 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6013 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6014 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6015 gen_set_label(l1);
6016 }
6017 #endif
6018 }
6019
6020 /* tlbwe */
6021 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
6022 {
6023 #if defined(CONFIG_USER_ONLY)
6024 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6025 #else
6026 if (unlikely(!ctx->mem_idx)) {
6027 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6028 return;
6029 }
6030 switch (rB(ctx->opcode)) {
6031 case 0:
6032 case 1:
6033 case 2:
6034 {
6035 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6036 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6037 tcg_temp_free_i32(t0);
6038 }
6039 break;
6040 default:
6041 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6042 break;
6043 }
6044 #endif
6045 }
6046
6047 /* wrtee */
6048 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6049 {
6050 #if defined(CONFIG_USER_ONLY)
6051 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6052 #else
6053 TCGv t0;
6054 if (unlikely(!ctx->mem_idx)) {
6055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6056 return;
6057 }
6058 t0 = tcg_temp_new();
6059 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6060 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6061 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6062 tcg_temp_free(t0);
6063 /* Stop translation to have a chance to raise an exception
6064 * if we just set msr_ee to 1
6065 */
6066 gen_stop_exception(ctx);
6067 #endif
6068 }
6069
6070 /* wrteei */
6071 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6072 {
6073 #if defined(CONFIG_USER_ONLY)
6074 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6075 #else
6076 if (unlikely(!ctx->mem_idx)) {
6077 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6078 return;
6079 }
6080 if (ctx->opcode & 0x00010000) {
6081 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6082 /* Stop translation to have a chance to raise an exception */
6083 gen_stop_exception(ctx);
6084 } else {
6085 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6086 }
6087 #endif
6088 }
6089
6090 /* PowerPC 440 specific instructions */
6091 /* dlmzb */
6092 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6093 {
6094 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6095 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6096 cpu_gpr[rB(ctx->opcode)], t0);
6097 tcg_temp_free_i32(t0);
6098 }
6099
6100 /* mbar replaces eieio on 440 */
6101 GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
6102 {
6103 /* interpreted as no-op */
6104 }
6105
6106 /* msync replaces sync on 440 */
6107 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
6108 {
6109 /* interpreted as no-op */
6110 }
6111
6112 /* icbt */
6113 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
6114 {
6115 /* interpreted as no-op */
6116 /* XXX: specification say this is treated as a load by the MMU
6117 * but does not generate any exception
6118 */
6119 }
6120
6121 /*** Altivec vector extension ***/
6122 /* Altivec registers moves */
6123
6124 static always_inline TCGv_ptr gen_avr_ptr(int reg)
6125 {
6126 TCGv_ptr r = tcg_temp_new_ptr();
6127 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6128 return r;
6129 }
6130
6131 #define GEN_VR_LDX(name, opc2, opc3) \
6132 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6133 { \
6134 TCGv EA; \
6135 if (unlikely(!ctx->altivec_enabled)) { \
6136 gen_exception(ctx, POWERPC_EXCP_VPU); \
6137 return; \
6138 } \
6139 gen_set_access_type(ctx, ACCESS_INT); \
6140 EA = tcg_temp_new(); \
6141 gen_addr_reg_index(ctx, EA); \
6142 tcg_gen_andi_tl(EA, EA, ~0xf); \
6143 if (ctx->le_mode) { \
6144 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6145 tcg_gen_addi_tl(EA, EA, 8); \
6146 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6147 } else { \
6148 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6149 tcg_gen_addi_tl(EA, EA, 8); \
6150 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6151 } \
6152 tcg_temp_free(EA); \
6153 }
6154
6155 #define GEN_VR_STX(name, opc2, opc3) \
6156 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6157 { \
6158 TCGv EA; \
6159 if (unlikely(!ctx->altivec_enabled)) { \
6160 gen_exception(ctx, POWERPC_EXCP_VPU); \
6161 return; \
6162 } \
6163 gen_set_access_type(ctx, ACCESS_INT); \
6164 EA = tcg_temp_new(); \
6165 gen_addr_reg_index(ctx, EA); \
6166 tcg_gen_andi_tl(EA, EA, ~0xf); \
6167 if (ctx->le_mode) { \
6168 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6169 tcg_gen_addi_tl(EA, EA, 8); \
6170 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6171 } else { \
6172 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6173 tcg_gen_addi_tl(EA, EA, 8); \
6174 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6175 } \
6176 tcg_temp_free(EA); \
6177 }
6178
6179 #define GEN_VR_LVE(name, opc2, opc3) \
6180 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6181 { \
6182 TCGv EA; \
6183 TCGv_ptr rs; \
6184 if (unlikely(!ctx->altivec_enabled)) { \
6185 gen_exception(ctx, POWERPC_EXCP_VPU); \
6186 return; \
6187 } \
6188 gen_set_access_type(ctx, ACCESS_INT); \
6189 EA = tcg_temp_new(); \
6190 gen_addr_reg_index(ctx, EA); \
6191 rs = gen_avr_ptr(rS(ctx->opcode)); \
6192 gen_helper_lve##name (rs, EA); \
6193 tcg_temp_free(EA); \
6194 tcg_temp_free_ptr(rs); \
6195 }
6196
6197 #define GEN_VR_STVE(name, opc2, opc3) \
6198 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6199 { \
6200 TCGv EA; \
6201 TCGv_ptr rs; \
6202 if (unlikely(!ctx->altivec_enabled)) { \
6203 gen_exception(ctx, POWERPC_EXCP_VPU); \
6204 return; \
6205 } \
6206 gen_set_access_type(ctx, ACCESS_INT); \
6207 EA = tcg_temp_new(); \
6208 gen_addr_reg_index(ctx, EA); \
6209 rs = gen_avr_ptr(rS(ctx->opcode)); \
6210 gen_helper_stve##name (rs, EA); \
6211 tcg_temp_free(EA); \
6212 tcg_temp_free_ptr(rs); \
6213 }
6214
6215 GEN_VR_LDX(lvx, 0x07, 0x03);
6216 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6217 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6218
6219 GEN_VR_LVE(bx, 0x07, 0x00);
6220 GEN_VR_LVE(hx, 0x07, 0x01);
6221 GEN_VR_LVE(wx, 0x07, 0x02);
6222
6223 GEN_VR_STX(svx, 0x07, 0x07);
6224 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6225 GEN_VR_STX(svxl, 0x07, 0x0F);
6226
6227 GEN_VR_STVE(bx, 0x07, 0x04);
6228 GEN_VR_STVE(hx, 0x07, 0x05);
6229 GEN_VR_STVE(wx, 0x07, 0x06);
6230
6231 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6232 {
6233 TCGv_ptr rd;
6234 TCGv EA;
6235 if (unlikely(!ctx->altivec_enabled)) {
6236 gen_exception(ctx, POWERPC_EXCP_VPU);
6237 return;
6238 }
6239 EA = tcg_temp_new();
6240 gen_addr_reg_index(ctx, EA);
6241 rd = gen_avr_ptr(rD(ctx->opcode));
6242 gen_helper_lvsl(rd, EA);
6243 tcg_temp_free(EA);
6244 tcg_temp_free_ptr(rd);
6245 }
6246
6247 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6248 {
6249 TCGv_ptr rd;
6250 TCGv EA;
6251 if (unlikely(!ctx->altivec_enabled)) {
6252 gen_exception(ctx, POWERPC_EXCP_VPU);
6253 return;
6254 }
6255 EA = tcg_temp_new();
6256 gen_addr_reg_index(ctx, EA);
6257 rd = gen_avr_ptr(rD(ctx->opcode));
6258 gen_helper_lvsr(rd, EA);
6259 tcg_temp_free(EA);
6260 tcg_temp_free_ptr(rd);
6261 }
6262
6263 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6264 {
6265 TCGv_i32 t;
6266 if (unlikely(!ctx->altivec_enabled)) {
6267 gen_exception(ctx, POWERPC_EXCP_VPU);
6268 return;
6269 }
6270 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6271 t = tcg_temp_new_i32();
6272 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6273 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6274 tcg_temp_free_i32(t);
6275 }
6276
6277 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6278 {
6279 TCGv_ptr p;
6280 if (unlikely(!ctx->altivec_enabled)) {
6281 gen_exception(ctx, POWERPC_EXCP_VPU);
6282 return;
6283 }
6284 p = gen_avr_ptr(rD(ctx->opcode));
6285 gen_helper_mtvscr(p);
6286 tcg_temp_free_ptr(p);
6287 }
6288
6289 /* Logical operations */
6290 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6291 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6292 { \
6293 if (unlikely(!ctx->altivec_enabled)) { \
6294 gen_exception(ctx, POWERPC_EXCP_VPU); \
6295 return; \
6296 } \
6297 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6298 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6299 }
6300
6301 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6302 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6303 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6304 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6305 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6306
6307 #define GEN_VXFORM(name, opc2, opc3) \
6308 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6309 { \
6310 TCGv_ptr ra, rb, rd; \
6311 if (unlikely(!ctx->altivec_enabled)) { \
6312 gen_exception(ctx, POWERPC_EXCP_VPU); \
6313 return; \
6314 } \
6315 ra = gen_avr_ptr(rA(ctx->opcode)); \
6316 rb = gen_avr_ptr(rB(ctx->opcode)); \
6317 rd = gen_avr_ptr(rD(ctx->opcode)); \
6318 gen_helper_##name (rd, ra, rb); \
6319 tcg_temp_free_ptr(ra); \
6320 tcg_temp_free_ptr(rb); \
6321 tcg_temp_free_ptr(rd); \
6322 }
6323
6324 GEN_VXFORM(vaddubm, 0, 0);
6325 GEN_VXFORM(vadduhm, 0, 1);
6326 GEN_VXFORM(vadduwm, 0, 2);
6327 GEN_VXFORM(vsububm, 0, 16);
6328 GEN_VXFORM(vsubuhm, 0, 17);
6329 GEN_VXFORM(vsubuwm, 0, 18);
6330 GEN_VXFORM(vmaxub, 1, 0);
6331 GEN_VXFORM(vmaxuh, 1, 1);
6332 GEN_VXFORM(vmaxuw, 1, 2);
6333 GEN_VXFORM(vmaxsb, 1, 4);
6334 GEN_VXFORM(vmaxsh, 1, 5);
6335 GEN_VXFORM(vmaxsw, 1, 6);
6336 GEN_VXFORM(vminub, 1, 8);
6337 GEN_VXFORM(vminuh, 1, 9);
6338 GEN_VXFORM(vminuw, 1, 10);
6339 GEN_VXFORM(vminsb, 1, 12);
6340 GEN_VXFORM(vminsh, 1, 13);
6341 GEN_VXFORM(vminsw, 1, 14);
6342 GEN_VXFORM(vavgub, 1, 16);
6343 GEN_VXFORM(vavguh, 1, 17);
6344 GEN_VXFORM(vavguw, 1, 18);
6345 GEN_VXFORM(vavgsb, 1, 20);
6346 GEN_VXFORM(vavgsh, 1, 21);
6347 GEN_VXFORM(vavgsw, 1, 22);
6348 GEN_VXFORM(vmrghb, 6, 0);
6349 GEN_VXFORM(vmrghh, 6, 1);
6350 GEN_VXFORM(vmrghw, 6, 2);
6351 GEN_VXFORM(vmrglb, 6, 4);
6352 GEN_VXFORM(vmrglh, 6, 5);
6353 GEN_VXFORM(vmrglw, 6, 6);
6354 GEN_VXFORM(vmuloub, 4, 0);
6355 GEN_VXFORM(vmulouh, 4, 1);
6356 GEN_VXFORM(vmulosb, 4, 4);
6357 GEN_VXFORM(vmulosh, 4, 5);
6358 GEN_VXFORM(vmuleub, 4, 8);
6359 GEN_VXFORM(vmuleuh, 4, 9);
6360 GEN_VXFORM(vmulesb, 4, 12);
6361 GEN_VXFORM(vmulesh, 4, 13);
6362 GEN_VXFORM(vslb, 2, 4);
6363 GEN_VXFORM(vslh, 2, 5);
6364 GEN_VXFORM(vslw, 2, 6);
6365 GEN_VXFORM(vsrb, 2, 8);
6366 GEN_VXFORM(vsrh, 2, 9);
6367 GEN_VXFORM(vsrw, 2, 10);
6368 GEN_VXFORM(vsrab, 2, 12);
6369 GEN_VXFORM(vsrah, 2, 13);
6370 GEN_VXFORM(vsraw, 2, 14);
6371 GEN_VXFORM(vslo, 6, 16);
6372 GEN_VXFORM(vsro, 6, 17);
6373 GEN_VXFORM(vaddcuw, 0, 6);
6374 GEN_VXFORM(vsubcuw, 0, 22);
6375 GEN_VXFORM(vaddubs, 0, 8);
6376 GEN_VXFORM(vadduhs, 0, 9);
6377 GEN_VXFORM(vadduws, 0, 10);
6378 GEN_VXFORM(vaddsbs, 0, 12);
6379 GEN_VXFORM(vaddshs, 0, 13);
6380 GEN_VXFORM(vaddsws, 0, 14);
6381 GEN_VXFORM(vsububs, 0, 24);
6382 GEN_VXFORM(vsubuhs, 0, 25);
6383 GEN_VXFORM(vsubuws, 0, 26);
6384 GEN_VXFORM(vsubsbs, 0, 28);
6385 GEN_VXFORM(vsubshs, 0, 29);
6386 GEN_VXFORM(vsubsws, 0, 30);
6387 GEN_VXFORM(vrlb, 2, 0);
6388 GEN_VXFORM(vrlh, 2, 1);
6389 GEN_VXFORM(vrlw, 2, 2);
6390 GEN_VXFORM(vsl, 2, 7);
6391 GEN_VXFORM(vsr, 2, 11);
6392 GEN_VXFORM(vpkuhum, 7, 0);
6393 GEN_VXFORM(vpkuwum, 7, 1);
6394 GEN_VXFORM(vpkuhus, 7, 2);
6395 GEN_VXFORM(vpkuwus, 7, 3);
6396 GEN_VXFORM(vpkshus, 7, 4);
6397 GEN_VXFORM(vpkswus, 7, 5);
6398 GEN_VXFORM(vpkshss, 7, 6);
6399 GEN_VXFORM(vpkswss, 7, 7);
6400 GEN_VXFORM(vpkpx, 7, 12);
6401 GEN_VXFORM(vsum4ubs, 4, 24);
6402 GEN_VXFORM(vsum4sbs, 4, 28);
6403 GEN_VXFORM(vsum4shs, 4, 25);
6404 GEN_VXFORM(vsum2sws, 4, 26);
6405 GEN_VXFORM(vsumsws, 4, 30);
6406 GEN_VXFORM(vaddfp, 5, 0);
6407 GEN_VXFORM(vsubfp, 5, 1);
6408 GEN_VXFORM(vmaxfp, 5, 16);
6409 GEN_VXFORM(vminfp, 5, 17);
6410
6411 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6412 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6413 { \
6414 TCGv_ptr ra, rb, rd; \
6415 if (unlikely(!ctx->altivec_enabled)) { \
6416 gen_exception(ctx, POWERPC_EXCP_VPU); \
6417 return; \
6418 } \
6419 ra = gen_avr_ptr(rA(ctx->opcode)); \
6420 rb = gen_avr_ptr(rB(ctx->opcode)); \
6421 rd = gen_avr_ptr(rD(ctx->opcode)); \
6422 gen_helper_##opname (rd, ra, rb); \
6423 tcg_temp_free_ptr(ra); \
6424 tcg_temp_free_ptr(rb); \
6425 tcg_temp_free_ptr(rd); \
6426 }
6427
6428 #define GEN_VXRFORM(name, opc2, opc3) \
6429 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6430 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6431
6432 GEN_VXRFORM(vcmpequb, 3, 0)
6433 GEN_VXRFORM(vcmpequh, 3, 1)
6434 GEN_VXRFORM(vcmpequw, 3, 2)
6435 GEN_VXRFORM(vcmpgtsb, 3, 12)
6436 GEN_VXRFORM(vcmpgtsh, 3, 13)
6437 GEN_VXRFORM(vcmpgtsw, 3, 14)
6438 GEN_VXRFORM(vcmpgtub, 3, 8)
6439 GEN_VXRFORM(vcmpgtuh, 3, 9)
6440 GEN_VXRFORM(vcmpgtuw, 3, 10)
6441 GEN_VXRFORM(vcmpeqfp, 3, 3)
6442 GEN_VXRFORM(vcmpgefp, 3, 7)
6443 GEN_VXRFORM(vcmpgtfp, 3, 11)
6444 GEN_VXRFORM(vcmpbfp, 3, 15)
6445
6446 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6447 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6448 { \
6449 TCGv_ptr rd; \
6450 TCGv_i32 simm; \
6451 if (unlikely(!ctx->altivec_enabled)) { \
6452 gen_exception(ctx, POWERPC_EXCP_VPU); \
6453 return; \
6454 } \
6455 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6456 rd = gen_avr_ptr(rD(ctx->opcode)); \
6457 gen_helper_##name (rd, simm); \
6458 tcg_temp_free_i32(simm); \
6459 tcg_temp_free_ptr(rd); \
6460 }
6461
6462 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6463 GEN_VXFORM_SIMM(vspltish, 6, 13);
6464 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6465
6466 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6467 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6468 { \
6469 TCGv_ptr rb, rd; \
6470 if (unlikely(!ctx->altivec_enabled)) { \
6471 gen_exception(ctx, POWERPC_EXCP_VPU); \
6472 return; \
6473 } \
6474 rb = gen_avr_ptr(rB(ctx->opcode)); \
6475 rd = gen_avr_ptr(rD(ctx->opcode)); \
6476 gen_helper_##name (rd, rb); \
6477 tcg_temp_free_ptr(rb); \
6478 tcg_temp_free_ptr(rd); \
6479 }
6480
6481 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6482 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6483 GEN_VXFORM_NOA(vupklsb, 7, 10);
6484 GEN_VXFORM_NOA(vupklsh, 7, 11);
6485 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6486 GEN_VXFORM_NOA(vupklpx, 7, 15);
6487 GEN_VXFORM_NOA(vrefp, 5, 4);
6488 GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6489 GEN_VXFORM_NOA(vlogefp, 5, 7);
6490 GEN_VXFORM_NOA(vrfim, 5, 8);
6491 GEN_VXFORM_NOA(vrfin, 5, 9);
6492 GEN_VXFORM_NOA(vrfip, 5, 10);
6493 GEN_VXFORM_NOA(vrfiz, 5, 11);
6494
6495 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6496 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6497 { \
6498 TCGv_ptr rd; \
6499 TCGv_i32 simm; \
6500 if (unlikely(!ctx->altivec_enabled)) { \
6501 gen_exception(ctx, POWERPC_EXCP_VPU); \
6502 return; \
6503 } \
6504 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6505 rd = gen_avr_ptr(rD(ctx->opcode)); \
6506 gen_helper_##name (rd, simm); \
6507 tcg_temp_free_i32(simm); \
6508 tcg_temp_free_ptr(rd); \
6509 }
6510
6511 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6512 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6513 { \
6514 TCGv_ptr rb, rd; \
6515 TCGv_i32 uimm; \
6516 if (unlikely(!ctx->altivec_enabled)) { \
6517 gen_exception(ctx, POWERPC_EXCP_VPU); \
6518 return; \
6519 } \
6520 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6521 rb = gen_avr_ptr(rB(ctx->opcode)); \
6522 rd = gen_avr_ptr(rD(ctx->opcode)); \
6523 gen_helper_##name (rd, rb, uimm); \
6524 tcg_temp_free_i32(uimm); \
6525 tcg_temp_free_ptr(rb); \
6526 tcg_temp_free_ptr(rd); \
6527 }
6528
6529 GEN_VXFORM_UIMM(vspltb, 6, 8);
6530 GEN_VXFORM_UIMM(vsplth, 6, 9);
6531 GEN_VXFORM_UIMM(vspltw, 6, 10);
6532 GEN_VXFORM_UIMM(vcfux, 5, 12);
6533 GEN_VXFORM_UIMM(vcfsx, 5, 13);
6534 GEN_VXFORM_UIMM(vctuxs, 5, 14);
6535 GEN_VXFORM_UIMM(vctsxs, 5, 15);
6536
6537 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6538 {
6539 TCGv_ptr ra, rb, rd;
6540 TCGv_i32 sh;
6541 if (unlikely(!ctx->altivec_enabled)) {
6542 gen_exception(ctx, POWERPC_EXCP_VPU);
6543 return;
6544 }
6545 ra = gen_avr_ptr(rA(ctx->opcode));
6546 rb = gen_avr_ptr(rB(ctx->opcode));
6547 rd = gen_avr_ptr(rD(ctx->opcode));
6548 sh = tcg_const_i32(VSH(ctx->opcode));
6549 gen_helper_vsldoi (rd, ra, rb, sh);
6550 tcg_temp_free_ptr(ra);
6551 tcg_temp_free_ptr(rb);
6552 tcg_temp_free_ptr(rd);
6553 tcg_temp_free_i32(sh);
6554 }
6555
6556 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6557 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6558 { \
6559 TCGv_ptr ra, rb, rc, rd; \
6560 if (unlikely(!ctx->altivec_enabled)) { \
6561 gen_exception(ctx, POWERPC_EXCP_VPU); \
6562 return; \
6563 } \
6564 ra = gen_avr_ptr(rA(ctx->opcode)); \
6565 rb = gen_avr_ptr(rB(ctx->opcode)); \
6566 rc = gen_avr_ptr(rC(ctx->opcode)); \
6567 rd = gen_avr_ptr(rD(ctx->opcode)); \
6568 if (Rc(ctx->opcode)) { \
6569 gen_helper_##name1 (rd, ra, rb, rc); \
6570 } else { \
6571 gen_helper_##name0 (rd, ra, rb, rc); \
6572 } \
6573 tcg_temp_free_ptr(ra); \
6574 tcg_temp_free_ptr(rb); \
6575 tcg_temp_free_ptr(rc); \
6576 tcg_temp_free_ptr(rd); \
6577 }
6578
6579 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6580
6581 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6582 {
6583 TCGv_ptr ra, rb, rc, rd;
6584 if (unlikely(!ctx->altivec_enabled)) {
6585 gen_exception(ctx, POWERPC_EXCP_VPU);
6586 return;
6587 }
6588 ra = gen_avr_ptr(rA(ctx->opcode));
6589 rb = gen_avr_ptr(rB(ctx->opcode));
6590 rc = gen_avr_ptr(rC(ctx->opcode));
6591 rd = gen_avr_ptr(rD(ctx->opcode));
6592 gen_helper_vmladduhm(rd, ra, rb, rc);
6593 tcg_temp_free_ptr(ra);
6594 tcg_temp_free_ptr(rb);
6595 tcg_temp_free_ptr(rc);
6596 tcg_temp_free_ptr(rd);
6597 }
6598
6599 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6600 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6601 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6602 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6603 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6604
6605 /*** SPE extension ***/
6606 /* Register moves */
6607
6608 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
6609 #if defined(TARGET_PPC64)
6610 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6611 #else
6612 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6613 #endif
6614 }
6615
6616 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
6617 #if defined(TARGET_PPC64)
6618 tcg_gen_mov_i64(cpu_gpr[reg], t);
6619 #else
6620 TCGv_i64 tmp = tcg_temp_new_i64();
6621 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6622 tcg_gen_shri_i64(tmp, t, 32);
6623 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6624 tcg_temp_free_i64(tmp);
6625 #endif
6626 }
6627
6628 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6629 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6630 { \
6631 if (Rc(ctx->opcode)) \
6632 gen_##name1(ctx); \
6633 else \
6634 gen_##name0(ctx); \
6635 }
6636
6637 /* Handler for undefined SPE opcodes */
6638 static always_inline void gen_speundef (DisasContext *ctx)
6639 {
6640 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6641 }
6642
6643 /* SPE logic */
6644 #if defined(TARGET_PPC64)
6645 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6646 static always_inline void gen_##name (DisasContext *ctx) \
6647 { \
6648 if (unlikely(!ctx->spe_enabled)) { \
6649 gen_exception(ctx, POWERPC_EXCP_APU); \
6650 return; \
6651 } \
6652 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6653 cpu_gpr[rB(ctx->opcode)]); \
6654 }
6655 #else
6656 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6657 static always_inline void gen_##name (DisasContext *ctx) \
6658 { \
6659 if (unlikely(!ctx->spe_enabled)) { \
6660 gen_exception(ctx, POWERPC_EXCP_APU); \
6661 return; \
6662 } \
6663 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6664 cpu_gpr[rB(ctx->opcode)]); \
6665 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6666 cpu_gprh[rB(ctx->opcode)]); \
6667 }
6668 #endif
6669
6670 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6671 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6672 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6673 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6674 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6675 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6676 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6677 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6678
6679 /* SPE logic immediate */
6680 #if defined(TARGET_PPC64)
6681 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6682 static always_inline void gen_##name (DisasContext *ctx) \
6683 { \
6684 if (unlikely(!ctx->spe_enabled)) { \
6685 gen_exception(ctx, POWERPC_EXCP_APU); \
6686 return; \
6687 } \
6688 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6689 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6690 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6691 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6692 tcg_opi(t0, t0, rB(ctx->opcode)); \
6693 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6694 tcg_gen_trunc_i64_i32(t1, t2); \
6695 tcg_temp_free_i64(t2); \
6696 tcg_opi(t1, t1, rB(ctx->opcode)); \
6697 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6698 tcg_temp_free_i32(t0); \
6699 tcg_temp_free_i32(t1); \
6700 }
6701 #else
6702 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6703 static always_inline void gen_##name (DisasContext *ctx) \
6704 { \
6705 if (unlikely(!ctx->spe_enabled)) { \
6706 gen_exception(ctx, POWERPC_EXCP_APU); \
6707 return; \
6708 } \
6709 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6710 rB(ctx->opcode)); \
6711 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6712 rB(ctx->opcode)); \
6713 }
6714 #endif
6715 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6716 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6717 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6718 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6719
6720 /* SPE arithmetic */
6721 #if defined(TARGET_PPC64)
6722 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6723 static always_inline void gen_##name (DisasContext *ctx) \
6724 { \
6725 if (unlikely(!ctx->spe_enabled)) { \
6726 gen_exception(ctx, POWERPC_EXCP_APU); \
6727 return; \
6728 } \
6729 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6730 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6731 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6732 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6733 tcg_op(t0, t0); \
6734 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6735 tcg_gen_trunc_i64_i32(t1, t2); \
6736 tcg_temp_free_i64(t2); \
6737 tcg_op(t1, t1); \
6738 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6739 tcg_temp_free_i32(t0); \
6740 tcg_temp_free_i32(t1); \
6741 }
6742 #else
6743 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6744 static always_inline void gen_##name (DisasContext *ctx) \
6745 { \
6746 if (unlikely(!ctx->spe_enabled)) { \
6747 gen_exception(ctx, POWERPC_EXCP_APU); \
6748 return; \
6749 } \
6750 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6751 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6752 }
6753 #endif
6754
6755 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6756 {
6757 int l1 = gen_new_label();
6758 int l2 = gen_new_label();
6759
6760 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6761 tcg_gen_neg_i32(ret, arg1);
6762 tcg_gen_br(l2);
6763 gen_set_label(l1);
6764 tcg_gen_mov_i32(ret, arg1);
6765 gen_set_label(l2);
6766 }
6767 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6768 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6769 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6770 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6771 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6772 {
6773 tcg_gen_addi_i32(ret, arg1, 0x8000);
6774 tcg_gen_ext16u_i32(ret, ret);
6775 }
6776 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6777 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6778 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6779
6780 #if defined(TARGET_PPC64)
6781 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6782 static always_inline void gen_##name (DisasContext *ctx) \
6783 { \
6784 if (unlikely(!ctx->spe_enabled)) { \
6785 gen_exception(ctx, POWERPC_EXCP_APU); \
6786 return; \
6787 } \
6788 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6789 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6790 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6791 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6792 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6793 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6794 tcg_op(t0, t0, t2); \
6795 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6796 tcg_gen_trunc_i64_i32(t1, t3); \
6797 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6798 tcg_gen_trunc_i64_i32(t2, t3); \
6799 tcg_temp_free_i64(t3); \
6800 tcg_op(t1, t1, t2); \
6801 tcg_temp_free_i32(t2); \
6802 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6803 tcg_temp_free_i32(t0); \
6804 tcg_temp_free_i32(t1); \
6805 }
6806 #else
6807 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6808 static always_inline void gen_##name (DisasContext *ctx) \
6809 { \
6810 if (unlikely(!ctx->spe_enabled)) { \
6811 gen_exception(ctx, POWERPC_EXCP_APU); \
6812 return; \
6813 } \
6814 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6815 cpu_gpr[rB(ctx->opcode)]); \
6816 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6817 cpu_gprh[rB(ctx->opcode)]); \
6818 }
6819 #endif
6820
6821 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6822 {
6823 TCGv_i32 t0;
6824 int l1, l2;
6825
6826 l1 = gen_new_label();
6827 l2 = gen_new_label();
6828 t0 = tcg_temp_local_new_i32();
6829 /* No error here: 6 bits are used */
6830 tcg_gen_andi_i32(t0, arg2, 0x3F);
6831 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6832 tcg_gen_shr_i32(ret, arg1, t0);
6833 tcg_gen_br(l2);
6834 gen_set_label(l1);
6835 tcg_gen_movi_i32(ret, 0);
6836 tcg_gen_br(l2);
6837 tcg_temp_free_i32(t0);
6838 }
6839 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6840 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6841 {
6842 TCGv_i32 t0;
6843 int l1, l2;
6844
6845 l1 = gen_new_label();
6846 l2 = gen_new_label();
6847 t0 = tcg_temp_local_new_i32();
6848 /* No error here: 6 bits are used */
6849 tcg_gen_andi_i32(t0, arg2, 0x3F);
6850 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6851 tcg_gen_sar_i32(ret, arg1, t0);
6852 tcg_gen_br(l2);
6853 gen_set_label(l1);
6854 tcg_gen_movi_i32(ret, 0);
6855 tcg_gen_br(l2);
6856 tcg_temp_free_i32(t0);
6857 }
6858 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6859 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6860 {
6861 TCGv_i32 t0;
6862 int l1, l2;
6863
6864 l1 = gen_new_label();
6865 l2 = gen_new_label();
6866 t0 = tcg_temp_local_new_i32();
6867 /* No error here: 6 bits are used */
6868 tcg_gen_andi_i32(t0, arg2, 0x3F);
6869 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6870 tcg_gen_shl_i32(ret, arg1, t0);
6871 tcg_gen_br(l2);
6872 gen_set_label(l1);
6873 tcg_gen_movi_i32(ret, 0);
6874 tcg_gen_br(l2);
6875 tcg_temp_free_i32(t0);
6876 }
6877 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6878 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6879 {
6880 TCGv_i32 t0 = tcg_temp_new_i32();
6881 tcg_gen_andi_i32(t0, arg2, 0x1F);
6882 tcg_gen_rotl_i32(ret, arg1, t0);
6883 tcg_temp_free_i32(t0);
6884 }
6885 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6886 static always_inline void gen_evmergehi (DisasContext *ctx)
6887 {
6888 if (unlikely(!ctx->spe_enabled)) {
6889 gen_exception(ctx, POWERPC_EXCP_APU);
6890 return;
6891 }
6892 #if defined(TARGET_PPC64)
6893 TCGv t0 = tcg_temp_new();
6894 TCGv t1 = tcg_temp_new();
6895 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6896 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6897 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6898 tcg_temp_free(t0);
6899 tcg_temp_free(t1);
6900 #else
6901 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6902 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6903 #endif
6904 }
6905 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6906 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6907 {
6908 tcg_gen_sub_i32(ret, arg2, arg1);
6909 }
6910 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6911
6912 /* SPE arithmetic immediate */
6913 #if defined(TARGET_PPC64)
6914 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6915 static always_inline void gen_##name (DisasContext *ctx) \
6916 { \
6917 if (unlikely(!ctx->spe_enabled)) { \
6918 gen_exception(ctx, POWERPC_EXCP_APU); \
6919 return; \
6920 } \
6921 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6922 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6923 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6924 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6925 tcg_op(t0, t0, rA(ctx->opcode)); \
6926 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6927 tcg_gen_trunc_i64_i32(t1, t2); \
6928 tcg_temp_free_i64(t2); \
6929 tcg_op(t1, t1, rA(ctx->opcode)); \
6930 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6931 tcg_temp_free_i32(t0); \
6932 tcg_temp_free_i32(t1); \
6933 }
6934 #else
6935 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6936 static always_inline void gen_##name (DisasContext *ctx) \
6937 { \
6938 if (unlikely(!ctx->spe_enabled)) { \
6939 gen_exception(ctx, POWERPC_EXCP_APU); \
6940 return; \
6941 } \
6942 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6943 rA(ctx->opcode)); \
6944 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6945 rA(ctx->opcode)); \
6946 }
6947 #endif
6948 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6949 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6950
6951 /* SPE comparison */
6952 #if defined(TARGET_PPC64)
6953 #define GEN_SPEOP_COMP(name, tcg_cond) \
6954 static always_inline void gen_##name (DisasContext *ctx) \
6955 { \
6956 if (unlikely(!ctx->spe_enabled)) { \
6957 gen_exception(ctx, POWERPC_EXCP_APU); \
6958 return; \
6959 } \
6960 int l1 = gen_new_label(); \
6961 int l2 = gen_new_label(); \
6962 int l3 = gen_new_label(); \
6963 int l4 = gen_new_label(); \
6964 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6965 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6966 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6967 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6968 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6969 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6970 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6971 tcg_gen_br(l2); \
6972 gen_set_label(l1); \
6973 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6974 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6975 gen_set_label(l2); \
6976 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6977 tcg_gen_trunc_i64_i32(t0, t2); \
6978 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6979 tcg_gen_trunc_i64_i32(t1, t2); \
6980 tcg_temp_free_i64(t2); \
6981 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6982 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6983 ~(CRF_CH | CRF_CH_AND_CL)); \
6984 tcg_gen_br(l4); \
6985 gen_set_label(l3); \
6986 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6987 CRF_CH | CRF_CH_OR_CL); \
6988 gen_set_label(l4); \
6989 tcg_temp_free_i32(t0); \
6990 tcg_temp_free_i32(t1); \
6991 }
6992 #else
6993 #define GEN_SPEOP_COMP(name, tcg_cond) \
6994 static always_inline void gen_##name (DisasContext *ctx) \
6995 { \
6996 if (unlikely(!ctx->spe_enabled)) { \
6997 gen_exception(ctx, POWERPC_EXCP_APU); \
6998 return; \
6999 } \
7000 int l1 = gen_new_label(); \
7001 int l2 = gen_new_label(); \
7002 int l3 = gen_new_label(); \
7003 int l4 = gen_new_label(); \
7004 \
7005 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7006 cpu_gpr[rB(ctx->opcode)], l1); \
7007 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7008 tcg_gen_br(l2); \
7009 gen_set_label(l1); \
7010 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7011 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7012 gen_set_label(l2); \
7013 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7014 cpu_gprh[rB(ctx->opcode)], l3); \
7015 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7016 ~(CRF_CH | CRF_CH_AND_CL)); \
7017 tcg_gen_br(l4); \
7018 gen_set_label(l3); \
7019 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7020 CRF_CH | CRF_CH_OR_CL); \
7021 gen_set_label(l4); \
7022 }
7023 #endif
7024 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7025 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7026 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7027 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7028 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7029
7030 /* SPE misc */
7031 static always_inline void gen_brinc (DisasContext *ctx)
7032 {
7033 /* Note: brinc is usable even if SPE is disabled */
7034 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7035 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7036 }
7037 static always_inline void gen_evmergelo (DisasContext *ctx)
7038 {
7039 if (unlikely(!ctx->spe_enabled)) {
7040 gen_exception(ctx, POWERPC_EXCP_APU);
7041 return;
7042 }
7043 #if defined(TARGET_PPC64)
7044 TCGv t0 = tcg_temp_new();
7045 TCGv t1 = tcg_temp_new();
7046 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7047 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7048 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7049 tcg_temp_free(t0);
7050 tcg_temp_free(t1);
7051 #else
7052 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7053 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7054 #endif
7055 }
7056 static always_inline void gen_evmergehilo (DisasContext *ctx)
7057 {
7058 if (unlikely(!ctx->spe_enabled)) {
7059 gen_exception(ctx, POWERPC_EXCP_APU);
7060 return;
7061 }
7062 #if defined(TARGET_PPC64)
7063 TCGv t0 = tcg_temp_new();
7064 TCGv t1 = tcg_temp_new();
7065 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7066 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7067 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7068 tcg_temp_free(t0);
7069 tcg_temp_free(t1);
7070 #else
7071 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7072 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7073 #endif
7074 }
7075 static always_inline void gen_evmergelohi (DisasContext *ctx)
7076 {
7077 if (unlikely(!ctx->spe_enabled)) {
7078 gen_exception(ctx, POWERPC_EXCP_APU);
7079 return;
7080 }
7081 #if defined(TARGET_PPC64)
7082 TCGv t0 = tcg_temp_new();
7083 TCGv t1 = tcg_temp_new();
7084 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7085 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7086 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7087 tcg_temp_free(t0);
7088 tcg_temp_free(t1);
7089 #else
7090 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7091 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7092 #endif
7093 }
7094 static always_inline void gen_evsplati (DisasContext *ctx)
7095 {
7096 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
7097
7098 #if defined(TARGET_PPC64)
7099 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7100 #else
7101 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7102 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7103 #endif
7104 }
7105 static always_inline void gen_evsplatfi (DisasContext *ctx)
7106 {
7107 uint64_t imm = rA(ctx->opcode) << 11;
7108
7109 #if defined(TARGET_PPC64)
7110 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7111 #else
7112 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7113 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7114 #endif
7115 }
7116
7117 static always_inline void gen_evsel (DisasContext *ctx)
7118 {
7119 int l1 = gen_new_label();
7120 int l2 = gen_new_label();
7121 int l3 = gen_new_label();
7122 int l4 = gen_new_label();
7123 TCGv_i32 t0 = tcg_temp_local_new_i32();
7124 #if defined(TARGET_PPC64)
7125 TCGv t1 = tcg_temp_local_new();
7126 TCGv t2 = tcg_temp_local_new();
7127 #endif
7128 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7129 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7130 #if defined(TARGET_PPC64)
7131 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7132 #else
7133 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7134 #endif
7135 tcg_gen_br(l2);
7136 gen_set_label(l1);
7137 #if defined(TARGET_PPC64)
7138 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7139 #else
7140 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7141 #endif
7142 gen_set_label(l2);
7143 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7144 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7145 #if defined(TARGET_PPC64)
7146 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7147 #else
7148 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7149 #endif
7150 tcg_gen_br(l4);
7151 gen_set_label(l3);
7152 #if defined(TARGET_PPC64)
7153 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7154 #else
7155 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7156 #endif
7157 gen_set_label(l4);
7158 tcg_temp_free_i32(t0);
7159 #if defined(TARGET_PPC64)
7160 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7161 tcg_temp_free(t1);
7162 tcg_temp_free(t2);
7163 #endif
7164 }
7165 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7166 {
7167 gen_evsel(ctx);
7168 }
7169 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7170 {
7171 gen_evsel(ctx);
7172 }
7173 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7174 {
7175 gen_evsel(ctx);
7176 }
7177 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7178 {
7179 gen_evsel(ctx);
7180 }
7181
7182 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7183 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7184 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7185 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7186 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7187 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7188 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7189 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7190 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7191 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7192 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7193 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7194 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7195 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7196 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7197 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7198 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7199 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7200 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7201 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7202 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7203 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7204 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7205 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7206 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7207
7208 /* SPE load and stores */
7209 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
7210 {
7211 target_ulong uimm = rB(ctx->opcode);
7212
7213 if (rA(ctx->opcode) == 0) {
7214 tcg_gen_movi_tl(EA, uimm << sh);
7215 } else {
7216 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7217 #if defined(TARGET_PPC64)
7218 if (!ctx->sf_mode) {
7219 tcg_gen_ext32u_tl(EA, EA);
7220 }
7221 #endif
7222 }
7223 }
7224
7225 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7226 {
7227 #if defined(TARGET_PPC64)
7228 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7229 #else
7230 TCGv_i64 t0 = tcg_temp_new_i64();
7231 gen_qemu_ld64(ctx, t0, addr);
7232 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7233 tcg_gen_shri_i64(t0, t0, 32);
7234 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7235 tcg_temp_free_i64(t0);
7236 #endif
7237 }
7238
7239 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7240 {
7241 #if defined(TARGET_PPC64)
7242 TCGv t0 = tcg_temp_new();
7243 gen_qemu_ld32u(ctx, t0, addr);
7244 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7245 gen_addr_add(ctx, addr, addr, 4);
7246 gen_qemu_ld32u(ctx, t0, addr);
7247 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7248 tcg_temp_free(t0);
7249 #else
7250 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7251 gen_addr_add(ctx, addr, addr, 4);
7252 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7253 #endif
7254 }
7255
7256 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7257 {
7258 TCGv t0 = tcg_temp_new();
7259 #if defined(TARGET_PPC64)
7260 gen_qemu_ld16u(ctx, t0, addr);
7261 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7262 gen_addr_add(ctx, addr, addr, 2);
7263 gen_qemu_ld16u(ctx, t0, addr);
7264 tcg_gen_shli_tl(t0, t0, 32);
7265 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7266 gen_addr_add(ctx, addr, addr, 2);
7267 gen_qemu_ld16u(ctx, t0, addr);
7268 tcg_gen_shli_tl(t0, t0, 16);
7269 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7270 gen_addr_add(ctx, addr, addr, 2);
7271 gen_qemu_ld16u(ctx, t0, addr);
7272 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7273 #else
7274 gen_qemu_ld16u(ctx, t0, addr);
7275 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7276 gen_addr_add(ctx, addr, addr, 2);
7277 gen_qemu_ld16u(ctx, t0, addr);
7278 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7279 gen_addr_add(ctx, addr, addr, 2);
7280 gen_qemu_ld16u(ctx, t0, addr);
7281 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7282 gen_addr_add(ctx, addr, addr, 2);
7283 gen_qemu_ld16u(ctx, t0, addr);
7284 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7285 #endif
7286 tcg_temp_free(t0);
7287 }
7288
7289 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7290 {
7291 TCGv t0 = tcg_temp_new();
7292 gen_qemu_ld16u(ctx, t0, addr);
7293 #if defined(TARGET_PPC64)
7294 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7295 tcg_gen_shli_tl(t0, t0, 16);
7296 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7297 #else
7298 tcg_gen_shli_tl(t0, t0, 16);
7299 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7300 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7301 #endif
7302 tcg_temp_free(t0);
7303 }
7304
7305 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7306 {
7307 TCGv t0 = tcg_temp_new();
7308 gen_qemu_ld16u(ctx, t0, addr);
7309 #if defined(TARGET_PPC64)
7310 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7311 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7312 #else
7313 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7314 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7315 #endif
7316 tcg_temp_free(t0);
7317 }
7318
7319 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7320 {
7321 TCGv t0 = tcg_temp_new();
7322 gen_qemu_ld16s(ctx, t0, addr);
7323 #if defined(TARGET_PPC64)
7324 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7325 tcg_gen_ext32u_tl(t0, t0);
7326 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7327 #else
7328 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7329 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7330 #endif
7331 tcg_temp_free(t0);
7332 }
7333
7334 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7335 {
7336 TCGv t0 = tcg_temp_new();
7337 #if defined(TARGET_PPC64)
7338 gen_qemu_ld16u(ctx, t0, addr);
7339 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7340 gen_addr_add(ctx, addr, addr, 2);
7341 gen_qemu_ld16u(ctx, t0, addr);
7342 tcg_gen_shli_tl(t0, t0, 16);
7343 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7344 #else
7345 gen_qemu_ld16u(ctx, t0, addr);
7346 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7347 gen_addr_add(ctx, addr, addr, 2);
7348 gen_qemu_ld16u(ctx, t0, addr);
7349 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7350 #endif
7351 tcg_temp_free(t0);
7352 }
7353
7354 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7355 {
7356 #if defined(TARGET_PPC64)
7357 TCGv t0 = tcg_temp_new();
7358 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7359 gen_addr_add(ctx, addr, addr, 2);
7360 gen_qemu_ld16u(ctx, t0, addr);
7361 tcg_gen_shli_tl(t0, t0, 32);
7362 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7363 tcg_temp_free(t0);
7364 #else
7365 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7366 gen_addr_add(ctx, addr, addr, 2);
7367 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7368 #endif
7369 }
7370
7371 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7372 {
7373 #if defined(TARGET_PPC64)
7374 TCGv t0 = tcg_temp_new();
7375 gen_qemu_ld16s(ctx, t0, addr);
7376 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7377 gen_addr_add(ctx, addr, addr, 2);
7378 gen_qemu_ld16s(ctx, t0, addr);
7379 tcg_gen_shli_tl(t0, t0, 32);
7380 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7381 tcg_temp_free(t0);
7382 #else
7383 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7384 gen_addr_add(ctx, addr, addr, 2);
7385 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7386 #endif
7387 }
7388
7389 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7390 {
7391 TCGv t0 = tcg_temp_new();
7392 gen_qemu_ld32u(ctx, t0, addr);
7393 #if defined(TARGET_PPC64)
7394 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7395 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7396 #else
7397 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7398 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7399 #endif
7400 tcg_temp_free(t0);
7401 }
7402
7403 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7404 {
7405 TCGv t0 = tcg_temp_new();
7406 #if defined(TARGET_PPC64)
7407 gen_qemu_ld16u(ctx, t0, addr);
7408 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7409 tcg_gen_shli_tl(t0, t0, 32);
7410 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7411 gen_addr_add(ctx, addr, addr, 2);
7412 gen_qemu_ld16u(ctx, t0, addr);
7413 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7414 tcg_gen_shli_tl(t0, t0, 16);
7415 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7416 #else
7417 gen_qemu_ld16u(ctx, t0, addr);
7418 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7419 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7420 gen_addr_add(ctx, addr, addr, 2);
7421 gen_qemu_ld16u(ctx, t0, addr);
7422 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7423 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7424 #endif
7425 tcg_temp_free(t0);
7426 }
7427
7428 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7429 {
7430 #if defined(TARGET_PPC64)
7431 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7432 #else
7433 TCGv_i64 t0 = tcg_temp_new_i64();
7434 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7435 gen_qemu_st64(ctx, t0, addr);
7436 tcg_temp_free_i64(t0);
7437 #endif
7438 }
7439
7440 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7441 {
7442 #if defined(TARGET_PPC64)
7443 TCGv t0 = tcg_temp_new();
7444 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7445 gen_qemu_st32(ctx, t0, addr);
7446 tcg_temp_free(t0);
7447 #else
7448 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7449 #endif
7450 gen_addr_add(ctx, addr, addr, 4);
7451 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7452 }
7453
7454 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7455 {
7456 TCGv t0 = tcg_temp_new();
7457 #if defined(TARGET_PPC64)
7458 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7459 #else
7460 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7461 #endif
7462 gen_qemu_st16(ctx, t0, addr);
7463 gen_addr_add(ctx, addr, addr, 2);
7464 #if defined(TARGET_PPC64)
7465 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7466 gen_qemu_st16(ctx, t0, addr);
7467 #else
7468 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7469 #endif
7470 gen_addr_add(ctx, addr, addr, 2);
7471 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7472 gen_qemu_st16(ctx, t0, addr);
7473 tcg_temp_free(t0);
7474 gen_addr_add(ctx, addr, addr, 2);
7475 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7476 }
7477
7478 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7479 {
7480 TCGv t0 = tcg_temp_new();
7481 #if defined(TARGET_PPC64)
7482 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7483 #else
7484 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7485 #endif
7486 gen_qemu_st16(ctx, t0, addr);
7487 gen_addr_add(ctx, addr, addr, 2);
7488 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7489 gen_qemu_st16(ctx, t0, addr);
7490 tcg_temp_free(t0);
7491 }
7492
7493 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7494 {
7495 #if defined(TARGET_PPC64)
7496 TCGv t0 = tcg_temp_new();
7497 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7498 gen_qemu_st16(ctx, t0, addr);
7499 tcg_temp_free(t0);
7500 #else
7501 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7502 #endif
7503 gen_addr_add(ctx, addr, addr, 2);
7504 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7505 }
7506
7507 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7508 {
7509 #if defined(TARGET_PPC64)
7510 TCGv t0 = tcg_temp_new();
7511 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7512 gen_qemu_st32(ctx, t0, addr);
7513 tcg_temp_free(t0);
7514 #else
7515 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7516 #endif
7517 }
7518
7519 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7520 {
7521 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7522 }
7523
7524 #define GEN_SPEOP_LDST(name, opc2, sh) \
7525 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7526 { \
7527 TCGv t0; \
7528 if (unlikely(!ctx->spe_enabled)) { \
7529 gen_exception(ctx, POWERPC_EXCP_APU); \
7530 return; \
7531 } \
7532 gen_set_access_type(ctx, ACCESS_INT); \
7533 t0 = tcg_temp_new(); \
7534 if (Rc(ctx->opcode)) { \
7535 gen_addr_spe_imm_index(ctx, t0, sh); \
7536 } else { \
7537 gen_addr_reg_index(ctx, t0); \
7538 } \
7539 gen_op_##name(ctx, t0); \
7540 tcg_temp_free(t0); \
7541 }
7542
7543 GEN_SPEOP_LDST(evldd, 0x00, 3);
7544 GEN_SPEOP_LDST(evldw, 0x01, 3);
7545 GEN_SPEOP_LDST(evldh, 0x02, 3);
7546 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7547 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7548 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7549 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7550 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7551 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7552 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7553 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7554
7555 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7556 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7557 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7558 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7559 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7560 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7561 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7562
7563 /* Multiply and add - TODO */
7564 #if 0
7565 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7566 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7567 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7568 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7569 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7570 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7571 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7572 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7573 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7574 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7575 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7576 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7577
7578 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7579 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7580 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7581 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7582 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7583 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7584 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7585 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7586 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7587 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7588 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7589 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7590 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7591 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7592
7593 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7594 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7595 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7596 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7597 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7598 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7599
7600 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7601 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7602 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7603 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7604 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7605 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7606 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7607 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7608 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7609 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7610 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7611 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7612
7613 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7614 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7615 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7616 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7617 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7618
7619 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7620 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7621 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7622 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7623 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7624 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7625 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7626 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7627 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7628 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7629 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7630 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7631
7632 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7633 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7634 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7635 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7636 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7637 #endif
7638
7639 /*** SPE floating-point extension ***/
7640 #if defined(TARGET_PPC64)
7641 #define GEN_SPEFPUOP_CONV_32_32(name) \
7642 static always_inline void gen_##name (DisasContext *ctx) \
7643 { \
7644 TCGv_i32 t0; \
7645 TCGv t1; \
7646 t0 = tcg_temp_new_i32(); \
7647 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7648 gen_helper_##name(t0, t0); \
7649 t1 = tcg_temp_new(); \
7650 tcg_gen_extu_i32_tl(t1, t0); \
7651 tcg_temp_free_i32(t0); \
7652 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7653 0xFFFFFFFF00000000ULL); \
7654 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7655 tcg_temp_free(t1); \
7656 }
7657 #define GEN_SPEFPUOP_CONV_32_64(name) \
7658 static always_inline void gen_##name (DisasContext *ctx) \
7659 { \
7660 TCGv_i32 t0; \
7661 TCGv t1; \
7662 t0 = tcg_temp_new_i32(); \
7663 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7664 t1 = tcg_temp_new(); \
7665 tcg_gen_extu_i32_tl(t1, t0); \
7666 tcg_temp_free_i32(t0); \
7667 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7668 0xFFFFFFFF00000000ULL); \
7669 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7670 tcg_temp_free(t1); \
7671 }
7672 #define GEN_SPEFPUOP_CONV_64_32(name) \
7673 static always_inline void gen_##name (DisasContext *ctx) \
7674 { \
7675 TCGv_i32 t0 = tcg_temp_new_i32(); \
7676 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7677 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7678 tcg_temp_free_i32(t0); \
7679 }
7680 #define GEN_SPEFPUOP_CONV_64_64(name) \
7681 static always_inline void gen_##name (DisasContext *ctx) \
7682 { \
7683 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7684 }
7685 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7686 static always_inline void gen_##name (DisasContext *ctx) \
7687 { \
7688 TCGv_i32 t0, t1; \
7689 TCGv_i64 t2; \
7690 if (unlikely(!ctx->spe_enabled)) { \
7691 gen_exception(ctx, POWERPC_EXCP_APU); \
7692 return; \
7693 } \
7694 t0 = tcg_temp_new_i32(); \
7695 t1 = tcg_temp_new_i32(); \
7696 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7697 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7698 gen_helper_##name(t0, t0, t1); \
7699 tcg_temp_free_i32(t1); \
7700 t2 = tcg_temp_new(); \
7701 tcg_gen_extu_i32_tl(t2, t0); \
7702 tcg_temp_free_i32(t0); \
7703 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7704 0xFFFFFFFF00000000ULL); \
7705 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7706 tcg_temp_free(t2); \
7707 }
7708 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7709 static always_inline void gen_##name (DisasContext *ctx) \
7710 { \
7711 if (unlikely(!ctx->spe_enabled)) { \
7712 gen_exception(ctx, POWERPC_EXCP_APU); \
7713 return; \
7714 } \
7715 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7716 cpu_gpr[rB(ctx->opcode)]); \
7717 }
7718 #define GEN_SPEFPUOP_COMP_32(name) \
7719 static always_inline void gen_##name (DisasContext *ctx) \
7720 { \
7721 TCGv_i32 t0, t1; \
7722 if (unlikely(!ctx->spe_enabled)) { \
7723 gen_exception(ctx, POWERPC_EXCP_APU); \
7724 return; \
7725 } \
7726 t0 = tcg_temp_new_i32(); \
7727 t1 = tcg_temp_new_i32(); \
7728 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7729 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7730 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7731 tcg_temp_free_i32(t0); \
7732 tcg_temp_free_i32(t1); \
7733 }
7734 #define GEN_SPEFPUOP_COMP_64(name) \
7735 static always_inline void gen_##name (DisasContext *ctx) \
7736 { \
7737 if (unlikely(!ctx->spe_enabled)) { \
7738 gen_exception(ctx, POWERPC_EXCP_APU); \
7739 return; \
7740 } \
7741 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7742 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7743 }
7744 #else
7745 #define GEN_SPEFPUOP_CONV_32_32(name) \
7746 static always_inline void gen_##name (DisasContext *ctx) \
7747 { \
7748 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7749 }
7750 #define GEN_SPEFPUOP_CONV_32_64(name) \
7751 static always_inline void gen_##name (DisasContext *ctx) \
7752 { \
7753 TCGv_i64 t0 = tcg_temp_new_i64(); \
7754 gen_load_gpr64(t0, rB(ctx->opcode)); \
7755 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7756 tcg_temp_free_i64(t0); \
7757 }
7758 #define GEN_SPEFPUOP_CONV_64_32(name) \
7759 static always_inline void gen_##name (DisasContext *ctx) \
7760 { \
7761 TCGv_i64 t0 = tcg_temp_new_i64(); \
7762 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7763 gen_store_gpr64(rD(ctx->opcode), t0); \
7764 tcg_temp_free_i64(t0); \
7765 }
7766 #define GEN_SPEFPUOP_CONV_64_64(name) \
7767 static always_inline void gen_##name (DisasContext *ctx) \
7768 { \
7769 TCGv_i64 t0 = tcg_temp_new_i64(); \
7770 gen_load_gpr64(t0, rB(ctx->opcode)); \
7771 gen_helper_##name(t0, t0); \
7772 gen_store_gpr64(rD(ctx->opcode), t0); \
7773 tcg_temp_free_i64(t0); \
7774 }
7775 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7776 static always_inline void gen_##name (DisasContext *ctx) \
7777 { \
7778 if (unlikely(!ctx->spe_enabled)) { \
7779 gen_exception(ctx, POWERPC_EXCP_APU); \
7780 return; \
7781 } \
7782 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7783 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7784 }
7785 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7786 static always_inline void gen_##name (DisasContext *ctx) \
7787 { \
7788 TCGv_i64 t0, t1; \
7789 if (unlikely(!ctx->spe_enabled)) { \
7790 gen_exception(ctx, POWERPC_EXCP_APU); \
7791 return; \
7792 } \
7793 t0 = tcg_temp_new_i64(); \
7794 t1 = tcg_temp_new_i64(); \
7795 gen_load_gpr64(t0, rA(ctx->opcode)); \
7796 gen_load_gpr64(t1, rB(ctx->opcode)); \
7797 gen_helper_##name(t0, t0, t1); \
7798 gen_store_gpr64(rD(ctx->opcode), t0); \
7799 tcg_temp_free_i64(t0); \
7800 tcg_temp_free_i64(t1); \
7801 }
7802 #define GEN_SPEFPUOP_COMP_32(name) \
7803 static always_inline void gen_##name (DisasContext *ctx) \
7804 { \
7805 if (unlikely(!ctx->spe_enabled)) { \
7806 gen_exception(ctx, POWERPC_EXCP_APU); \
7807 return; \
7808 } \
7809 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7810 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7811 }
7812 #define GEN_SPEFPUOP_COMP_64(name) \
7813 static always_inline void gen_##name (DisasContext *ctx) \
7814 { \
7815 TCGv_i64 t0, t1; \
7816 if (unlikely(!ctx->spe_enabled)) { \
7817 gen_exception(ctx, POWERPC_EXCP_APU); \
7818 return; \
7819 } \
7820 t0 = tcg_temp_new_i64(); \
7821 t1 = tcg_temp_new_i64(); \
7822 gen_load_gpr64(t0, rA(ctx->opcode)); \
7823 gen_load_gpr64(t1, rB(ctx->opcode)); \
7824 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7825 tcg_temp_free_i64(t0); \
7826 tcg_temp_free_i64(t1); \
7827 }
7828 #endif
7829
7830 /* Single precision floating-point vectors operations */
7831 /* Arithmetic */
7832 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7833 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7834 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7835 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7836 static always_inline void gen_evfsabs (DisasContext *ctx)
7837 {
7838 if (unlikely(!ctx->spe_enabled)) {
7839 gen_exception(ctx, POWERPC_EXCP_APU);
7840 return;
7841 }
7842 #if defined(TARGET_PPC64)
7843 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7844 #else
7845 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7846 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7847 #endif
7848 }
7849 static always_inline void gen_evfsnabs (DisasContext *ctx)
7850 {
7851 if (unlikely(!ctx->spe_enabled)) {
7852 gen_exception(ctx, POWERPC_EXCP_APU);
7853 return;
7854 }
7855 #if defined(TARGET_PPC64)
7856 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7857 #else
7858 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7859 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7860 #endif
7861 }
7862 static always_inline void gen_evfsneg (DisasContext *ctx)
7863 {
7864 if (unlikely(!ctx->spe_enabled)) {
7865 gen_exception(ctx, POWERPC_EXCP_APU);
7866 return;
7867 }
7868 #if defined(TARGET_PPC64)
7869 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7870 #else
7871 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7872 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7873 #endif
7874 }
7875
7876 /* Conversion */
7877 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7878 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7879 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7880 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7881 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7882 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7883 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7884 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7885 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7886 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7887
7888 /* Comparison */
7889 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7890 GEN_SPEFPUOP_COMP_64(evfscmplt);
7891 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7892 GEN_SPEFPUOP_COMP_64(evfststgt);
7893 GEN_SPEFPUOP_COMP_64(evfststlt);
7894 GEN_SPEFPUOP_COMP_64(evfststeq);
7895
7896 /* Opcodes definitions */
7897 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7898 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7899 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7900 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7901 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7902 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7903 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7904 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7905 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7906 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7907 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7908 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7909 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7910 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7911
7912 /* Single precision floating-point operations */
7913 /* Arithmetic */
7914 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7915 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7916 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7917 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7918 static always_inline void gen_efsabs (DisasContext *ctx)
7919 {
7920 if (unlikely(!ctx->spe_enabled)) {
7921 gen_exception(ctx, POWERPC_EXCP_APU);
7922 return;
7923 }
7924 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7925 }
7926 static always_inline void gen_efsnabs (DisasContext *ctx)
7927 {
7928 if (unlikely(!ctx->spe_enabled)) {
7929 gen_exception(ctx, POWERPC_EXCP_APU);
7930 return;
7931 }
7932 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7933 }
7934 static always_inline void gen_efsneg (DisasContext *ctx)
7935 {
7936 if (unlikely(!ctx->spe_enabled)) {
7937 gen_exception(ctx, POWERPC_EXCP_APU);
7938 return;
7939 }
7940 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7941 }
7942
7943 /* Conversion */
7944 GEN_SPEFPUOP_CONV_32_32(efscfui);
7945 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7946 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7947 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7948 GEN_SPEFPUOP_CONV_32_32(efsctui);
7949 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7950 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7951 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7952 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7953 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7954 GEN_SPEFPUOP_CONV_32_64(efscfd);
7955
7956 /* Comparison */
7957 GEN_SPEFPUOP_COMP_32(efscmpgt);
7958 GEN_SPEFPUOP_COMP_32(efscmplt);
7959 GEN_SPEFPUOP_COMP_32(efscmpeq);
7960 GEN_SPEFPUOP_COMP_32(efststgt);
7961 GEN_SPEFPUOP_COMP_32(efststlt);
7962 GEN_SPEFPUOP_COMP_32(efststeq);
7963
7964 /* Opcodes definitions */
7965 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7966 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7967 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7968 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7969 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7970 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7971 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7972 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7973 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7974 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7975 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7976 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7977 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7978 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7979
7980 /* Double precision floating-point operations */
7981 /* Arithmetic */
7982 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7983 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7984 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7985 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7986 static always_inline void gen_efdabs (DisasContext *ctx)
7987 {
7988 if (unlikely(!ctx->spe_enabled)) {
7989 gen_exception(ctx, POWERPC_EXCP_APU);
7990 return;
7991 }
7992 #if defined(TARGET_PPC64)
7993 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7994 #else
7995 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7996 #endif
7997 }
7998 static always_inline void gen_efdnabs (DisasContext *ctx)
7999 {
8000 if (unlikely(!ctx->spe_enabled)) {
8001 gen_exception(ctx, POWERPC_EXCP_APU);
8002 return;
8003 }
8004 #if defined(TARGET_PPC64)
8005 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8006 #else
8007 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8008 #endif
8009 }
8010 static always_inline void gen_efdneg (DisasContext *ctx)
8011 {
8012 if (unlikely(!ctx->spe_enabled)) {
8013 gen_exception(ctx, POWERPC_EXCP_APU);
8014 return;
8015 }
8016 #if defined(TARGET_PPC64)
8017 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8018 #else
8019 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8020 #endif
8021 }
8022
8023 /* Conversion */
8024 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8025 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8026 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8027 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8028 GEN_SPEFPUOP_CONV_32_64(efdctui);
8029 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8030 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8031 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8032 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8033 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8034 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8035 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8036 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8037 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8038 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8039
8040 /* Comparison */
8041 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8042 GEN_SPEFPUOP_COMP_64(efdcmplt);
8043 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8044 GEN_SPEFPUOP_COMP_64(efdtstgt);
8045 GEN_SPEFPUOP_COMP_64(efdtstlt);
8046 GEN_SPEFPUOP_COMP_64(efdtsteq);
8047
8048 /* Opcodes definitions */
8049 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8050 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8051 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8052 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8053 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8054 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8055 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8056 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8057 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8058 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8059 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8060 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8061 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8062 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8063 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8064 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8065
8066 /* End opcode list */
8067 GEN_OPCODE_MARK(end);
8068
8069 #include "translate_init.c"
8070 #include "helper_regs.h"
8071
8072 /*****************************************************************************/
8073 /* Misc PowerPC helpers */
8074 void cpu_dump_state (CPUState *env, FILE *f,
8075 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8076 int flags)
8077 {
8078 #define RGPL 4
8079 #define RFPL 4
8080
8081 int i;
8082
8083 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
8084 env->nip, env->lr, env->ctr, env->xer);
8085 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8086 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
8087 #if !defined(NO_TIMER_DUMP)
8088 cpu_fprintf(f, "TB %08x %08x "
8089 #if !defined(CONFIG_USER_ONLY)
8090 "DECR %08x"
8091 #endif
8092 "\n",
8093 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8094 #if !defined(CONFIG_USER_ONLY)
8095 , cpu_ppc_load_decr(env)
8096 #endif
8097 );
8098 #endif
8099 for (i = 0; i < 32; i++) {
8100 if ((i & (RGPL - 1)) == 0)
8101 cpu_fprintf(f, "GPR%02d", i);
8102 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
8103 if ((i & (RGPL - 1)) == (RGPL - 1))
8104 cpu_fprintf(f, "\n");
8105 }
8106 cpu_fprintf(f, "CR ");
8107 for (i = 0; i < 8; i++)
8108 cpu_fprintf(f, "%01x", env->crf[i]);
8109 cpu_fprintf(f, " [");
8110 for (i = 0; i < 8; i++) {
8111 char a = '-';
8112 if (env->crf[i] & 0x08)
8113 a = 'L';
8114 else if (env->crf[i] & 0x04)
8115 a = 'G';
8116 else if (env->crf[i] & 0x02)
8117 a = 'E';
8118 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8119 }
8120 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
8121 for (i = 0; i < 32; i++) {
8122 if ((i & (RFPL - 1)) == 0)
8123 cpu_fprintf(f, "FPR%02d", i);
8124 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
8125 if ((i & (RFPL - 1)) == (RFPL - 1))
8126 cpu_fprintf(f, "\n");
8127 }
8128 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
8129 #if !defined(CONFIG_USER_ONLY)
8130 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
8131 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
8132 #endif
8133
8134 #undef RGPL
8135 #undef RFPL
8136 }
8137
8138 void cpu_dump_statistics (CPUState *env, FILE*f,
8139 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8140 int flags)
8141 {
8142 #if defined(DO_PPC_STATISTICS)
8143 opc_handler_t **t1, **t2, **t3, *handler;
8144 int op1, op2, op3;
8145
8146 t1 = env->opcodes;
8147 for (op1 = 0; op1 < 64; op1++) {
8148 handler = t1[op1];
8149 if (is_indirect_opcode(handler)) {
8150 t2 = ind_table(handler);
8151 for (op2 = 0; op2 < 32; op2++) {
8152 handler = t2[op2];
8153 if (is_indirect_opcode(handler)) {
8154 t3 = ind_table(handler);
8155 for (op3 = 0; op3 < 32; op3++) {
8156 handler = t3[op3];
8157 if (handler->count == 0)
8158 continue;
8159 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8160 "%016llx %lld\n",
8161 op1, op2, op3, op1, (op3 << 5) | op2,
8162 handler->oname,
8163 handler->count, handler->count);
8164 }
8165 } else {
8166 if (handler->count == 0)
8167 continue;
8168 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8169 "%016llx %lld\n",
8170 op1, op2, op1, op2, handler->oname,
8171 handler->count, handler->count);
8172 }
8173 }
8174 } else {
8175 if (handler->count == 0)
8176 continue;
8177 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8178 op1, op1, handler->oname,
8179 handler->count, handler->count);
8180 }
8181 }
8182 #endif
8183 }
8184
8185 /*****************************************************************************/
8186 static always_inline void gen_intermediate_code_internal (CPUState *env,
8187 TranslationBlock *tb,
8188 int search_pc)
8189 {
8190 DisasContext ctx, *ctxp = &ctx;
8191 opc_handler_t **table, *handler;
8192 target_ulong pc_start;
8193 uint16_t *gen_opc_end;
8194 CPUBreakpoint *bp;
8195 int j, lj = -1;
8196 int num_insns;
8197 int max_insns;
8198
8199 pc_start = tb->pc;
8200 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8201 ctx.nip = pc_start;
8202 ctx.tb = tb;
8203 ctx.exception = POWERPC_EXCP_NONE;
8204 ctx.spr_cb = env->spr_cb;
8205 ctx.mem_idx = env->mmu_idx;
8206 ctx.access_type = -1;
8207 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
8208 #if defined(TARGET_PPC64)
8209 ctx.sf_mode = msr_sf;
8210 #endif
8211 ctx.fpu_enabled = msr_fp;
8212 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
8213 ctx.spe_enabled = msr_spe;
8214 else
8215 ctx.spe_enabled = 0;
8216 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8217 ctx.altivec_enabled = msr_vr;
8218 else
8219 ctx.altivec_enabled = 0;
8220 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8221 ctx.singlestep_enabled = CPU_SINGLE_STEP;
8222 else
8223 ctx.singlestep_enabled = 0;
8224 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8225 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8226 if (unlikely(env->singlestep_enabled))
8227 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
8228 #if defined (DO_SINGLE_STEP) && 0
8229 /* Single step trace mode */
8230 msr_se = 1;
8231 #endif
8232 num_insns = 0;
8233 max_insns = tb->cflags & CF_COUNT_MASK;
8234 if (max_insns == 0)
8235 max_insns = CF_COUNT_MASK;
8236
8237 gen_icount_start();
8238 /* Set env in case of segfault during code fetch */
8239 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
8240 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8241 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
8242 if (bp->pc == ctx.nip) {
8243 gen_debug_exception(ctxp);
8244 break;
8245 }
8246 }
8247 }
8248 if (unlikely(search_pc)) {
8249 j = gen_opc_ptr - gen_opc_buf;
8250 if (lj < j) {
8251 lj++;
8252 while (lj < j)
8253 gen_opc_instr_start[lj++] = 0;
8254 gen_opc_pc[lj] = ctx.nip;
8255 gen_opc_instr_start[lj] = 1;
8256 gen_opc_icount[lj] = num_insns;
8257 }
8258 }
8259 LOG_DISAS("----------------\n");
8260 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8261 ctx.nip, ctx.mem_idx, (int)msr_ir);
8262 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8263 gen_io_start();
8264 if (unlikely(ctx.le_mode)) {
8265 ctx.opcode = bswap32(ldl_code(ctx.nip));
8266 } else {
8267 ctx.opcode = ldl_code(ctx.nip);
8268 }
8269 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
8270 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
8271 opc3(ctx.opcode), little_endian ? "little" : "big");
8272 ctx.nip += 4;
8273 table = env->opcodes;
8274 num_insns++;
8275 handler = table[opc1(ctx.opcode)];
8276 if (is_indirect_opcode(handler)) {
8277 table = ind_table(handler);
8278 handler = table[opc2(ctx.opcode)];
8279 if (is_indirect_opcode(handler)) {
8280 table = ind_table(handler);
8281 handler = table[opc3(ctx.opcode)];
8282 }
8283 }
8284 /* Is opcode *REALLY* valid ? */
8285 if (unlikely(handler->handler == &gen_invalid)) {
8286 if (qemu_log_enabled()) {
8287 qemu_log("invalid/unsupported opcode: "
8288 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8289 opc1(ctx.opcode), opc2(ctx.opcode),
8290 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8291 } else {
8292 printf("invalid/unsupported opcode: "
8293 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8294 opc1(ctx.opcode), opc2(ctx.opcode),
8295 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8296 }
8297 } else {
8298 if (unlikely((ctx.opcode & handler->inval) != 0)) {
8299 if (qemu_log_enabled()) {
8300 qemu_log("invalid bits: %08x for opcode: "
8301 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8302 ctx.opcode & handler->inval, opc1(ctx.opcode),
8303 opc2(ctx.opcode), opc3(ctx.opcode),
8304 ctx.opcode, ctx.nip - 4);
8305 } else {
8306 printf("invalid bits: %08x for opcode: "
8307 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8308 ctx.opcode & handler->inval, opc1(ctx.opcode),
8309 opc2(ctx.opcode), opc3(ctx.opcode),
8310 ctx.opcode, ctx.nip - 4);
8311 }
8312 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
8313 break;
8314 }
8315 }
8316 (*(handler->handler))(&ctx);
8317 #if defined(DO_PPC_STATISTICS)
8318 handler->count++;
8319 #endif
8320 /* Check trace mode exceptions */
8321 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8322 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8323 ctx.exception != POWERPC_SYSCALL &&
8324 ctx.exception != POWERPC_EXCP_TRAP &&
8325 ctx.exception != POWERPC_EXCP_BRANCH)) {
8326 gen_exception(ctxp, POWERPC_EXCP_TRACE);
8327 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
8328 (env->singlestep_enabled) ||
8329 num_insns >= max_insns)) {
8330 /* if we reach a page boundary or are single stepping, stop
8331 * generation
8332 */
8333 break;
8334 }
8335 #if defined (DO_SINGLE_STEP)
8336 break;
8337 #endif
8338 }
8339 if (tb->cflags & CF_LAST_IO)
8340 gen_io_end();
8341 if (ctx.exception == POWERPC_EXCP_NONE) {
8342 gen_goto_tb(&ctx, 0, ctx.nip);
8343 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8344 if (unlikely(env->singlestep_enabled)) {
8345 gen_debug_exception(ctxp);
8346 }
8347 /* Generate the return instruction */
8348 tcg_gen_exit_tb(0);
8349 }
8350 gen_icount_end(tb, num_insns);
8351 *gen_opc_ptr = INDEX_op_end;
8352 if (unlikely(search_pc)) {
8353 j = gen_opc_ptr - gen_opc_buf;
8354 lj++;
8355 while (lj <= j)
8356 gen_opc_instr_start[lj++] = 0;
8357 } else {
8358 tb->size = ctx.nip - pc_start;
8359 tb->icount = num_insns;
8360 }
8361 #if defined(DEBUG_DISAS)
8362 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
8363 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8364 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8365 int flags;
8366 flags = env->bfd_mach;
8367 flags |= ctx.le_mode << 16;
8368 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8369 log_target_disas(pc_start, ctx.nip - pc_start, flags);
8370 qemu_log("\n");
8371 }
8372 #endif
8373 }
8374
8375 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
8376 {
8377 gen_intermediate_code_internal(env, tb, 0);
8378 }
8379
8380 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
8381 {
8382 gen_intermediate_code_internal(env, tb, 1);
8383 }
8384
8385 void gen_pc_load(CPUState *env, TranslationBlock *tb,
8386 unsigned long searched_pc, int pc_pos, void *puc)
8387 {
8388 env->nip = gen_opc_pc[pc_pos];
8389 }
Samsung s3c2440 and arm920t support for the mini2440 dev board