hw/pxa2xx_lcd.c

   1 /*
   2  * Intel XScale PXA255/270 LCDC emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPLv2.
   8  */
   9
  10 #include "hw.h"
  11 #include "console.h"
  12 #include "pxa.h"
  13 #include "pixel_ops.h"
  14 /* FIXME: For graphic_rotate. Should probably be done in common code.  */
  15 #include "sysemu.h"
  16 #include "framebuffer.h"
  17
  18 struct pxa2xx_lcdc_s {
  19     qemu_irq irq;
  20     int irqlevel;
  21
  22     int invalidated;
  23     DisplayState *ds;
  24     drawfn *line_fn[2];
  25     int dest_width;
  26     int xres, yres;
  27     int pal_for;
  28     int transp;
  29     enum {
  30         pxa_lcdc_2bpp = 1,
  31         pxa_lcdc_4bpp = 2,
  32         pxa_lcdc_8bpp = 3,
  33         pxa_lcdc_16bpp = 4,
  34         pxa_lcdc_18bpp = 5,
  35         pxa_lcdc_18pbpp = 6,
  36         pxa_lcdc_19bpp = 7,
  37         pxa_lcdc_19pbpp = 8,
  38         pxa_lcdc_24bpp = 9,
  39         pxa_lcdc_25bpp = 10,
  40     } bpp;
  41
  42     uint32_t control[6];
  43     uint32_t status[2];
  44     uint32_t ovl1c[2];
  45     uint32_t ovl2c[2];
  46     uint32_t ccr;
  47     uint32_t cmdcr;
  48     uint32_t trgbr;
  49     uint32_t tcr;
  50     uint32_t liidr;
  51     uint8_t bscntr;
  52
  53     struct {
  54         target_phys_addr_t branch;
  55         int up;
  56         uint8_t palette[1024];
  57         uint8_t pbuffer[1024];
  58         void (*redraw)(struct pxa2xx_lcdc_s *s, target_phys_addr_t addr,
  59                         int *miny, int *maxy);
  60
  61         target_phys_addr_t descriptor;
  62         target_phys_addr_t source;
  63         uint32_t id;
  64         uint32_t command;
  65     } dma_ch[7];
  66
  67     qemu_irq vsync_cb;
  68     int orientation;
  69 };
  70
  71 struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
  72     uint32_t fdaddr;
  73     uint32_t fsaddr;
  74     uint32_t fidr;
  75     uint32_t ldcmd;
  76 };
  77
  78 #define LCCR0   0x000   /* LCD Controller Control register 0 */
  79 #define LCCR1   0x004   /* LCD Controller Control register 1 */
  80 #define LCCR2   0x008   /* LCD Controller Control register 2 */
  81 #define LCCR3   0x00c   /* LCD Controller Control register 3 */
  82 #define LCCR4   0x010   /* LCD Controller Control register 4 */
  83 #define LCCR5   0x014   /* LCD Controller Control register 5 */
  84
  85 #define FBR0    0x020   /* DMA Channel 0 Frame Branch register */
  86 #define FBR1    0x024   /* DMA Channel 1 Frame Branch register */
  87 #define FBR2    0x028   /* DMA Channel 2 Frame Branch register */
  88 #define FBR3    0x02c   /* DMA Channel 3 Frame Branch register */
  89 #define FBR4    0x030   /* DMA Channel 4 Frame Branch register */
  90 #define FBR5    0x110   /* DMA Channel 5 Frame Branch register */
  91 #define FBR6    0x114   /* DMA Channel 6 Frame Branch register */
  92
  93 #define LCSR1   0x034   /* LCD Controller Status register 1 */
  94 #define LCSR0   0x038   /* LCD Controller Status register 0 */
  95 #define LIIDR   0x03c   /* LCD Controller Interrupt ID register */
  96
  97 #define TRGBR   0x040   /* TMED RGB Seed register */
  98 #define TCR     0x044   /* TMED Control register */
  99
 100 #define OVL1C1  0x050   /* Overlay 1 Control register 1 */
 101 #define OVL1C2  0x060   /* Overlay 1 Control register 2 */
 102 #define OVL2C1  0x070   /* Overlay 2 Control register 1 */
 103 #define OVL2C2  0x080   /* Overlay 2 Control register 2 */
 104 #define CCR     0x090   /* Cursor Control register */
 105
 106 #define CMDCR   0x100   /* Command Control register */
 107 #define PRSR    0x104   /* Panel Read Status register */
 108
 109 #define PXA_LCDDMA_CHANS        7
 110 #define DMA_FDADR               0x00    /* Frame Descriptor Address register */
 111 #define DMA_FSADR               0x04    /* Frame Source Address register */
 112 #define DMA_FIDR                0x08    /* Frame ID register */
 113 #define DMA_LDCMD               0x0c    /* Command register */
 114
 115 /* LCD Buffer Strength Control register */
 116 #define BSCNTR  0x04000054
 117
 118 /* Bitfield masks */
 119 #define LCCR0_ENB       (1 << 0)
 120 #define LCCR0_CMS       (1 << 1)
 121 #define LCCR0_SDS       (1 << 2)
 122 #define LCCR0_LDM       (1 << 3)
 123 #define LCCR0_SOFM0     (1 << 4)
 124 #define LCCR0_IUM       (1 << 5)
 125 #define LCCR0_EOFM0     (1 << 6)
 126 #define LCCR0_PAS       (1 << 7)
 127 #define LCCR0_DPD       (1 << 9)
 128 #define LCCR0_DIS       (1 << 10)
 129 #define LCCR0_QDM       (1 << 11)
 130 #define LCCR0_PDD       (0xff << 12)
 131 #define LCCR0_BSM0      (1 << 20)
 132 #define LCCR0_OUM       (1 << 21)
 133 #define LCCR0_LCDT      (1 << 22)
 134 #define LCCR0_RDSTM     (1 << 23)
 135 #define LCCR0_CMDIM     (1 << 24)
 136 #define LCCR0_OUC       (1 << 25)
 137 #define LCCR0_LDDALT    (1 << 26)
 138 #define LCCR1_PPL(x)    ((x) & 0x3ff)
 139 #define LCCR2_LPP(x)    ((x) & 0x3ff)
 140 #define LCCR3_API       (15 << 16)
 141 #define LCCR3_BPP(x)    ((((x) >> 24) & 7) | (((x) >> 26) & 8))
 142 #define LCCR3_PDFOR(x)  (((x) >> 30) & 3)
 143 #define LCCR4_K1(x)     (((x) >> 0) & 7)
 144 #define LCCR4_K2(x)     (((x) >> 3) & 7)
 145 #define LCCR4_K3(x)     (((x) >> 6) & 7)
 146 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
 147 #define LCCR5_SOFM(ch)  (1 << (ch - 1))
 148 #define LCCR5_EOFM(ch)  (1 << (ch + 7))
 149 #define LCCR5_BSM(ch)   (1 << (ch + 15))
 150 #define LCCR5_IUM(ch)   (1 << (ch + 23))
 151 #define OVLC1_EN        (1 << 31)
 152 #define CCR_CEN         (1 << 31)
 153 #define FBR_BRA         (1 << 0)
 154 #define FBR_BINT        (1 << 1)
 155 #define FBR_SRCADDR     (0xfffffff << 4)
 156 #define LCSR0_LDD       (1 << 0)
 157 #define LCSR0_SOF0      (1 << 1)
 158 #define LCSR0_BER       (1 << 2)
 159 #define LCSR0_ABC       (1 << 3)
 160 #define LCSR0_IU0       (1 << 4)
 161 #define LCSR0_IU1       (1 << 5)
 162 #define LCSR0_OU        (1 << 6)
 163 #define LCSR0_QD        (1 << 7)
 164 #define LCSR0_EOF0      (1 << 8)
 165 #define LCSR0_BS0       (1 << 9)
 166 #define LCSR0_SINT      (1 << 10)
 167 #define LCSR0_RDST      (1 << 11)
 168 #define LCSR0_CMDINT    (1 << 12)
 169 #define LCSR0_BERCH(x)  (((x) & 7) << 28)
 170 #define LCSR1_SOF(ch)   (1 << (ch - 1))
 171 #define LCSR1_EOF(ch)   (1 << (ch + 7))
 172 #define LCSR1_BS(ch)    (1 << (ch + 15))
 173 #define LCSR1_IU(ch)    (1 << (ch + 23))
 174 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
 175 #define LDCMD_EOFINT    (1 << 21)
 176 #define LDCMD_SOFINT    (1 << 22)
 177 #define LDCMD_PAL       (1 << 26)
 178
 179 /* Route internal interrupt lines to the global IC */
 180 static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s)
 181 {
 182     int level = 0;
 183     level |= (s->status[0] & LCSR0_LDD)    && !(s->control[0] & LCCR0_LDM);
 184     level |= (s->status[0] & LCSR0_SOF0)   && !(s->control[0] & LCCR0_SOFM0);
 185     level |= (s->status[0] & LCSR0_IU0)    && !(s->control[0] & LCCR0_IUM);
 186     level |= (s->status[0] & LCSR0_IU1)    && !(s->control[5] & LCCR5_IUM(1));
 187     level |= (s->status[0] & LCSR0_OU)     && !(s->control[0] & LCCR0_OUM);
 188     level |= (s->status[0] & LCSR0_QD)     && !(s->control[0] & LCCR0_QDM);
 189     level |= (s->status[0] & LCSR0_EOF0)   && !(s->control[0] & LCCR0_EOFM0);
 190     level |= (s->status[0] & LCSR0_BS0)    && !(s->control[0] & LCCR0_BSM0);
 191     level |= (s->status[0] & LCSR0_RDST)   && !(s->control[0] & LCCR0_RDSTM);
 192     level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
 193     level |= (s->status[1] & ~s->control[5]);
 194
 195     qemu_set_irq(s->irq, !!level);
 196     s->irqlevel = level;
 197 }
 198
 199 /* Set Branch Status interrupt high and poke associated registers */
 200 static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch)
 201 {
 202     int unmasked;
 203     if (ch == 0) {
 204         s->status[0] |= LCSR0_BS0;
 205         unmasked = !(s->control[0] & LCCR0_BSM0);
 206     } else {
 207         s->status[1] |= LCSR1_BS(ch);
 208         unmasked = !(s->control[5] & LCCR5_BSM(ch));
 209     }
 210
 211     if (unmasked) {
 212         if (s->irqlevel)
 213             s->status[0] |= LCSR0_SINT;
 214         else
 215             s->liidr = s->dma_ch[ch].id;
 216     }
 217 }
 218
 219 /* Set Start Of Frame Status interrupt high and poke associated registers */
 220 static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch)
 221 {
 222     int unmasked;
 223     if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
 224         return;
 225
 226     if (ch == 0) {
 227         s->status[0] |= LCSR0_SOF0;
 228         unmasked = !(s->control[0] & LCCR0_SOFM0);
 229     } else {
 230         s->status[1] |= LCSR1_SOF(ch);
 231         unmasked = !(s->control[5] & LCCR5_SOFM(ch));
 232     }
 233
 234     if (unmasked) {
 235         if (s->irqlevel)
 236             s->status[0] |= LCSR0_SINT;
 237         else
 238             s->liidr = s->dma_ch[ch].id;
 239     }
 240 }
 241
 242 /* Set End Of Frame Status interrupt high and poke associated registers */
 243 static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch)
 244 {
 245     int unmasked;
 246     if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
 247         return;
 248
 249     if (ch == 0) {
 250         s->status[0] |= LCSR0_EOF0;
 251         unmasked = !(s->control[0] & LCCR0_EOFM0);
 252     } else {
 253         s->status[1] |= LCSR1_EOF(ch);
 254         unmasked = !(s->control[5] & LCCR5_EOFM(ch));
 255     }
 256
 257     if (unmasked) {
 258         if (s->irqlevel)
 259             s->status[0] |= LCSR0_SINT;
 260         else
 261             s->liidr = s->dma_ch[ch].id;
 262     }
 263 }
 264
 265 /* Set Bus Error Status interrupt high and poke associated registers */
 266 static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch)
 267 {
 268     s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
 269     if (s->irqlevel)
 270         s->status[0] |= LCSR0_SINT;
 271     else
 272         s->liidr = s->dma_ch[ch].id;
 273 }
 274
 275 /* Set Read Status interrupt high and poke associated registers */
 276 static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
 277 {
 278     s->status[0] |= LCSR0_RDST;
 279     if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
 280         s->status[0] |= LCSR0_SINT;
 281 }
 282
 283 /* Load new Frame Descriptors from DMA */
 284 static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
 285 {
 286     struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
 287     target_phys_addr_t descptr;
 288     int i;
 289
 290     for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
 291         desc[i] = 0;
 292         s->dma_ch[i].source = 0;
 293
 294         if (!s->dma_ch[i].up)
 295             continue;
 296
 297         if (s->dma_ch[i].branch & FBR_BRA) {
 298             descptr = s->dma_ch[i].branch & FBR_SRCADDR;
 299             if (s->dma_ch[i].branch & FBR_BINT)
 300                 pxa2xx_dma_bs_set(s, i);
 301             s->dma_ch[i].branch &= ~FBR_BRA;
 302         } else
 303             descptr = s->dma_ch[i].descriptor;
 304
 305         if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
 306                     sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
 307             continue;
 308
 309         descptr -= PXA2XX_SDRAM_BASE;
 310         desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr);
 311         s->dma_ch[i].descriptor = desc[i]->fdaddr;
 312         s->dma_ch[i].source = desc[i]->fsaddr;
 313         s->dma_ch[i].id = desc[i]->fidr;
 314         s->dma_ch[i].command = desc[i]->ldcmd;
 315     }
 316 }
 317
 318 static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
 319 {
 320     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 321     int ch;
 322
 323     switch (offset) {
 324     case LCCR0:
 325         return s->control[0];
 326     case LCCR1:
 327         return s->control[1];
 328     case LCCR2:
 329         return s->control[2];
 330     case LCCR3:
 331         return s->control[3];
 332     case LCCR4:
 333         return s->control[4];
 334     case LCCR5:
 335         return s->control[5];
 336
 337     case OVL1C1:
 338         return s->ovl1c[0];
 339     case OVL1C2:
 340         return s->ovl1c[1];
 341     case OVL2C1:
 342         return s->ovl2c[0];
 343     case OVL2C2:
 344         return s->ovl2c[1];
 345
 346     case CCR:
 347         return s->ccr;
 348
 349     case CMDCR:
 350         return s->cmdcr;
 351
 352     case TRGBR:
 353         return s->trgbr;
 354     case TCR:
 355         return s->tcr;
 356
 357     case 0x200 ... 0x1000:      /* DMA per-channel registers */
 358         ch = (offset - 0x200) >> 4;
 359         if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
 360             goto fail;
 361
 362         switch (offset & 0xf) {
 363         case DMA_FDADR:
 364             return s->dma_ch[ch].descriptor;
 365         case DMA_FSADR:
 366             return s->dma_ch[ch].source;
 367         case DMA_FIDR:
 368             return s->dma_ch[ch].id;
 369         case DMA_LDCMD:
 370             return s->dma_ch[ch].command;
 371         default:
 372             goto fail;
 373         }
 374
 375     case FBR0:
 376         return s->dma_ch[0].branch;
 377     case FBR1:
 378         return s->dma_ch[1].branch;
 379     case FBR2:
 380         return s->dma_ch[2].branch;
 381     case FBR3:
 382         return s->dma_ch[3].branch;
 383     case FBR4:
 384         return s->dma_ch[4].branch;
 385     case FBR5:
 386         return s->dma_ch[5].branch;
 387     case FBR6:
 388         return s->dma_ch[6].branch;
 389
 390     case BSCNTR:
 391         return s->bscntr;
 392
 393     case PRSR:
 394         return 0;
 395
 396     case LCSR0:
 397         return s->status[0];
 398     case LCSR1:
 399         return s->status[1];
 400     case LIIDR:
 401         return s->liidr;
 402
 403     default:
 404     fail:
 405         cpu_abort(cpu_single_env,
 406                 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 407     }
 408
 409     return 0;
 410 }
 411
 412 static void pxa2xx_lcdc_write(void *opaque,
 413                 target_phys_addr_t offset, uint32_t value)
 414 {
 415     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 416     int ch;
 417
 418     switch (offset) {
 419     case LCCR0:
 420         /* ACK Quick Disable done */
 421         if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
 422             s->status[0] |= LCSR0_QD;
 423
 424         if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
 425             printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
 426
 427         if ((s->control[3] & LCCR3_API) &&
 428                 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
 429             s->status[0] |= LCSR0_ABC;
 430
 431         s->control[0] = value & 0x07ffffff;
 432         pxa2xx_lcdc_int_update(s);
 433
 434         s->dma_ch[0].up = !!(value & LCCR0_ENB);
 435         s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
 436         break;
 437
 438     case LCCR1:
 439         s->control[1] = value;
 440         break;
 441
 442     case LCCR2:
 443         s->control[2] = value;
 444         break;
 445
 446     case LCCR3:
 447         s->control[3] = value & 0xefffffff;
 448         s->bpp = LCCR3_BPP(value);
 449         break;
 450
 451     case LCCR4:
 452         s->control[4] = value & 0x83ff81ff;
 453         break;
 454
 455     case LCCR5:
 456         s->control[5] = value & 0x3f3f3f3f;
 457         break;
 458
 459     case OVL1C1:
 460         if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
 461             printf("%s: Overlay 1 not supported\n", __FUNCTION__);
 462
 463         s->ovl1c[0] = value & 0x80ffffff;
 464         s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
 465         break;
 466
 467     case OVL1C2:
 468         s->ovl1c[1] = value & 0x000fffff;
 469         break;
 470
 471     case OVL2C1:
 472         if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
 473             printf("%s: Overlay 2 not supported\n", __FUNCTION__);
 474
 475         s->ovl2c[0] = value & 0x80ffffff;
 476         s->dma_ch[2].up = !!(value & OVLC1_EN);
 477         s->dma_ch[3].up = !!(value & OVLC1_EN);
 478         s->dma_ch[4].up = !!(value & OVLC1_EN);
 479         break;
 480
 481     case OVL2C2:
 482         s->ovl2c[1] = value & 0x007fffff;
 483         break;
 484
 485     case CCR:
 486         if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
 487             printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
 488
 489         s->ccr = value & 0x81ffffe7;
 490         s->dma_ch[5].up = !!(value & CCR_CEN);
 491         break;
 492
 493     case CMDCR:
 494         s->cmdcr = value & 0xff;
 495         break;
 496
 497     case TRGBR:
 498         s->trgbr = value & 0x00ffffff;
 499         break;
 500
 501     case TCR:
 502         s->tcr = value & 0x7fff;
 503         break;
 504
 505     case 0x200 ... 0x1000:      /* DMA per-channel registers */
 506         ch = (offset - 0x200) >> 4;
 507         if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
 508             goto fail;
 509
 510         switch (offset & 0xf) {
 511         case DMA_FDADR:
 512             s->dma_ch[ch].descriptor = value & 0xfffffff0;
 513             break;
 514
 515         default:
 516             goto fail;
 517         }
 518         break;
 519
 520     case FBR0:
 521         s->dma_ch[0].branch = value & 0xfffffff3;
 522         break;
 523     case FBR1:
 524         s->dma_ch[1].branch = value & 0xfffffff3;
 525         break;
 526     case FBR2:
 527         s->dma_ch[2].branch = value & 0xfffffff3;
 528         break;
 529     case FBR3:
 530         s->dma_ch[3].branch = value & 0xfffffff3;
 531         break;
 532     case FBR4:
 533         s->dma_ch[4].branch = value & 0xfffffff3;
 534         break;
 535     case FBR5:
 536         s->dma_ch[5].branch = value & 0xfffffff3;
 537         break;
 538     case FBR6:
 539         s->dma_ch[6].branch = value & 0xfffffff3;
 540         break;
 541
 542     case BSCNTR:
 543         s->bscntr = value & 0xf;
 544         break;
 545
 546     case PRSR:
 547         break;
 548
 549     case LCSR0:
 550         s->status[0] &= ~(value & 0xfff);
 551         if (value & LCSR0_BER)
 552             s->status[0] &= ~LCSR0_BERCH(7);
 553         break;
 554
 555     case LCSR1:
 556         s->status[1] &= ~(value & 0x3e3f3f);
 557         break;
 558
 559     default:
 560     fail:
 561         cpu_abort(cpu_single_env,
 562                 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 563     }
 564 }
 565
 566 static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
 567     pxa2xx_lcdc_read,
 568     pxa2xx_lcdc_read,
 569     pxa2xx_lcdc_read
 570 };
 571
 572 static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
 573     pxa2xx_lcdc_write,
 574     pxa2xx_lcdc_write,
 575     pxa2xx_lcdc_write
 576 };
 577
 578 /* Load new palette for a given DMA channel, convert to internal format */
 579 static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp)
 580 {
 581     int i, n, format, r, g, b, alpha;
 582     uint32_t *dest, *src;
 583     s->pal_for = LCCR4_PALFOR(s->control[4]);
 584     format = s->pal_for;
 585
 586     switch (bpp) {
 587     case pxa_lcdc_2bpp:
 588         n = 4;
 589         break;
 590     case pxa_lcdc_4bpp:
 591         n = 16;
 592         break;
 593     case pxa_lcdc_8bpp:
 594         n = 256;
 595         break;
 596     default:
 597         format = 0;
 598         return;
 599     }
 600
 601     src = (uint32_t *) s->dma_ch[ch].pbuffer;
 602     dest = (uint32_t *) s->dma_ch[ch].palette;
 603     alpha = r = g = b = 0;
 604
 605     for (i = 0; i < n; i ++) {
 606         switch (format) {
 607         case 0: /* 16 bpp, no transparency */
 608             alpha = 0;
 609             if (s->control[0] & LCCR0_CMS)
 610                 r = g = b = *src & 0xff;
 611             else {
 612                 r = (*src & 0xf800) >> 8;
 613                 g = (*src & 0x07e0) >> 3;
 614                 b = (*src & 0x001f) << 3;
 615             }
 616             break;
 617         case 1: /* 16 bpp plus transparency */
 618             alpha = *src & (1 << 24);
 619             if (s->control[0] & LCCR0_CMS)
 620                 r = g = b = *src & 0xff;
 621             else {
 622                 r = (*src & 0xf800) >> 8;
 623                 g = (*src & 0x07e0) >> 3;
 624                 b = (*src & 0x001f) << 3;
 625             }
 626             break;
 627         case 2: /* 18 bpp plus transparency */
 628             alpha = *src & (1 << 24);
 629             if (s->control[0] & LCCR0_CMS)
 630                 r = g = b = *src & 0xff;
 631             else {
 632                 r = (*src & 0xf80000) >> 16;
 633                 g = (*src & 0x00fc00) >> 8;
 634                 b = (*src & 0x0000f8);
 635             }
 636             break;
 637         case 3: /* 24 bpp plus transparency */
 638             alpha = *src & (1 << 24);
 639             if (s->control[0] & LCCR0_CMS)
 640                 r = g = b = *src & 0xff;
 641             else {
 642                 r = (*src & 0xff0000) >> 16;
 643                 g = (*src & 0x00ff00) >> 8;
 644                 b = (*src & 0x0000ff);
 645             }
 646             break;
 647         }
 648         switch (ds_get_bits_per_pixel(s->ds)) {
 649         case 8:
 650             *dest = rgb_to_pixel8(r, g, b) | alpha;
 651             break;
 652         case 15:
 653             *dest = rgb_to_pixel15(r, g, b) | alpha;
 654             break;
 655         case 16:
 656             *dest = rgb_to_pixel16(r, g, b) | alpha;
 657             break;
 658         case 24:
 659             *dest = rgb_to_pixel24(r, g, b) | alpha;
 660             break;
 661         case 32:
 662             *dest = rgb_to_pixel32(r, g, b) | alpha;
 663             break;
 664         }
 665         src ++;
 666         dest ++;
 667     }
 668 }
 669
 670 static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s,
 671                 target_phys_addr_t addr, int *miny, int *maxy)
 672 {
 673     int src_width, dest_width;
 674     drawfn fn = 0;
 675     if (s->dest_width)
 676         fn = s->line_fn[s->transp][s->bpp];
 677     if (!fn)
 678         return;
 679
 680     src_width = (s->xres + 3) & ~3;     /* Pad to a 4 pixels multiple */
 681     if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
 682         src_width *= 3;
 683     else if (s->bpp > pxa_lcdc_16bpp)
 684         src_width *= 4;
 685     else if (s->bpp > pxa_lcdc_8bpp)
 686         src_width *= 2;
 687
 688     dest_width = s->xres * s->dest_width;
 689     *miny = 0;
 690     framebuffer_update_display(s->ds,
 691                                addr, s->xres, s->yres,
 692                                src_width, dest_width, s->dest_width,
 693                                s->invalidated,
 694                                fn, s->dma_ch[0].palette, miny, maxy);
 695 }
 696
 697 static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s,
 698                target_phys_addr_t addr, int *miny, int *maxy)
 699 {
 700     int src_width, dest_width;
 701     drawfn fn = 0;
 702     if (s->dest_width)
 703         fn = s->line_fn[s->transp][s->bpp];
 704     if (!fn)
 705         return;
 706
 707     src_width = (s->xres + 3) & ~3;     /* Pad to a 4 pixels multiple */
 708     if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
 709         src_width *= 3;
 710     else if (s->bpp > pxa_lcdc_16bpp)
 711         src_width *= 4;
 712     else if (s->bpp > pxa_lcdc_8bpp)
 713         src_width *= 2;
 714
 715     dest_width = s->yres * s->dest_width;
 716     *miny = 0;
 717     framebuffer_update_display(s->ds,
 718                                addr, s->xres, s->yres,
 719                                src_width, s->dest_width, -dest_width,
 720                                s->invalidated,
 721                                fn, s->dma_ch[0].palette,
 722                                miny, maxy);
 723 }
 724
 725 static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
 726 {
 727     int width, height;
 728     if (!(s->control[0] & LCCR0_ENB))
 729         return;
 730
 731     width = LCCR1_PPL(s->control[1]) + 1;
 732     height = LCCR2_LPP(s->control[2]) + 1;
 733
 734     if (width != s->xres || height != s->yres) {
 735         if (s->orientation)
 736             qemu_console_resize(s->ds, height, width);
 737         else
 738             qemu_console_resize(s->ds, width, height);
 739         s->invalidated = 1;
 740         s->xres = width;
 741         s->yres = height;
 742     }
 743 }
 744
 745 static void pxa2xx_update_display(void *opaque)
 746 {
 747     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 748     target_phys_addr_t fbptr;
 749     int miny, maxy;
 750     int ch;
 751     if (!(s->control[0] & LCCR0_ENB))
 752         return;
 753
 754     pxa2xx_descriptor_load(s);
 755
 756     pxa2xx_lcdc_resize(s);
 757     miny = s->yres;
 758     maxy = 0;
 759     s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
 760     /* Note: With overlay planes the order depends on LCCR0 bit 25.  */
 761     for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
 762         if (s->dma_ch[ch].up) {
 763             if (!s->dma_ch[ch].source) {
 764                 pxa2xx_dma_ber_set(s, ch);
 765                 continue;
 766             }
 767             fbptr = s->dma_ch[ch].source;
 768             if (!(fbptr >= PXA2XX_SDRAM_BASE &&
 769                     fbptr <= PXA2XX_SDRAM_BASE + phys_ram_size)) {
 770                 pxa2xx_dma_ber_set(s, ch);
 771                 continue;
 772             }
 773
 774             if (s->dma_ch[ch].command & LDCMD_PAL) {
 775                 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
 776                     MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
 777                         sizeof(s->dma_ch[ch].pbuffer)));
 778                 pxa2xx_palette_parse(s, ch, s->bpp);
 779             } else {
 780                 /* Do we need to reparse palette */
 781                 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
 782                     pxa2xx_palette_parse(s, ch, s->bpp);
 783
 784                 /* ACK frame start */
 785                 pxa2xx_dma_sof_set(s, ch);
 786
 787                 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
 788                 s->invalidated = 0;
 789
 790                 /* ACK frame completed */
 791                 pxa2xx_dma_eof_set(s, ch);
 792             }
 793         }
 794
 795     if (s->control[0] & LCCR0_DIS) {
 796         /* ACK last frame completed */
 797         s->control[0] &= ~LCCR0_ENB;
 798         s->status[0] |= LCSR0_LDD;
 799     }
 800
 801     if (miny >= 0) {
 802         if (s->orientation)
 803             dpy_update(s->ds, miny, 0, maxy, s->xres);
 804         else
 805             dpy_update(s->ds, 0, miny, s->xres, maxy);
 806     }
 807     pxa2xx_lcdc_int_update(s);
 808
 809     qemu_irq_raise(s->vsync_cb);
 810 }
 811
 812 static void pxa2xx_invalidate_display(void *opaque)
 813 {
 814     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 815     s->invalidated = 1;
 816 }
 817
 818 static void pxa2xx_screen_dump(void *opaque, const char *filename)
 819 {
 820     /* TODO */
 821 }
 822
 823 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
 824 {
 825     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 826
 827     if (angle) {
 828         s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
 829     } else {
 830         s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
 831     }
 832
 833     s->orientation = angle;
 834     s->xres = s->yres = -1;
 835     pxa2xx_lcdc_resize(s);
 836 }
 837
 838 static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
 839 {
 840     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 841     int i;
 842
 843     qemu_put_be32(f, s->irqlevel);
 844     qemu_put_be32(f, s->transp);
 845
 846     for (i = 0; i < 6; i ++)
 847         qemu_put_be32s(f, &s->control[i]);
 848     for (i = 0; i < 2; i ++)
 849         qemu_put_be32s(f, &s->status[i]);
 850     for (i = 0; i < 2; i ++)
 851         qemu_put_be32s(f, &s->ovl1c[i]);
 852     for (i = 0; i < 2; i ++)
 853         qemu_put_be32s(f, &s->ovl2c[i]);
 854     qemu_put_be32s(f, &s->ccr);
 855     qemu_put_be32s(f, &s->cmdcr);
 856     qemu_put_be32s(f, &s->trgbr);
 857     qemu_put_be32s(f, &s->tcr);
 858     qemu_put_be32s(f, &s->liidr);
 859     qemu_put_8s(f, &s->bscntr);
 860
 861     for (i = 0; i < 7; i ++) {
 862         qemu_put_betl(f, s->dma_ch[i].branch);
 863         qemu_put_byte(f, s->dma_ch[i].up);
 864         qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
 865
 866         qemu_put_betl(f, s->dma_ch[i].descriptor);
 867         qemu_put_betl(f, s->dma_ch[i].source);
 868         qemu_put_be32s(f, &s->dma_ch[i].id);
 869         qemu_put_be32s(f, &s->dma_ch[i].command);
 870     }
 871 }
 872
 873 static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
 874 {
 875     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 876     int i;
 877
 878     s->irqlevel = qemu_get_be32(f);
 879     s->transp = qemu_get_be32(f);
 880
 881     for (i = 0; i < 6; i ++)
 882         qemu_get_be32s(f, &s->control[i]);
 883     for (i = 0; i < 2; i ++)
 884         qemu_get_be32s(f, &s->status[i]);
 885     for (i = 0; i < 2; i ++)
 886         qemu_get_be32s(f, &s->ovl1c[i]);
 887     for (i = 0; i < 2; i ++)
 888         qemu_get_be32s(f, &s->ovl2c[i]);
 889     qemu_get_be32s(f, &s->ccr);
 890     qemu_get_be32s(f, &s->cmdcr);
 891     qemu_get_be32s(f, &s->trgbr);
 892     qemu_get_be32s(f, &s->tcr);
 893     qemu_get_be32s(f, &s->liidr);
 894     qemu_get_8s(f, &s->bscntr);
 895
 896     for (i = 0; i < 7; i ++) {
 897         s->dma_ch[i].branch = qemu_get_betl(f);
 898         s->dma_ch[i].up = qemu_get_byte(f);
 899         qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
 900
 901         s->dma_ch[i].descriptor = qemu_get_betl(f);
 902         s->dma_ch[i].source = qemu_get_betl(f);
 903         qemu_get_be32s(f, &s->dma_ch[i].id);
 904         qemu_get_be32s(f, &s->dma_ch[i].command);
 905     }
 906
 907     s->bpp = LCCR3_BPP(s->control[3]);
 908     s->xres = s->yres = s->pal_for = -1;
 909
 910     return 0;
 911 }
 912
 913 #define BITS 8
 914 #include "pxa2xx_template.h"
 915 #define BITS 15
 916 #include "pxa2xx_template.h"
 917 #define BITS 16
 918 #include "pxa2xx_template.h"
 919 #define BITS 24
 920 #include "pxa2xx_template.h"
 921 #define BITS 32
 922 #include "pxa2xx_template.h"
 923
 924 struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
 925 {
 926     int iomemtype;
 927     struct pxa2xx_lcdc_s *s;
 928
 929     s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
 930     s->invalidated = 1;
 931     s->irq = irq;
 932
 933     pxa2xx_lcdc_orientation(s, graphic_rotate);
 934
 935     iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
 936                     pxa2xx_lcdc_writefn, s);
 937     cpu_register_physical_memory(base, 0x00100000, iomemtype);
 938
 939     s->ds = graphic_console_init(pxa2xx_update_display,
 940                                  pxa2xx_invalidate_display,
 941                                  pxa2xx_screen_dump, NULL, s);
 942
 943     switch (ds_get_bits_per_pixel(s->ds)) {
 944     case 0:
 945         s->dest_width = 0;
 946         break;
 947     case 8:
 948         s->line_fn[0] = pxa2xx_draw_fn_8;
 949         s->line_fn[1] = pxa2xx_draw_fn_8t;
 950         s->dest_width = 1;
 951         break;
 952     case 15:
 953         s->line_fn[0] = pxa2xx_draw_fn_15;
 954         s->line_fn[1] = pxa2xx_draw_fn_15t;
 955         s->dest_width = 2;
 956         break;
 957     case 16:
 958         s->line_fn[0] = pxa2xx_draw_fn_16;
 959         s->line_fn[1] = pxa2xx_draw_fn_16t;
 960         s->dest_width = 2;
 961         break;
 962     case 24:
 963         s->line_fn[0] = pxa2xx_draw_fn_24;
 964         s->line_fn[1] = pxa2xx_draw_fn_24t;
 965         s->dest_width = 3;
 966         break;
 967     case 32:
 968         s->line_fn[0] = pxa2xx_draw_fn_32;
 969         s->line_fn[1] = pxa2xx_draw_fn_32t;
 970         s->dest_width = 4;
 971         break;
 972     default:
 973         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
 974         exit(1);
 975     }
 976
 977     register_savevm("pxa2xx_lcdc", 0, 0,
 978                     pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);
 979
 980     return s;
 981 }
 982
 983 void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler)
 984 {
 985     s->vsync_cb = handler;
 986 }