hw/lsi53c895a.c

   1 /*
   2  * QEMU LSI53C895A SCSI Host Bus Adapter emulation
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the LGPL.
   8  */
   9
  10 /* ??? Need to check if the {read,write}[wl] routines work properly on
  11    big-endian targets.  */
  12
  13 #include "hw.h"
  14 #include "pci.h"
  15 #include "scsi-disk.h"
  16
  17 //#define DEBUG_LSI
  18 //#define DEBUG_LSI_REG
  19
  20 #ifdef DEBUG_LSI
  21 #define DPRINTF(fmt, args...) \
  22 do { printf("lsi_scsi: " fmt , ##args); } while (0)
  23 #define BADF(fmt, args...) \
  24 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args); exit(1);} while (0)
  25 #else
  26 #define DPRINTF(fmt, args...) do {} while(0)
  27 #define BADF(fmt, args...) \
  28 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args);} while (0)
  29 #endif
  30
  31 #define LSI_SCNTL0_TRG    0x01
  32 #define LSI_SCNTL0_AAP    0x02
  33 #define LSI_SCNTL0_EPC    0x08
  34 #define LSI_SCNTL0_WATN   0x10
  35 #define LSI_SCNTL0_START  0x20
  36
  37 #define LSI_SCNTL1_SST    0x01
  38 #define LSI_SCNTL1_IARB   0x02
  39 #define LSI_SCNTL1_AESP   0x04
  40 #define LSI_SCNTL1_RST    0x08
  41 #define LSI_SCNTL1_CON    0x10
  42 #define LSI_SCNTL1_DHP    0x20
  43 #define LSI_SCNTL1_ADB    0x40
  44 #define LSI_SCNTL1_EXC    0x80
  45
  46 #define LSI_SCNTL2_WSR    0x01
  47 #define LSI_SCNTL2_VUE0   0x02
  48 #define LSI_SCNTL2_VUE1   0x04
  49 #define LSI_SCNTL2_WSS    0x08
  50 #define LSI_SCNTL2_SLPHBEN 0x10
  51 #define LSI_SCNTL2_SLPMD  0x20
  52 #define LSI_SCNTL2_CHM    0x40
  53 #define LSI_SCNTL2_SDU    0x80
  54
  55 #define LSI_ISTAT0_DIP    0x01
  56 #define LSI_ISTAT0_SIP    0x02
  57 #define LSI_ISTAT0_INTF   0x04
  58 #define LSI_ISTAT0_CON    0x08
  59 #define LSI_ISTAT0_SEM    0x10
  60 #define LSI_ISTAT0_SIGP   0x20
  61 #define LSI_ISTAT0_SRST   0x40
  62 #define LSI_ISTAT0_ABRT   0x80
  63
  64 #define LSI_ISTAT1_SI     0x01
  65 #define LSI_ISTAT1_SRUN   0x02
  66 #define LSI_ISTAT1_FLSH   0x04
  67
  68 #define LSI_SSTAT0_SDP0   0x01
  69 #define LSI_SSTAT0_RST    0x02
  70 #define LSI_SSTAT0_WOA    0x04
  71 #define LSI_SSTAT0_LOA    0x08
  72 #define LSI_SSTAT0_AIP    0x10
  73 #define LSI_SSTAT0_OLF    0x20
  74 #define LSI_SSTAT0_ORF    0x40
  75 #define LSI_SSTAT0_ILF    0x80
  76
  77 #define LSI_SIST0_PAR     0x01
  78 #define LSI_SIST0_RST     0x02
  79 #define LSI_SIST0_UDC     0x04
  80 #define LSI_SIST0_SGE     0x08
  81 #define LSI_SIST0_RSL     0x10
  82 #define LSI_SIST0_SEL     0x20
  83 #define LSI_SIST0_CMP     0x40
  84 #define LSI_SIST0_MA      0x80
  85
  86 #define LSI_SIST1_HTH     0x01
  87 #define LSI_SIST1_GEN     0x02
  88 #define LSI_SIST1_STO     0x04
  89 #define LSI_SIST1_SBMC    0x10
  90
  91 #define LSI_SOCL_IO       0x01
  92 #define LSI_SOCL_CD       0x02
  93 #define LSI_SOCL_MSG      0x04
  94 #define LSI_SOCL_ATN      0x08
  95 #define LSI_SOCL_SEL      0x10
  96 #define LSI_SOCL_BSY      0x20
  97 #define LSI_SOCL_ACK      0x40
  98 #define LSI_SOCL_REQ      0x80
  99
 100 #define LSI_DSTAT_IID     0x01
 101 #define LSI_DSTAT_SIR     0x04
 102 #define LSI_DSTAT_SSI     0x08
 103 #define LSI_DSTAT_ABRT    0x10
 104 #define LSI_DSTAT_BF      0x20
 105 #define LSI_DSTAT_MDPE    0x40
 106 #define LSI_DSTAT_DFE     0x80
 107
 108 #define LSI_DCNTL_COM     0x01
 109 #define LSI_DCNTL_IRQD    0x02
 110 #define LSI_DCNTL_STD     0x04
 111 #define LSI_DCNTL_IRQM    0x08
 112 #define LSI_DCNTL_SSM     0x10
 113 #define LSI_DCNTL_PFEN    0x20
 114 #define LSI_DCNTL_PFF     0x40
 115 #define LSI_DCNTL_CLSE    0x80
 116
 117 #define LSI_DMODE_MAN     0x01
 118 #define LSI_DMODE_BOF     0x02
 119 #define LSI_DMODE_ERMP    0x04
 120 #define LSI_DMODE_ERL     0x08
 121 #define LSI_DMODE_DIOM    0x10
 122 #define LSI_DMODE_SIOM    0x20
 123
 124 #define LSI_CTEST2_DACK   0x01
 125 #define LSI_CTEST2_DREQ   0x02
 126 #define LSI_CTEST2_TEOP   0x04
 127 #define LSI_CTEST2_PCICIE 0x08
 128 #define LSI_CTEST2_CM     0x10
 129 #define LSI_CTEST2_CIO    0x20
 130 #define LSI_CTEST2_SIGP   0x40
 131 #define LSI_CTEST2_DDIR   0x80
 132
 133 #define LSI_CTEST5_BL2    0x04
 134 #define LSI_CTEST5_DDIR   0x08
 135 #define LSI_CTEST5_MASR   0x10
 136 #define LSI_CTEST5_DFSN   0x20
 137 #define LSI_CTEST5_BBCK   0x40
 138 #define LSI_CTEST5_ADCK   0x80
 139
 140 #define LSI_CCNTL0_DILS   0x01
 141 #define LSI_CCNTL0_DISFC  0x10
 142 #define LSI_CCNTL0_ENNDJ  0x20
 143 #define LSI_CCNTL0_PMJCTL 0x40
 144 #define LSI_CCNTL0_ENPMJ  0x80
 145
 146 #define PHASE_DO          0
 147 #define PHASE_DI          1
 148 #define PHASE_CMD         2
 149 #define PHASE_ST          3
 150 #define PHASE_MO          6
 151 #define PHASE_MI          7
 152 #define PHASE_MASK        7
 153
 154 /* Maximum length of MSG IN data.  */
 155 #define LSI_MAX_MSGIN_LEN 8
 156
 157 /* Flag set if this is a tagged command.  */
 158 #define LSI_TAG_VALID     (1 << 16)
 159
 160 typedef struct {
 161     uint32_t tag;
 162     uint32_t pending;
 163     int out;
 164 } lsi_queue;
 165
 166 typedef struct {
 167     PCIDevice pci_dev;
 168     int mmio_io_addr;
 169     int ram_io_addr;
 170     uint32_t script_ram_base;
 171
 172     int carry; /* ??? Should this be an a visible register somewhere?  */
 173     int sense;
 174     /* Action to take at the end of a MSG IN phase.
 175        0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN.  */
 176     int msg_action;
 177     int msg_len;
 178     uint8_t msg[LSI_MAX_MSGIN_LEN];
 179     /* 0 if SCRIPTS are running or stopped.
 180      * 1 if a Wait Reselect instruction has been issued.
 181      * 2 if processing DMA from lsi_execute_script.
 182      * 3 if a DMA operation is in progress.  */
 183     int waiting;
 184     SCSIDevice *scsi_dev[LSI_MAX_DEVS];
 185     SCSIDevice *current_dev;
 186     int current_lun;
 187     /* The tag is a combination of the device ID and the SCSI tag.  */
 188     uint32_t current_tag;
 189     uint32_t current_dma_len;
 190     int command_complete;
 191     uint8_t *dma_buf;
 192     lsi_queue *queue;
 193     int queue_len;
 194     int active_commands;
 195
 196     uint32_t dsa;
 197     uint32_t temp;
 198     uint32_t dnad;
 199     uint32_t dbc;
 200     uint8_t istat0;
 201     uint8_t istat1;
 202     uint8_t dcmd;
 203     uint8_t dstat;
 204     uint8_t dien;
 205     uint8_t sist0;
 206     uint8_t sist1;
 207     uint8_t sien0;
 208     uint8_t sien1;
 209     uint8_t mbox0;
 210     uint8_t mbox1;
 211     uint8_t dfifo;
 212     uint8_t ctest3;
 213     uint8_t ctest4;
 214     uint8_t ctest5;
 215     uint8_t ccntl0;
 216     uint8_t ccntl1;
 217     uint32_t dsp;
 218     uint32_t dsps;
 219     uint8_t dmode;
 220     uint8_t dcntl;
 221     uint8_t scntl0;
 222     uint8_t scntl1;
 223     uint8_t scntl2;
 224     uint8_t scntl3;
 225     uint8_t sstat0;
 226     uint8_t sstat1;
 227     uint8_t scid;
 228     uint8_t sxfer;
 229     uint8_t socl;
 230     uint8_t sdid;
 231     uint8_t ssid;
 232     uint8_t sfbr;
 233     uint8_t stest1;
 234     uint8_t stest2;
 235     uint8_t stest3;
 236     uint8_t sidl;
 237     uint8_t stime0;
 238     uint8_t respid0;
 239     uint8_t respid1;
 240     uint32_t mmrs;
 241     uint32_t mmws;
 242     uint32_t sfs;
 243     uint32_t drs;
 244     uint32_t sbms;
 245     uint32_t dmbs;
 246     uint32_t dnad64;
 247     uint32_t pmjad1;
 248     uint32_t pmjad2;
 249     uint32_t rbc;
 250     uint32_t ua;
 251     uint32_t ia;
 252     uint32_t sbc;
 253     uint32_t csbc;
 254     uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
 255
 256     /* Script ram is stored as 32-bit words in host byteorder.  */
 257     uint32_t script_ram[2048];
 258 } LSIState;
 259
 260 static void lsi_soft_reset(LSIState *s)
 261 {
 262     DPRINTF("Reset\n");
 263     s->carry = 0;
 264
 265     s->waiting = 0;
 266     s->dsa = 0;
 267     s->dnad = 0;
 268     s->dbc = 0;
 269     s->temp = 0;
 270     memset(s->scratch, 0, sizeof(s->scratch));
 271     s->istat0 = 0;
 272     s->istat1 = 0;
 273     s->dcmd = 0;
 274     s->dstat = 0;
 275     s->dien = 0;
 276     s->sist0 = 0;
 277     s->sist1 = 0;
 278     s->sien0 = 0;
 279     s->sien1 = 0;
 280     s->mbox0 = 0;
 281     s->mbox1 = 0;
 282     s->dfifo = 0;
 283     s->ctest3 = 0;
 284     s->ctest4 = 0;
 285     s->ctest5 = 0;
 286     s->ccntl0 = 0;
 287     s->ccntl1 = 0;
 288     s->dsp = 0;
 289     s->dsps = 0;
 290     s->dmode = 0;
 291     s->dcntl = 0;
 292     s->scntl0 = 0xc0;
 293     s->scntl1 = 0;
 294     s->scntl2 = 0;
 295     s->scntl3 = 0;
 296     s->sstat0 = 0;
 297     s->sstat1 = 0;
 298     s->scid = 7;
 299     s->sxfer = 0;
 300     s->socl = 0;
 301     s->stest1 = 0;
 302     s->stest2 = 0;
 303     s->stest3 = 0;
 304     s->sidl = 0;
 305     s->stime0 = 0;
 306     s->respid0 = 0x80;
 307     s->respid1 = 0;
 308     s->mmrs = 0;
 309     s->mmws = 0;
 310     s->sfs = 0;
 311     s->drs = 0;
 312     s->sbms = 0;
 313     s->dmbs = 0;
 314     s->dnad64 = 0;
 315     s->pmjad1 = 0;
 316     s->pmjad2 = 0;
 317     s->rbc = 0;
 318     s->ua = 0;
 319     s->ia = 0;
 320     s->sbc = 0;
 321     s->csbc = 0;
 322 }
 323
 324 static uint8_t lsi_reg_readb(LSIState *s, int offset);
 325 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val);
 326 static void lsi_execute_script(LSIState *s);
 327
 328 static inline uint32_t read_dword(LSIState *s, uint32_t addr)
 329 {
 330     uint32_t buf;
 331
 332     /* Optimize reading from SCRIPTS RAM.  */
 333     if ((addr & 0xffffe000) == s->script_ram_base) {
 334         return s->script_ram[(addr & 0x1fff) >> 2];
 335     }
 336     cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
 337     return cpu_to_le32(buf);
 338 }
 339
 340 static void lsi_stop_script(LSIState *s)
 341 {
 342     s->istat1 &= ~LSI_ISTAT1_SRUN;
 343 }
 344
 345 static void lsi_update_irq(LSIState *s)
 346 {
 347     int level;
 348     static int last_level;
 349
 350     /* It's unclear whether the DIP/SIP bits should be cleared when the
 351        Interrupt Status Registers are cleared or when istat0 is read.
 352        We currently do the formwer, which seems to work.  */
 353     level = 0;
 354     if (s->dstat) {
 355         if (s->dstat & s->dien)
 356             level = 1;
 357         s->istat0 |= LSI_ISTAT0_DIP;
 358     } else {
 359         s->istat0 &= ~LSI_ISTAT0_DIP;
 360     }
 361
 362     if (s->sist0 || s->sist1) {
 363         if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
 364             level = 1;
 365         s->istat0 |= LSI_ISTAT0_SIP;
 366     } else {
 367         s->istat0 &= ~LSI_ISTAT0_SIP;
 368     }
 369     if (s->istat0 & LSI_ISTAT0_INTF)
 370         level = 1;
 371
 372     if (level != last_level) {
 373         DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
 374                 level, s->dstat, s->sist1, s->sist0);
 375         last_level = level;
 376     }
 377     qemu_set_irq(s->pci_dev.irq[0], level);
 378 }
 379
 380 /* Stop SCRIPTS execution and raise a SCSI interrupt.  */
 381 static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1)
 382 {
 383     uint32_t mask0;
 384     uint32_t mask1;
 385
 386     DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
 387             stat1, stat0, s->sist1, s->sist0);
 388     s->sist0 |= stat0;
 389     s->sist1 |= stat1;
 390     /* Stop processor on fatal or unmasked interrupt.  As a special hack
 391        we don't stop processing when raising STO.  Instead continue
 392        execution and stop at the next insn that accesses the SCSI bus.  */
 393     mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL);
 394     mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
 395     mask1 &= ~LSI_SIST1_STO;
 396     if (s->sist0 & mask0 || s->sist1 & mask1) {
 397         lsi_stop_script(s);
 398     }
 399     lsi_update_irq(s);
 400 }
 401
 402 /* Stop SCRIPTS execution and raise a DMA interrupt.  */
 403 static void lsi_script_dma_interrupt(LSIState *s, int stat)
 404 {
 405     DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
 406     s->dstat |= stat;
 407     lsi_update_irq(s);
 408     lsi_stop_script(s);
 409 }
 410
 411 static inline void lsi_set_phase(LSIState *s, int phase)
 412 {
 413     s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase;
 414 }
 415
 416 static void lsi_bad_phase(LSIState *s, int out, int new_phase)
 417 {
 418     /* Trigger a phase mismatch.  */
 419     if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
 420         if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
 421             s->dsp = s->pmjad1;
 422         } else {
 423             s->dsp = s->pmjad2;
 424         }
 425         DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
 426     } else {
 427         DPRINTF("Phase mismatch interrupt\n");
 428         lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 429         lsi_stop_script(s);
 430     }
 431     lsi_set_phase(s, new_phase);
 432 }
 433
 434
 435 /* Resume SCRIPTS execution after a DMA operation.  */
 436 static void lsi_resume_script(LSIState *s)
 437 {
 438     if (s->waiting != 2) {
 439         s->waiting = 0;
 440         lsi_execute_script(s);
 441     } else {
 442         s->waiting = 0;
 443     }
 444 }
 445
 446 /* Initiate a SCSI layer data transfer.  */
 447 static void lsi_do_dma(LSIState *s, int out)
 448 {
 449     uint32_t count;
 450     uint32_t addr;
 451
 452     if (!s->current_dma_len) {
 453         /* Wait until data is available.  */
 454         DPRINTF("DMA no data available\n");
 455         return;
 456     }
 457
 458     count = s->dbc;
 459     if (count > s->current_dma_len)
 460         count = s->current_dma_len;
 461     DPRINTF("DMA addr=0x%08x len=%d\n", s->dnad, count);
 462
 463     addr = s->dnad;
 464     s->csbc += count;
 465     s->dnad += count;
 466     s->dbc -= count;
 467
 468     if (s->dma_buf == NULL) {
 469         s->dma_buf = s->current_dev->get_buf(s->current_dev,
 470                                              s->current_tag);
 471     }
 472
 473     /* ??? Set SFBR to first data byte.  */
 474     if (out) {
 475         cpu_physical_memory_read(addr, s->dma_buf, count);
 476     } else {
 477         cpu_physical_memory_write(addr, s->dma_buf, count);
 478     }
 479     s->current_dma_len -= count;
 480     if (s->current_dma_len == 0) {
 481         s->dma_buf = NULL;
 482         if (out) {
 483             /* Write the data.  */
 484             s->current_dev->write_data(s->current_dev, s->current_tag);
 485         } else {
 486             /* Request any remaining data.  */
 487             s->current_dev->read_data(s->current_dev, s->current_tag);
 488         }
 489     } else {
 490         s->dma_buf += count;
 491         lsi_resume_script(s);
 492     }
 493 }
 494
 495
 496 /* Add a command to the queue.  */
 497 static void lsi_queue_command(LSIState *s)
 498 {
 499     lsi_queue *p;
 500
 501     DPRINTF("Queueing tag=0x%x\n", s->current_tag);
 502     if (s->queue_len == s->active_commands) {
 503         s->queue_len++;
 504         s->queue = realloc(s->queue, s->queue_len * sizeof(lsi_queue));
 505     }
 506     p = &s->queue[s->active_commands++];
 507     p->tag = s->current_tag;
 508     p->pending = 0;
 509     p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
 510 }
 511
 512 /* Queue a byte for a MSG IN phase.  */
 513 static void lsi_add_msg_byte(LSIState *s, uint8_t data)
 514 {
 515     if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
 516         BADF("MSG IN data too long\n");
 517     } else {
 518         DPRINTF("MSG IN 0x%02x\n", data);
 519         s->msg[s->msg_len++] = data;
 520     }
 521 }
 522
 523 /* Perform reselection to continue a command.  */
 524 static void lsi_reselect(LSIState *s, uint32_t tag)
 525 {
 526     lsi_queue *p;
 527     int n;
 528     int id;
 529
 530     p = NULL;
 531     for (n = 0; n < s->active_commands; n++) {
 532         p = &s->queue[n];
 533         if (p->tag == tag)
 534             break;
 535     }
 536     if (n == s->active_commands) {
 537         BADF("Reselected non-existant command tag=0x%x\n", tag);
 538         return;
 539     }
 540     id = (tag >> 8) & 0xf;
 541     s->ssid = id | 0x80;
 542     DPRINTF("Reselected target %d\n", id);
 543     s->current_dev = s->scsi_dev[id];
 544     s->current_tag = tag;
 545     s->scntl1 |= LSI_SCNTL1_CON;
 546     lsi_set_phase(s, PHASE_MI);
 547     s->msg_action = p->out ? 2 : 3;
 548     s->current_dma_len = p->pending;
 549     s->dma_buf = NULL;
 550     lsi_add_msg_byte(s, 0x80);
 551     if (s->current_tag & LSI_TAG_VALID) {
 552         lsi_add_msg_byte(s, 0x20);
 553         lsi_add_msg_byte(s, tag & 0xff);
 554     }
 555
 556     s->active_commands--;
 557     if (n != s->active_commands) {
 558         s->queue[n] = s->queue[s->active_commands];
 559     }
 560 }
 561
 562 /* Record that data is available for a queued command.  Returns zero if
 563    the device was reselected, nonzero if the IO is deferred.  */
 564 static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg)
 565 {
 566     lsi_queue *p;
 567     int i;
 568     for (i = 0; i < s->active_commands; i++) {
 569         p = &s->queue[i];
 570         if (p->tag == tag) {
 571             if (p->pending) {
 572                 BADF("Multiple IO pending for tag %d\n", tag);
 573             }
 574             p->pending = arg;
 575             if (s->waiting == 1) {
 576                 /* Reselect device.  */
 577                 lsi_reselect(s, tag);
 578                 return 0;
 579             } else {
 580                DPRINTF("Queueing IO tag=0x%x\n", tag);
 581                 p->pending = arg;
 582                 return 1;
 583             }
 584         }
 585     }
 586     BADF("IO with unknown tag %d\n", tag);
 587     return 1;
 588 }
 589
 590 /* Callback to indicate that the SCSI layer has completed a transfer.  */
 591 static void lsi_command_complete(void *opaque, int reason, uint32_t tag,
 592                                  uint32_t arg)
 593 {
 594     LSIState *s = (LSIState *)opaque;
 595     int out;
 596
 597     out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
 598     if (reason == SCSI_REASON_DONE) {
 599         DPRINTF("Command complete sense=%d\n", (int)arg);
 600         s->sense = arg;
 601         s->command_complete = 2;
 602         if (s->waiting && s->dbc != 0) {
 603             /* Raise phase mismatch for short transfers.  */
 604             lsi_bad_phase(s, out, PHASE_ST);
 605         } else {
 606             lsi_set_phase(s, PHASE_ST);
 607         }
 608         lsi_resume_script(s);
 609         return;
 610     }
 611
 612     if (s->waiting == 1 || tag != s->current_tag) {
 613         if (lsi_queue_tag(s, tag, arg))
 614             return;
 615     }
 616     DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
 617     s->current_dma_len = arg;
 618     s->command_complete = 1;
 619     if (!s->waiting)
 620         return;
 621     if (s->waiting == 1 || s->dbc == 0) {
 622         lsi_resume_script(s);
 623     } else {
 624         lsi_do_dma(s, out);
 625     }
 626 }
 627
 628 static void lsi_do_command(LSIState *s)
 629 {
 630     uint8_t buf[16];
 631     int n;
 632
 633     DPRINTF("Send command len=%d\n", s->dbc);
 634     if (s->dbc > 16)
 635         s->dbc = 16;
 636     cpu_physical_memory_read(s->dnad, buf, s->dbc);
 637     s->sfbr = buf[0];
 638     s->command_complete = 0;
 639     n = s->current_dev->send_command(s->current_dev, s->current_tag, buf,
 640                                      s->current_lun);
 641     if (n > 0) {
 642         lsi_set_phase(s, PHASE_DI);
 643         s->current_dev->read_data(s->current_dev, s->current_tag);
 644     } else if (n < 0) {
 645         lsi_set_phase(s, PHASE_DO);
 646         s->current_dev->write_data(s->current_dev, s->current_tag);
 647     }
 648
 649     if (!s->command_complete) {
 650         if (n) {
 651             /* Command did not complete immediately so disconnect.  */
 652             lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */
 653             lsi_add_msg_byte(s, 4); /* DISCONNECT */
 654             /* wait data */
 655             lsi_set_phase(s, PHASE_MI);
 656             s->msg_action = 1;
 657             lsi_queue_command(s);
 658         } else {
 659             /* wait command complete */
 660             lsi_set_phase(s, PHASE_DI);
 661         }
 662     }
 663 }
 664
 665 static void lsi_do_status(LSIState *s)
 666 {
 667     uint8_t sense;
 668     DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
 669     if (s->dbc != 1)
 670         BADF("Bad Status move\n");
 671     s->dbc = 1;
 672     sense = s->sense;
 673     s->sfbr = sense;
 674     cpu_physical_memory_write(s->dnad, &sense, 1);
 675     lsi_set_phase(s, PHASE_MI);
 676     s->msg_action = 1;
 677     lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
 678 }
 679
 680 static void lsi_disconnect(LSIState *s)
 681 {
 682     s->scntl1 &= ~LSI_SCNTL1_CON;
 683     s->sstat1 &= ~PHASE_MASK;
 684 }
 685
 686 static void lsi_do_msgin(LSIState *s)
 687 {
 688     int len;
 689     DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
 690     s->sfbr = s->msg[0];
 691     len = s->msg_len;
 692     if (len > s->dbc)
 693         len = s->dbc;
 694     cpu_physical_memory_write(s->dnad, s->msg, len);
 695     /* Linux drivers rely on the last byte being in the SIDL.  */
 696     s->sidl = s->msg[len - 1];
 697     s->msg_len -= len;
 698     if (s->msg_len) {
 699         memmove(s->msg, s->msg + len, s->msg_len);
 700     } else {
 701         /* ??? Check if ATN (not yet implemented) is asserted and maybe
 702            switch to PHASE_MO.  */
 703         switch (s->msg_action) {
 704         case 0:
 705             lsi_set_phase(s, PHASE_CMD);
 706             break;
 707         case 1:
 708             lsi_disconnect(s);
 709             break;
 710         case 2:
 711             lsi_set_phase(s, PHASE_DO);
 712             break;
 713         case 3:
 714             lsi_set_phase(s, PHASE_DI);
 715             break;
 716         default:
 717             abort();
 718         }
 719     }
 720 }
 721
 722 /* Read the next byte during a MSGOUT phase.  */
 723 static uint8_t lsi_get_msgbyte(LSIState *s)
 724 {
 725     uint8_t data;
 726     cpu_physical_memory_read(s->dnad, &data, 1);
 727     s->dnad++;
 728     s->dbc--;
 729     return data;
 730 }
 731
 732 static void lsi_do_msgout(LSIState *s)
 733 {
 734     uint8_t msg;
 735     int len;
 736
 737     DPRINTF("MSG out len=%d\n", s->dbc);
 738     while (s->dbc) {
 739         msg = lsi_get_msgbyte(s);
 740         s->sfbr = msg;
 741
 742         switch (msg) {
 743         case 0x00:
 744             DPRINTF("MSG: Disconnect\n");
 745             lsi_disconnect(s);
 746             break;
 747         case 0x08:
 748             DPRINTF("MSG: No Operation\n");
 749             lsi_set_phase(s, PHASE_CMD);
 750             break;
 751         case 0x01:
 752             len = lsi_get_msgbyte(s);
 753             msg = lsi_get_msgbyte(s);
 754             DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
 755             switch (msg) {
 756             case 1:
 757                 DPRINTF("SDTR (ignored)\n");
 758                 s->dbc -= 2;
 759                 break;
 760             case 3:
 761                 DPRINTF("WDTR (ignored)\n");
 762                 s->dbc -= 1;
 763                 break;
 764             default:
 765                 goto bad;
 766             }
 767             break;
 768         case 0x20: /* SIMPLE queue */
 769             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 770             DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff);
 771             break;
 772         case 0x21: /* HEAD of queue */
 773             BADF("HEAD queue not implemented\n");
 774             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 775             break;
 776         case 0x22: /* ORDERED queue */
 777             BADF("ORDERED queue not implemented\n");
 778             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 779             break;
 780         default:
 781             if ((msg & 0x80) == 0) {
 782                 goto bad;
 783             }
 784             s->current_lun = msg & 7;
 785             DPRINTF("Select LUN %d\n", s->current_lun);
 786             lsi_set_phase(s, PHASE_CMD);
 787             break;
 788         }
 789     }
 790     return;
 791 bad:
 792     BADF("Unimplemented message 0x%02x\n", msg);
 793     lsi_set_phase(s, PHASE_MI);
 794     lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */
 795     s->msg_action = 0;
 796 }
 797
 798 /* Sign extend a 24-bit value.  */
 799 static inline int32_t sxt24(int32_t n)
 800 {
 801     return (n << 8) >> 8;
 802 }
 803
 804 static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
 805 {
 806     int n;
 807     uint8_t buf[TARGET_PAGE_SIZE];
 808
 809     DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
 810     while (count) {
 811         n = (count > TARGET_PAGE_SIZE) ? TARGET_PAGE_SIZE : count;
 812         cpu_physical_memory_read(src, buf, n);
 813         cpu_physical_memory_write(dest, buf, n);
 814         src += n;
 815         dest += n;
 816         count -= n;
 817     }
 818 }
 819
 820 static void lsi_wait_reselect(LSIState *s)
 821 {
 822     int i;
 823     DPRINTF("Wait Reselect\n");
 824     if (s->current_dma_len)
 825         BADF("Reselect with pending DMA\n");
 826     for (i = 0; i < s->active_commands; i++) {
 827         if (s->queue[i].pending) {
 828             lsi_reselect(s, s->queue[i].tag);
 829             break;
 830         }
 831     }
 832     if (s->current_dma_len == 0) {
 833         s->waiting = 1;
 834     }
 835 }
 836
 837 static void lsi_execute_script(LSIState *s)
 838 {
 839     uint32_t insn;
 840     uint32_t addr;
 841     int opcode;
 842
 843     s->istat1 |= LSI_ISTAT1_SRUN;
 844 again:
 845     insn = read_dword(s, s->dsp);
 846     addr = read_dword(s, s->dsp + 4);
 847     DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
 848     s->dsps = addr;
 849     s->dcmd = insn >> 24;
 850     s->dsp += 8;
 851     switch (insn >> 30) {
 852     case 0: /* Block move.  */
 853         if (s->sist1 & LSI_SIST1_STO) {
 854             DPRINTF("Delayed select timeout\n");
 855             lsi_stop_script(s);
 856             break;
 857         }
 858         s->dbc = insn & 0xffffff;
 859         s->rbc = s->dbc;
 860         if (insn & (1 << 29)) {
 861             /* Indirect addressing.  */
 862             addr = read_dword(s, addr);
 863         } else if (insn & (1 << 28)) {
 864             uint32_t buf[2];
 865             int32_t offset;
 866             /* Table indirect addressing.  */
 867             offset = sxt24(addr);
 868             cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
 869             s->dbc = cpu_to_le32(buf[0]);
 870             s->rbc = s->dbc;
 871             addr = cpu_to_le32(buf[1]);
 872         }
 873         if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
 874             DPRINTF("Wrong phase got %d expected %d\n",
 875                     s->sstat1 & PHASE_MASK, (insn >> 24) & 7);
 876             lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 877             break;
 878         }
 879         s->dnad = addr;
 880         /* ??? Set ESA.  */
 881         s->ia = s->dsp - 8;
 882         switch (s->sstat1 & 0x7) {
 883         case PHASE_DO:
 884             s->waiting = 2;
 885             lsi_do_dma(s, 1);
 886             if (s->waiting)
 887                 s->waiting = 3;
 888             break;
 889         case PHASE_DI:
 890             s->waiting = 2;
 891             lsi_do_dma(s, 0);
 892             if (s->waiting)
 893                 s->waiting = 3;
 894             break;
 895         case PHASE_CMD:
 896             lsi_do_command(s);
 897             break;
 898         case PHASE_ST:
 899             lsi_do_status(s);
 900             break;
 901         case PHASE_MO:
 902             lsi_do_msgout(s);
 903             break;
 904         case PHASE_MI:
 905             lsi_do_msgin(s);
 906             break;
 907         default:
 908             BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
 909             exit(1);
 910         }
 911         s->dfifo = s->dbc & 0xff;
 912         s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
 913         s->sbc = s->dbc;
 914         s->rbc -= s->dbc;
 915         s->ua = addr + s->dbc;
 916         break;
 917
 918     case 1: /* IO or Read/Write instruction.  */
 919         opcode = (insn >> 27) & 7;
 920         if (opcode < 5) {
 921             uint32_t id;
 922
 923             if (insn & (1 << 25)) {
 924                 id = read_dword(s, s->dsa + sxt24(insn));
 925             } else {
 926                 id = addr;
 927             }
 928             id = (id >> 16) & 0xf;
 929             if (insn & (1 << 26)) {
 930                 addr = s->dsp + sxt24(addr);
 931             }
 932             s->dnad = addr;
 933             switch (opcode) {
 934             case 0: /* Select */
 935                 s->sdid = id;
 936                 if (s->current_dma_len && (s->ssid & 0xf) == id) {
 937                     DPRINTF("Already reselected by target %d\n", id);
 938                     break;
 939                 }
 940                 s->sstat0 |= LSI_SSTAT0_WOA;
 941                 s->scntl1 &= ~LSI_SCNTL1_IARB;
 942                 if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
 943                     DPRINTF("Selected absent target %d\n", id);
 944                     lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
 945                     lsi_disconnect(s);
 946                     break;
 947                 }
 948                 DPRINTF("Selected target %d%s\n",
 949                         id, insn & (1 << 3) ? " ATN" : "");
 950                 /* ??? Linux drivers compain when this is set.  Maybe
 951                    it only applies in low-level mode (unimplemented).
 952                 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
 953                 s->current_dev = s->scsi_dev[id];
 954                 s->current_tag = id << 8;
 955                 s->scntl1 |= LSI_SCNTL1_CON;
 956                 if (insn & (1 << 3)) {
 957                     s->socl |= LSI_SOCL_ATN;
 958                 }
 959                 lsi_set_phase(s, PHASE_MO);
 960                 break;
 961             case 1: /* Disconnect */
 962                 DPRINTF("Wait Disconect\n");
 963                 s->scntl1 &= ~LSI_SCNTL1_CON;
 964                 break;
 965             case 2: /* Wait Reselect */
 966                 lsi_wait_reselect(s);
 967                 break;
 968             case 3: /* Set */
 969                 DPRINTF("Set%s%s%s%s\n",
 970                         insn & (1 << 3) ? " ATN" : "",
 971                         insn & (1 << 6) ? " ACK" : "",
 972                         insn & (1 << 9) ? " TM" : "",
 973                         insn & (1 << 10) ? " CC" : "");
 974                 if (insn & (1 << 3)) {
 975                     s->socl |= LSI_SOCL_ATN;
 976                     lsi_set_phase(s, PHASE_MO);
 977                 }
 978                 if (insn & (1 << 9)) {
 979                     BADF("Target mode not implemented\n");
 980                     exit(1);
 981                 }
 982                 if (insn & (1 << 10))
 983                     s->carry = 1;
 984                 break;
 985             case 4: /* Clear */
 986                 DPRINTF("Clear%s%s%s%s\n",
 987                         insn & (1 << 3) ? " ATN" : "",
 988                         insn & (1 << 6) ? " ACK" : "",
 989                         insn & (1 << 9) ? " TM" : "",
 990                         insn & (1 << 10) ? " CC" : "");
 991                 if (insn & (1 << 3)) {
 992                     s->socl &= ~LSI_SOCL_ATN;
 993                 }
 994                 if (insn & (1 << 10))
 995                     s->carry = 0;
 996                 break;
 997             }
 998         } else {
 999             uint8_t op0;
1000             uint8_t op1;
1001             uint8_t data8;
1002             int reg;
1003             int operator;
1004 #ifdef DEBUG_LSI
1005             static const char *opcode_names[3] =
1006                 {"Write", "Read", "Read-Modify-Write"};
1007             static const char *operator_names[8] =
1008                 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1009 #endif
1010
1011             reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
1012             data8 = (insn >> 8) & 0xff;
1013             opcode = (insn >> 27) & 7;
1014             operator = (insn >> 24) & 7;
1015             DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1016                     opcode_names[opcode - 5], reg,
1017                     operator_names[operator], data8, s->sfbr,
1018                     (insn & (1 << 23)) ? " SFBR" : "");
1019             op0 = op1 = 0;
1020             switch (opcode) {
1021             case 5: /* From SFBR */
1022                 op0 = s->sfbr;
1023                 op1 = data8;
1024                 break;
1025             case 6: /* To SFBR */
1026                 if (operator)
1027                     op0 = lsi_reg_readb(s, reg);
1028                 op1 = data8;
1029                 break;
1030             case 7: /* Read-modify-write */
1031                 if (operator)
1032                     op0 = lsi_reg_readb(s, reg);
1033                 if (insn & (1 << 23)) {
1034                     op1 = s->sfbr;
1035                 } else {
1036                     op1 = data8;
1037                 }
1038                 break;
1039             }
1040
1041             switch (operator) {
1042             case 0: /* move */
1043                 op0 = op1;
1044                 break;
1045             case 1: /* Shift left */
1046                 op1 = op0 >> 7;
1047                 op0 = (op0 << 1) | s->carry;
1048                 s->carry = op1;
1049                 break;
1050             case 2: /* OR */
1051                 op0 |= op1;
1052                 break;
1053             case 3: /* XOR */
1054                 op0 ^= op1;
1055                 break;
1056             case 4: /* AND */
1057                 op0 &= op1;
1058                 break;
1059             case 5: /* SHR */
1060                 op1 = op0 & 1;
1061                 op0 = (op0 >> 1) | (s->carry << 7);
1062                 s->carry = op1;
1063                 break;
1064             case 6: /* ADD */
1065                 op0 += op1;
1066                 s->carry = op0 < op1;
1067                 break;
1068             case 7: /* ADC */
1069                 op0 += op1 + s->carry;
1070                 if (s->carry)
1071                     s->carry = op0 <= op1;
1072                 else
1073                     s->carry = op0 < op1;
1074                 break;
1075             }
1076
1077             switch (opcode) {
1078             case 5: /* From SFBR */
1079             case 7: /* Read-modify-write */
1080                 lsi_reg_writeb(s, reg, op0);
1081                 break;
1082             case 6: /* To SFBR */
1083                 s->sfbr = op0;
1084                 break;
1085             }
1086         }
1087         break;
1088
1089     case 2: /* Transfer Control.  */
1090         {
1091             int cond;
1092             int jmp;
1093
1094             if ((insn & 0x002e0000) == 0) {
1095                 DPRINTF("NOP\n");
1096                 break;
1097             }
1098             if (s->sist1 & LSI_SIST1_STO) {
1099                 DPRINTF("Delayed select timeout\n");
1100                 lsi_stop_script(s);
1101                 break;
1102             }
1103             cond = jmp = (insn & (1 << 19)) != 0;
1104             if (cond == jmp && (insn & (1 << 21))) {
1105                 DPRINTF("Compare carry %d\n", s->carry == jmp);
1106                 cond = s->carry != 0;
1107             }
1108             if (cond == jmp && (insn & (1 << 17))) {
1109                 DPRINTF("Compare phase %d %c= %d\n",
1110                         (s->sstat1 & PHASE_MASK),
1111                         jmp ? '=' : '!',
1112                         ((insn >> 24) & 7));
1113                 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7);
1114             }
1115             if (cond == jmp && (insn & (1 << 18))) {
1116                 uint8_t mask;
1117
1118                 mask = (~insn >> 8) & 0xff;
1119                 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1120                         s->sfbr, mask, jmp ? '=' : '!', insn & mask);
1121                 cond = (s->sfbr & mask) == (insn & mask);
1122             }
1123             if (cond == jmp) {
1124                 if (insn & (1 << 23)) {
1125                     /* Relative address.  */
1126                     addr = s->dsp + sxt24(addr);
1127                 }
1128                 switch ((insn >> 27) & 7) {
1129                 case 0: /* Jump */
1130                     DPRINTF("Jump to 0x%08x\n", addr);
1131                     s->dsp = addr;
1132                     break;
1133                 case 1: /* Call */
1134                     DPRINTF("Call 0x%08x\n", addr);
1135                     s->temp = s->dsp;
1136                     s->dsp = addr;
1137                     break;
1138                 case 2: /* Return */
1139                     DPRINTF("Return to 0x%08x\n", s->temp);
1140                     s->dsp = s->temp;
1141                     break;
1142                 case 3: /* Interrupt */
1143                     DPRINTF("Interrupt 0x%08x\n", s->dsps);
1144                     if ((insn & (1 << 20)) != 0) {
1145                         s->istat0 |= LSI_ISTAT0_INTF;
1146                         lsi_update_irq(s);
1147                     } else {
1148                         lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
1149                     }
1150                     break;
1151                 default:
1152                     DPRINTF("Illegal transfer control\n");
1153                     lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
1154                     break;
1155                 }
1156             } else {
1157                 DPRINTF("Control condition failed\n");
1158             }
1159         }
1160         break;
1161
1162     case 3:
1163         if ((insn & (1 << 29)) == 0) {
1164             /* Memory move.  */
1165             uint32_t dest;
1166             /* ??? The docs imply the destination address is loaded into
1167                the TEMP register.  However the Linux drivers rely on
1168                the value being presrved.  */
1169             dest = read_dword(s, s->dsp);
1170             s->dsp += 4;
1171             lsi_memcpy(s, dest, addr, insn & 0xffffff);
1172         } else {
1173             uint8_t data[7];
1174             int reg;
1175             int n;
1176             int i;
1177
1178             if (insn & (1 << 28)) {
1179                 addr = s->dsa + sxt24(addr);
1180             }
1181             n = (insn & 7);
1182             reg = (insn >> 16) & 0xff;
1183             if (insn & (1 << 24)) {
1184                 cpu_physical_memory_read(addr, data, n);
1185                 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1186                         addr, *(int *)data);
1187                 for (i = 0; i < n; i++) {
1188                     lsi_reg_writeb(s, reg + i, data[i]);
1189                 }
1190             } else {
1191                 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
1192                 for (i = 0; i < n; i++) {
1193                     data[i] = lsi_reg_readb(s, reg + i);
1194                 }
1195                 cpu_physical_memory_write(addr, data, n);
1196             }
1197         }
1198     }
1199     /* ??? Need to avoid infinite loops.  */
1200     if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
1201         if (s->dcntl & LSI_DCNTL_SSM) {
1202             lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
1203         } else {
1204             goto again;
1205         }
1206     }
1207     DPRINTF("SCRIPTS execution stopped\n");
1208 }
1209
1210 static uint8_t lsi_reg_readb(LSIState *s, int offset)
1211 {
1212     uint8_t tmp;
1213 #define CASE_GET_REG32(name, addr) \
1214     case addr: return s->name & 0xff; \
1215     case addr + 1: return (s->name >> 8) & 0xff; \
1216     case addr + 2: return (s->name >> 16) & 0xff; \
1217     case addr + 3: return (s->name >> 24) & 0xff;
1218
1219 #ifdef DEBUG_LSI_REG
1220     DPRINTF("Read reg %x\n", offset);
1221 #endif
1222     switch (offset) {
1223     case 0x00: /* SCNTL0 */
1224         return s->scntl0;
1225     case 0x01: /* SCNTL1 */
1226         return s->scntl1;
1227     case 0x02: /* SCNTL2 */
1228         return s->scntl2;
1229     case 0x03: /* SCNTL3 */
1230         return s->scntl3;
1231     case 0x04: /* SCID */
1232         return s->scid;
1233     case 0x05: /* SXFER */
1234         return s->sxfer;
1235     case 0x06: /* SDID */
1236         return s->sdid;
1237     case 0x07: /* GPREG0 */
1238         return 0x7f;
1239     case 0x08: /* Revision ID */
1240         return 0x00;
1241     case 0xa: /* SSID */
1242         return s->ssid;
1243     case 0xb: /* SBCL */
1244         /* ??? This is not correct. However it's (hopefully) only
1245            used for diagnostics, so should be ok.  */
1246         return 0;
1247     case 0xc: /* DSTAT */
1248         tmp = s->dstat | 0x80;
1249         if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1250             s->dstat = 0;
1251         lsi_update_irq(s);
1252         return tmp;
1253     case 0x0d: /* SSTAT0 */
1254         return s->sstat0;
1255     case 0x0e: /* SSTAT1 */
1256         return s->sstat1;
1257     case 0x0f: /* SSTAT2 */
1258         return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
1259     CASE_GET_REG32(dsa, 0x10)
1260     case 0x14: /* ISTAT0 */
1261         return s->istat0;
1262     case 0x16: /* MBOX0 */
1263         return s->mbox0;
1264     case 0x17: /* MBOX1 */
1265         return s->mbox1;
1266     case 0x18: /* CTEST0 */
1267         return 0xff;
1268     case 0x19: /* CTEST1 */
1269         return 0;
1270     case 0x1a: /* CTEST2 */
1271         tmp = LSI_CTEST2_DACK | LSI_CTEST2_CM;
1272         if (s->istat0 & LSI_ISTAT0_SIGP) {
1273             s->istat0 &= ~LSI_ISTAT0_SIGP;
1274             tmp |= LSI_CTEST2_SIGP;
1275         }
1276         return tmp;
1277     case 0x1b: /* CTEST3 */
1278         return s->ctest3;
1279     CASE_GET_REG32(temp, 0x1c)
1280     case 0x20: /* DFIFO */
1281         return 0;
1282     case 0x21: /* CTEST4 */
1283         return s->ctest4;
1284     case 0x22: /* CTEST5 */
1285         return s->ctest5;
1286     case 0x23: /* CTEST6 */
1287          return 0;
1288     case 0x24: /* DBC[0:7] */
1289         return s->dbc & 0xff;
1290     case 0x25: /* DBC[8:15] */
1291         return (s->dbc >> 8) & 0xff;
1292     case 0x26: /* DBC[16->23] */
1293         return (s->dbc >> 16) & 0xff;
1294     case 0x27: /* DCMD */
1295         return s->dcmd;
1296     CASE_GET_REG32(dsp, 0x2c)
1297     CASE_GET_REG32(dsps, 0x30)
1298     CASE_GET_REG32(scratch[0], 0x34)
1299     case 0x38: /* DMODE */
1300         return s->dmode;
1301     case 0x39: /* DIEN */
1302         return s->dien;
1303     case 0x3b: /* DCNTL */
1304         return s->dcntl;
1305     case 0x40: /* SIEN0 */
1306         return s->sien0;
1307     case 0x41: /* SIEN1 */
1308         return s->sien1;
1309     case 0x42: /* SIST0 */
1310         tmp = s->sist0;
1311         s->sist0 = 0;
1312         lsi_update_irq(s);
1313         return tmp;
1314     case 0x43: /* SIST1 */
1315         tmp = s->sist1;
1316         s->sist1 = 0;
1317         lsi_update_irq(s);
1318         return tmp;
1319     case 0x47: /* GPCNTL0 */
1320         return 0x0f;
1321     case 0x48: /* STIME0 */
1322         return s->stime0;
1323     case 0x4a: /* RESPID0 */
1324         return s->respid0;
1325     case 0x4b: /* RESPID1 */
1326         return s->respid1;
1327     case 0x4d: /* STEST1 */
1328         return s->stest1;
1329     case 0x4e: /* STEST2 */
1330         return s->stest2;
1331     case 0x4f: /* STEST3 */
1332         return s->stest3;
1333     case 0x50: /* SIDL */
1334         /* This is needed by the linux drivers.  We currently only update it
1335            during the MSG IN phase.  */
1336         return s->sidl;
1337     case 0x52: /* STEST4 */
1338         return 0xe0;
1339     case 0x56: /* CCNTL0 */
1340         return s->ccntl0;
1341     case 0x57: /* CCNTL1 */
1342         return s->ccntl1;
1343     case 0x58: /* SBDL */
1344         /* Some drivers peek at the data bus during the MSG IN phase.  */
1345         if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
1346             return s->msg[0];
1347         return 0;
1348     case 0x59: /* SBDL high */
1349         return 0;
1350     CASE_GET_REG32(mmrs, 0xa0)
1351     CASE_GET_REG32(mmws, 0xa4)
1352     CASE_GET_REG32(sfs, 0xa8)
1353     CASE_GET_REG32(drs, 0xac)
1354     CASE_GET_REG32(sbms, 0xb0)
1355     CASE_GET_REG32(dmbs, 0xb4)
1356     CASE_GET_REG32(dnad64, 0xb8)
1357     CASE_GET_REG32(pmjad1, 0xc0)
1358     CASE_GET_REG32(pmjad2, 0xc4)
1359     CASE_GET_REG32(rbc, 0xc8)
1360     CASE_GET_REG32(ua, 0xcc)
1361     CASE_GET_REG32(ia, 0xd4)
1362     CASE_GET_REG32(sbc, 0xd8)
1363     CASE_GET_REG32(csbc, 0xdc)
1364     }
1365     if (offset >= 0x5c && offset < 0xa0) {
1366         int n;
1367         int shift;
1368         n = (offset - 0x58) >> 2;
1369         shift = (offset & 3) * 8;
1370         return (s->scratch[n] >> shift) & 0xff;
1371     }
1372     BADF("readb 0x%x\n", offset);
1373     exit(1);
1374 #undef CASE_GET_REG32
1375 }
1376
1377 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
1378 {
1379 #define CASE_SET_REG32(name, addr) \
1380     case addr    : s->name &= 0xffffff00; s->name |= val;       break; \
1381     case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8;  break; \
1382     case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1383     case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1384
1385 #ifdef DEBUG_LSI_REG
1386     DPRINTF("Write reg %x = %02x\n", offset, val);
1387 #endif
1388     switch (offset) {
1389     case 0x00: /* SCNTL0 */
1390         s->scntl0 = val;
1391         if (val & LSI_SCNTL0_START) {
1392             BADF("Start sequence not implemented\n");
1393         }
1394         break;
1395     case 0x01: /* SCNTL1 */
1396         s->scntl1 = val & ~LSI_SCNTL1_SST;
1397         if (val & LSI_SCNTL1_IARB) {
1398             BADF("Immediate Arbritration not implemented\n");
1399         }
1400         if (val & LSI_SCNTL1_RST) {
1401             s->sstat0 |= LSI_SSTAT0_RST;
1402             lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1403         } else {
1404             s->sstat0 &= ~LSI_SSTAT0_RST;
1405         }
1406         break;
1407     case 0x02: /* SCNTL2 */
1408         val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
1409         s->scntl2 = val;
1410         break;
1411     case 0x03: /* SCNTL3 */
1412         s->scntl3 = val;
1413         break;
1414     case 0x04: /* SCID */
1415         s->scid = val;
1416         break;
1417     case 0x05: /* SXFER */
1418         s->sxfer = val;
1419         break;
1420     case 0x06: /* SDID */
1421         if ((val & 0xf) != (s->ssid & 0xf))
1422             BADF("Destination ID does not match SSID\n");
1423         s->sdid = val & 0xf;
1424         break;
1425     case 0x07: /* GPREG0 */
1426         break;
1427     case 0x08: /* SFBR */
1428         /* The CPU is not allowed to write to this register.  However the
1429            SCRIPTS register move instructions are.  */
1430         s->sfbr = val;
1431         break;
1432     case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1433         /* Linux writes to these readonly registers on startup.  */
1434         return;
1435     CASE_SET_REG32(dsa, 0x10)
1436     case 0x14: /* ISTAT0 */
1437         s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1438         if (val & LSI_ISTAT0_ABRT) {
1439             lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1440         }
1441         if (val & LSI_ISTAT0_INTF) {
1442             s->istat0 &= ~LSI_ISTAT0_INTF;
1443             lsi_update_irq(s);
1444         }
1445         if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
1446             DPRINTF("Woken by SIGP\n");
1447             s->waiting = 0;
1448             s->dsp = s->dnad;
1449             lsi_execute_script(s);
1450         }
1451         if (val & LSI_ISTAT0_SRST) {
1452             lsi_soft_reset(s);
1453         }
1454         break;
1455     case 0x16: /* MBOX0 */
1456         s->mbox0 = val;
1457         break;
1458     case 0x17: /* MBOX1 */
1459         s->mbox1 = val;
1460         break;
1461     case 0x1b: /* CTEST3 */
1462         s->ctest3 = val & 0x0f;
1463         break;
1464     CASE_SET_REG32(temp, 0x1c)
1465     case 0x21: /* CTEST4 */
1466         if (val & 7) {
1467            BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
1468         }
1469         s->ctest4 = val;
1470         break;
1471     case 0x22: /* CTEST5 */
1472         if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
1473             BADF("CTEST5 DMA increment not implemented\n");
1474         }
1475         s->ctest5 = val;
1476         break;
1477     case 0x2c: /* DSP[0:7] */
1478         s->dsp &= 0xffffff00;
1479         s->dsp |= val;
1480         break;
1481     case 0x2d: /* DSP[8:15] */
1482         s->dsp &= 0xffff00ff;
1483         s->dsp |= val << 8;
1484         break;
1485     case 0x2e: /* DSP[16:23] */
1486         s->dsp &= 0xff00ffff;
1487         s->dsp |= val << 16;
1488         break;
1489     case 0x2f: /* DSP[24:31] */
1490         s->dsp &= 0x00ffffff;
1491         s->dsp |= val << 24;
1492         if ((s->dmode & LSI_DMODE_MAN) == 0
1493             && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1494             lsi_execute_script(s);
1495         break;
1496     CASE_SET_REG32(dsps, 0x30)
1497     CASE_SET_REG32(scratch[0], 0x34)
1498     case 0x38: /* DMODE */
1499         if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1500             BADF("IO mappings not implemented\n");
1501         }
1502         s->dmode = val;
1503         break;
1504     case 0x39: /* DIEN */
1505         s->dien = val;
1506         lsi_update_irq(s);
1507         break;
1508     case 0x3b: /* DCNTL */
1509         s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1510         if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1511             lsi_execute_script(s);
1512         break;
1513     case 0x40: /* SIEN0 */
1514         s->sien0 = val;
1515         lsi_update_irq(s);
1516         break;
1517     case 0x41: /* SIEN1 */
1518         s->sien1 = val;
1519         lsi_update_irq(s);
1520         break;
1521     case 0x47: /* GPCNTL0 */
1522         break;
1523     case 0x48: /* STIME0 */
1524         s->stime0 = val;
1525         break;
1526     case 0x49: /* STIME1 */
1527         if (val & 0xf) {
1528             DPRINTF("General purpose timer not implemented\n");
1529             /* ??? Raising the interrupt immediately seems to be sufficient
1530                to keep the FreeBSD driver happy.  */
1531             lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
1532         }
1533         break;
1534     case 0x4a: /* RESPID0 */
1535         s->respid0 = val;
1536         break;
1537     case 0x4b: /* RESPID1 */
1538         s->respid1 = val;
1539         break;
1540     case 0x4d: /* STEST1 */
1541         s->stest1 = val;
1542         break;
1543     case 0x4e: /* STEST2 */
1544         if (val & 1) {
1545             BADF("Low level mode not implemented\n");
1546         }
1547         s->stest2 = val;
1548         break;
1549     case 0x4f: /* STEST3 */
1550         if (val & 0x41) {
1551             BADF("SCSI FIFO test mode not implemented\n");
1552         }
1553         s->stest3 = val;
1554         break;
1555     case 0x56: /* CCNTL0 */
1556         s->ccntl0 = val;
1557         break;
1558     case 0x57: /* CCNTL1 */
1559         s->ccntl1 = val;
1560         break;
1561     CASE_SET_REG32(mmrs, 0xa0)
1562     CASE_SET_REG32(mmws, 0xa4)
1563     CASE_SET_REG32(sfs, 0xa8)
1564     CASE_SET_REG32(drs, 0xac)
1565     CASE_SET_REG32(sbms, 0xb0)
1566     CASE_SET_REG32(dmbs, 0xb4)
1567     CASE_SET_REG32(dnad64, 0xb8)
1568     CASE_SET_REG32(pmjad1, 0xc0)
1569     CASE_SET_REG32(pmjad2, 0xc4)
1570     CASE_SET_REG32(rbc, 0xc8)
1571     CASE_SET_REG32(ua, 0xcc)
1572     CASE_SET_REG32(ia, 0xd4)
1573     CASE_SET_REG32(sbc, 0xd8)
1574     CASE_SET_REG32(csbc, 0xdc)
1575     default:
1576         if (offset >= 0x5c && offset < 0xa0) {
1577             int n;
1578             int shift;
1579             n = (offset - 0x58) >> 2;
1580             shift = (offset & 3) * 8;
1581             s->scratch[n] &= ~(0xff << shift);
1582             s->scratch[n] |= (val & 0xff) << shift;
1583         } else {
1584             BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
1585         }
1586     }
1587 #undef CASE_SET_REG32
1588 }
1589
1590 static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1591 {
1592     LSIState *s = (LSIState *)opaque;
1593
1594     lsi_reg_writeb(s, addr & 0xff, val);
1595 }
1596
1597 static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1598 {
1599     LSIState *s = (LSIState *)opaque;
1600
1601     addr &= 0xff;
1602     lsi_reg_writeb(s, addr, val & 0xff);
1603     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1604 }
1605
1606 static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1607 {
1608     LSIState *s = (LSIState *)opaque;
1609
1610     addr &= 0xff;
1611     lsi_reg_writeb(s, addr, val & 0xff);
1612     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1613     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1614     lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1615 }
1616
1617 static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
1618 {
1619     LSIState *s = (LSIState *)opaque;
1620
1621     return lsi_reg_readb(s, addr & 0xff);
1622 }
1623
1624 static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
1625 {
1626     LSIState *s = (LSIState *)opaque;
1627     uint32_t val;
1628
1629     addr &= 0xff;
1630     val = lsi_reg_readb(s, addr);
1631     val |= lsi_reg_readb(s, addr + 1) << 8;
1632     return val;
1633 }
1634
1635 static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
1636 {
1637     LSIState *s = (LSIState *)opaque;
1638     uint32_t val;
1639     addr &= 0xff;
1640     val = lsi_reg_readb(s, addr);
1641     val |= lsi_reg_readb(s, addr + 1) << 8;
1642     val |= lsi_reg_readb(s, addr + 2) << 16;
1643     val |= lsi_reg_readb(s, addr + 3) << 24;
1644     return val;
1645 }
1646
1647 static CPUReadMemoryFunc *lsi_mmio_readfn[3] = {
1648     lsi_mmio_readb,
1649     lsi_mmio_readw,
1650     lsi_mmio_readl,
1651 };
1652
1653 static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = {
1654     lsi_mmio_writeb,
1655     lsi_mmio_writew,
1656     lsi_mmio_writel,
1657 };
1658
1659 static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1660 {
1661     LSIState *s = (LSIState *)opaque;
1662     uint32_t newval;
1663     int shift;
1664
1665     addr &= 0x1fff;
1666     newval = s->script_ram[addr >> 2];
1667     shift = (addr & 3) * 8;
1668     newval &= ~(0xff << shift);
1669     newval |= val << shift;
1670     s->script_ram[addr >> 2] = newval;
1671 }
1672
1673 static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1674 {
1675     LSIState *s = (LSIState *)opaque;
1676     uint32_t newval;
1677
1678     addr &= 0x1fff;
1679     newval = s->script_ram[addr >> 2];
1680     if (addr & 2) {
1681         newval = (newval & 0xffff) | (val << 16);
1682     } else {
1683         newval = (newval & 0xffff0000) | val;
1684     }
1685     s->script_ram[addr >> 2] = newval;
1686 }
1687
1688
1689 static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1690 {
1691     LSIState *s = (LSIState *)opaque;
1692
1693     addr &= 0x1fff;
1694     s->script_ram[addr >> 2] = val;
1695 }
1696
1697 static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
1698 {
1699     LSIState *s = (LSIState *)opaque;
1700     uint32_t val;
1701
1702     addr &= 0x1fff;
1703     val = s->script_ram[addr >> 2];
1704     val >>= (addr & 3) * 8;
1705     return val & 0xff;
1706 }
1707
1708 static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
1709 {
1710     LSIState *s = (LSIState *)opaque;
1711     uint32_t val;
1712
1713     addr &= 0x1fff;
1714     val = s->script_ram[addr >> 2];
1715     if (addr & 2)
1716         val >>= 16;
1717     return le16_to_cpu(val);
1718 }
1719
1720 static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
1721 {
1722     LSIState *s = (LSIState *)opaque;
1723
1724     addr &= 0x1fff;
1725     return le32_to_cpu(s->script_ram[addr >> 2]);
1726 }
1727
1728 static CPUReadMemoryFunc *lsi_ram_readfn[3] = {
1729     lsi_ram_readb,
1730     lsi_ram_readw,
1731     lsi_ram_readl,
1732 };
1733
1734 static CPUWriteMemoryFunc *lsi_ram_writefn[3] = {
1735     lsi_ram_writeb,
1736     lsi_ram_writew,
1737     lsi_ram_writel,
1738 };
1739
1740 static uint32_t lsi_io_readb(void *opaque, uint32_t addr)
1741 {
1742     LSIState *s = (LSIState *)opaque;
1743     return lsi_reg_readb(s, addr & 0xff);
1744 }
1745
1746 static uint32_t lsi_io_readw(void *opaque, uint32_t addr)
1747 {
1748     LSIState *s = (LSIState *)opaque;
1749     uint32_t val;
1750     addr &= 0xff;
1751     val = lsi_reg_readb(s, addr);
1752     val |= lsi_reg_readb(s, addr + 1) << 8;
1753     return val;
1754 }
1755
1756 static uint32_t lsi_io_readl(void *opaque, uint32_t addr)
1757 {
1758     LSIState *s = (LSIState *)opaque;
1759     uint32_t val;
1760     addr &= 0xff;
1761     val = lsi_reg_readb(s, addr);
1762     val |= lsi_reg_readb(s, addr + 1) << 8;
1763     val |= lsi_reg_readb(s, addr + 2) << 16;
1764     val |= lsi_reg_readb(s, addr + 3) << 24;
1765     return val;
1766 }
1767
1768 static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val)
1769 {
1770     LSIState *s = (LSIState *)opaque;
1771     lsi_reg_writeb(s, addr & 0xff, val);
1772 }
1773
1774 static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val)
1775 {
1776     LSIState *s = (LSIState *)opaque;
1777     addr &= 0xff;
1778     lsi_reg_writeb(s, addr, val & 0xff);
1779     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1780 }
1781
1782 static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
1783 {
1784     LSIState *s = (LSIState *)opaque;
1785     addr &= 0xff;
1786     lsi_reg_writeb(s, addr, val & 0xff);
1787     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1788     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1789     lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1790 }
1791
1792 static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
1793                            uint32_t addr, uint32_t size, int type)
1794 {
1795     LSIState *s = (LSIState *)pci_dev;
1796
1797     DPRINTF("Mapping IO at %08x\n", addr);
1798
1799     register_ioport_write(addr, 256, 1, lsi_io_writeb, s);
1800     register_ioport_read(addr, 256, 1, lsi_io_readb, s);
1801     register_ioport_write(addr, 256, 2, lsi_io_writew, s);
1802     register_ioport_read(addr, 256, 2, lsi_io_readw, s);
1803     register_ioport_write(addr, 256, 4, lsi_io_writel, s);
1804     register_ioport_read(addr, 256, 4, lsi_io_readl, s);
1805 }
1806
1807 static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
1808                             uint32_t addr, uint32_t size, int type)
1809 {
1810     LSIState *s = (LSIState *)pci_dev;
1811
1812     DPRINTF("Mapping ram at %08x\n", addr);
1813     s->script_ram_base = addr;
1814     cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
1815 }
1816
1817 static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
1818                              uint32_t addr, uint32_t size, int type)
1819 {
1820     LSIState *s = (LSIState *)pci_dev;
1821
1822     DPRINTF("Mapping registers at %08x\n", addr);
1823     cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
1824 }
1825
1826 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id)
1827 {
1828     LSIState *s = (LSIState *)opaque;
1829
1830     if (id < 0) {
1831         for (id = 0; id < LSI_MAX_DEVS; id++) {
1832             if (s->scsi_dev[id] == NULL)
1833                 break;
1834         }
1835     }
1836     if (id >= LSI_MAX_DEVS) {
1837         BADF("Bad Device ID %d\n", id);
1838         return;
1839     }
1840     if (s->scsi_dev[id]) {
1841         DPRINTF("Destroying device %d\n", id);
1842         s->scsi_dev[id]->destroy(s->scsi_dev[id]);
1843     }
1844     DPRINTF("Attaching block device %d\n", id);
1845     s->scsi_dev[id] = scsi_generic_init(bd, 1, lsi_command_complete, s);
1846     if (s->scsi_dev[id] == NULL)
1847         s->scsi_dev[id] = scsi_disk_init(bd, 1, lsi_command_complete, s);
1848 }
1849
1850 void *lsi_scsi_init(PCIBus *bus, int devfn)
1851 {
1852     LSIState *s;
1853
1854     s = (LSIState *)pci_register_device(bus, "LSI53C895A SCSI HBA",
1855                                         sizeof(*s), devfn, NULL, NULL);
1856     if (s == NULL) {
1857         fprintf(stderr, "lsi-scsi: Failed to register PCI device\n");
1858         return NULL;
1859     }
1860
1861     s->pci_dev.config[0x00] = 0x00;
1862     s->pci_dev.config[0x01] = 0x10;
1863     s->pci_dev.config[0x02] = 0x12;
1864     s->pci_dev.config[0x03] = 0x00;
1865     s->pci_dev.config[0x0b] = 0x01;
1866     s->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
1867
1868     s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn,
1869                                              lsi_mmio_writefn, s);
1870     s->ram_io_addr = cpu_register_io_memory(0, lsi_ram_readfn,
1871                                             lsi_ram_writefn, s);
1872
1873     pci_register_io_region((struct PCIDevice *)s, 0, 256,
1874                            PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc);
1875     pci_register_io_region((struct PCIDevice *)s, 1, 0x400,
1876                            PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc);
1877     pci_register_io_region((struct PCIDevice *)s, 2, 0x2000,
1878                            PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc);
1879     s->queue = qemu_malloc(sizeof(lsi_queue));
1880     s->queue_len = 1;
1881     s->active_commands = 0;
1882
1883     lsi_soft_reset(s);
1884
1885     return s;
1886 }
1887