hw/sh7750.c

   1 /*
   2  * SH7750 device
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Copyright (c) 2005 Samuel Tardieu
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <stdio.h>
  26 #include <assert.h>
  27 #include "hw.h"
  28 #include "sh.h"
  29 #include "sysemu.h"
  30 #include "sh7750_regs.h"
  31 #include "sh7750_regnames.h"
  32 #include "sh_intc.h"
  33
  34 #define NB_DEVICES 4
  35
  36 typedef struct SH7750State {
  37     /* CPU */
  38     CPUSH4State *cpu;
  39     /* Peripheral frequency in Hz */
  40     uint32_t periph_freq;
  41     /* SDRAM controller */
  42     uint16_t rfcr;
  43     /* IO ports */
  44     uint16_t gpioic;
  45     uint32_t pctra;
  46     uint32_t pctrb;
  47     uint16_t portdira;          /* Cached */
  48     uint16_t portpullupa;       /* Cached */
  49     uint16_t portdirb;          /* Cached */
  50     uint16_t portpullupb;       /* Cached */
  51     uint16_t pdtra;
  52     uint16_t pdtrb;
  53     uint16_t periph_pdtra;      /* Imposed by the peripherals */
  54     uint16_t periph_portdira;   /* Direction seen from the peripherals */
  55     uint16_t periph_pdtrb;      /* Imposed by the peripherals */
  56     uint16_t periph_portdirb;   /* Direction seen from the peripherals */
  57     sh7750_io_device *devices[NB_DEVICES];      /* External peripherals */
  58
  59     uint16_t icr;
  60     /* Cache */
  61     uint32_t ccr;
  62
  63     struct intc_desc intc;
  64 } SH7750State;
  65
  66
  67 /**********************************************************************
  68  I/O ports
  69 **********************************************************************/
  70
  71 int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
  72 {
  73     int i;
  74
  75     for (i = 0; i < NB_DEVICES; i++) {
  76         if (s->devices[i] == NULL) {
  77             s->devices[i] = device;
  78             return 0;
  79         }
  80     }
  81     return -1;
  82 }
  83
  84 static uint16_t portdir(uint32_t v)
  85 {
  86 #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
  87     return
  88         EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
  89         EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
  90         EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
  91         EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
  92         EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
  93         EVENPORTMASK(0);
  94 }
  95
  96 static uint16_t portpullup(uint32_t v)
  97 {
  98 #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
  99     return
 100         ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
 101         ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
 102         ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
 103         ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
 104         ODDPORTMASK(1) | ODDPORTMASK(0);
 105 }
 106
 107 static uint16_t porta_lines(SH7750State * s)
 108 {
 109     return (s->portdira & s->pdtra) |   /* CPU */
 110         (s->periph_portdira & s->periph_pdtra) |        /* Peripherals */
 111         (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
 112 }
 113
 114 static uint16_t portb_lines(SH7750State * s)
 115 {
 116     return (s->portdirb & s->pdtrb) |   /* CPU */
 117         (s->periph_portdirb & s->periph_pdtrb) |        /* Peripherals */
 118         (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
 119 }
 120
 121 static void gen_port_interrupts(SH7750State * s)
 122 {
 123     /* XXXXX interrupts not generated */
 124 }
 125
 126 static void porta_changed(SH7750State * s, uint16_t prev)
 127 {
 128     uint16_t currenta, changes;
 129     int i, r = 0;
 130
 131 #if 0
 132     fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
 133             prev, porta_lines(s));
 134     fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
 135 #endif
 136     currenta = porta_lines(s);
 137     if (currenta == prev)
 138         return;
 139     changes = currenta ^ prev;
 140
 141     for (i = 0; i < NB_DEVICES; i++) {
 142         if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
 143             r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
 144                                                &s->periph_pdtra,
 145                                                &s->periph_portdira,
 146                                                &s->periph_pdtrb,
 147                                                &s->periph_portdirb);
 148         }
 149     }
 150
 151     if (r)
 152         gen_port_interrupts(s);
 153 }
 154
 155 static void portb_changed(SH7750State * s, uint16_t prev)
 156 {
 157     uint16_t currentb, changes;
 158     int i, r = 0;
 159
 160     currentb = portb_lines(s);
 161     if (currentb == prev)
 162         return;
 163     changes = currentb ^ prev;
 164
 165     for (i = 0; i < NB_DEVICES; i++) {
 166         if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
 167             r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
 168                                                &s->periph_pdtra,
 169                                                &s->periph_portdira,
 170                                                &s->periph_pdtrb,
 171                                                &s->periph_portdirb);
 172         }
 173     }
 174
 175     if (r)
 176         gen_port_interrupts(s);
 177 }
 178
 179 /**********************************************************************
 180  Memory
 181 **********************************************************************/
 182
 183 static void error_access(const char *kind, target_phys_addr_t addr)
 184 {
 185     fprintf(stderr, "%s to %s (0x%08x) not supported\n",
 186             kind, regname(addr), addr);
 187 }
 188
 189 static void ignore_access(const char *kind, target_phys_addr_t addr)
 190 {
 191     fprintf(stderr, "%s to %s (0x%08x) ignored\n",
 192             kind, regname(addr), addr);
 193 }
 194
 195 static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
 196 {
 197     switch (addr) {
 198     default:
 199         error_access("byte read", addr);
 200         assert(0);
 201     }
 202 }
 203
 204 static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
 205 {
 206     SH7750State *s = opaque;
 207
 208     switch (addr) {
 209     case SH7750_FRQCR_A7:
 210         return 0;
 211     case SH7750_RFCR_A7:
 212         fprintf(stderr,
 213                 "Read access to refresh count register, incrementing\n");
 214         return s->rfcr++;
 215     case SH7750_PDTRA_A7:
 216         return porta_lines(s);
 217     case SH7750_PDTRB_A7:
 218         return portb_lines(s);
 219     case 0x1fd00000:
 220         return s->icr;
 221     default:
 222         error_access("word read", addr);
 223         assert(0);
 224     }
 225 }
 226
 227 static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
 228 {
 229     SH7750State *s = opaque;
 230
 231     switch (addr) {
 232     case SH7750_MMUCR_A7:
 233         return s->cpu->mmucr;
 234     case SH7750_PTEH_A7:
 235         return s->cpu->pteh;
 236     case SH7750_PTEL_A7:
 237         return s->cpu->ptel;
 238     case SH7750_TTB_A7:
 239         return s->cpu->ttb;
 240     case SH7750_TEA_A7:
 241         return s->cpu->tea;
 242     case SH7750_TRA_A7:
 243         return s->cpu->tra;
 244     case SH7750_EXPEVT_A7:
 245         return s->cpu->expevt;
 246     case SH7750_INTEVT_A7:
 247         return s->cpu->intevt;
 248     case SH7750_CCR_A7:
 249         return s->ccr;
 250     case 0x1f000030:            /* Processor version PVR */
 251         return 0x00050000;      /* SH7750R */
 252     case 0x1f000040:            /* Processor version CVR */
 253         return 0x00110000;      /* Minimum caches */
 254     case 0x1f000044:            /* Processor version PRR */
 255         return 0x00000100;      /* SH7750R */
 256     default:
 257         error_access("long read", addr);
 258         assert(0);
 259     }
 260 }
 261
 262 static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
 263                               uint32_t mem_value)
 264 {
 265     switch (addr) {
 266         /* PRECHARGE ? XXXXX */
 267     case SH7750_PRECHARGE0_A7:
 268     case SH7750_PRECHARGE1_A7:
 269         ignore_access("byte write", addr);
 270         return;
 271     default:
 272         error_access("byte write", addr);
 273         assert(0);
 274     }
 275 }
 276
 277 static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
 278                               uint32_t mem_value)
 279 {
 280     SH7750State *s = opaque;
 281     uint16_t temp;
 282
 283     switch (addr) {
 284         /* SDRAM controller */
 285     case SH7750_BCR2_A7:
 286     case SH7750_BCR3_A7:
 287     case SH7750_RTCOR_A7:
 288     case SH7750_RTCNT_A7:
 289     case SH7750_RTCSR_A7:
 290         ignore_access("word write", addr);
 291         return;
 292         /* IO ports */
 293     case SH7750_PDTRA_A7:
 294         temp = porta_lines(s);
 295         s->pdtra = mem_value;
 296         porta_changed(s, temp);
 297         return;
 298     case SH7750_PDTRB_A7:
 299         temp = portb_lines(s);
 300         s->pdtrb = mem_value;
 301         portb_changed(s, temp);
 302         return;
 303     case SH7750_RFCR_A7:
 304         fprintf(stderr, "Write access to refresh count register\n");
 305         s->rfcr = mem_value;
 306         return;
 307     case SH7750_GPIOIC_A7:
 308         s->gpioic = mem_value;
 309         if (mem_value != 0) {
 310             fprintf(stderr, "I/O interrupts not implemented\n");
 311             assert(0);
 312         }
 313         return;
 314     case 0x1fd00000:
 315         s->icr = mem_value;
 316         return;
 317     default:
 318         error_access("word write", addr);
 319         assert(0);
 320     }
 321 }
 322
 323 static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
 324                               uint32_t mem_value)
 325 {
 326     SH7750State *s = opaque;
 327     uint16_t temp;
 328
 329     switch (addr) {
 330         /* SDRAM controller */
 331     case SH7750_BCR1_A7:
 332     case SH7750_BCR4_A7:
 333     case SH7750_WCR1_A7:
 334     case SH7750_WCR2_A7:
 335     case SH7750_WCR3_A7:
 336     case SH7750_MCR_A7:
 337         ignore_access("long write", addr);
 338         return;
 339         /* IO ports */
 340     case SH7750_PCTRA_A7:
 341         temp = porta_lines(s);
 342         s->pctra = mem_value;
 343         s->portdira = portdir(mem_value);
 344         s->portpullupa = portpullup(mem_value);
 345         porta_changed(s, temp);
 346         return;
 347     case SH7750_PCTRB_A7:
 348         temp = portb_lines(s);
 349         s->pctrb = mem_value;
 350         s->portdirb = portdir(mem_value);
 351         s->portpullupb = portpullup(mem_value);
 352         portb_changed(s, temp);
 353         return;
 354     case SH7750_MMUCR_A7:
 355         s->cpu->mmucr = mem_value;
 356         return;
 357     case SH7750_PTEH_A7:
 358         s->cpu->pteh = mem_value;
 359         return;
 360     case SH7750_PTEL_A7:
 361         s->cpu->ptel = mem_value;
 362         return;
 363     case SH7750_TTB_A7:
 364         s->cpu->ttb = mem_value;
 365         return;
 366     case SH7750_TEA_A7:
 367         s->cpu->tea = mem_value;
 368         return;
 369     case SH7750_TRA_A7:
 370         s->cpu->tra = mem_value & 0x000007ff;
 371         return;
 372     case SH7750_EXPEVT_A7:
 373         s->cpu->expevt = mem_value & 0x000007ff;
 374         return;
 375     case SH7750_INTEVT_A7:
 376         s->cpu->intevt = mem_value & 0x000007ff;
 377         return;
 378     case SH7750_CCR_A7:
 379         s->ccr = mem_value;
 380         return;
 381     default:
 382         error_access("long write", addr);
 383         assert(0);
 384     }
 385 }
 386
 387 static CPUReadMemoryFunc *sh7750_mem_read[] = {
 388     sh7750_mem_readb,
 389     sh7750_mem_readw,
 390     sh7750_mem_readl
 391 };
 392
 393 static CPUWriteMemoryFunc *sh7750_mem_write[] = {
 394     sh7750_mem_writeb,
 395     sh7750_mem_writew,
 396     sh7750_mem_writel
 397 };
 398
 399 /* sh775x interrupt controller tables for sh_intc.c
 400  * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
 401  */
 402
 403 enum {
 404         UNUSED = 0,
 405
 406         /* interrupt sources */
 407         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
 408         HUDI, GPIOI,
 409         DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
 410         DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
 411         DMAC_DMAE,
 412         PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 413         PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
 414         TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
 415         RTC_ATI, RTC_PRI, RTC_CUI,
 416         SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
 417         SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
 418         WDT,
 419         REF_RCMI, REF_ROVI,
 420
 421         /* interrupt groups */
 422         DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
 423
 424         NR_SOURCES,
 425 };
 426
 427 static struct intc_vect vectors[] = {
 428         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
 429         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 430         INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
 431         INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
 432         INTC_VECT(RTC_CUI, 0x4c0),
 433         INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
 434         INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
 435         INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
 436         INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
 437         INTC_VECT(WDT, 0x560),
 438         INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
 439 };
 440
 441 static struct intc_group groups[] = {
 442         INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
 443         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 444         INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
 445         INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
 446         INTC_GROUP(REF, REF_RCMI, REF_ROVI),
 447 };
 448
 449 static struct intc_prio_reg prio_registers[] = {
 450         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 451         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
 452         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
 453         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 454         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
 455                                                  TMU4, TMU3,
 456                                                  PCIC1, PCIC0_PCISERR } },
 457 };
 458
 459 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
 460
 461 static struct intc_vect vectors_dma4[] = {
 462         INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
 463         INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
 464         INTC_VECT(DMAC_DMAE, 0x6c0),
 465 };
 466
 467 static struct intc_group groups_dma4[] = {
 468         INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
 469                    DMAC_DMTE3, DMAC_DMAE),
 470 };
 471
 472 /* SH7750R and SH7751R both have 8-channel DMA controllers */
 473
 474 static struct intc_vect vectors_dma8[] = {
 475         INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
 476         INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
 477         INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
 478         INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
 479         INTC_VECT(DMAC_DMAE, 0x6c0),
 480 };
 481
 482 static struct intc_group groups_dma8[] = {
 483         INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
 484                    DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
 485                    DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
 486 };
 487
 488 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 489
 490 static struct intc_vect vectors_tmu34[] = {
 491         INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
 492 };
 493
 494 static struct intc_mask_reg mask_registers[] = {
 495         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
 496           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 497             0, 0, 0, 0, 0, 0, TMU4, TMU3,
 498             PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 499             PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
 500             PCIC1_PCIDMA3, PCIC0_PCISERR } },
 501 };
 502
 503 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
 504
 505 static struct intc_vect vectors_irlm[] = {
 506         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 507         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 508 };
 509
 510 /* SH7751 and SH7751R both have PCI */
 511
 512 static struct intc_vect vectors_pci[] = {
 513         INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
 514         INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
 515         INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
 516         INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
 517 };
 518
 519 static struct intc_group groups_pci[] = {
 520         INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 521                    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 522 };
 523
 524 #define SH_CPU_SH7750  (1 << 0)
 525 #define SH_CPU_SH7750S (1 << 1)
 526 #define SH_CPU_SH7750R (1 << 2)
 527 #define SH_CPU_SH7751  (1 << 3)
 528 #define SH_CPU_SH7751R (1 << 4)
 529 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
 530 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
 531
 532 SH7750State *sh7750_init(CPUSH4State * cpu)
 533 {
 534     SH7750State *s;
 535     int sh7750_io_memory;
 536     int cpu_model = SH_CPU_SH7751R; /* for now */
 537
 538     s = qemu_mallocz(sizeof(SH7750State));
 539     s->cpu = cpu;
 540     s->periph_freq = 60000000;  /* 60MHz */
 541     sh7750_io_memory = cpu_register_io_memory(0,
 542                                               sh7750_mem_read,
 543                                               sh7750_mem_write, s);
 544     cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
 545
 546     sh_intc_init(&s->intc, NR_SOURCES,
 547                  _INTC_ARRAY(mask_registers),
 548                  _INTC_ARRAY(prio_registers));
 549
 550     sh_intc_register_sources(&s->intc,
 551                              _INTC_ARRAY(vectors),
 552                              _INTC_ARRAY(groups));
 553
 554     sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]);
 555     sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
 556                    s->periph_freq, serial_hds[1]);
 557
 558     tmu012_init(0x1fd80000,
 559                 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
 560                 s->periph_freq);
 561
 562
 563     if (cpu_model & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
 564         sh_intc_register_sources(&s->intc,
 565                                  _INTC_ARRAY(vectors_dma4),
 566                                  _INTC_ARRAY(groups_dma4));
 567     }
 568
 569     if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
 570         sh_intc_register_sources(&s->intc,
 571                                  _INTC_ARRAY(vectors_dma8),
 572                                  _INTC_ARRAY(groups_dma8));
 573     }
 574
 575     if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
 576         sh_intc_register_sources(&s->intc,
 577                                  _INTC_ARRAY(vectors_tmu34),
 578                                  NULL, 0);
 579         tmu012_init(0x1e100000, 0, s->periph_freq);
 580     }
 581
 582     if (cpu_model & (SH_CPU_SH7751_ALL)) {
 583         sh_intc_register_sources(&s->intc,
 584                                  _INTC_ARRAY(vectors_pci),
 585                                  _INTC_ARRAY(groups_pci));
 586     }
 587
 588     if (cpu_model & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
 589         sh_intc_register_sources(&s->intc,
 590                                  _INTC_ARRAY(vectors_irlm),
 591                                  NULL, 0);
 592     }
 593
 594     return s;
 595 }