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Break up vl.h.
[qemu/mini2440.git] / hw / ppc405_uc.c
blob0a2f087d85bf390d96fb6b40486a7456901cd871
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "pc.h"
28 #include "qemu-timer.h"
29 #include "sysemu.h"
30
31 extern int loglevel;
32 extern FILE *logfile;
33
34 #define DEBUG_OPBA
35 #define DEBUG_SDRAM
36 #define DEBUG_GPIO
37 #define DEBUG_SERIAL
38 #define DEBUG_OCM
39 //#define DEBUG_I2C
40 #define DEBUG_GPT
41 #define DEBUG_MAL
42 #define DEBUG_CLOCKS
43 //#define DEBUG_UNASSIGNED
44
45 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
46 uint32_t flags)
47 {
48 ram_addr_t bdloc;
49 int i, n;
50
51 /* We put the bd structure at the top of memory */
52 if (bd->bi_memsize >= 0x01000000UL)
53 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
54 else
55 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
56 stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
57 stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
58 stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
59 stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
60 stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
61 stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
62 stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
63 stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
64 stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
65 for (i = 0; i < 6; i++)
66 stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
67 stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
68 stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
69 stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
70 stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
71 for (i = 0; i < 4; i++)
72 stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
73 for (i = 0; i < 32; i++)
74 stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
75 stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
76 stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
77 for (i = 0; i < 6; i++)
78 stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
79 n = 0x6A;
80 if (flags & 0x00000001) {
81 for (i = 0; i < 6; i++)
82 stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);
83 }
84 stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq);
85 n += 4;
86 for (i = 0; i < 2; i++) {
87 stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]);
88 n += 4;
89 }
90
91 return bdloc;
92 }
93
94 /*****************************************************************************/
95 /* Shared peripherals */
96
97 /*****************************************************************************/
98 /* Peripheral local bus arbitrer */
99 enum {
100 PLB0_BESR = 0x084,
101 PLB0_BEAR = 0x086,
102 PLB0_ACR = 0x087,
103 };
104
105 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
106 struct ppc4xx_plb_t {
107 uint32_t acr;
108 uint32_t bear;
109 uint32_t besr;
110 };
111
112 static target_ulong dcr_read_plb (void *opaque, int dcrn)
113 {
114 ppc4xx_plb_t *plb;
115 target_ulong ret;
116
117 plb = opaque;
118 switch (dcrn) {
119 case PLB0_ACR:
120 ret = plb->acr;
121 break;
122 case PLB0_BEAR:
123 ret = plb->bear;
124 break;
125 case PLB0_BESR:
126 ret = plb->besr;
127 break;
128 default:
129 /* Avoid gcc warning */
130 ret = 0;
131 break;
132 }
133
134 return ret;
135 }
136
137 static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
138 {
139 ppc4xx_plb_t *plb;
140
141 plb = opaque;
142 switch (dcrn) {
143 case PLB0_ACR:
144 /* We don't care about the actual parameters written as
145 * we don't manage any priorities on the bus
146 */
147 plb->acr = val & 0xF8000000;
148 break;
149 case PLB0_BEAR:
150 /* Read only */
151 break;
152 case PLB0_BESR:
153 /* Write-clear */
154 plb->besr &= ~val;
155 break;
156 }
157 }
158
159 static void ppc4xx_plb_reset (void *opaque)
160 {
161 ppc4xx_plb_t *plb;
162
163 plb = opaque;
164 plb->acr = 0x00000000;
165 plb->bear = 0x00000000;
166 plb->besr = 0x00000000;
167 }
168
169 void ppc4xx_plb_init (CPUState *env)
170 {
171 ppc4xx_plb_t *plb;
172
173 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
174 if (plb != NULL) {
175 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
176 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
177 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
178 ppc4xx_plb_reset(plb);
179 qemu_register_reset(ppc4xx_plb_reset, plb);
180 }
181 }
182
183 /*****************************************************************************/
184 /* PLB to OPB bridge */
185 enum {
186 POB0_BESR0 = 0x0A0,
187 POB0_BESR1 = 0x0A2,
188 POB0_BEAR = 0x0A4,
189 };
190
191 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
192 struct ppc4xx_pob_t {
193 uint32_t bear;
194 uint32_t besr[2];
195 };
196
197 static target_ulong dcr_read_pob (void *opaque, int dcrn)
198 {
199 ppc4xx_pob_t *pob;
200 target_ulong ret;
201
202 pob = opaque;
203 switch (dcrn) {
204 case POB0_BEAR:
205 ret = pob->bear;
206 break;
207 case POB0_BESR0:
208 case POB0_BESR1:
209 ret = pob->besr[dcrn - POB0_BESR0];
210 break;
211 default:
212 /* Avoid gcc warning */
213 ret = 0;
214 break;
215 }
216
217 return ret;
218 }
219
220 static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
221 {
222 ppc4xx_pob_t *pob;
223
224 pob = opaque;
225 switch (dcrn) {
226 case POB0_BEAR:
227 /* Read only */
228 break;
229 case POB0_BESR0:
230 case POB0_BESR1:
231 /* Write-clear */
232 pob->besr[dcrn - POB0_BESR0] &= ~val;
233 break;
234 }
235 }
236
237 static void ppc4xx_pob_reset (void *opaque)
238 {
239 ppc4xx_pob_t *pob;
240
241 pob = opaque;
242 /* No error */
243 pob->bear = 0x00000000;
244 pob->besr[0] = 0x0000000;
245 pob->besr[1] = 0x0000000;
246 }
247
248 void ppc4xx_pob_init (CPUState *env)
249 {
250 ppc4xx_pob_t *pob;
251
252 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
253 if (pob != NULL) {
254 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
255 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
256 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
257 qemu_register_reset(ppc4xx_pob_reset, pob);
258 ppc4xx_pob_reset(env);
259 }
260 }
261
262 /*****************************************************************************/
263 /* OPB arbitrer */
264 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
265 struct ppc4xx_opba_t {
266 target_phys_addr_t base;
267 uint8_t cr;
268 uint8_t pr;
269 };
270
271 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
272 {
273 ppc4xx_opba_t *opba;
274 uint32_t ret;
275
276 #ifdef DEBUG_OPBA
277 printf("%s: addr " PADDRX "\n", __func__, addr);
278 #endif
279 opba = opaque;
280 switch (addr - opba->base) {
281 case 0x00:
282 ret = opba->cr;
283 break;
284 case 0x01:
285 ret = opba->pr;
286 break;
287 default:
288 ret = 0x00;
289 break;
290 }
291
292 return ret;
293 }
294
295 static void opba_writeb (void *opaque,
296 target_phys_addr_t addr, uint32_t value)
297 {
298 ppc4xx_opba_t *opba;
299
300 #ifdef DEBUG_OPBA
301 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
302 #endif
303 opba = opaque;
304 switch (addr - opba->base) {
305 case 0x00:
306 opba->cr = value & 0xF8;
307 break;
308 case 0x01:
309 opba->pr = value & 0xFF;
310 break;
311 default:
312 break;
313 }
314 }
315
316 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
317 {
318 uint32_t ret;
319
320 #ifdef DEBUG_OPBA
321 printf("%s: addr " PADDRX "\n", __func__, addr);
322 #endif
323 ret = opba_readb(opaque, addr) << 8;
324 ret |= opba_readb(opaque, addr + 1);
325
326 return ret;
327 }
328
329 static void opba_writew (void *opaque,
330 target_phys_addr_t addr, uint32_t value)
331 {
332 #ifdef DEBUG_OPBA
333 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
334 #endif
335 opba_writeb(opaque, addr, value >> 8);
336 opba_writeb(opaque, addr + 1, value);
337 }
338
339 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
340 {
341 uint32_t ret;
342
343 #ifdef DEBUG_OPBA
344 printf("%s: addr " PADDRX "\n", __func__, addr);
345 #endif
346 ret = opba_readb(opaque, addr) << 24;
347 ret |= opba_readb(opaque, addr + 1) << 16;
348
349 return ret;
350 }
351
352 static void opba_writel (void *opaque,
353 target_phys_addr_t addr, uint32_t value)
354 {
355 #ifdef DEBUG_OPBA
356 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
357 #endif
358 opba_writeb(opaque, addr, value >> 24);
359 opba_writeb(opaque, addr + 1, value >> 16);
360 }
361
362 static CPUReadMemoryFunc *opba_read[] = {
363 &opba_readb,
364 &opba_readw,
365 &opba_readl,
366 };
367
368 static CPUWriteMemoryFunc *opba_write[] = {
369 &opba_writeb,
370 &opba_writew,
371 &opba_writel,
372 };
373
374 static void ppc4xx_opba_reset (void *opaque)
375 {
376 ppc4xx_opba_t *opba;
377
378 opba = opaque;
379 opba->cr = 0x00; /* No dynamic priorities - park disabled */
380 opba->pr = 0x11;
381 }
382
383 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
384 target_phys_addr_t offset)
385 {
386 ppc4xx_opba_t *opba;
387
388 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
389 if (opba != NULL) {
390 opba->base = offset;
391 #ifdef DEBUG_OPBA
392 printf("%s: offset=" PADDRX "\n", __func__, offset);
393 #endif
394 ppc4xx_mmio_register(env, mmio, offset, 0x002,
395 opba_read, opba_write, opba);
396 qemu_register_reset(ppc4xx_opba_reset, opba);
397 ppc4xx_opba_reset(opba);
398 }
399 }
400
401 /*****************************************************************************/
402 /* Code decompression controller */
403 /* XXX: TODO */
404
405 /*****************************************************************************/
406 /* SDRAM controller */
407 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
408 struct ppc4xx_sdram_t {
409 uint32_t addr;
410 int nbanks;
411 target_phys_addr_t ram_bases[4];
412 target_phys_addr_t ram_sizes[4];
413 uint32_t besr0;
414 uint32_t besr1;
415 uint32_t bear;
416 uint32_t cfg;
417 uint32_t status;
418 uint32_t rtr;
419 uint32_t pmit;
420 uint32_t bcr[4];
421 uint32_t tr;
422 uint32_t ecccfg;
423 uint32_t eccesr;
424 qemu_irq irq;
425 };
426
427 enum {
428 SDRAM0_CFGADDR = 0x010,
429 SDRAM0_CFGDATA = 0x011,
430 };
431
432 static uint32_t sdram_bcr (target_phys_addr_t ram_base,
433 target_phys_addr_t ram_size)
434 {
435 uint32_t bcr;
436
437 switch (ram_size) {
438 case (4 * 1024 * 1024):
439 bcr = 0x00000000;
440 break;
441 case (8 * 1024 * 1024):
442 bcr = 0x00020000;
443 break;
444 case (16 * 1024 * 1024):
445 bcr = 0x00040000;
446 break;
447 case (32 * 1024 * 1024):
448 bcr = 0x00060000;
449 break;
450 case (64 * 1024 * 1024):
451 bcr = 0x00080000;
452 break;
453 case (128 * 1024 * 1024):
454 bcr = 0x000A0000;
455 break;
456 case (256 * 1024 * 1024):
457 bcr = 0x000C0000;
458 break;
459 default:
460 printf("%s: invalid RAM size " TARGET_FMT_plx "\n",
461 __func__, ram_size);
462 return 0x00000000;
463 }
464 bcr |= ram_base & 0xFF800000;
465 bcr |= 1;
466
467 return bcr;
468 }
469
470 static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
471 {
472 return bcr & 0xFF800000;
473 }
474
475 static target_ulong sdram_size (uint32_t bcr)
476 {
477 target_ulong size;
478 int sh;
479
480 sh = (bcr >> 17) & 0x7;
481 if (sh == 7)
482 size = -1;
483 else
484 size = (4 * 1024 * 1024) << sh;
485
486 return size;
487 }
488
489 static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
490 {
491 if (*bcrp & 0x00000001) {
492 /* Unmap RAM */
493 #ifdef DEBUG_SDRAM
494 printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
495 __func__, sdram_base(*bcrp), sdram_size(*bcrp));
496 #endif
497 cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
498 IO_MEM_UNASSIGNED);
499 }
500 *bcrp = bcr & 0xFFDEE001;
501 if (enabled && (bcr & 0x00000001)) {
502 #ifdef DEBUG_SDRAM
503 printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
504 __func__, sdram_base(bcr), sdram_size(bcr));
505 #endif
506 cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
507 sdram_base(bcr) | IO_MEM_RAM);
508 }
509 }
510
511 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
512 {
513 int i;
514
515 for (i = 0; i < sdram->nbanks; i++) {
516 if (sdram->ram_sizes[i] != 0) {
517 sdram_set_bcr(&sdram->bcr[i],
518 sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
519 1);
520 } else {
521 sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
522 }
523 }
524 }
525
526 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
527 {
528 int i;
529
530 for (i = 0; i < sdram->nbanks; i++) {
531 #ifdef DEBUG_SDRAM
532 printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
533 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
534 #endif
535 cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
536 sdram_size(sdram->bcr[i]),
537 IO_MEM_UNASSIGNED);
538 }
539 }
540
541 static target_ulong dcr_read_sdram (void *opaque, int dcrn)
542 {
543 ppc4xx_sdram_t *sdram;
544 target_ulong ret;
545
546 sdram = opaque;
547 switch (dcrn) {
548 case SDRAM0_CFGADDR:
549 ret = sdram->addr;
550 break;
551 case SDRAM0_CFGDATA:
552 switch (sdram->addr) {
553 case 0x00: /* SDRAM_BESR0 */
554 ret = sdram->besr0;
555 break;
556 case 0x08: /* SDRAM_BESR1 */
557 ret = sdram->besr1;
558 break;
559 case 0x10: /* SDRAM_BEAR */
560 ret = sdram->bear;
561 break;
562 case 0x20: /* SDRAM_CFG */
563 ret = sdram->cfg;
564 break;
565 case 0x24: /* SDRAM_STATUS */
566 ret = sdram->status;
567 break;
568 case 0x30: /* SDRAM_RTR */
569 ret = sdram->rtr;
570 break;
571 case 0x34: /* SDRAM_PMIT */
572 ret = sdram->pmit;
573 break;
574 case 0x40: /* SDRAM_B0CR */
575 ret = sdram->bcr[0];
576 break;
577 case 0x44: /* SDRAM_B1CR */
578 ret = sdram->bcr[1];
579 break;
580 case 0x48: /* SDRAM_B2CR */
581 ret = sdram->bcr[2];
582 break;
583 case 0x4C: /* SDRAM_B3CR */
584 ret = sdram->bcr[3];
585 break;
586 case 0x80: /* SDRAM_TR */
587 ret = -1; /* ? */
588 break;
589 case 0x94: /* SDRAM_ECCCFG */
590 ret = sdram->ecccfg;
591 break;
592 case 0x98: /* SDRAM_ECCESR */
593 ret = sdram->eccesr;
594 break;
595 default: /* Error */
596 ret = -1;
597 break;
598 }
599 break;
600 default:
601 /* Avoid gcc warning */
602 ret = 0x00000000;
603 break;
604 }
605
606 return ret;
607 }
608
609 static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
610 {
611 ppc4xx_sdram_t *sdram;
612
613 sdram = opaque;
614 switch (dcrn) {
615 case SDRAM0_CFGADDR:
616 sdram->addr = val;
617 break;
618 case SDRAM0_CFGDATA:
619 switch (sdram->addr) {
620 case 0x00: /* SDRAM_BESR0 */
621 sdram->besr0 &= ~val;
622 break;
623 case 0x08: /* SDRAM_BESR1 */
624 sdram->besr1 &= ~val;
625 break;
626 case 0x10: /* SDRAM_BEAR */
627 sdram->bear = val;
628 break;
629 case 0x20: /* SDRAM_CFG */
630 val &= 0xFFE00000;
631 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
632 #ifdef DEBUG_SDRAM
633 printf("%s: enable SDRAM controller\n", __func__);
634 #endif
635 /* validate all RAM mappings */
636 sdram_map_bcr(sdram);
637 sdram->status &= ~0x80000000;
638 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
639 #ifdef DEBUG_SDRAM
640 printf("%s: disable SDRAM controller\n", __func__);
641 #endif
642 /* invalidate all RAM mappings */
643 sdram_unmap_bcr(sdram);
644 sdram->status |= 0x80000000;
645 }
646 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
647 sdram->status |= 0x40000000;
648 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
649 sdram->status &= ~0x40000000;
650 sdram->cfg = val;
651 break;
652 case 0x24: /* SDRAM_STATUS */
653 /* Read-only register */
654 break;
655 case 0x30: /* SDRAM_RTR */
656 sdram->rtr = val & 0x3FF80000;
657 break;
658 case 0x34: /* SDRAM_PMIT */
659 sdram->pmit = (val & 0xF8000000) | 0x07C00000;
660 break;
661 case 0x40: /* SDRAM_B0CR */
662 sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
663 break;
664 case 0x44: /* SDRAM_B1CR */
665 sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
666 break;
667 case 0x48: /* SDRAM_B2CR */
668 sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
669 break;
670 case 0x4C: /* SDRAM_B3CR */
671 sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
672 break;
673 case 0x80: /* SDRAM_TR */
674 sdram->tr = val & 0x018FC01F;
675 break;
676 case 0x94: /* SDRAM_ECCCFG */
677 sdram->ecccfg = val & 0x00F00000;
678 break;
679 case 0x98: /* SDRAM_ECCESR */
680 val &= 0xFFF0F000;
681 if (sdram->eccesr == 0 && val != 0)
682 qemu_irq_raise(sdram->irq);
683 else if (sdram->eccesr != 0 && val == 0)
684 qemu_irq_lower(sdram->irq);
685 sdram->eccesr = val;
686 break;
687 default: /* Error */
688 break;
689 }
690 break;
691 }
692 }
693
694 static void sdram_reset (void *opaque)
695 {
696 ppc4xx_sdram_t *sdram;
697
698 sdram = opaque;
699 sdram->addr = 0x00000000;
700 sdram->bear = 0x00000000;
701 sdram->besr0 = 0x00000000; /* No error */
702 sdram->besr1 = 0x00000000; /* No error */
703 sdram->cfg = 0x00000000;
704 sdram->ecccfg = 0x00000000; /* No ECC */
705 sdram->eccesr = 0x00000000; /* No error */
706 sdram->pmit = 0x07C00000;
707 sdram->rtr = 0x05F00000;
708 sdram->tr = 0x00854009;
709 /* We pre-initialize RAM banks */
710 sdram->status = 0x00000000;
711 sdram->cfg = 0x00800000;
712 sdram_unmap_bcr(sdram);
713 }
714
715 void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
716 target_phys_addr_t *ram_bases,
717 target_phys_addr_t *ram_sizes,
718 int do_init)
719 {
720 ppc4xx_sdram_t *sdram;
721
722 sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
723 if (sdram != NULL) {
724 sdram->irq = irq;
725 sdram->nbanks = nbanks;
726 memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
727 memcpy(sdram->ram_bases, ram_bases,
728 nbanks * sizeof(target_phys_addr_t));
729 memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
730 memcpy(sdram->ram_sizes, ram_sizes,
731 nbanks * sizeof(target_phys_addr_t));
732 sdram_reset(sdram);
733 qemu_register_reset(&sdram_reset, sdram);
734 ppc_dcr_register(env, SDRAM0_CFGADDR,
735 sdram, &dcr_read_sdram, &dcr_write_sdram);
736 ppc_dcr_register(env, SDRAM0_CFGDATA,
737 sdram, &dcr_read_sdram, &dcr_write_sdram);
738 if (do_init)
739 sdram_map_bcr(sdram);
740 }
741 }
742
743 /*****************************************************************************/
744 /* Peripheral controller */
745 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
746 struct ppc4xx_ebc_t {
747 uint32_t addr;
748 uint32_t bcr[8];
749 uint32_t bap[8];
750 uint32_t bear;
751 uint32_t besr0;
752 uint32_t besr1;
753 uint32_t cfg;
754 };
755
756 enum {
757 EBC0_CFGADDR = 0x012,
758 EBC0_CFGDATA = 0x013,
759 };
760
761 static target_ulong dcr_read_ebc (void *opaque, int dcrn)
762 {
763 ppc4xx_ebc_t *ebc;
764 target_ulong ret;
765
766 ebc = opaque;
767 switch (dcrn) {
768 case EBC0_CFGADDR:
769 ret = ebc->addr;
770 break;
771 case EBC0_CFGDATA:
772 switch (ebc->addr) {
773 case 0x00: /* B0CR */
774 ret = ebc->bcr[0];
775 break;
776 case 0x01: /* B1CR */
777 ret = ebc->bcr[1];
778 break;
779 case 0x02: /* B2CR */
780 ret = ebc->bcr[2];
781 break;
782 case 0x03: /* B3CR */
783 ret = ebc->bcr[3];
784 break;
785 case 0x04: /* B4CR */
786 ret = ebc->bcr[4];
787 break;
788 case 0x05: /* B5CR */
789 ret = ebc->bcr[5];
790 break;
791 case 0x06: /* B6CR */
792 ret = ebc->bcr[6];
793 break;
794 case 0x07: /* B7CR */
795 ret = ebc->bcr[7];
796 break;
797 case 0x10: /* B0AP */
798 ret = ebc->bap[0];
799 break;
800 case 0x11: /* B1AP */
801 ret = ebc->bap[1];
802 break;
803 case 0x12: /* B2AP */
804 ret = ebc->bap[2];
805 break;
806 case 0x13: /* B3AP */
807 ret = ebc->bap[3];
808 break;
809 case 0x14: /* B4AP */
810 ret = ebc->bap[4];
811 break;
812 case 0x15: /* B5AP */
813 ret = ebc->bap[5];
814 break;
815 case 0x16: /* B6AP */
816 ret = ebc->bap[6];
817 break;
818 case 0x17: /* B7AP */
819 ret = ebc->bap[7];
820 break;
821 case 0x20: /* BEAR */
822 ret = ebc->bear;
823 break;
824 case 0x21: /* BESR0 */
825 ret = ebc->besr0;
826 break;
827 case 0x22: /* BESR1 */
828 ret = ebc->besr1;
829 break;
830 case 0x23: /* CFG */
831 ret = ebc->cfg;
832 break;
833 default:
834 ret = 0x00000000;
835 break;
836 }
837 default:
838 ret = 0x00000000;
839 break;
840 }
841
842 return ret;
843 }
844
845 static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
846 {
847 ppc4xx_ebc_t *ebc;
848
849 ebc = opaque;
850 switch (dcrn) {
851 case EBC0_CFGADDR:
852 ebc->addr = val;
853 break;
854 case EBC0_CFGDATA:
855 switch (ebc->addr) {
856 case 0x00: /* B0CR */
857 break;
858 case 0x01: /* B1CR */
859 break;
860 case 0x02: /* B2CR */
861 break;
862 case 0x03: /* B3CR */
863 break;
864 case 0x04: /* B4CR */
865 break;
866 case 0x05: /* B5CR */
867 break;
868 case 0x06: /* B6CR */
869 break;
870 case 0x07: /* B7CR */
871 break;
872 case 0x10: /* B0AP */
873 break;
874 case 0x11: /* B1AP */
875 break;
876 case 0x12: /* B2AP */
877 break;
878 case 0x13: /* B3AP */
879 break;
880 case 0x14: /* B4AP */
881 break;
882 case 0x15: /* B5AP */
883 break;
884 case 0x16: /* B6AP */
885 break;
886 case 0x17: /* B7AP */
887 break;
888 case 0x20: /* BEAR */
889 break;
890 case 0x21: /* BESR0 */
891 break;
892 case 0x22: /* BESR1 */
893 break;
894 case 0x23: /* CFG */
895 break;
896 default:
897 break;
898 }
899 break;
900 default:
901 break;
902 }
903 }
904
905 static void ebc_reset (void *opaque)
906 {
907 ppc4xx_ebc_t *ebc;
908 int i;
909
910 ebc = opaque;
911 ebc->addr = 0x00000000;
912 ebc->bap[0] = 0x7F8FFE80;
913 ebc->bcr[0] = 0xFFE28000;
914 for (i = 0; i < 8; i++) {
915 ebc->bap[i] = 0x00000000;
916 ebc->bcr[i] = 0x00000000;
917 }
918 ebc->besr0 = 0x00000000;
919 ebc->besr1 = 0x00000000;
920 ebc->cfg = 0x80400000;
921 }
922
923 void ppc405_ebc_init (CPUState *env)
924 {
925 ppc4xx_ebc_t *ebc;
926
927 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
928 if (ebc != NULL) {
929 ebc_reset(ebc);
930 qemu_register_reset(&ebc_reset, ebc);
931 ppc_dcr_register(env, EBC0_CFGADDR,
932 ebc, &dcr_read_ebc, &dcr_write_ebc);
933 ppc_dcr_register(env, EBC0_CFGDATA,
934 ebc, &dcr_read_ebc, &dcr_write_ebc);
935 }
936 }
937
938 /*****************************************************************************/
939 /* DMA controller */
940 enum {
941 DMA0_CR0 = 0x100,
942 DMA0_CT0 = 0x101,
943 DMA0_DA0 = 0x102,
944 DMA0_SA0 = 0x103,
945 DMA0_SG0 = 0x104,
946 DMA0_CR1 = 0x108,
947 DMA0_CT1 = 0x109,
948 DMA0_DA1 = 0x10A,
949 DMA0_SA1 = 0x10B,
950 DMA0_SG1 = 0x10C,
951 DMA0_CR2 = 0x110,
952 DMA0_CT2 = 0x111,
953 DMA0_DA2 = 0x112,
954 DMA0_SA2 = 0x113,
955 DMA0_SG2 = 0x114,
956 DMA0_CR3 = 0x118,
957 DMA0_CT3 = 0x119,
958 DMA0_DA3 = 0x11A,
959 DMA0_SA3 = 0x11B,
960 DMA0_SG3 = 0x11C,
961 DMA0_SR = 0x120,
962 DMA0_SGC = 0x123,
963 DMA0_SLP = 0x125,
964 DMA0_POL = 0x126,
965 };
966
967 typedef struct ppc405_dma_t ppc405_dma_t;
968 struct ppc405_dma_t {
969 qemu_irq irqs[4];
970 uint32_t cr[4];
971 uint32_t ct[4];
972 uint32_t da[4];
973 uint32_t sa[4];
974 uint32_t sg[4];
975 uint32_t sr;
976 uint32_t sgc;
977 uint32_t slp;
978 uint32_t pol;
979 };
980
981 static target_ulong dcr_read_dma (void *opaque, int dcrn)
982 {
983 ppc405_dma_t *dma;
984
985 dma = opaque;
986
987 return 0;
988 }
989
990 static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
991 {
992 ppc405_dma_t *dma;
993
994 dma = opaque;
995 }
996
997 static void ppc405_dma_reset (void *opaque)
998 {
999 ppc405_dma_t *dma;
1000 int i;
1001
1002 dma = opaque;
1003 for (i = 0; i < 4; i++) {
1004 dma->cr[i] = 0x00000000;
1005 dma->ct[i] = 0x00000000;
1006 dma->da[i] = 0x00000000;
1007 dma->sa[i] = 0x00000000;
1008 dma->sg[i] = 0x00000000;
1009 }
1010 dma->sr = 0x00000000;
1011 dma->sgc = 0x00000000;
1012 dma->slp = 0x7C000000;
1013 dma->pol = 0x00000000;
1014 }
1015
1016 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
1017 {
1018 ppc405_dma_t *dma;
1019
1020 dma = qemu_mallocz(sizeof(ppc405_dma_t));
1021 if (dma != NULL) {
1022 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
1023 ppc405_dma_reset(dma);
1024 qemu_register_reset(&ppc405_dma_reset, dma);
1025 ppc_dcr_register(env, DMA0_CR0,
1026 dma, &dcr_read_dma, &dcr_write_dma);
1027 ppc_dcr_register(env, DMA0_CT0,
1028 dma, &dcr_read_dma, &dcr_write_dma);
1029 ppc_dcr_register(env, DMA0_DA0,
1030 dma, &dcr_read_dma, &dcr_write_dma);
1031 ppc_dcr_register(env, DMA0_SA0,
1032 dma, &dcr_read_dma, &dcr_write_dma);
1033 ppc_dcr_register(env, DMA0_SG0,
1034 dma, &dcr_read_dma, &dcr_write_dma);
1035 ppc_dcr_register(env, DMA0_CR1,
1036 dma, &dcr_read_dma, &dcr_write_dma);
1037 ppc_dcr_register(env, DMA0_CT1,
1038 dma, &dcr_read_dma, &dcr_write_dma);
1039 ppc_dcr_register(env, DMA0_DA1,
1040 dma, &dcr_read_dma, &dcr_write_dma);
1041 ppc_dcr_register(env, DMA0_SA1,
1042 dma, &dcr_read_dma, &dcr_write_dma);
1043 ppc_dcr_register(env, DMA0_SG1,
1044 dma, &dcr_read_dma, &dcr_write_dma);
1045 ppc_dcr_register(env, DMA0_CR2,
1046 dma, &dcr_read_dma, &dcr_write_dma);
1047 ppc_dcr_register(env, DMA0_CT2,
1048 dma, &dcr_read_dma, &dcr_write_dma);
1049 ppc_dcr_register(env, DMA0_DA2,
1050 dma, &dcr_read_dma, &dcr_write_dma);
1051 ppc_dcr_register(env, DMA0_SA2,
1052 dma, &dcr_read_dma, &dcr_write_dma);
1053 ppc_dcr_register(env, DMA0_SG2,
1054 dma, &dcr_read_dma, &dcr_write_dma);
1055 ppc_dcr_register(env, DMA0_CR3,
1056 dma, &dcr_read_dma, &dcr_write_dma);
1057 ppc_dcr_register(env, DMA0_CT3,
1058 dma, &dcr_read_dma, &dcr_write_dma);
1059 ppc_dcr_register(env, DMA0_DA3,
1060 dma, &dcr_read_dma, &dcr_write_dma);
1061 ppc_dcr_register(env, DMA0_SA3,
1062 dma, &dcr_read_dma, &dcr_write_dma);
1063 ppc_dcr_register(env, DMA0_SG3,
1064 dma, &dcr_read_dma, &dcr_write_dma);
1065 ppc_dcr_register(env, DMA0_SR,
1066 dma, &dcr_read_dma, &dcr_write_dma);
1067 ppc_dcr_register(env, DMA0_SGC,
1068 dma, &dcr_read_dma, &dcr_write_dma);
1069 ppc_dcr_register(env, DMA0_SLP,
1070 dma, &dcr_read_dma, &dcr_write_dma);
1071 ppc_dcr_register(env, DMA0_POL,
1072 dma, &dcr_read_dma, &dcr_write_dma);
1073 }
1074 }
1075
1076 /*****************************************************************************/
1077 /* GPIO */
1078 typedef struct ppc405_gpio_t ppc405_gpio_t;
1079 struct ppc405_gpio_t {
1080 target_phys_addr_t base;
1081 uint32_t or;
1082 uint32_t tcr;
1083 uint32_t osrh;
1084 uint32_t osrl;
1085 uint32_t tsrh;
1086 uint32_t tsrl;
1087 uint32_t odr;
1088 uint32_t ir;
1089 uint32_t rr1;
1090 uint32_t isr1h;
1091 uint32_t isr1l;
1092 };
1093
1094 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
1095 {
1096 ppc405_gpio_t *gpio;
1097
1098 gpio = opaque;
1099 #ifdef DEBUG_GPIO
1100 printf("%s: addr " PADDRX "\n", __func__, addr);
1101 #endif
1102
1103 return 0;
1104 }
1105
1106 static void ppc405_gpio_writeb (void *opaque,
1107 target_phys_addr_t addr, uint32_t value)
1108 {
1109 ppc405_gpio_t *gpio;
1110
1111 gpio = opaque;
1112 #ifdef DEBUG_GPIO
1113 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1114 #endif
1115 }
1116
1117 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
1118 {
1119 ppc405_gpio_t *gpio;
1120
1121 gpio = opaque;
1122 #ifdef DEBUG_GPIO
1123 printf("%s: addr " PADDRX "\n", __func__, addr);
1124 #endif
1125
1126 return 0;
1127 }
1128
1129 static void ppc405_gpio_writew (void *opaque,
1130 target_phys_addr_t addr, uint32_t value)
1131 {
1132 ppc405_gpio_t *gpio;
1133
1134 gpio = opaque;
1135 #ifdef DEBUG_GPIO
1136 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1137 #endif
1138 }
1139
1140 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
1141 {
1142 ppc405_gpio_t *gpio;
1143
1144 gpio = opaque;
1145 #ifdef DEBUG_GPIO
1146 printf("%s: addr " PADDRX "\n", __func__, addr);
1147 #endif
1148
1149 return 0;
1150 }
1151
1152 static void ppc405_gpio_writel (void *opaque,
1153 target_phys_addr_t addr, uint32_t value)
1154 {
1155 ppc405_gpio_t *gpio;
1156
1157 gpio = opaque;
1158 #ifdef DEBUG_GPIO
1159 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1160 #endif
1161 }
1162
1163 static CPUReadMemoryFunc *ppc405_gpio_read[] = {
1164 &ppc405_gpio_readb,
1165 &ppc405_gpio_readw,
1166 &ppc405_gpio_readl,
1167 };
1168
1169 static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
1170 &ppc405_gpio_writeb,
1171 &ppc405_gpio_writew,
1172 &ppc405_gpio_writel,
1173 };
1174
1175 static void ppc405_gpio_reset (void *opaque)
1176 {
1177 ppc405_gpio_t *gpio;
1178
1179 gpio = opaque;
1180 }
1181
1182 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
1183 target_phys_addr_t offset)
1184 {
1185 ppc405_gpio_t *gpio;
1186
1187 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
1188 if (gpio != NULL) {
1189 gpio->base = offset;
1190 ppc405_gpio_reset(gpio);
1191 qemu_register_reset(&ppc405_gpio_reset, gpio);
1192 #ifdef DEBUG_GPIO
1193 printf("%s: offset=" PADDRX "\n", __func__, offset);
1194 #endif
1195 ppc4xx_mmio_register(env, mmio, offset, 0x038,
1196 ppc405_gpio_read, ppc405_gpio_write, gpio);
1197 }
1198 }
1199
1200 /*****************************************************************************/
1201 /* Serial ports */
1202 static CPUReadMemoryFunc *serial_mm_read[] = {
1203 &serial_mm_readb,
1204 &serial_mm_readw,
1205 &serial_mm_readl,
1206 };
1207
1208 static CPUWriteMemoryFunc *serial_mm_write[] = {
1209 &serial_mm_writeb,
1210 &serial_mm_writew,
1211 &serial_mm_writel,
1212 };
1213
1214 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
1215 target_phys_addr_t offset, qemu_irq irq,
1216 CharDriverState *chr)
1217 {
1218 void *serial;
1219
1220 #ifdef DEBUG_SERIAL
1221 printf("%s: offset=" PADDRX "\n", __func__, offset);
1222 #endif
1223 serial = serial_mm_init(offset, 0, irq, chr, 0);
1224 ppc4xx_mmio_register(env, mmio, offset, 0x008,
1225 serial_mm_read, serial_mm_write, serial);
1226 }
1227
1228 /*****************************************************************************/
1229 /* On Chip Memory */
1230 enum {
1231 OCM0_ISARC = 0x018,
1232 OCM0_ISACNTL = 0x019,
1233 OCM0_DSARC = 0x01A,
1234 OCM0_DSACNTL = 0x01B,
1235 };
1236
1237 typedef struct ppc405_ocm_t ppc405_ocm_t;
1238 struct ppc405_ocm_t {
1239 target_ulong offset;
1240 uint32_t isarc;
1241 uint32_t isacntl;
1242 uint32_t dsarc;
1243 uint32_t dsacntl;
1244 };
1245
1246 static void ocm_update_mappings (ppc405_ocm_t *ocm,
1247 uint32_t isarc, uint32_t isacntl,
1248 uint32_t dsarc, uint32_t dsacntl)
1249 {
1250 #ifdef DEBUG_OCM
1251 printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n",
1252 isarc, isacntl, dsarc, dsacntl,
1253 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
1254 #endif
1255 if (ocm->isarc != isarc ||
1256 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
1257 if (ocm->isacntl & 0x80000000) {
1258 /* Unmap previously assigned memory region */
1259 printf("OCM unmap ISA %08x\n", ocm->isarc);
1260 cpu_register_physical_memory(ocm->isarc, 0x04000000,
1261 IO_MEM_UNASSIGNED);
1262 }
1263 if (isacntl & 0x80000000) {
1264 /* Map new instruction memory region */
1265 #ifdef DEBUG_OCM
1266 printf("OCM map ISA %08x\n", isarc);
1267 #endif
1268 cpu_register_physical_memory(isarc, 0x04000000,
1269 ocm->offset | IO_MEM_RAM);
1270 }
1271 }
1272 if (ocm->dsarc != dsarc ||
1273 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
1274 if (ocm->dsacntl & 0x80000000) {
1275 /* Beware not to unmap the region we just mapped */
1276 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
1277 /* Unmap previously assigned memory region */
1278 #ifdef DEBUG_OCM
1279 printf("OCM unmap DSA %08x\n", ocm->dsarc);
1280 #endif
1281 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
1282 IO_MEM_UNASSIGNED);
1283 }
1284 }
1285 if (dsacntl & 0x80000000) {
1286 /* Beware not to remap the region we just mapped */
1287 if (!(isacntl & 0x80000000) || dsarc != isarc) {
1288 /* Map new data memory region */
1289 #ifdef DEBUG_OCM
1290 printf("OCM map DSA %08x\n", dsarc);
1291 #endif
1292 cpu_register_physical_memory(dsarc, 0x04000000,
1293 ocm->offset | IO_MEM_RAM);
1294 }
1295 }
1296 }
1297 }
1298
1299 static target_ulong dcr_read_ocm (void *opaque, int dcrn)
1300 {
1301 ppc405_ocm_t *ocm;
1302 target_ulong ret;
1303
1304 ocm = opaque;
1305 switch (dcrn) {
1306 case OCM0_ISARC:
1307 ret = ocm->isarc;
1308 break;
1309 case OCM0_ISACNTL:
1310 ret = ocm->isacntl;
1311 break;
1312 case OCM0_DSARC:
1313 ret = ocm->dsarc;
1314 break;
1315 case OCM0_DSACNTL:
1316 ret = ocm->dsacntl;
1317 break;
1318 default:
1319 ret = 0;
1320 break;
1321 }
1322
1323 return ret;
1324 }
1325
1326 static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
1327 {
1328 ppc405_ocm_t *ocm;
1329 uint32_t isarc, dsarc, isacntl, dsacntl;
1330
1331 ocm = opaque;
1332 isarc = ocm->isarc;
1333 dsarc = ocm->dsarc;
1334 isacntl = ocm->isacntl;
1335 dsacntl = ocm->dsacntl;
1336 switch (dcrn) {
1337 case OCM0_ISARC:
1338 isarc = val & 0xFC000000;
1339 break;
1340 case OCM0_ISACNTL:
1341 isacntl = val & 0xC0000000;
1342 break;
1343 case OCM0_DSARC:
1344 isarc = val & 0xFC000000;
1345 break;
1346 case OCM0_DSACNTL:
1347 isacntl = val & 0xC0000000;
1348 break;
1349 }
1350 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1351 ocm->isarc = isarc;
1352 ocm->dsarc = dsarc;
1353 ocm->isacntl = isacntl;
1354 ocm->dsacntl = dsacntl;
1355 }
1356
1357 static void ocm_reset (void *opaque)
1358 {
1359 ppc405_ocm_t *ocm;
1360 uint32_t isarc, dsarc, isacntl, dsacntl;
1361
1362 ocm = opaque;
1363 isarc = 0x00000000;
1364 isacntl = 0x00000000;
1365 dsarc = 0x00000000;
1366 dsacntl = 0x00000000;
1367 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1368 ocm->isarc = isarc;
1369 ocm->dsarc = dsarc;
1370 ocm->isacntl = isacntl;
1371 ocm->dsacntl = dsacntl;
1372 }
1373
1374 void ppc405_ocm_init (CPUState *env, unsigned long offset)
1375 {
1376 ppc405_ocm_t *ocm;
1377
1378 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
1379 if (ocm != NULL) {
1380 ocm->offset = offset;
1381 ocm_reset(ocm);
1382 qemu_register_reset(&ocm_reset, ocm);
1383 ppc_dcr_register(env, OCM0_ISARC,
1384 ocm, &dcr_read_ocm, &dcr_write_ocm);
1385 ppc_dcr_register(env, OCM0_ISACNTL,
1386 ocm, &dcr_read_ocm, &dcr_write_ocm);
1387 ppc_dcr_register(env, OCM0_DSARC,
1388 ocm, &dcr_read_ocm, &dcr_write_ocm);
1389 ppc_dcr_register(env, OCM0_DSACNTL,
1390 ocm, &dcr_read_ocm, &dcr_write_ocm);
1391 }
1392 }
1393
1394 /*****************************************************************************/
1395 /* I2C controller */
1396 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
1397 struct ppc4xx_i2c_t {
1398 target_phys_addr_t base;
1399 qemu_irq irq;
1400 uint8_t mdata;
1401 uint8_t lmadr;
1402 uint8_t hmadr;
1403 uint8_t cntl;
1404 uint8_t mdcntl;
1405 uint8_t sts;
1406 uint8_t extsts;
1407 uint8_t sdata;
1408 uint8_t lsadr;
1409 uint8_t hsadr;
1410 uint8_t clkdiv;
1411 uint8_t intrmsk;
1412 uint8_t xfrcnt;
1413 uint8_t xtcntlss;
1414 uint8_t directcntl;
1415 };
1416
1417 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1418 {
1419 ppc4xx_i2c_t *i2c;
1420 uint32_t ret;
1421
1422 #ifdef DEBUG_I2C
1423 printf("%s: addr " PADDRX "\n", __func__, addr);
1424 #endif
1425 i2c = opaque;
1426 switch (addr - i2c->base) {
1427 case 0x00:
1428 // i2c_readbyte(&i2c->mdata);
1429 ret = i2c->mdata;
1430 break;
1431 case 0x02:
1432 ret = i2c->sdata;
1433 break;
1434 case 0x04:
1435 ret = i2c->lmadr;
1436 break;
1437 case 0x05:
1438 ret = i2c->hmadr;
1439 break;
1440 case 0x06:
1441 ret = i2c->cntl;
1442 break;
1443 case 0x07:
1444 ret = i2c->mdcntl;
1445 break;
1446 case 0x08:
1447 ret = i2c->sts;
1448 break;
1449 case 0x09:
1450 ret = i2c->extsts;
1451 break;
1452 case 0x0A:
1453 ret = i2c->lsadr;
1454 break;
1455 case 0x0B:
1456 ret = i2c->hsadr;
1457 break;
1458 case 0x0C:
1459 ret = i2c->clkdiv;
1460 break;
1461 case 0x0D:
1462 ret = i2c->intrmsk;
1463 break;
1464 case 0x0E:
1465 ret = i2c->xfrcnt;
1466 break;
1467 case 0x0F:
1468 ret = i2c->xtcntlss;
1469 break;
1470 case 0x10:
1471 ret = i2c->directcntl;
1472 break;
1473 default:
1474 ret = 0x00;
1475 break;
1476 }
1477 #ifdef DEBUG_I2C
1478 printf("%s: addr " PADDRX " %02x\n", __func__, addr, ret);
1479 #endif
1480
1481 return ret;
1482 }
1483
1484 static void ppc4xx_i2c_writeb (void *opaque,
1485 target_phys_addr_t addr, uint32_t value)
1486 {
1487 ppc4xx_i2c_t *i2c;
1488
1489 #ifdef DEBUG_I2C
1490 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1491 #endif
1492 i2c = opaque;
1493 switch (addr - i2c->base) {
1494 case 0x00:
1495 i2c->mdata = value;
1496 // i2c_sendbyte(&i2c->mdata);
1497 break;
1498 case 0x02:
1499 i2c->sdata = value;
1500 break;
1501 case 0x04:
1502 i2c->lmadr = value;
1503 break;
1504 case 0x05:
1505 i2c->hmadr = value;
1506 break;
1507 case 0x06:
1508 i2c->cntl = value;
1509 break;
1510 case 0x07:
1511 i2c->mdcntl = value & 0xDF;
1512 break;
1513 case 0x08:
1514 i2c->sts &= ~(value & 0x0A);
1515 break;
1516 case 0x09:
1517 i2c->extsts &= ~(value & 0x8F);
1518 break;
1519 case 0x0A:
1520 i2c->lsadr = value;
1521 break;
1522 case 0x0B:
1523 i2c->hsadr = value;
1524 break;
1525 case 0x0C:
1526 i2c->clkdiv = value;
1527 break;
1528 case 0x0D:
1529 i2c->intrmsk = value;
1530 break;
1531 case 0x0E:
1532 i2c->xfrcnt = value & 0x77;
1533 break;
1534 case 0x0F:
1535 i2c->xtcntlss = value;
1536 break;
1537 case 0x10:
1538 i2c->directcntl = value & 0x7;
1539 break;
1540 }
1541 }
1542
1543 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
1544 {
1545 uint32_t ret;
1546
1547 #ifdef DEBUG_I2C
1548 printf("%s: addr " PADDRX "\n", __func__, addr);
1549 #endif
1550 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1551 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1552
1553 return ret;
1554 }
1555
1556 static void ppc4xx_i2c_writew (void *opaque,
1557 target_phys_addr_t addr, uint32_t value)
1558 {
1559 #ifdef DEBUG_I2C
1560 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1561 #endif
1562 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1563 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1564 }
1565
1566 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
1567 {
1568 uint32_t ret;
1569
1570 #ifdef DEBUG_I2C
1571 printf("%s: addr " PADDRX "\n", __func__, addr);
1572 #endif
1573 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1574 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1575 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1576 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1577
1578 return ret;
1579 }
1580
1581 static void ppc4xx_i2c_writel (void *opaque,
1582 target_phys_addr_t addr, uint32_t value)
1583 {
1584 #ifdef DEBUG_I2C
1585 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1586 #endif
1587 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1588 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1589 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1590 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1591 }
1592
1593 static CPUReadMemoryFunc *i2c_read[] = {
1594 &ppc4xx_i2c_readb,
1595 &ppc4xx_i2c_readw,
1596 &ppc4xx_i2c_readl,
1597 };
1598
1599 static CPUWriteMemoryFunc *i2c_write[] = {
1600 &ppc4xx_i2c_writeb,
1601 &ppc4xx_i2c_writew,
1602 &ppc4xx_i2c_writel,
1603 };
1604
1605 static void ppc4xx_i2c_reset (void *opaque)
1606 {
1607 ppc4xx_i2c_t *i2c;
1608
1609 i2c = opaque;
1610 i2c->mdata = 0x00;
1611 i2c->sdata = 0x00;
1612 i2c->cntl = 0x00;
1613 i2c->mdcntl = 0x00;
1614 i2c->sts = 0x00;
1615 i2c->extsts = 0x00;
1616 i2c->clkdiv = 0x00;
1617 i2c->xfrcnt = 0x00;
1618 i2c->directcntl = 0x0F;
1619 }
1620
1621 void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
1622 target_phys_addr_t offset, qemu_irq irq)
1623 {
1624 ppc4xx_i2c_t *i2c;
1625
1626 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
1627 if (i2c != NULL) {
1628 i2c->base = offset;
1629 i2c->irq = irq;
1630 ppc4xx_i2c_reset(i2c);
1631 #ifdef DEBUG_I2C
1632 printf("%s: offset=" PADDRX "\n", __func__, offset);
1633 #endif
1634 ppc4xx_mmio_register(env, mmio, offset, 0x011,
1635 i2c_read, i2c_write, i2c);
1636 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1637 }
1638 }
1639
1640 /*****************************************************************************/
1641 /* General purpose timers */
1642 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1643 struct ppc4xx_gpt_t {
1644 target_phys_addr_t base;
1645 int64_t tb_offset;
1646 uint32_t tb_freq;
1647 struct QEMUTimer *timer;
1648 qemu_irq irqs[5];
1649 uint32_t oe;
1650 uint32_t ol;
1651 uint32_t im;
1652 uint32_t is;
1653 uint32_t ie;
1654 uint32_t comp[5];
1655 uint32_t mask[5];
1656 };
1657
1658 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
1659 {
1660 #ifdef DEBUG_GPT
1661 printf("%s: addr " PADDRX "\n", __func__, addr);
1662 #endif
1663 /* XXX: generate a bus fault */
1664 return -1;
1665 }
1666
1667 static void ppc4xx_gpt_writeb (void *opaque,
1668 target_phys_addr_t addr, uint32_t value)
1669 {
1670 #ifdef DEBUG_I2C
1671 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1672 #endif
1673 /* XXX: generate a bus fault */
1674 }
1675
1676 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
1677 {
1678 #ifdef DEBUG_GPT
1679 printf("%s: addr " PADDRX "\n", __func__, addr);
1680 #endif
1681 /* XXX: generate a bus fault */
1682 return -1;
1683 }
1684
1685 static void ppc4xx_gpt_writew (void *opaque,
1686 target_phys_addr_t addr, uint32_t value)
1687 {
1688 #ifdef DEBUG_I2C
1689 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1690 #endif
1691 /* XXX: generate a bus fault */
1692 }
1693
1694 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1695 {
1696 /* XXX: TODO */
1697 return 0;
1698 }
1699
1700 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1701 {
1702 /* XXX: TODO */
1703 }
1704
1705 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1706 {
1707 uint32_t mask;
1708 int i;
1709
1710 mask = 0x80000000;
1711 for (i = 0; i < 5; i++) {
1712 if (gpt->oe & mask) {
1713 /* Output is enabled */
1714 if (ppc4xx_gpt_compare(gpt, i)) {
1715 /* Comparison is OK */
1716 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1717 } else {
1718 /* Comparison is KO */
1719 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1720 }
1721 }
1722 mask = mask >> 1;
1723 }
1724 }
1725
1726 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1727 {
1728 uint32_t mask;
1729 int i;
1730
1731 mask = 0x00008000;
1732 for (i = 0; i < 5; i++) {
1733 if (gpt->is & gpt->im & mask)
1734 qemu_irq_raise(gpt->irqs[i]);
1735 else
1736 qemu_irq_lower(gpt->irqs[i]);
1737 mask = mask >> 1;
1738 }
1739 }
1740
1741 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1742 {
1743 /* XXX: TODO */
1744 }
1745
1746 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
1747 {
1748 ppc4xx_gpt_t *gpt;
1749 uint32_t ret;
1750 int idx;
1751
1752 #ifdef DEBUG_GPT
1753 printf("%s: addr " PADDRX "\n", __func__, addr);
1754 #endif
1755 gpt = opaque;
1756 switch (addr - gpt->base) {
1757 case 0x00:
1758 /* Time base counter */
1759 ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
1760 gpt->tb_freq, ticks_per_sec);
1761 break;
1762 case 0x10:
1763 /* Output enable */
1764 ret = gpt->oe;
1765 break;
1766 case 0x14:
1767 /* Output level */
1768 ret = gpt->ol;
1769 break;
1770 case 0x18:
1771 /* Interrupt mask */
1772 ret = gpt->im;
1773 break;
1774 case 0x1C:
1775 case 0x20:
1776 /* Interrupt status */
1777 ret = gpt->is;
1778 break;
1779 case 0x24:
1780 /* Interrupt enable */
1781 ret = gpt->ie;
1782 break;
1783 case 0x80 ... 0x90:
1784 /* Compare timer */
1785 idx = ((addr - gpt->base) - 0x80) >> 2;
1786 ret = gpt->comp[idx];
1787 break;
1788 case 0xC0 ... 0xD0:
1789 /* Compare mask */
1790 idx = ((addr - gpt->base) - 0xC0) >> 2;
1791 ret = gpt->mask[idx];
1792 break;
1793 default:
1794 ret = -1;
1795 break;
1796 }
1797
1798 return ret;
1799 }
1800
1801 static void ppc4xx_gpt_writel (void *opaque,
1802 target_phys_addr_t addr, uint32_t value)
1803 {
1804 ppc4xx_gpt_t *gpt;
1805 int idx;
1806
1807 #ifdef DEBUG_I2C
1808 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1809 #endif
1810 gpt = opaque;
1811 switch (addr - gpt->base) {
1812 case 0x00:
1813 /* Time base counter */
1814 gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq)
1815 - qemu_get_clock(vm_clock);
1816 ppc4xx_gpt_compute_timer(gpt);
1817 break;
1818 case 0x10:
1819 /* Output enable */
1820 gpt->oe = value & 0xF8000000;
1821 ppc4xx_gpt_set_outputs(gpt);
1822 break;
1823 case 0x14:
1824 /* Output level */
1825 gpt->ol = value & 0xF8000000;
1826 ppc4xx_gpt_set_outputs(gpt);
1827 break;
1828 case 0x18:
1829 /* Interrupt mask */
1830 gpt->im = value & 0x0000F800;
1831 break;
1832 case 0x1C:
1833 /* Interrupt status set */
1834 gpt->is |= value & 0x0000F800;
1835 ppc4xx_gpt_set_irqs(gpt);
1836 break;
1837 case 0x20:
1838 /* Interrupt status clear */
1839 gpt->is &= ~(value & 0x0000F800);
1840 ppc4xx_gpt_set_irqs(gpt);
1841 break;
1842 case 0x24:
1843 /* Interrupt enable */
1844 gpt->ie = value & 0x0000F800;
1845 ppc4xx_gpt_set_irqs(gpt);
1846 break;
1847 case 0x80 ... 0x90:
1848 /* Compare timer */
1849 idx = ((addr - gpt->base) - 0x80) >> 2;
1850 gpt->comp[idx] = value & 0xF8000000;
1851 ppc4xx_gpt_compute_timer(gpt);
1852 break;
1853 case 0xC0 ... 0xD0:
1854 /* Compare mask */
1855 idx = ((addr - gpt->base) - 0xC0) >> 2;
1856 gpt->mask[idx] = value & 0xF8000000;
1857 ppc4xx_gpt_compute_timer(gpt);
1858 break;
1859 }
1860 }
1861
1862 static CPUReadMemoryFunc *gpt_read[] = {
1863 &ppc4xx_gpt_readb,
1864 &ppc4xx_gpt_readw,
1865 &ppc4xx_gpt_readl,
1866 };
1867
1868 static CPUWriteMemoryFunc *gpt_write[] = {
1869 &ppc4xx_gpt_writeb,
1870 &ppc4xx_gpt_writew,
1871 &ppc4xx_gpt_writel,
1872 };
1873
1874 static void ppc4xx_gpt_cb (void *opaque)
1875 {
1876 ppc4xx_gpt_t *gpt;
1877
1878 gpt = opaque;
1879 ppc4xx_gpt_set_irqs(gpt);
1880 ppc4xx_gpt_set_outputs(gpt);
1881 ppc4xx_gpt_compute_timer(gpt);
1882 }
1883
1884 static void ppc4xx_gpt_reset (void *opaque)
1885 {
1886 ppc4xx_gpt_t *gpt;
1887 int i;
1888
1889 gpt = opaque;
1890 qemu_del_timer(gpt->timer);
1891 gpt->oe = 0x00000000;
1892 gpt->ol = 0x00000000;
1893 gpt->im = 0x00000000;
1894 gpt->is = 0x00000000;
1895 gpt->ie = 0x00000000;
1896 for (i = 0; i < 5; i++) {
1897 gpt->comp[i] = 0x00000000;
1898 gpt->mask[i] = 0x00000000;
1899 }
1900 }
1901
1902 void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
1903 target_phys_addr_t offset, qemu_irq irqs[5])
1904 {
1905 ppc4xx_gpt_t *gpt;
1906 int i;
1907
1908 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
1909 if (gpt != NULL) {
1910 gpt->base = offset;
1911 for (i = 0; i < 5; i++)
1912 gpt->irqs[i] = irqs[i];
1913 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
1914 ppc4xx_gpt_reset(gpt);
1915 #ifdef DEBUG_GPT
1916 printf("%s: offset=" PADDRX "\n", __func__, offset);
1917 #endif
1918 ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
1919 gpt_read, gpt_write, gpt);
1920 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1921 }
1922 }
1923
1924 /*****************************************************************************/
1925 /* MAL */
1926 enum {
1927 MAL0_CFG = 0x180,
1928 MAL0_ESR = 0x181,
1929 MAL0_IER = 0x182,
1930 MAL0_TXCASR = 0x184,
1931 MAL0_TXCARR = 0x185,
1932 MAL0_TXEOBISR = 0x186,
1933 MAL0_TXDEIR = 0x187,
1934 MAL0_RXCASR = 0x190,
1935 MAL0_RXCARR = 0x191,
1936 MAL0_RXEOBISR = 0x192,
1937 MAL0_RXDEIR = 0x193,
1938 MAL0_TXCTP0R = 0x1A0,
1939 MAL0_TXCTP1R = 0x1A1,
1940 MAL0_TXCTP2R = 0x1A2,
1941 MAL0_TXCTP3R = 0x1A3,
1942 MAL0_RXCTP0R = 0x1C0,
1943 MAL0_RXCTP1R = 0x1C1,
1944 MAL0_RCBS0 = 0x1E0,
1945 MAL0_RCBS1 = 0x1E1,
1946 };
1947
1948 typedef struct ppc40x_mal_t ppc40x_mal_t;
1949 struct ppc40x_mal_t {
1950 qemu_irq irqs[4];
1951 uint32_t cfg;
1952 uint32_t esr;
1953 uint32_t ier;
1954 uint32_t txcasr;
1955 uint32_t txcarr;
1956 uint32_t txeobisr;
1957 uint32_t txdeir;
1958 uint32_t rxcasr;
1959 uint32_t rxcarr;
1960 uint32_t rxeobisr;
1961 uint32_t rxdeir;
1962 uint32_t txctpr[4];
1963 uint32_t rxctpr[2];
1964 uint32_t rcbs[2];
1965 };
1966
1967 static void ppc40x_mal_reset (void *opaque);
1968
1969 static target_ulong dcr_read_mal (void *opaque, int dcrn)
1970 {
1971 ppc40x_mal_t *mal;
1972 target_ulong ret;
1973
1974 mal = opaque;
1975 switch (dcrn) {
1976 case MAL0_CFG:
1977 ret = mal->cfg;
1978 break;
1979 case MAL0_ESR:
1980 ret = mal->esr;
1981 break;
1982 case MAL0_IER:
1983 ret = mal->ier;
1984 break;
1985 case MAL0_TXCASR:
1986 ret = mal->txcasr;
1987 break;
1988 case MAL0_TXCARR:
1989 ret = mal->txcarr;
1990 break;
1991 case MAL0_TXEOBISR:
1992 ret = mal->txeobisr;
1993 break;
1994 case MAL0_TXDEIR:
1995 ret = mal->txdeir;
1996 break;
1997 case MAL0_RXCASR:
1998 ret = mal->rxcasr;
1999 break;
2000 case MAL0_RXCARR:
2001 ret = mal->rxcarr;
2002 break;
2003 case MAL0_RXEOBISR:
2004 ret = mal->rxeobisr;
2005 break;
2006 case MAL0_RXDEIR:
2007 ret = mal->rxdeir;
2008 break;
2009 case MAL0_TXCTP0R:
2010 ret = mal->txctpr[0];
2011 break;
2012 case MAL0_TXCTP1R:
2013 ret = mal->txctpr[1];
2014 break;
2015 case MAL0_TXCTP2R:
2016 ret = mal->txctpr[2];
2017 break;
2018 case MAL0_TXCTP3R:
2019 ret = mal->txctpr[3];
2020 break;
2021 case MAL0_RXCTP0R:
2022 ret = mal->rxctpr[0];
2023 break;
2024 case MAL0_RXCTP1R:
2025 ret = mal->rxctpr[1];
2026 break;
2027 case MAL0_RCBS0:
2028 ret = mal->rcbs[0];
2029 break;
2030 case MAL0_RCBS1:
2031 ret = mal->rcbs[1];
2032 break;
2033 default:
2034 ret = 0;
2035 break;
2036 }
2037
2038 return ret;
2039 }
2040
2041 static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
2042 {
2043 ppc40x_mal_t *mal;
2044 int idx;
2045
2046 mal = opaque;
2047 switch (dcrn) {
2048 case MAL0_CFG:
2049 if (val & 0x80000000)
2050 ppc40x_mal_reset(mal);
2051 mal->cfg = val & 0x00FFC087;
2052 break;
2053 case MAL0_ESR:
2054 /* Read/clear */
2055 mal->esr &= ~val;
2056 break;
2057 case MAL0_IER:
2058 mal->ier = val & 0x0000001F;
2059 break;
2060 case MAL0_TXCASR:
2061 mal->txcasr = val & 0xF0000000;
2062 break;
2063 case MAL0_TXCARR:
2064 mal->txcarr = val & 0xF0000000;
2065 break;
2066 case MAL0_TXEOBISR:
2067 /* Read/clear */
2068 mal->txeobisr &= ~val;
2069 break;
2070 case MAL0_TXDEIR:
2071 /* Read/clear */
2072 mal->txdeir &= ~val;
2073 break;
2074 case MAL0_RXCASR:
2075 mal->rxcasr = val & 0xC0000000;
2076 break;
2077 case MAL0_RXCARR:
2078 mal->rxcarr = val & 0xC0000000;
2079 break;
2080 case MAL0_RXEOBISR:
2081 /* Read/clear */
2082 mal->rxeobisr &= ~val;
2083 break;
2084 case MAL0_RXDEIR:
2085 /* Read/clear */
2086 mal->rxdeir &= ~val;
2087 break;
2088 case MAL0_TXCTP0R:
2089 idx = 0;
2090 goto update_tx_ptr;
2091 case MAL0_TXCTP1R:
2092 idx = 1;
2093 goto update_tx_ptr;
2094 case MAL0_TXCTP2R:
2095 idx = 2;
2096 goto update_tx_ptr;
2097 case MAL0_TXCTP3R:
2098 idx = 3;
2099 update_tx_ptr:
2100 mal->txctpr[idx] = val;
2101 break;
2102 case MAL0_RXCTP0R:
2103 idx = 0;
2104 goto update_rx_ptr;
2105 case MAL0_RXCTP1R:
2106 idx = 1;
2107 update_rx_ptr:
2108 mal->rxctpr[idx] = val;
2109 break;
2110 case MAL0_RCBS0:
2111 idx = 0;
2112 goto update_rx_size;
2113 case MAL0_RCBS1:
2114 idx = 1;
2115 update_rx_size:
2116 mal->rcbs[idx] = val & 0x000000FF;
2117 break;
2118 }
2119 }
2120
2121 static void ppc40x_mal_reset (void *opaque)
2122 {
2123 ppc40x_mal_t *mal;
2124
2125 mal = opaque;
2126 mal->cfg = 0x0007C000;
2127 mal->esr = 0x00000000;
2128 mal->ier = 0x00000000;
2129 mal->rxcasr = 0x00000000;
2130 mal->rxdeir = 0x00000000;
2131 mal->rxeobisr = 0x00000000;
2132 mal->txcasr = 0x00000000;
2133 mal->txdeir = 0x00000000;
2134 mal->txeobisr = 0x00000000;
2135 }
2136
2137 void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
2138 {
2139 ppc40x_mal_t *mal;
2140 int i;
2141
2142 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
2143 if (mal != NULL) {
2144 for (i = 0; i < 4; i++)
2145 mal->irqs[i] = irqs[i];
2146 ppc40x_mal_reset(mal);
2147 qemu_register_reset(&ppc40x_mal_reset, mal);
2148 ppc_dcr_register(env, MAL0_CFG,
2149 mal, &dcr_read_mal, &dcr_write_mal);
2150 ppc_dcr_register(env, MAL0_ESR,
2151 mal, &dcr_read_mal, &dcr_write_mal);
2152 ppc_dcr_register(env, MAL0_IER,
2153 mal, &dcr_read_mal, &dcr_write_mal);
2154 ppc_dcr_register(env, MAL0_TXCASR,
2155 mal, &dcr_read_mal, &dcr_write_mal);
2156 ppc_dcr_register(env, MAL0_TXCARR,
2157 mal, &dcr_read_mal, &dcr_write_mal);
2158 ppc_dcr_register(env, MAL0_TXEOBISR,
2159 mal, &dcr_read_mal, &dcr_write_mal);
2160 ppc_dcr_register(env, MAL0_TXDEIR,
2161 mal, &dcr_read_mal, &dcr_write_mal);
2162 ppc_dcr_register(env, MAL0_RXCASR,
2163 mal, &dcr_read_mal, &dcr_write_mal);
2164 ppc_dcr_register(env, MAL0_RXCARR,
2165 mal, &dcr_read_mal, &dcr_write_mal);
2166 ppc_dcr_register(env, MAL0_RXEOBISR,
2167 mal, &dcr_read_mal, &dcr_write_mal);
2168 ppc_dcr_register(env, MAL0_RXDEIR,
2169 mal, &dcr_read_mal, &dcr_write_mal);
2170 ppc_dcr_register(env, MAL0_TXCTP0R,
2171 mal, &dcr_read_mal, &dcr_write_mal);
2172 ppc_dcr_register(env, MAL0_TXCTP1R,
2173 mal, &dcr_read_mal, &dcr_write_mal);
2174 ppc_dcr_register(env, MAL0_TXCTP2R,
2175 mal, &dcr_read_mal, &dcr_write_mal);
2176 ppc_dcr_register(env, MAL0_TXCTP3R,
2177 mal, &dcr_read_mal, &dcr_write_mal);
2178 ppc_dcr_register(env, MAL0_RXCTP0R,
2179 mal, &dcr_read_mal, &dcr_write_mal);
2180 ppc_dcr_register(env, MAL0_RXCTP1R,
2181 mal, &dcr_read_mal, &dcr_write_mal);
2182 ppc_dcr_register(env, MAL0_RCBS0,
2183 mal, &dcr_read_mal, &dcr_write_mal);
2184 ppc_dcr_register(env, MAL0_RCBS1,
2185 mal, &dcr_read_mal, &dcr_write_mal);
2186 }
2187 }
2188
2189 /*****************************************************************************/
2190 /* SPR */
2191 void ppc40x_core_reset (CPUState *env)
2192 {
2193 target_ulong dbsr;
2194
2195 printf("Reset PowerPC core\n");
2196 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2197 /* XXX: TOFIX */
2198 #if 0
2199 cpu_ppc_reset(env);
2200 #else
2201 qemu_system_reset_request();
2202 #endif
2203 dbsr = env->spr[SPR_40x_DBSR];
2204 dbsr &= ~0x00000300;
2205 dbsr |= 0x00000100;
2206 env->spr[SPR_40x_DBSR] = dbsr;
2207 }
2208
2209 void ppc40x_chip_reset (CPUState *env)
2210 {
2211 target_ulong dbsr;
2212
2213 printf("Reset PowerPC chip\n");
2214 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2215 /* XXX: TOFIX */
2216 #if 0
2217 cpu_ppc_reset(env);
2218 #else
2219 qemu_system_reset_request();
2220 #endif
2221 /* XXX: TODO reset all internal peripherals */
2222 dbsr = env->spr[SPR_40x_DBSR];
2223 dbsr &= ~0x00000300;
2224 dbsr |= 0x00000200;
2225 env->spr[SPR_40x_DBSR] = dbsr;
2226 }
2227
2228 void ppc40x_system_reset (CPUState *env)
2229 {
2230 printf("Reset PowerPC system\n");
2231 qemu_system_reset_request();
2232 }
2233
2234 void store_40x_dbcr0 (CPUState *env, uint32_t val)
2235 {
2236 switch ((val >> 28) & 0x3) {
2237 case 0x0:
2238 /* No action */
2239 break;
2240 case 0x1:
2241 /* Core reset */
2242 ppc40x_core_reset(env);
2243 break;
2244 case 0x2:
2245 /* Chip reset */
2246 ppc40x_chip_reset(env);
2247 break;
2248 case 0x3:
2249 /* System reset */
2250 ppc40x_system_reset(env);
2251 break;
2252 }
2253 }
2254
2255 /*****************************************************************************/
2256 /* PowerPC 405CR */
2257 enum {
2258 PPC405CR_CPC0_PLLMR = 0x0B0,
2259 PPC405CR_CPC0_CR0 = 0x0B1,
2260 PPC405CR_CPC0_CR1 = 0x0B2,
2261 PPC405CR_CPC0_PSR = 0x0B4,
2262 PPC405CR_CPC0_JTAGID = 0x0B5,
2263 PPC405CR_CPC0_ER = 0x0B9,
2264 PPC405CR_CPC0_FR = 0x0BA,
2265 PPC405CR_CPC0_SR = 0x0BB,
2266 };
2267
2268 enum {
2269 PPC405CR_CPU_CLK = 0,
2270 PPC405CR_TMR_CLK = 1,
2271 PPC405CR_PLB_CLK = 2,
2272 PPC405CR_SDRAM_CLK = 3,
2273 PPC405CR_OPB_CLK = 4,
2274 PPC405CR_EXT_CLK = 5,
2275 PPC405CR_UART_CLK = 6,
2276 PPC405CR_CLK_NB = 7,
2277 };
2278
2279 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
2280 struct ppc405cr_cpc_t {
2281 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2282 uint32_t sysclk;
2283 uint32_t psr;
2284 uint32_t cr0;
2285 uint32_t cr1;
2286 uint32_t jtagid;
2287 uint32_t pllmr;
2288 uint32_t er;
2289 uint32_t fr;
2290 };
2291
2292 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
2293 {
2294 uint64_t VCO_out, PLL_out;
2295 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
2296 int M, D0, D1, D2;
2297
2298 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
2299 if (cpc->pllmr & 0x80000000) {
2300 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
2301 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
2302 M = D0 * D1 * D2;
2303 VCO_out = cpc->sysclk * M;
2304 if (VCO_out < 400000000 || VCO_out > 800000000) {
2305 /* PLL cannot lock */
2306 cpc->pllmr &= ~0x80000000;
2307 goto bypass_pll;
2308 }
2309 PLL_out = VCO_out / D2;
2310 } else {
2311 /* Bypass PLL */
2312 bypass_pll:
2313 M = D0;
2314 PLL_out = cpc->sysclk * M;
2315 }
2316 CPU_clk = PLL_out;
2317 if (cpc->cr1 & 0x00800000)
2318 TMR_clk = cpc->sysclk; /* Should have a separate clock */
2319 else
2320 TMR_clk = CPU_clk;
2321 PLB_clk = CPU_clk / D0;
2322 SDRAM_clk = PLB_clk;
2323 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
2324 OPB_clk = PLB_clk / D0;
2325 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
2326 EXT_clk = PLB_clk / D0;
2327 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
2328 UART_clk = CPU_clk / D0;
2329 /* Setup CPU clocks */
2330 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
2331 /* Setup time-base clock */
2332 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
2333 /* Setup PLB clock */
2334 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
2335 /* Setup SDRAM clock */
2336 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
2337 /* Setup OPB clock */
2338 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
2339 /* Setup external clock */
2340 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
2341 /* Setup UART clock */
2342 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
2343 }
2344
2345 static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
2346 {
2347 ppc405cr_cpc_t *cpc;
2348 target_ulong ret;
2349
2350 cpc = opaque;
2351 switch (dcrn) {
2352 case PPC405CR_CPC0_PLLMR:
2353 ret = cpc->pllmr;
2354 break;
2355 case PPC405CR_CPC0_CR0:
2356 ret = cpc->cr0;
2357 break;
2358 case PPC405CR_CPC0_CR1:
2359 ret = cpc->cr1;
2360 break;
2361 case PPC405CR_CPC0_PSR:
2362 ret = cpc->psr;
2363 break;
2364 case PPC405CR_CPC0_JTAGID:
2365 ret = cpc->jtagid;
2366 break;
2367 case PPC405CR_CPC0_ER:
2368 ret = cpc->er;
2369 break;
2370 case PPC405CR_CPC0_FR:
2371 ret = cpc->fr;
2372 break;
2373 case PPC405CR_CPC0_SR:
2374 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
2375 break;
2376 default:
2377 /* Avoid gcc warning */
2378 ret = 0;
2379 break;
2380 }
2381
2382 return ret;
2383 }
2384
2385 static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
2386 {
2387 ppc405cr_cpc_t *cpc;
2388
2389 cpc = opaque;
2390 switch (dcrn) {
2391 case PPC405CR_CPC0_PLLMR:
2392 cpc->pllmr = val & 0xFFF77C3F;
2393 break;
2394 case PPC405CR_CPC0_CR0:
2395 cpc->cr0 = val & 0x0FFFFFFE;
2396 break;
2397 case PPC405CR_CPC0_CR1:
2398 cpc->cr1 = val & 0x00800000;
2399 break;
2400 case PPC405CR_CPC0_PSR:
2401 /* Read-only */
2402 break;
2403 case PPC405CR_CPC0_JTAGID:
2404 /* Read-only */
2405 break;
2406 case PPC405CR_CPC0_ER:
2407 cpc->er = val & 0xBFFC0000;
2408 break;
2409 case PPC405CR_CPC0_FR:
2410 cpc->fr = val & 0xBFFC0000;
2411 break;
2412 case PPC405CR_CPC0_SR:
2413 /* Read-only */
2414 break;
2415 }
2416 }
2417
2418 static void ppc405cr_cpc_reset (void *opaque)
2419 {
2420 ppc405cr_cpc_t *cpc;
2421 int D;
2422
2423 cpc = opaque;
2424 /* Compute PLLMR value from PSR settings */
2425 cpc->pllmr = 0x80000000;
2426 /* PFWD */
2427 switch ((cpc->psr >> 30) & 3) {
2428 case 0:
2429 /* Bypass */
2430 cpc->pllmr &= ~0x80000000;
2431 break;
2432 case 1:
2433 /* Divide by 3 */
2434 cpc->pllmr |= 5 << 16;
2435 break;
2436 case 2:
2437 /* Divide by 4 */
2438 cpc->pllmr |= 4 << 16;
2439 break;
2440 case 3:
2441 /* Divide by 6 */
2442 cpc->pllmr |= 2 << 16;
2443 break;
2444 }
2445 /* PFBD */
2446 D = (cpc->psr >> 28) & 3;
2447 cpc->pllmr |= (D + 1) << 20;
2448 /* PT */
2449 D = (cpc->psr >> 25) & 7;
2450 switch (D) {
2451 case 0x2:
2452 cpc->pllmr |= 0x13;
2453 break;
2454 case 0x4:
2455 cpc->pllmr |= 0x15;
2456 break;
2457 case 0x5:
2458 cpc->pllmr |= 0x16;
2459 break;
2460 default:
2461 break;
2462 }
2463 /* PDC */
2464 D = (cpc->psr >> 23) & 3;
2465 cpc->pllmr |= D << 26;
2466 /* ODP */
2467 D = (cpc->psr >> 21) & 3;
2468 cpc->pllmr |= D << 10;
2469 /* EBPD */
2470 D = (cpc->psr >> 17) & 3;
2471 cpc->pllmr |= D << 24;
2472 cpc->cr0 = 0x0000003C;
2473 cpc->cr1 = 0x2B0D8800;
2474 cpc->er = 0x00000000;
2475 cpc->fr = 0x00000000;
2476 ppc405cr_clk_setup(cpc);
2477 }
2478
2479 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2480 {
2481 int D;
2482
2483 /* XXX: this should be read from IO pins */
2484 cpc->psr = 0x00000000; /* 8 bits ROM */
2485 /* PFWD */
2486 D = 0x2; /* Divide by 4 */
2487 cpc->psr |= D << 30;
2488 /* PFBD */
2489 D = 0x1; /* Divide by 2 */
2490 cpc->psr |= D << 28;
2491 /* PDC */
2492 D = 0x1; /* Divide by 2 */
2493 cpc->psr |= D << 23;
2494 /* PT */
2495 D = 0x5; /* M = 16 */
2496 cpc->psr |= D << 25;
2497 /* ODP */
2498 D = 0x1; /* Divide by 2 */
2499 cpc->psr |= D << 21;
2500 /* EBDP */
2501 D = 0x2; /* Divide by 4 */
2502 cpc->psr |= D << 17;
2503 }
2504
2505 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2506 uint32_t sysclk)
2507 {
2508 ppc405cr_cpc_t *cpc;
2509
2510 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2511 if (cpc != NULL) {
2512 memcpy(cpc->clk_setup, clk_setup,
2513 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2514 cpc->sysclk = sysclk;
2515 cpc->jtagid = 0x42051049;
2516 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2517 &dcr_read_crcpc, &dcr_write_crcpc);
2518 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2519 &dcr_read_crcpc, &dcr_write_crcpc);
2520 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2521 &dcr_read_crcpc, &dcr_write_crcpc);
2522 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2523 &dcr_read_crcpc, &dcr_write_crcpc);
2524 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2525 &dcr_read_crcpc, &dcr_write_crcpc);
2526 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2527 &dcr_read_crcpc, &dcr_write_crcpc);
2528 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2529 &dcr_read_crcpc, &dcr_write_crcpc);
2530 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2531 &dcr_read_crcpc, &dcr_write_crcpc);
2532 ppc405cr_clk_init(cpc);
2533 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2534 ppc405cr_cpc_reset(cpc);
2535 }
2536 }
2537
2538 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
2539 target_phys_addr_t ram_sizes[4],
2540 uint32_t sysclk, qemu_irq **picp,
2541 ram_addr_t *offsetp, int do_init)
2542 {
2543 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2544 qemu_irq dma_irqs[4];
2545 CPUState *env;
2546 ppc4xx_mmio_t *mmio;
2547 qemu_irq *pic, *irqs;
2548 ram_addr_t offset;
2549 int i;
2550
2551 memset(clk_setup, 0, sizeof(clk_setup));
2552 env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2553 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2554 /* Memory mapped devices registers */
2555 mmio = ppc4xx_mmio_init(env, 0xEF600000);
2556 /* PLB arbitrer */
2557 ppc4xx_plb_init(env);
2558 /* PLB to OPB bridge */
2559 ppc4xx_pob_init(env);
2560 /* OBP arbitrer */
2561 ppc4xx_opba_init(env, mmio, 0x600);
2562 /* Universal interrupt controller */
2563 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2564 irqs[PPCUIC_OUTPUT_INT] =
2565 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2566 irqs[PPCUIC_OUTPUT_CINT] =
2567 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2568 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2569 *picp = pic;
2570 /* SDRAM controller */
2571 ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
2572 offset = 0;
2573 for (i = 0; i < 4; i++)
2574 offset += ram_sizes[i];
2575 /* External bus controller */
2576 ppc405_ebc_init(env);
2577 /* DMA controller */
2578 dma_irqs[0] = pic[26];
2579 dma_irqs[1] = pic[25];
2580 dma_irqs[2] = pic[24];
2581 dma_irqs[3] = pic[23];
2582 ppc405_dma_init(env, dma_irqs);
2583 /* Serial ports */
2584 if (serial_hds[0] != NULL) {
2585 ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
2586 }
2587 if (serial_hds[1] != NULL) {
2588 ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
2589 }
2590 /* IIC controller */
2591 ppc405_i2c_init(env, mmio, 0x500, pic[29]);
2592 /* GPIO */
2593 ppc405_gpio_init(env, mmio, 0x700);
2594 /* CPU control */
2595 ppc405cr_cpc_init(env, clk_setup, sysclk);
2596 *offsetp = offset;
2597
2598 return env;
2599 }
2600
2601 /*****************************************************************************/
2602 /* PowerPC 405EP */
2603 /* CPU control */
2604 enum {
2605 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2606 PPC405EP_CPC0_BOOT = 0x0F1,
2607 PPC405EP_CPC0_EPCTL = 0x0F3,
2608 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2609 PPC405EP_CPC0_UCR = 0x0F5,
2610 PPC405EP_CPC0_SRR = 0x0F6,
2611 PPC405EP_CPC0_JTAGID = 0x0F7,
2612 PPC405EP_CPC0_PCI = 0x0F9,
2613 #if 0
2614 PPC405EP_CPC0_ER = xxx,
2615 PPC405EP_CPC0_FR = xxx,
2616 PPC405EP_CPC0_SR = xxx,
2617 #endif
2618 };
2619
2620 enum {
2621 PPC405EP_CPU_CLK = 0,
2622 PPC405EP_PLB_CLK = 1,
2623 PPC405EP_OPB_CLK = 2,
2624 PPC405EP_EBC_CLK = 3,
2625 PPC405EP_MAL_CLK = 4,
2626 PPC405EP_PCI_CLK = 5,
2627 PPC405EP_UART0_CLK = 6,
2628 PPC405EP_UART1_CLK = 7,
2629 PPC405EP_CLK_NB = 8,
2630 };
2631
2632 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2633 struct ppc405ep_cpc_t {
2634 uint32_t sysclk;
2635 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2636 uint32_t boot;
2637 uint32_t epctl;
2638 uint32_t pllmr[2];
2639 uint32_t ucr;
2640 uint32_t srr;
2641 uint32_t jtagid;
2642 uint32_t pci;
2643 /* Clock and power management */
2644 uint32_t er;
2645 uint32_t fr;
2646 uint32_t sr;
2647 };
2648
2649 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2650 {
2651 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2652 uint32_t UART0_clk, UART1_clk;
2653 uint64_t VCO_out, PLL_out;
2654 int M, D;
2655
2656 VCO_out = 0;
2657 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2658 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2659 // printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2660 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2661 // printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2662 VCO_out = cpc->sysclk * M * D;
2663 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2664 /* Error - unlock the PLL */
2665 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2666 #if 0
2667 cpc->pllmr[1] &= ~0x80000000;
2668 goto pll_bypass;
2669 #endif
2670 }
2671 PLL_out = VCO_out / D;
2672 /* Pretend the PLL is locked */
2673 cpc->boot |= 0x00000001;
2674 } else {
2675 #if 0
2676 pll_bypass:
2677 #endif
2678 PLL_out = cpc->sysclk;
2679 if (cpc->pllmr[1] & 0x40000000) {
2680 /* Pretend the PLL is not locked */
2681 cpc->boot &= ~0x00000001;
2682 }
2683 }
2684 /* Now, compute all other clocks */
2685 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2686 #ifdef DEBUG_CLOCKS
2687 // printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2688 #endif
2689 CPU_clk = PLL_out / D;
2690 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2691 #ifdef DEBUG_CLOCKS
2692 // printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2693 #endif
2694 PLB_clk = CPU_clk / D;
2695 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2696 #ifdef DEBUG_CLOCKS
2697 // printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2698 #endif
2699 OPB_clk = PLB_clk / D;
2700 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2701 #ifdef DEBUG_CLOCKS
2702 // printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2703 #endif
2704 EBC_clk = PLB_clk / D;
2705 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2706 #ifdef DEBUG_CLOCKS
2707 // printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2708 #endif
2709 MAL_clk = PLB_clk / D;
2710 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2711 #ifdef DEBUG_CLOCKS
2712 // printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D);
2713 #endif
2714 PCI_clk = PLB_clk / D;
2715 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2716 #ifdef DEBUG_CLOCKS
2717 // printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D);
2718 #endif
2719 UART0_clk = PLL_out / D;
2720 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2721 #ifdef DEBUG_CLOCKS
2722 // printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D);
2723 #endif
2724 UART1_clk = PLL_out / D;
2725 #ifdef DEBUG_CLOCKS
2726 printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64
2727 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2728 printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n",
2729 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2730 UART0_clk, UART1_clk);
2731 printf("CB %p opaque %p\n", cpc->clk_setup[PPC405EP_CPU_CLK].cb,
2732 cpc->clk_setup[PPC405EP_CPU_CLK].opaque);
2733 #endif
2734 /* Setup CPU clocks */
2735 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2736 /* Setup PLB clock */
2737 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2738 /* Setup OPB clock */
2739 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2740 /* Setup external clock */
2741 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2742 /* Setup MAL clock */
2743 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2744 /* Setup PCI clock */
2745 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2746 /* Setup UART0 clock */
2747 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2748 /* Setup UART1 clock */
2749 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2750 }
2751
2752 static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
2753 {
2754 ppc405ep_cpc_t *cpc;
2755 target_ulong ret;
2756
2757 cpc = opaque;
2758 switch (dcrn) {
2759 case PPC405EP_CPC0_BOOT:
2760 ret = cpc->boot;
2761 break;
2762 case PPC405EP_CPC0_EPCTL:
2763 ret = cpc->epctl;
2764 break;
2765 case PPC405EP_CPC0_PLLMR0:
2766 ret = cpc->pllmr[0];
2767 break;
2768 case PPC405EP_CPC0_PLLMR1:
2769 ret = cpc->pllmr[1];
2770 break;
2771 case PPC405EP_CPC0_UCR:
2772 ret = cpc->ucr;
2773 break;
2774 case PPC405EP_CPC0_SRR:
2775 ret = cpc->srr;
2776 break;
2777 case PPC405EP_CPC0_JTAGID:
2778 ret = cpc->jtagid;
2779 break;
2780 case PPC405EP_CPC0_PCI:
2781 ret = cpc->pci;
2782 break;
2783 default:
2784 /* Avoid gcc warning */
2785 ret = 0;
2786 break;
2787 }
2788
2789 return ret;
2790 }
2791
2792 static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
2793 {
2794 ppc405ep_cpc_t *cpc;
2795
2796 cpc = opaque;
2797 switch (dcrn) {
2798 case PPC405EP_CPC0_BOOT:
2799 /* Read-only register */
2800 break;
2801 case PPC405EP_CPC0_EPCTL:
2802 /* Don't care for now */
2803 cpc->epctl = val & 0xC00000F3;
2804 break;
2805 case PPC405EP_CPC0_PLLMR0:
2806 cpc->pllmr[0] = val & 0x00633333;
2807 ppc405ep_compute_clocks(cpc);
2808 break;
2809 case PPC405EP_CPC0_PLLMR1:
2810 cpc->pllmr[1] = val & 0xC0F73FFF;
2811 ppc405ep_compute_clocks(cpc);
2812 break;
2813 case PPC405EP_CPC0_UCR:
2814 /* UART control - don't care for now */
2815 cpc->ucr = val & 0x003F7F7F;
2816 break;
2817 case PPC405EP_CPC0_SRR:
2818 cpc->srr = val;
2819 break;
2820 case PPC405EP_CPC0_JTAGID:
2821 /* Read-only */
2822 break;
2823 case PPC405EP_CPC0_PCI:
2824 cpc->pci = val;
2825 break;
2826 }
2827 }
2828
2829 static void ppc405ep_cpc_reset (void *opaque)
2830 {
2831 ppc405ep_cpc_t *cpc = opaque;
2832
2833 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2834 cpc->epctl = 0x00000000;
2835 cpc->pllmr[0] = 0x00011010;
2836 cpc->pllmr[1] = 0x40000000;
2837 cpc->ucr = 0x00000000;
2838 cpc->srr = 0x00040000;
2839 cpc->pci = 0x00000000;
2840 cpc->er = 0x00000000;
2841 cpc->fr = 0x00000000;
2842 cpc->sr = 0x00000000;
2843 ppc405ep_compute_clocks(cpc);
2844 }
2845
2846 /* XXX: sysclk should be between 25 and 100 MHz */
2847 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
2848 uint32_t sysclk)
2849 {
2850 ppc405ep_cpc_t *cpc;
2851
2852 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
2853 if (cpc != NULL) {
2854 memcpy(cpc->clk_setup, clk_setup,
2855 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2856 cpc->jtagid = 0x20267049;
2857 cpc->sysclk = sysclk;
2858 ppc405ep_cpc_reset(cpc);
2859 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2860 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2861 &dcr_read_epcpc, &dcr_write_epcpc);
2862 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2863 &dcr_read_epcpc, &dcr_write_epcpc);
2864 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2865 &dcr_read_epcpc, &dcr_write_epcpc);
2866 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2867 &dcr_read_epcpc, &dcr_write_epcpc);
2868 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2869 &dcr_read_epcpc, &dcr_write_epcpc);
2870 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2871 &dcr_read_epcpc, &dcr_write_epcpc);
2872 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2873 &dcr_read_epcpc, &dcr_write_epcpc);
2874 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2875 &dcr_read_epcpc, &dcr_write_epcpc);
2876 #if 0
2877 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2878 &dcr_read_epcpc, &dcr_write_epcpc);
2879 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2880 &dcr_read_epcpc, &dcr_write_epcpc);
2881 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2882 &dcr_read_epcpc, &dcr_write_epcpc);
2883 #endif
2884 }
2885 }
2886
2887 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
2888 target_phys_addr_t ram_sizes[2],
2889 uint32_t sysclk, qemu_irq **picp,
2890 ram_addr_t *offsetp, int do_init)
2891 {
2892 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2893 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2894 CPUState *env;
2895 ppc4xx_mmio_t *mmio;
2896 qemu_irq *pic, *irqs;
2897 ram_addr_t offset;
2898 int i;
2899
2900 memset(clk_setup, 0, sizeof(clk_setup));
2901 /* init CPUs */
2902 env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2903 &tlb_clk_setup, sysclk);
2904 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2905 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2906 /* Internal devices init */
2907 /* Memory mapped devices registers */
2908 mmio = ppc4xx_mmio_init(env, 0xEF600000);
2909 /* PLB arbitrer */
2910 ppc4xx_plb_init(env);
2911 /* PLB to OPB bridge */
2912 ppc4xx_pob_init(env);
2913 /* OBP arbitrer */
2914 ppc4xx_opba_init(env, mmio, 0x600);
2915 /* Universal interrupt controller */
2916 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2917 irqs[PPCUIC_OUTPUT_INT] =
2918 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2919 irqs[PPCUIC_OUTPUT_CINT] =
2920 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2921 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2922 *picp = pic;
2923 /* SDRAM controller */
2924 ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init);
2925 offset = 0;
2926 for (i = 0; i < 2; i++)
2927 offset += ram_sizes[i];
2928 /* External bus controller */
2929 ppc405_ebc_init(env);
2930 /* DMA controller */
2931 dma_irqs[0] = pic[26];
2932 dma_irqs[1] = pic[25];
2933 dma_irqs[2] = pic[24];
2934 dma_irqs[3] = pic[23];
2935 ppc405_dma_init(env, dma_irqs);
2936 /* IIC controller */
2937 ppc405_i2c_init(env, mmio, 0x500, pic[29]);
2938 /* GPIO */
2939 ppc405_gpio_init(env, mmio, 0x700);
2940 /* Serial ports */
2941 if (serial_hds[0] != NULL) {
2942 ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
2943 }
2944 if (serial_hds[1] != NULL) {
2945 ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
2946 }
2947 /* OCM */
2948 ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]);
2949 offset += 4096;
2950 /* GPT */
2951 gpt_irqs[0] = pic[12];
2952 gpt_irqs[1] = pic[11];
2953 gpt_irqs[2] = pic[10];
2954 gpt_irqs[3] = pic[9];
2955 gpt_irqs[4] = pic[8];
2956 ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
2957 /* PCI */
2958 /* Uses pic[28], pic[15], pic[13] */
2959 /* MAL */
2960 mal_irqs[0] = pic[20];
2961 mal_irqs[1] = pic[19];
2962 mal_irqs[2] = pic[18];
2963 mal_irqs[3] = pic[17];
2964 ppc405_mal_init(env, mal_irqs);
2965 /* Ethernet */
2966 /* Uses pic[22], pic[16], pic[14] */
2967 /* CPU control */
2968 ppc405ep_cpc_init(env, clk_setup, sysclk);
2969 *offsetp = offset;
2970
2971 return env;
2972 }
Samsung s3c2440 and arm920t support for the mini2440 dev board