2 * Samsung S3C24xx series LCD controller.
4 * Copyright (c) 2007 OpenMoko, Inc.
5 * Author: Andrzej Zaborowski <andrew@openedhand.com>
7 * This code is licenced under the GNU GPL v2.
14 typedef void (*s3c_drawfn_t
)(uint32_t *, uint8_t *, const uint8_t *, int, int);
16 struct s3c_lcd_state_s
{
17 target_phys_addr_t base
;
20 s3c_drawfn_t
*line_fn
;
34 uint16_t raw_pal
[0x100];
43 uint32_t palette
[0x100];
51 static void s3c_lcd_update(struct s3c_lcd_state_s
*s
)
53 s
->intpnd
|= s
->srcpnd
& ~s
->intmsk
;
54 qemu_set_irq(s
->irq
, !!s
->intpnd
);
57 void s3c_lcd_reset(struct s3c_lcd_state_s
*s
)
65 s
->con
[0] = 0x00000000;
66 s
->con
[1] = 0x00000000;
67 s
->con
[2] = 0x00000000;
68 s
->con
[3] = 0x00000000;
69 s
->con
[4] = 0x00000000;
70 s
->saddr
[0] = 0x00000000;
71 s
->saddr
[1] = 0x00000000;
72 s
->saddr
[2] = 0x00000000;
76 s
->dithmode
= 0x00000;
85 #define S3C_LCDCON1 0x00 /* LCD Control register 1 */
86 #define S3C_LCDCON2 0x04 /* LCD Control register 2 */
87 #define S3C_LCDCON3 0x08 /* LCD Control register 3 */
88 #define S3C_LCDCON4 0x0c /* LCD Control register 4 */
89 #define S3C_LCDCON5 0x10 /* LCD Control register 5 */
90 #define S3C_LCDSADDR1 0x14 /* Framebuffer Start Address 1 register */
91 #define S3C_LCDSADDR2 0x18 /* Framebuffer Start Address 2 register */
92 #define S3C_LCDSADDR3 0x1c /* Framebuffer Start Address 3 register */
93 #define S3C_REDLUT 0x20 /* Red Lookup Table register */
94 #define S3C_GREENLUT 0x24 /* Green Lookup Table register */
95 #define S3C_BLUELUT 0x28 /* Blue Lookup Table register */
96 #define S3C_DITHMODE 0x4c /* Dithering Mode register */
97 #define S3C_TPAL 0x50 /* Temporary Palette register */
98 #define S3C_LCDINTPND 0x54 /* LCD Interrupt Pending register */
99 #define S3C_LCDSRCPND 0x58 /* LCD Interrupt Source Pending register */
100 #define S3C_LCDINTMSK 0x5c /* LCD Interrupt Mask register */
101 #define S3C_LPCSEL 0x60 /* LPC3600 Control register */
103 #define S3C_PALETTE 0x400 /* Palette IO start offset */
104 #define S3C_PALETTEEND 0x5ff /* Palette IO end offset */
106 static uint32_t s3c_lcd_read(void *opaque
, target_phys_addr_t addr
)
108 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
112 return s
->con
[0]; /* XXX Return random LINECNT? */
120 return s
->con
[4]; /* XXX Return random STATUS? */
145 case S3C_PALETTE
... S3C_PALETTEEND
:
146 /* XXX assuming 16bit access */
147 return s
->raw_pal
[(addr
- S3C_PALETTE
) >> 1];
149 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
155 static void s3c_lcd_write(void *opaque
, target_phys_addr_t addr
,
158 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
162 s
->con
[0] = value
& 0x0003ffff;
163 s
->enable
= value
& 1;
164 s
->bpp
= (value
>> 1) & 0xf;
177 s
->con
[3] = value
& 0xffff;
180 s
->con
[4] = value
& 0x1fff;
181 s
->frm565
= (value
>> 11) & 1;
182 s
->msb
= (value
>> 12) & 1;
188 s
->fb
= phys_ram_base
+
189 (((s
->saddr
[0] << 1) & 0x7ffffffe) - S3C_RAM_BASE
);
224 s
->intpnd
= value
& 3;
227 s
->srcpnd
= value
& 3;
230 s
->intmsk
= value
& 7;
234 s
->lpcsel
= (value
& 3) | 4;
236 printf("%s: attempt to enable LPC3600\n", __FUNCTION__
);
238 case S3C_PALETTE
... S3C_PALETTEEND
:
239 /* XXX assuming 16bit access */
240 s
->raw_pal
[(addr
- S3C_PALETTE
) >> 1] = value
;
243 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
247 static CPUReadMemoryFunc
*s3c_lcd_readfn
[] = {
253 static CPUWriteMemoryFunc
*s3c_lcd_writefn
[] = {
259 static inline void s3c_lcd_resize(struct s3c_lcd_state_s
*s
)
261 int new_width
, new_height
;
262 new_height
= ((s
->con
[1] >> 14) & 0x3ff) + 1;
263 new_width
= ((s
->con
[2] >> 8) & 0x7ff) + 1;
264 if (s
->width
!= new_width
|| s
->height
!= new_height
) {
265 s
->width
= new_width
;
266 s
->height
= new_height
;
267 // dpy_resize(s->ds, s->width, s->height);
273 uint32_t s3c_rgb_to_pixel8(unsigned int r
, unsigned int g
, unsigned b
)
275 return ((r
>> 5) << 5) | ((g
>> 5) << 2) | (b
>> 6);
279 uint32_t s3c_rgb_to_pixel15(unsigned int r
, unsigned int g
, unsigned b
)
281 return ((r
>> 3) << 10) | ((g
>> 3) << 5) | (b
>> 3);
285 uint32_t s3c_rgb_to_pixel16(unsigned int r
, unsigned int g
, unsigned b
)
287 return ((r
>> 3) << 11) | ((g
>> 2) << 5) | (b
>> 3);
291 uint32_t s3c_rgb_to_pixel24(unsigned int r
, unsigned int g
, unsigned b
)
293 return (r
<< 16) | (g
<< 8) | b
;
297 uint32_t s3c_rgb_to_pixel32(unsigned int r
, unsigned int g
, unsigned b
)
299 return (r
<< 16) | (g
<< 8) | b
;
302 static inline uint32_t s3c_rgb(struct s3c_lcd_state_s
*s
,
303 unsigned int r
, unsigned int g
, unsigned b
)
305 switch (ds_get_bits_per_pixel(s
->ds
)) {
307 return s3c_rgb_to_pixel32(r
<< 2, g
<< 2, b
<< 2);
309 return s3c_rgb_to_pixel15(r
<< 2, g
<< 2, b
<< 2);
311 return s3c_rgb_to_pixel16(r
<< 2, g
<< 2, b
<< 2);
313 return s3c_rgb_to_pixel24(r
<< 2, g
<< 2, b
<< 2);
315 return s3c_rgb_to_pixel32(r
<< 2, g
<< 2, b
<< 2);
317 fprintf(stderr
, "%s: Bad color depth\n", __FUNCTION__
);
322 static void s3c_lcd_palette_load(struct s3c_lcd_state_s
*s
)
329 s
->src_width
= s
->width
>> 3;
330 s
->fn
= s
->line_fn
[0];
335 s
->src_width
= s
->width
>> 2;
336 s
->fn
= s
->line_fn
[1];
341 s
->src_width
= s
->width
>> 1;
342 s
->fn
= s
->line_fn
[2];
347 s
->src_width
= s
->width
>> 0;
348 s
->fn
= s
->line_fn
[3];
351 s
->src_width
= (s
->width
* 3) >> 1;
352 s
->fn
= s
->line_fn
[4];
355 s
->src_width
= s
->width
<< 1;
357 s
->fn
= s
->line_fn
[5];
359 s
->fn
= s
->line_fn
[6];
362 s
->src_width
= s
->width
<< 2;
363 s
->fn
= s
->line_fn
[7];
369 for (i
= 0; i
< n
; i
++)
371 s
->palette
[i
] = s3c_rgb(s
,
372 (s
->raw_pal
[i
] >> 10) & 0x3e,
373 (s
->raw_pal
[i
] >> 5) & 0x3f,
374 (s
->raw_pal
[i
] << 1) & 0x3e);
376 s
->palette
[i
] = s3c_rgb(s
,
377 ((s
->raw_pal
[i
] >> 10) & 0x3e) | (s
->raw_pal
[i
] & 1),
378 ((s
->raw_pal
[i
] >> 6) & 0x3e) | (s
->raw_pal
[i
] & 1),
379 s
->raw_pal
[i
] & 0x3f);
381 for (i
= 0; i
< n
; i
++)
383 s
->palette
[i
] = s3c_rgb(s
,
384 ((s
->r
>> (i
* 4)) & 0xf) << 2,
385 ((s
->g
>> (i
* 4)) & 0xf) << 2,
386 ((s
->b
>> (i
* 4)) & 0xf) << 2);
388 s
->palette
[i
] = s3c_rgb(s
,
389 ((s
->r
>> (((i
>> 5) & 7) * 4)) & 0xf) << 2,
390 ((s
->g
>> (((i
>> 2) & 7) * 4)) & 0xf) << 2,
391 ((s
->b
>> ((i
& 3) * 4)) & 0xf) << 2);
395 static void s3c_update_display(void *opaque
)
397 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
398 int y
, src_width
, dest_width
, dirty
[2], miny
, maxy
;
399 ram_addr_t x
, addr
, new_addr
, start
, end
;
401 if (!s
->enable
|| !s
->dest_width
)
406 if (s
->invalidatep
) {
407 s3c_lcd_palette_load(s
);
412 src_width
= s
->src_width
;
414 dest
= ds_get_data(s
->ds
);
415 dest_width
= s
->width
* s
->dest_width
;
417 addr
= (ram_addr_t
) (s
->fb
- (void *) phys_ram_base
);
418 start
= addr
+ s
->height
* src_width
;
420 dirty
[0] = dirty
[1] = cpu_physical_memory_get_dirty(start
, VGA_DIRTY_FLAG
);
423 for (y
= 0; y
< s
->height
; y
++) {
424 new_addr
= addr
+ src_width
;
425 for (x
= addr
+ TARGET_PAGE_SIZE
; x
< new_addr
;
426 x
+= TARGET_PAGE_SIZE
) {
427 dirty
[1] = cpu_physical_memory_get_dirty(x
, VGA_DIRTY_FLAG
);
428 dirty
[0] |= dirty
[1];
430 if (dirty
[0] || s
->invalidate
) {
431 s
->fn(s
->palette
, dest
, src
, s
->width
, s
->dest_width
);
447 cpu_physical_memory_reset_dirty(start
, end
, VGA_DIRTY_FLAG
);
448 s
->srcpnd
|= (1 << 1); /* INT_FrSyn */
450 dpy_update(s
->ds
, 0, miny
, s
->width
, maxy
);
453 static void s3c_invalidate_display(void *opaque
)
455 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
459 static void s3c_screen_dump(void *opaque
, const char *filename
)
465 #include "s3c24xx_template.h"
467 #include "s3c24xx_template.h"
469 #include "s3c24xx_template.h"
471 #include "s3c24xx_template.h"
473 #include "s3c24xx_template.h"
475 static void s3c_lcd_save(QEMUFile
*f
, void *opaque
)
477 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
479 for (i
= 0; i
< 5; i
++)
480 qemu_put_be32s(f
, &s
->con
[i
]);
481 for (i
= 0; i
< 3; i
++)
482 qemu_put_be32s(f
, &s
->saddr
[i
]);
483 qemu_put_be32s(f
, &s
->r
);
484 qemu_put_be32s(f
, &s
->g
);
485 qemu_put_be16s(f
, &s
->b
);
486 qemu_put_be32s(f
, &s
->dithmode
);
487 qemu_put_be32s(f
, &s
->tpal
);
488 qemu_put_8s(f
, &s
->intpnd
);
489 qemu_put_8s(f
, &s
->srcpnd
);
490 qemu_put_8s(f
, &s
->intmsk
);
491 qemu_put_8s(f
, &s
->lpcsel
);
492 for (i
= 0; i
< 0x100; i
++)
493 qemu_put_be16s(f
, &s
->raw_pal
[i
]);
496 static int s3c_lcd_load(QEMUFile
*f
, void *opaque
, int version_id
)
498 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
500 for (i
= 0; i
< 5; i
++)
501 qemu_get_be32s(f
, &s
->con
[i
]);
502 for (i
= 0; i
< 3; i
++)
503 qemu_get_be32s(f
, &s
->saddr
[i
]);
504 qemu_get_be32s(f
, &s
->r
);
505 qemu_get_be32s(f
, &s
->g
);
506 qemu_get_be16s(f
, &s
->b
);
507 qemu_get_be32s(f
, &s
->dithmode
);
508 qemu_get_be32s(f
, &s
->tpal
);
509 qemu_get_8s(f
, &s
->intpnd
);
510 qemu_get_8s(f
, &s
->srcpnd
);
511 qemu_get_8s(f
, &s
->intmsk
);
512 qemu_get_8s(f
, &s
->lpcsel
);
518 s
->bpp
= (s
->con
[0] >> 1) & 0xf;
519 s
->enable
= s
->con
[0] & 1;
520 s
->msb
= (s
->con
[4] >> 12) & 1;
521 s
->frm565
= (s
->con
[4] >> 11) & 1;
522 s
->fb
= phys_ram_base
+ (((s
->saddr
[0] << 1) & 0x7ffffffe) - S3C_RAM_BASE
);
524 for (i
= 0; i
< 0x100; i
++)
525 qemu_get_be16s(f
, &s
->raw_pal
[i
]);
530 struct s3c_lcd_state_s
*s3c_lcd_init(target_phys_addr_t base
, DisplayState
*ds
,
534 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*)
535 qemu_mallocz(sizeof(struct s3c_lcd_state_s
));
543 s
->ds
= graphic_console_init(ds
, s3c_update_display
,
544 s3c_invalidate_display
, s3c_screen_dump
, s
);
546 iomemtype
= cpu_register_io_memory(0, s3c_lcd_readfn
,
548 cpu_register_physical_memory(s
->base
, 0xffffff, iomemtype
);
550 register_savevm("s3c24xx_lcd", 0, 0, s3c_lcd_save
, s3c_lcd_load
, s
);
552 switch (ds_get_bits_per_pixel(s
->ds
)) {
557 s
->line_fn
= s3c_draw_fn_8
;
561 s
->line_fn
= s3c_draw_fn_15
;
565 s
->line_fn
= s3c_draw_fn_16
;
569 s
->line_fn
= s3c_draw_fn_24
;
573 s
->line_fn
= s3c_draw_fn_32
;
577 fprintf(stderr
, "%s: Bad color depth\n", __FUNCTION__
);