hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "fdc.h"
  27 #include "pci.h"
  28 #include "block.h"
  29 #include "sysemu.h"
  30 #include "audio/audio.h"
  31 #include "net.h"
  32 #include "smbus.h"
  33 #include "boards.h"
  34 #include "monitor.h"
  35 #include "fw_cfg.h"
  36 #include "virtio-blk.h"
  37 #include "virtio-balloon.h"
  38 #include "virtio-console.h"
  39 #include "hpet_emul.h"
  40 #include "watchdog.h"
  41 #include "smbios.h"
  42
  43 /* output Bochs bios info messages */
  44 //#define DEBUG_BIOS
  45
  46 #define BIOS_FILENAME "bios.bin"
  47 #define VGABIOS_FILENAME "vgabios.bin"
  48 #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
  49
  50 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  51
  52 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  53 #define ACPI_DATA_SIZE       0x10000
  54 #define BIOS_CFG_IOPORT 0x510
  55 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  56 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  57
  58 #define MAX_IDE_BUS 2
  59
  60 static fdctrl_t *floppy_controller;
  61 static RTCState *rtc_state;
  62 static PITState *pit;
  63 static IOAPICState *ioapic;
  64 static PCIDevice *i440fx_state;
  65
  66 typedef struct rom_reset_data {
  67     uint8_t *data;
  68     target_phys_addr_t addr;
  69     unsigned size;
  70 } RomResetData;
  71
  72 static void option_rom_reset(void *_rrd)
  73 {
  74     RomResetData *rrd = _rrd;
  75
  76     cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
  77 }
  78
  79 static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
  80 {
  81     RomResetData *rrd = qemu_malloc(sizeof *rrd);
  82
  83     rrd->data = qemu_malloc(size);
  84     cpu_physical_memory_read(addr, rrd->data, size);
  85     rrd->addr = addr;
  86     rrd->size = size;
  87     qemu_register_reset(option_rom_reset, rrd);
  88 }
  89
  90 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
  91 {
  92 }
  93
  94 /* MSDOS compatibility mode FPU exception support */
  95 static qemu_irq ferr_irq;
  96 /* XXX: add IGNNE support */
  97 void cpu_set_ferr(CPUX86State *s)
  98 {
  99     qemu_irq_raise(ferr_irq);
 100 }
 101
 102 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 103 {
 104     qemu_irq_lower(ferr_irq);
 105 }
 106
 107 /* TSC handling */
 108 uint64_t cpu_get_tsc(CPUX86State *env)
 109 {
 110     /* Note: when using kqemu, it is more logical to return the host TSC
 111        because kqemu does not trap the RDTSC instruction for
 112        performance reasons */
 113 #ifdef CONFIG_KQEMU
 114     if (env->kqemu_enabled) {
 115         return cpu_get_real_ticks();
 116     } else
 117 #endif
 118     {
 119         return cpu_get_ticks();
 120     }
 121 }
 122
 123 /* SMM support */
 124 void cpu_smm_update(CPUState *env)
 125 {
 126     if (i440fx_state && env == first_cpu)
 127         i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
 128 }
 129
 130
 131 /* IRQ handling */
 132 int cpu_get_pic_interrupt(CPUState *env)
 133 {
 134     int intno;
 135
 136     intno = apic_get_interrupt(env);
 137     if (intno >= 0) {
 138         /* set irq request if a PIC irq is still pending */
 139         /* XXX: improve that */
 140         pic_update_irq(isa_pic);
 141         return intno;
 142     }
 143     /* read the irq from the PIC */
 144     if (!apic_accept_pic_intr(env))
 145         return -1;
 146
 147     intno = pic_read_irq(isa_pic);
 148     return intno;
 149 }
 150
 151 static void pic_irq_request(void *opaque, int irq, int level)
 152 {
 153     CPUState *env = first_cpu;
 154
 155     if (env->apic_state) {
 156         while (env) {
 157             if (apic_accept_pic_intr(env))
 158                 apic_deliver_pic_intr(env, level);
 159             env = env->next_cpu;
 160         }
 161     } else {
 162         if (level)
 163             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 164         else
 165             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 166     }
 167 }
 168
 169 /* PC cmos mappings */
 170
 171 #define REG_EQUIPMENT_BYTE          0x14
 172
 173 static int cmos_get_fd_drive_type(int fd0)
 174 {
 175     int val;
 176
 177     switch (fd0) {
 178     case 0:
 179         /* 1.44 Mb 3"5 drive */
 180         val = 4;
 181         break;
 182     case 1:
 183         /* 2.88 Mb 3"5 drive */
 184         val = 5;
 185         break;
 186     case 2:
 187         /* 1.2 Mb 5"5 drive */
 188         val = 2;
 189         break;
 190     default:
 191         val = 0;
 192         break;
 193     }
 194     return val;
 195 }
 196
 197 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 198 {
 199     RTCState *s = rtc_state;
 200     int cylinders, heads, sectors;
 201     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 202     rtc_set_memory(s, type_ofs, 47);
 203     rtc_set_memory(s, info_ofs, cylinders);
 204     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 205     rtc_set_memory(s, info_ofs + 2, heads);
 206     rtc_set_memory(s, info_ofs + 3, 0xff);
 207     rtc_set_memory(s, info_ofs + 4, 0xff);
 208     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 209     rtc_set_memory(s, info_ofs + 6, cylinders);
 210     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 211     rtc_set_memory(s, info_ofs + 8, sectors);
 212 }
 213
 214 /* convert boot_device letter to something recognizable by the bios */
 215 static int boot_device2nibble(char boot_device)
 216 {
 217     switch(boot_device) {
 218     case 'a':
 219     case 'b':
 220         return 0x01; /* floppy boot */
 221     case 'c':
 222         return 0x02; /* hard drive boot */
 223     case 'd':
 224         return 0x03; /* CD-ROM boot */
 225     case 'n':
 226         return 0x04; /* Network boot */
 227     }
 228     return 0;
 229 }
 230
 231 /* copy/pasted from cmos_init, should be made a general function
 232  and used there as well */
 233 static int pc_boot_set(void *opaque, const char *boot_device)
 234 {
 235     Monitor *mon = cur_mon;
 236 #define PC_MAX_BOOT_DEVICES 3
 237     RTCState *s = (RTCState *)opaque;
 238     int nbds, bds[3] = { 0, };
 239     int i;
 240
 241     nbds = strlen(boot_device);
 242     if (nbds > PC_MAX_BOOT_DEVICES) {
 243         monitor_printf(mon, "Too many boot devices for PC\n");
 244         return(1);
 245     }
 246     for (i = 0; i < nbds; i++) {
 247         bds[i] = boot_device2nibble(boot_device[i]);
 248         if (bds[i] == 0) {
 249             monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
 250                            boot_device[i]);
 251             return(1);
 252         }
 253     }
 254     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 255     rtc_set_memory(s, 0x38, (bds[2] << 4));
 256     return(0);
 257 }
 258
 259 /* hd_table must contain 4 block drivers */
 260 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 261                       const char *boot_device, BlockDriverState **hd_table)
 262 {
 263     RTCState *s = rtc_state;
 264     int nbds, bds[3] = { 0, };
 265     int val;
 266     int fd0, fd1, nb;
 267     int i;
 268
 269     /* various important CMOS locations needed by PC/Bochs bios */
 270
 271     /* memory size */
 272     val = 640; /* base memory in K */
 273     rtc_set_memory(s, 0x15, val);
 274     rtc_set_memory(s, 0x16, val >> 8);
 275
 276     val = (ram_size / 1024) - 1024;
 277     if (val > 65535)
 278         val = 65535;
 279     rtc_set_memory(s, 0x17, val);
 280     rtc_set_memory(s, 0x18, val >> 8);
 281     rtc_set_memory(s, 0x30, val);
 282     rtc_set_memory(s, 0x31, val >> 8);
 283
 284     if (above_4g_mem_size) {
 285         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 286         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 287         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 288     }
 289
 290     if (ram_size > (16 * 1024 * 1024))
 291         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 292     else
 293         val = 0;
 294     if (val > 65535)
 295         val = 65535;
 296     rtc_set_memory(s, 0x34, val);
 297     rtc_set_memory(s, 0x35, val >> 8);
 298
 299     /* set the number of CPU */
 300     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 301
 302     /* set boot devices, and disable floppy signature check if requested */
 303 #define PC_MAX_BOOT_DEVICES 3
 304     nbds = strlen(boot_device);
 305     if (nbds > PC_MAX_BOOT_DEVICES) {
 306         fprintf(stderr, "Too many boot devices for PC\n");
 307         exit(1);
 308     }
 309     for (i = 0; i < nbds; i++) {
 310         bds[i] = boot_device2nibble(boot_device[i]);
 311         if (bds[i] == 0) {
 312             fprintf(stderr, "Invalid boot device for PC: '%c'\n",
 313                     boot_device[i]);
 314             exit(1);
 315         }
 316     }
 317     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 318     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
 319
 320     /* floppy type */
 321
 322     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 323     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 324
 325     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 326     rtc_set_memory(s, 0x10, val);
 327
 328     val = 0;
 329     nb = 0;
 330     if (fd0 < 3)
 331         nb++;
 332     if (fd1 < 3)
 333         nb++;
 334     switch (nb) {
 335     case 0:
 336         break;
 337     case 1:
 338         val |= 0x01; /* 1 drive, ready for boot */
 339         break;
 340     case 2:
 341         val |= 0x41; /* 2 drives, ready for boot */
 342         break;
 343     }
 344     val |= 0x02; /* FPU is there */
 345     val |= 0x04; /* PS/2 mouse installed */
 346     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 347
 348     /* hard drives */
 349
 350     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 351     if (hd_table[0])
 352         cmos_init_hd(0x19, 0x1b, hd_table[0]);
 353     if (hd_table[1])
 354         cmos_init_hd(0x1a, 0x24, hd_table[1]);
 355
 356     val = 0;
 357     for (i = 0; i < 4; i++) {
 358         if (hd_table[i]) {
 359             int cylinders, heads, sectors, translation;
 360             /* NOTE: bdrv_get_geometry_hint() returns the physical
 361                 geometry.  It is always such that: 1 <= sects <= 63, 1
 362                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 363                 geometry can be different if a translation is done. */
 364             translation = bdrv_get_translation_hint(hd_table[i]);
 365             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 366                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 367                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 368                     /* No translation. */
 369                     translation = 0;
 370                 } else {
 371                     /* LBA translation. */
 372                     translation = 1;
 373                 }
 374             } else {
 375                 translation--;
 376             }
 377             val |= translation << (i * 2);
 378         }
 379     }
 380     rtc_set_memory(s, 0x39, val);
 381 }
 382
 383 void ioport_set_a20(int enable)
 384 {
 385     /* XXX: send to all CPUs ? */
 386     cpu_x86_set_a20(first_cpu, enable);
 387 }
 388
 389 int ioport_get_a20(void)
 390 {
 391     return ((first_cpu->a20_mask >> 20) & 1);
 392 }
 393
 394 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
 395 {
 396     ioport_set_a20((val >> 1) & 1);
 397     /* XXX: bit 0 is fast reset */
 398 }
 399
 400 static uint32_t ioport92_read(void *opaque, uint32_t addr)
 401 {
 402     return ioport_get_a20() << 1;
 403 }
 404
 405 /***********************************************************/
 406 /* Bochs BIOS debug ports */
 407
 408 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 409 {
 410     static const char shutdown_str[8] = "Shutdown";
 411     static int shutdown_index = 0;
 412
 413     switch(addr) {
 414         /* Bochs BIOS messages */
 415     case 0x400:
 416     case 0x401:
 417         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 418         exit(1);
 419     case 0x402:
 420     case 0x403:
 421 #ifdef DEBUG_BIOS
 422         fprintf(stderr, "%c", val);
 423 #endif
 424         break;
 425     case 0x8900:
 426         /* same as Bochs power off */
 427         if (val == shutdown_str[shutdown_index]) {
 428             shutdown_index++;
 429             if (shutdown_index == 8) {
 430                 shutdown_index = 0;
 431                 qemu_system_shutdown_request();
 432             }
 433         } else {
 434             shutdown_index = 0;
 435         }
 436         break;
 437
 438         /* LGPL'ed VGA BIOS messages */
 439     case 0x501:
 440     case 0x502:
 441         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 442         exit(1);
 443     case 0x500:
 444     case 0x503:
 445 #ifdef DEBUG_BIOS
 446         fprintf(stderr, "%c", val);
 447 #endif
 448         break;
 449     }
 450 }
 451
 452 extern uint64_t node_cpumask[MAX_NODES];
 453
 454 static void bochs_bios_init(void)
 455 {
 456     void *fw_cfg;
 457     uint8_t *smbios_table;
 458     size_t smbios_len;
 459     uint64_t *numa_fw_cfg;
 460     int i, j;
 461
 462     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 463     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 464     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 465     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 466     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 467
 468     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 469     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 470     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 471     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 472
 473     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 474     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 475     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 476     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 477                      acpi_tables_len);
 478
 479     smbios_table = smbios_get_table(&smbios_len);
 480     if (smbios_table)
 481         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 482                          smbios_table, smbios_len);
 483
 484     /* allocate memory for the NUMA channel: one (64bit) word for the number
 485      * of nodes, one word for each VCPU->node and one word for each node to
 486      * hold the amount of memory.
 487      */
 488     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 489     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 490     for (i = 0; i < smp_cpus; i++) {
 491         for (j = 0; j < nb_numa_nodes; j++) {
 492             if (node_cpumask[j] & (1 << i)) {
 493                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 494                 break;
 495             }
 496         }
 497     }
 498     for (i = 0; i < nb_numa_nodes; i++) {
 499         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 500     }
 501     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 502                      (1 + smp_cpus + nb_numa_nodes) * 8);
 503 }
 504
 505 /* Generate an initial boot sector which sets state and jump to
 506    a specified vector */
 507 static void generate_bootsect(target_phys_addr_t option_rom,
 508                               uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
 509 {
 510     uint8_t rom[512], *p, *reloc;
 511     uint8_t sum;
 512     int i;
 513
 514     memset(rom, 0, sizeof(rom));
 515
 516     p = rom;
 517     /* Make sure we have an option rom signature */
 518     *p++ = 0x55;
 519     *p++ = 0xaa;
 520
 521     /* ROM size in sectors*/
 522     *p++ = 1;
 523
 524     /* Hook int19 */
 525
 526     *p++ = 0x50;                /* push ax */
 527     *p++ = 0x1e;                /* push ds */
 528     *p++ = 0x31; *p++ = 0xc0;   /* xor ax, ax */
 529     *p++ = 0x8e; *p++ = 0xd8;   /* mov ax, ds */
 530
 531     *p++ = 0xc7; *p++ = 0x06;   /* movvw _start,0x64 */
 532     *p++ = 0x64; *p++ = 0x00;
 533     reloc = p;
 534     *p++ = 0x00; *p++ = 0x00;
 535
 536     *p++ = 0x8c; *p++ = 0x0e;   /* mov cs,0x66 */
 537     *p++ = 0x66; *p++ = 0x00;
 538
 539     *p++ = 0x1f;                /* pop ds */
 540     *p++ = 0x58;                /* pop ax */
 541     *p++ = 0xcb;                /* lret */
 542
 543     /* Actual code */
 544     *reloc = (p - rom);
 545
 546     *p++ = 0xfa;                /* CLI */
 547     *p++ = 0xfc;                /* CLD */
 548
 549     for (i = 0; i < 6; i++) {
 550         if (i == 1)             /* Skip CS */
 551             continue;
 552
 553         *p++ = 0xb8;            /* MOV AX,imm16 */
 554         *p++ = segs[i];
 555         *p++ = segs[i] >> 8;
 556         *p++ = 0x8e;            /* MOV <seg>,AX */
 557         *p++ = 0xc0 + (i << 3);
 558     }
 559
 560     for (i = 0; i < 8; i++) {
 561         *p++ = 0x66;            /* 32-bit operand size */
 562         *p++ = 0xb8 + i;        /* MOV <reg>,imm32 */
 563         *p++ = gpr[i];
 564         *p++ = gpr[i] >> 8;
 565         *p++ = gpr[i] >> 16;
 566         *p++ = gpr[i] >> 24;
 567     }
 568
 569     *p++ = 0xea;                /* JMP FAR */
 570     *p++ = ip;                  /* IP */
 571     *p++ = ip >> 8;
 572     *p++ = segs[1];             /* CS */
 573     *p++ = segs[1] >> 8;
 574
 575     /* sign rom */
 576     sum = 0;
 577     for (i = 0; i < (sizeof(rom) - 1); i++)
 578         sum += rom[i];
 579     rom[sizeof(rom) - 1] = -sum;
 580
 581     cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
 582     option_rom_setup_reset(option_rom, sizeof (rom));
 583 }
 584
 585 static long get_file_size(FILE *f)
 586 {
 587     long where, size;
 588
 589     /* XXX: on Unix systems, using fstat() probably makes more sense */
 590
 591     where = ftell(f);
 592     fseek(f, 0, SEEK_END);
 593     size = ftell(f);
 594     fseek(f, where, SEEK_SET);
 595
 596     return size;
 597 }
 598
 599 static void load_linux(target_phys_addr_t option_rom,
 600                        const char *kernel_filename,
 601                        const char *initrd_filename,
 602                        const char *kernel_cmdline)
 603 {
 604     uint16_t protocol;
 605     uint32_t gpr[8];
 606     uint16_t seg[6];
 607     uint16_t real_seg;
 608     int setup_size, kernel_size, initrd_size, cmdline_size;
 609     uint32_t initrd_max;
 610     uint8_t header[1024];
 611     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr;
 612     FILE *f, *fi;
 613
 614     /* Align to 16 bytes as a paranoia measure */
 615     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 616
 617     /* load the kernel header */
 618     f = fopen(kernel_filename, "rb");
 619     if (!f || !(kernel_size = get_file_size(f)) ||
 620         fread(header, 1, 1024, f) != 1024) {
 621         fprintf(stderr, "qemu: could not load kernel '%s'\n",
 622                 kernel_filename);
 623         exit(1);
 624     }
 625
 626     /* kernel protocol version */
 627 #if 0
 628     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 629 #endif
 630     if (ldl_p(header+0x202) == 0x53726448)
 631         protocol = lduw_p(header+0x206);
 632     else
 633         protocol = 0;
 634
 635     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 636         /* Low kernel */
 637         real_addr    = 0x90000;
 638         cmdline_addr = 0x9a000 - cmdline_size;
 639         prot_addr    = 0x10000;
 640     } else if (protocol < 0x202) {
 641         /* High but ancient kernel */
 642         real_addr    = 0x90000;
 643         cmdline_addr = 0x9a000 - cmdline_size;
 644         prot_addr    = 0x100000;
 645     } else {
 646         /* High and recent kernel */
 647         real_addr    = 0x10000;
 648         cmdline_addr = 0x20000;
 649         prot_addr    = 0x100000;
 650     }
 651
 652 #if 0
 653     fprintf(stderr,
 654             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 655             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 656             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 657             real_addr,
 658             cmdline_addr,
 659             prot_addr);
 660 #endif
 661
 662     /* highest address for loading the initrd */
 663     if (protocol >= 0x203)
 664         initrd_max = ldl_p(header+0x22c);
 665     else
 666         initrd_max = 0x37ffffff;
 667
 668     if (initrd_max >= ram_size-ACPI_DATA_SIZE)
 669         initrd_max = ram_size-ACPI_DATA_SIZE-1;
 670
 671     /* kernel command line */
 672     pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
 673
 674     if (protocol >= 0x202) {
 675         stl_p(header+0x228, cmdline_addr);
 676     } else {
 677         stw_p(header+0x20, 0xA33F);
 678         stw_p(header+0x22, cmdline_addr-real_addr);
 679     }
 680
 681     /* loader type */
 682     /* High nybble = B reserved for Qemu; low nybble is revision number.
 683        If this code is substantially changed, you may want to consider
 684        incrementing the revision. */
 685     if (protocol >= 0x200)
 686         header[0x210] = 0xB0;
 687
 688     /* heap */
 689     if (protocol >= 0x201) {
 690         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 691         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 692     }
 693
 694     /* load initrd */
 695     if (initrd_filename) {
 696         if (protocol < 0x200) {
 697             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 698             exit(1);
 699         }
 700
 701         fi = fopen(initrd_filename, "rb");
 702         if (!fi) {
 703             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 704                     initrd_filename);
 705             exit(1);
 706         }
 707
 708         initrd_size = get_file_size(fi);
 709         initrd_addr = (initrd_max-initrd_size) & ~4095;
 710
 711         fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx
 712                 "\n", initrd_size, initrd_addr);
 713
 714         if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
 715             fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
 716                     initrd_filename);
 717             exit(1);
 718         }
 719         fclose(fi);
 720
 721         stl_p(header+0x218, initrd_addr);
 722         stl_p(header+0x21c, initrd_size);
 723     }
 724
 725     /* store the finalized header and load the rest of the kernel */
 726     cpu_physical_memory_write(real_addr, header, 1024);
 727
 728     setup_size = header[0x1f1];
 729     if (setup_size == 0)
 730         setup_size = 4;
 731
 732     setup_size = (setup_size+1)*512;
 733     kernel_size -= setup_size;  /* Size of protected-mode code */
 734
 735     if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) ||
 736         !fread_targphys_ok(prot_addr, kernel_size, f)) {
 737         fprintf(stderr, "qemu: read error on kernel '%s'\n",
 738                 kernel_filename);
 739         exit(1);
 740     }
 741     fclose(f);
 742
 743     /* generate bootsector to set up the initial register state */
 744     real_seg = real_addr >> 4;
 745     seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
 746     seg[1] = real_seg+0x20;     /* CS */
 747     memset(gpr, 0, sizeof gpr);
 748     gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */
 749
 750     option_rom_setup_reset(real_addr, setup_size);
 751     option_rom_setup_reset(prot_addr, kernel_size);
 752     option_rom_setup_reset(cmdline_addr, cmdline_size);
 753     if (initrd_filename)
 754         option_rom_setup_reset(initrd_addr, initrd_size);
 755
 756     generate_bootsect(option_rom, gpr, seg, 0);
 757 }
 758
 759 static void main_cpu_reset(void *opaque)
 760 {
 761     CPUState *env = opaque;
 762     cpu_reset(env);
 763 }
 764
 765 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 766 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 767 static const int ide_irq[2] = { 14, 15 };
 768
 769 #define NE2000_NB_MAX 6
 770
 771 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
 772 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 773
 774 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 775 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 776
 777 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 778 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 779
 780 #ifdef HAS_AUDIO
 781 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 782 {
 783     struct soundhw *c;
 784     int audio_enabled = 0;
 785
 786     for (c = soundhw; !audio_enabled && c->name; ++c) {
 787         audio_enabled = c->enabled;
 788     }
 789
 790     if (audio_enabled) {
 791         for (c = soundhw; c->name; ++c) {
 792             if (c->enabled) {
 793                 if (c->isa) {
 794                     c->init.init_isa(pic);
 795                 } else {
 796                     if (pci_bus) {
 797                         c->init.init_pci(pci_bus);
 798                     }
 799                 }
 800             }
 801         }
 802     }
 803 }
 804 #endif
 805
 806 static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
 807 {
 808     static int nb_ne2k = 0;
 809
 810     if (nb_ne2k == NE2000_NB_MAX)
 811         return;
 812     isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
 813     nb_ne2k++;
 814 }
 815
 816 static int load_option_rom(const char *oprom, target_phys_addr_t start,
 817                            target_phys_addr_t end)
 818 {
 819         int size;
 820
 821         size = get_image_size(oprom);
 822         if (size > 0 && start + size > end) {
 823             fprintf(stderr, "Not enough space to load option rom '%s'\n",
 824                     oprom);
 825             exit(1);
 826         }
 827         size = load_image_targphys(oprom, start, end - start);
 828         if (size < 0) {
 829             fprintf(stderr, "Could not load option rom '%s'\n", oprom);
 830             exit(1);
 831         }
 832         /* Round up optiom rom size to the next 2k boundary */
 833         size = (size + 2047) & ~2047;
 834         option_rom_setup_reset(start, size);
 835         return size;
 836 }
 837
 838 /* PC hardware initialisation */
 839 static void pc_init1(ram_addr_t ram_size,
 840                      const char *boot_device,
 841                      const char *kernel_filename, const char *kernel_cmdline,
 842                      const char *initrd_filename,
 843                      int pci_enabled, const char *cpu_model)
 844 {
 845     char buf[1024];
 846     int ret, linux_boot, i;
 847     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 848     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 849     int bios_size, isa_bios_size, oprom_area_size;
 850     PCIBus *pci_bus;
 851     int piix3_devfn = -1;
 852     CPUState *env;
 853     qemu_irq *cpu_irq;
 854     qemu_irq *i8259;
 855     int index;
 856     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 857     BlockDriverState *fd[MAX_FD];
 858     int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
 859
 860     if (ram_size >= 0xe0000000 ) {
 861         above_4g_mem_size = ram_size - 0xe0000000;
 862         below_4g_mem_size = 0xe0000000;
 863     } else {
 864         below_4g_mem_size = ram_size;
 865     }
 866
 867     linux_boot = (kernel_filename != NULL);
 868
 869     /* init CPUs */
 870     if (cpu_model == NULL) {
 871 #ifdef TARGET_X86_64
 872         cpu_model = "qemu64";
 873 #else
 874         cpu_model = "qemu32";
 875 #endif
 876     }
 877
 878     for(i = 0; i < smp_cpus; i++) {
 879         env = cpu_init(cpu_model);
 880         if (!env) {
 881             fprintf(stderr, "Unable to find x86 CPU definition\n");
 882             exit(1);
 883         }
 884         if (i != 0)
 885             env->halted = 1;
 886         if (smp_cpus > 1) {
 887             /* XXX: enable it in all cases */
 888             env->cpuid_features |= CPUID_APIC;
 889         }
 890         qemu_register_reset(main_cpu_reset, env);
 891         if (pci_enabled) {
 892             apic_init(env);
 893         }
 894     }
 895
 896     vmport_init();
 897
 898     /* allocate RAM */
 899     ram_addr = qemu_ram_alloc(0xa0000);
 900     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 901
 902     /* Allocate, even though we won't register, so we don't break the
 903      * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
 904      * and some bios areas, which will be registered later
 905      */
 906     ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
 907     ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
 908     cpu_register_physical_memory(0x100000,
 909                  below_4g_mem_size - 0x100000,
 910                  ram_addr);
 911
 912     /* above 4giga memory allocation */
 913     if (above_4g_mem_size > 0) {
 914         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 915         cpu_register_physical_memory(0x100000000ULL,
 916                                      above_4g_mem_size,
 917                                      ram_addr);
 918     }
 919
 920
 921     /* BIOS load */
 922     if (bios_name == NULL)
 923         bios_name = BIOS_FILENAME;
 924     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 925     bios_size = get_image_size(buf);
 926     if (bios_size <= 0 ||
 927         (bios_size % 65536) != 0) {
 928         goto bios_error;
 929     }
 930     bios_offset = qemu_ram_alloc(bios_size);
 931     ret = load_image(buf, qemu_get_ram_ptr(bios_offset));
 932     if (ret != bios_size) {
 933     bios_error:
 934         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
 935         exit(1);
 936     }
 937     /* map the last 128KB of the BIOS in ISA space */
 938     isa_bios_size = bios_size;
 939     if (isa_bios_size > (128 * 1024))
 940         isa_bios_size = 128 * 1024;
 941     cpu_register_physical_memory(0x100000 - isa_bios_size,
 942                                  isa_bios_size,
 943                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 944
 945
 946
 947     option_rom_offset = qemu_ram_alloc(0x20000);
 948     oprom_area_size = 0;
 949     cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset);
 950
 951     if (using_vga) {
 952         /* VGA BIOS load */
 953         if (cirrus_vga_enabled) {
 954             snprintf(buf, sizeof(buf), "%s/%s", bios_dir,
 955                      VGABIOS_CIRRUS_FILENAME);
 956         } else {
 957             snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 958         }
 959         oprom_area_size = load_option_rom(buf, 0xc0000, 0xe0000);
 960     }
 961     /* Although video roms can grow larger than 0x8000, the area between
 962      * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
 963      * for any other kind of option rom inside this area */
 964     if (oprom_area_size < 0x8000)
 965         oprom_area_size = 0x8000;
 966
 967     if (linux_boot) {
 968         load_linux(0xc0000 + oprom_area_size,
 969                    kernel_filename, initrd_filename, kernel_cmdline);
 970         oprom_area_size += 2048;
 971     }
 972
 973     for (i = 0; i < nb_option_roms; i++) {
 974         oprom_area_size += load_option_rom(option_rom[i],
 975                                            0xc0000 + oprom_area_size, 0xe0000);
 976     }
 977
 978     /* map all the bios at the top of memory */
 979     cpu_register_physical_memory((uint32_t)(-bios_size),
 980                                  bios_size, bios_offset | IO_MEM_ROM);
 981
 982     bochs_bios_init();
 983
 984     cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
 985     i8259 = i8259_init(cpu_irq[0]);
 986     ferr_irq = i8259[13];
 987
 988     if (pci_enabled) {
 989         pci_bus = i440fx_init(&i440fx_state, i8259);
 990         piix3_devfn = piix3_init(pci_bus, -1);
 991     } else {
 992         pci_bus = NULL;
 993     }
 994
 995     /* init basic PC hardware */
 996     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
 997
 998     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
 999
1000     if (cirrus_vga_enabled) {
1001         if (pci_enabled) {
1002             pci_cirrus_vga_init(pci_bus);
1003         } else {
1004             isa_cirrus_vga_init();
1005         }
1006     } else if (vmsvga_enabled) {
1007         if (pci_enabled)
1008             pci_vmsvga_init(pci_bus);
1009         else
1010             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1011     } else if (std_vga_enabled) {
1012         if (pci_enabled) {
1013             pci_vga_init(pci_bus, 0, 0);
1014         } else {
1015             isa_vga_init();
1016         }
1017     }
1018
1019     rtc_state = rtc_init(0x70, i8259[8], 2000);
1020
1021     qemu_register_boot_set(pc_boot_set, rtc_state);
1022
1023     register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1024     register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1025
1026     if (pci_enabled) {
1027         ioapic = ioapic_init();
1028     }
1029     pit = pit_init(0x40, i8259[0]);
1030     pcspk_init(pit);
1031     if (!no_hpet) {
1032         hpet_init(i8259);
1033     }
1034     if (pci_enabled) {
1035         pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
1036     }
1037
1038     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1039         if (serial_hds[i]) {
1040             serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
1041                         serial_hds[i]);
1042         }
1043     }
1044
1045     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1046         if (parallel_hds[i]) {
1047             parallel_init(parallel_io[i], i8259[parallel_irq[i]],
1048                           parallel_hds[i]);
1049         }
1050     }
1051
1052     watchdog_pc_init(pci_bus);
1053
1054     for(i = 0; i < nb_nics; i++) {
1055         NICInfo *nd = &nd_table[i];
1056
1057         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1058             pc_init_ne2k_isa(nd, i8259);
1059         else
1060             pci_nic_init(pci_bus, nd, -1, "ne2k_pci");
1061     }
1062
1063     qemu_system_hot_add_init();
1064
1065     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1066         fprintf(stderr, "qemu: too many IDE bus\n");
1067         exit(1);
1068     }
1069
1070     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1071         index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1072         if (index != -1)
1073             hd[i] = drives_table[index].bdrv;
1074         else
1075             hd[i] = NULL;
1076     }
1077
1078     if (pci_enabled) {
1079         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
1080     } else {
1081         for(i = 0; i < MAX_IDE_BUS; i++) {
1082             isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
1083                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1084         }
1085     }
1086
1087     i8042_init(i8259[1], i8259[12], 0x60);
1088     DMA_init(0);
1089 #ifdef HAS_AUDIO
1090     audio_init(pci_enabled ? pci_bus : NULL, i8259);
1091 #endif
1092
1093     for(i = 0; i < MAX_FD; i++) {
1094         index = drive_get_index(IF_FLOPPY, 0, i);
1095         if (index != -1)
1096             fd[i] = drives_table[index].bdrv;
1097         else
1098             fd[i] = NULL;
1099     }
1100     floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1101
1102     cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1103
1104     if (pci_enabled && usb_enabled) {
1105         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1106     }
1107
1108     if (pci_enabled && acpi_enabled) {
1109         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1110         i2c_bus *smbus;
1111
1112         /* TODO: Populate SPD eeprom data.  */
1113         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1114         for (i = 0; i < 8; i++) {
1115             smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
1116         }
1117     }
1118
1119     if (i440fx_state) {
1120         i440fx_init_memory_mappings(i440fx_state);
1121     }
1122
1123     if (pci_enabled) {
1124         int max_bus;
1125         int bus;
1126
1127         max_bus = drive_get_max_bus(IF_SCSI);
1128         for (bus = 0; bus <= max_bus; bus++) {
1129             pci_create_simple(pci_bus, -1, "lsi53c895a");
1130         }
1131     }
1132
1133     /* Add virtio block devices */
1134     if (pci_enabled) {
1135         int index;
1136         int unit_id = 0;
1137
1138         while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
1139             virtio_blk_init(pci_bus, drives_table[index].bdrv);
1140             unit_id++;
1141         }
1142     }
1143
1144     /* Add virtio balloon device */
1145     if (pci_enabled)
1146         virtio_balloon_init(pci_bus);
1147
1148     /* Add virtio console devices */
1149     if (pci_enabled) {
1150         for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1151             if (virtcon_hds[i])
1152                 virtio_console_init(pci_bus, virtcon_hds[i]);
1153         }
1154     }
1155 }
1156
1157 static void pc_init_pci(ram_addr_t ram_size,
1158                         const char *boot_device,
1159                         const char *kernel_filename,
1160                         const char *kernel_cmdline,
1161                         const char *initrd_filename,
1162                         const char *cpu_model)
1163 {
1164     pc_init1(ram_size, boot_device,
1165              kernel_filename, kernel_cmdline,
1166              initrd_filename, 1, cpu_model);
1167 }
1168
1169 static void pc_init_isa(ram_addr_t ram_size,
1170                         const char *boot_device,
1171                         const char *kernel_filename,
1172                         const char *kernel_cmdline,
1173                         const char *initrd_filename,
1174                         const char *cpu_model)
1175 {
1176     pc_init1(ram_size, boot_device,
1177              kernel_filename, kernel_cmdline,
1178              initrd_filename, 0, cpu_model);
1179 }
1180
1181 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1182    BIOS will read it and start S3 resume at POST Entry */
1183 void cmos_set_s3_resume(void)
1184 {
1185     if (rtc_state)
1186         rtc_set_memory(rtc_state, 0xF, 0xFE);
1187 }
1188
1189 QEMUMachine pc_machine = {
1190     .name = "pc",
1191     .desc = "Standard PC",
1192     .init = pc_init_pci,
1193     .max_cpus = 255,
1194 };
1195
1196 QEMUMachine isapc_machine = {
1197     .name = "isapc",
1198     .desc = "ISA-only PC",
1199     .init = pc_init_isa,
1200     .max_cpus = 1,
1201 };