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S3C: Fixed remaining warnings
[qemu/mini2440.git] / hw / s3c2410.c
blob55bed2a3b122796d0f02f1b06519e874c7eb73bd
1 /*
2 * Samsung S3C2410A RISC Microprocessor support (ARM920T based SoC).
3 *
4 * Copyright (c) 2007 OpenMoko, Inc.
5 * Author: Andrzej Zaborowski <andrew@openedhand.com>
6 * With: Michel Pollet <buserror@gmail.com>
7 *
8 * This code is licenced under the GNU GPL v2.
9 */
10
11 #include "s3c.h"
12 #include "qemu-timer.h"
13 #include "qemu-char.h"
14 #include "hw.h"
15 #include "console.h"
16 #include "devices.h"
17 #include "arm-misc.h"
18 #include "i2c.h"
19 #include "pxa.h"
20 #include "sysemu.h"
21
22 /* Interrupt controller */
23 struct s3c_pic_state_s {
24 target_phys_addr_t base;
25 qemu_irq *parent_pic;
26 qemu_irq *irqs;
27
28 uint32_t srcpnd;
29 uint32_t intpnd;
30 uint32_t intmsk;
31 uint32_t intmod;
32 uint32_t priority;
33 int intoffset;
34 uint32_t subsrcpnd;
35 uint32_t intsubmsk;
36 };
37
38 static void s3c_pic_update(struct s3c_pic_state_s *s)
39 {
40 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ],
41 s->srcpnd & s->intmod);
42 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ],
43 s->intpnd & ~s->intmsk & ~s->intmod);
44 }
45
46 /*
47 * Performs interrupt arbitration and notifies the CPU.
48 *
49 * Since it's a complex logic which cannot be relied on by the OS
50 * anyway - first because real hardware doesn't do it accurately,
51 * second because it only matters when interrupts occur at the
52 * same time which normally can't be predicted - we use a simpler
53 * version for non-debug runs.
54 */
55 #ifdef DEBUG
56 static const uint32_t s3c_arbmsk[6] = {
57 0x0000000f,
58 0x000003f0,
59 0x0000fc00,
60 0x003f0000,
61 0x0fc00000,
62 0xf0000000,
63 };
64
65 # define S3C_ARB_SEL(i) ((s->priority >> (7 + (i << 1))) & 3)
66 # define S3C_ARB_MODE(i) ((s->priority >> i) & 1)
67 # define S3C_ARB_SEL_SET(i, v) \
68 s->priority &= ~(3 << (7 + (i << 1))); \
69 s->priority |= v << (7 + (i << 1));
70
71 static void s3c_pic_arbitrate(struct s3c_pic_state_s *s)
72 {
73 uint32_t pnd = s->srcpnd & ~s->intmsk & ~s->intmod;
74 int offset, i, arb;
75 if (s->intpnd || !pnd) {
76 s3c_pic_update(s);
77 return;
78 }
79
80 if (pnd & s3c_arbmsk[0]) {
81 offset = 0;
82 arb = 0;
83 } else if (pnd & 0x0ffffff0) {
84 i = S3C_ARB_SEL(6);
85 i ^= i << 1;
86 if (!(pnd & s3c_arbmsk[1 + (i & 3)]))
87 if (!(pnd & s3c_arbmsk[1 + (++ i & 3)]))
88 if (!(pnd & s3c_arbmsk[1 + (++ i & 3)]))
89 i ++;
90
91 if (S3C_ARB_MODE(6))
92 S3C_ARB_SEL_SET(6, ((i + 1) & 3));
93 offset = (i & 3) * 6 + 4;
94 if (pnd & (1 << offset))
95 goto known_offset;
96 else if (!(pnd & (0x1f << offset))) {
97 offset += 5;
98 goto known_offset;
99 }
100 offset ++;
101 arb = (i & 3) + 1;
102 } else {
103 arb = 5;
104 offset = 28;
105 }
106
107 pnd >>= offset;
108 i = S3C_ARB_SEL(arb);
109 i ^= i << 1;
110 if (!(pnd & (1 << (i & 3))))
111 if (!(pnd & (1 << (++ i & 3))))
112 if (!(pnd & (1 << (++ i & 3))))
113 i ++;
114
115 if (S3C_ARB_MODE(arb))
116 S3C_ARB_SEL_SET(arb, ((i + 1) & 3));
117 offset += i & 3;
118 known_offset:
119 s->intoffset = offset;
120 s->intpnd = 1 << offset;
121 s3c_pic_update(s);
122 }
123 #else
124 inline static void s3c_pic_arbitrate(struct s3c_pic_state_s *s)
125 {
126 uint32_t pnd = s->srcpnd & ~s->intmsk & ~s->intmod;
127 if (pnd && !s->intpnd)
128 s->intpnd = 1 << (s->intoffset = ffs(pnd) - 1);
129 s3c_pic_update(s);
130 }
131 #endif
132
133 static const int s3c_sub_src_map[] = {
134 [S3C_PICS_RXD0 & 31] = S3C_PIC_UART0,
135 [S3C_PICS_TXD0 & 31] = S3C_PIC_UART0,
136 [S3C_PICS_ERR0 & 31] = S3C_PIC_UART0,
137 [S3C_PICS_RXD1 & 31] = S3C_PIC_UART1,
138 [S3C_PICS_TXD1 & 31] = S3C_PIC_UART1,
139 [S3C_PICS_ERR1 & 31] = S3C_PIC_UART1,
140 [S3C_PICS_RXD2 & 31] = S3C_PIC_UART2,
141 [S3C_PICS_TXD2 & 31] = S3C_PIC_UART2,
142 [S3C_PICS_ERR2 & 31] = S3C_PIC_UART2,
143 [S3C_PICS_TC & 31] = S3C_PIC_ADC,
144 [S3C_PICS_ADC & 31] = S3C_PIC_ADC,
145 };
146
147 static void s3c_pic_subupdate(struct s3c_pic_state_s *s)
148 {
149 int next;
150 const int *sub = &s3c_sub_src_map[-1];
151 uint32_t pnd = s->subsrcpnd & ~s->intsubmsk;
152 while ((next = ffs(pnd))) {
153 sub += next;
154 pnd >>= next;
155 s->srcpnd |= 1 << *sub;
156 }
157 s3c_pic_arbitrate(s);
158 }
159
160 static void s3c_pic_set_irq(void *opaque, int irq, int req)
161 {
162 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
163 uint32_t mask;
164 /* This interrupt controller doesn't clear any request signals
165 * or register bits automatically. */
166 if (!req)
167 return;
168
169 if (irq & 32) {
170 irq &= 31;
171 s->subsrcpnd |= 1 << irq;
172 if (s->intsubmsk & (1 << irq))
173 return;
174 else
175 irq = s3c_sub_src_map[irq];
176 }
177 s->srcpnd |= (mask = 1 << irq);
178
179 /* A FIQ */
180 if (s->intmod & mask)
181 qemu_irq_raise(s->parent_pic[ARM_PIC_CPU_FIQ]);
182 else if (!s->intpnd && !(s->intmsk & mask)) {
183 #ifdef DEBUG
184 s3c_pic_arbitrate(s);
185 #else
186 s->intpnd = mask;
187 s->intoffset = irq;
188 qemu_irq_raise(s->parent_pic[ARM_PIC_CPU_IRQ]);
189 #endif
190 }
191 }
192
193 static void s3c_pic_reset(struct s3c_pic_state_s *s)
194 {
195 s->srcpnd = 0;
196 s->intpnd = 0;
197 s->intmsk = 0xffffffff;
198 s->intmod = 0;
199 s->priority = 0x7f;
200 s->intoffset = 0;
201 s->subsrcpnd = 0;
202 s->intsubmsk = 0x7ff;
203 s3c_pic_update(s);
204 }
205
206 #define S3C_SRCPND 0x00 /* Source Pending register */
207 #define S3C_INTMOD 0x04 /* Source Mode register */
208 #define S3C_INTMSK 0x08 /* Interrupt Mask register */
209 #define S3C_PRIORITY 0x0c /* Priority register */
210 #define S3C_INTPND 0x10 /* Interrupt Pending register */
211 #define S3C_INTOFFSET 0x14 /* Interrupt Offset register */
212 #define S3C_SUBSRCPND 0x18 /* Sub Source Pending register */
213 #define S3C_INTSUBMSK 0x1c /* Interrupt Sub Mask register */
214
215 static uint32_t s3c_pic_read(void *opaque, target_phys_addr_t addr)
216 {
217 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
218
219 switch (addr) {
220 case S3C_SRCPND:
221 return s->srcpnd;
222 case S3C_INTPND:
223 return s->intpnd;
224 case S3C_INTMSK:
225 return s->intmsk;
226 case S3C_INTMOD:
227 return s->intmod;
228 case S3C_PRIORITY:
229 return s->priority;
230 case S3C_INTOFFSET:
231 return s->intoffset;
232 case S3C_SUBSRCPND:
233 return s->subsrcpnd;
234 case S3C_INTSUBMSK:
235 return s->intsubmsk;
236 default:
237 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
238 break;
239 }
240 return 0;
241 }
242
243 static void s3c_pic_write(void *opaque, target_phys_addr_t addr,
244 uint32_t value)
245 {
246 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
247
248 switch (addr) {
249 case S3C_SRCPND:
250 s->srcpnd &= ~value;
251 if (value & s->intmod)
252 s3c_pic_update(s);
253 break;
254 case S3C_INTPND:
255 if (s->intpnd & value) {
256 s->intpnd = 0;
257 s->intoffset = 0;
258 s3c_pic_arbitrate(s);
259 }
260 break;
261 case S3C_INTMSK:
262 s->intmsk = value;
263 if (s->intpnd & value) {
264 s->intpnd = 0;
265 s->intoffset = 0;
266 }
267 s3c_pic_arbitrate(s);
268 break;
269 case S3C_INTMOD:
270 s->intmod = value;
271 break;
272 case S3C_PRIORITY:
273 s->priority = value;
274 break;
275 case S3C_SUBSRCPND:
276 s->subsrcpnd &= ~value;
277 break;
278 case S3C_INTSUBMSK:
279 s->intsubmsk = value;
280 s3c_pic_subupdate(s);
281 break;
282 default:
283 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
284 }
285 }
286
287 static CPUReadMemoryFunc *s3c_pic_readfn[] = {
288 s3c_pic_read,
289 s3c_pic_read,
290 s3c_pic_read,
291 };
292
293 static CPUWriteMemoryFunc *s3c_pic_writefn[] = {
294 s3c_pic_write,
295 s3c_pic_write,
296 s3c_pic_write,
297 };
298
299 static void s3c_pic_save(QEMUFile *f, void *opaque)
300 {
301 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
302 qemu_put_be32s(f, &s->srcpnd);
303 qemu_put_be32s(f, &s->intpnd);
304 qemu_put_be32s(f, &s->intmsk);
305 qemu_put_be32s(f, &s->intmod);
306 qemu_put_be32s(f, &s->priority);
307 qemu_put_be32s(f, &s->subsrcpnd);
308 qemu_put_be32s(f, &s->intsubmsk);
309 qemu_put_be32(f, s->intoffset);
310 }
311
312 static int s3c_pic_load(QEMUFile *f, void *opaque, int version_id)
313 {
314 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
315 qemu_get_be32s(f, &s->srcpnd);
316 qemu_get_be32s(f, &s->intpnd);
317 qemu_get_be32s(f, &s->intmsk);
318 qemu_get_be32s(f, &s->intmod);
319 qemu_get_be32s(f, &s->priority);
320 qemu_get_be32s(f, &s->subsrcpnd);
321 qemu_get_be32s(f, &s->intsubmsk);
322 s->intoffset = qemu_get_be32(f);
323 s3c_pic_update(s);
324 return 0;
325 }
326
327 struct s3c_pic_state_s *s3c_pic_init(target_phys_addr_t base,
328 qemu_irq *arm_pic)
329 {
330 int iomemtype;
331 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *)
332 qemu_mallocz(sizeof(struct s3c_pic_state_s));
333
334 s->base = base;
335 s->parent_pic = arm_pic;
336 s->irqs = qemu_allocate_irqs(s3c_pic_set_irq, s, S3C_PIC_MAX);
337
338 s3c_pic_reset(s);
339
340 iomemtype = cpu_register_io_memory(0, s3c_pic_readfn,
341 s3c_pic_writefn, s);
342 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
343
344 register_savevm("s3c24xx_pic", 0, 0, s3c_pic_save, s3c_pic_load, s);
345
346 return s;
347 }
348
349 qemu_irq *s3c_pic_get(struct s3c_pic_state_s *s)
350 {
351 return s->irqs;
352 }
353
354 /* Memory controller */
355 #define S3C_BWSCON 0x00 /* Bus Width & Wait Control register */
356 #define S3C_BANKCON0 0x04 /* Bank 0 Control register */
357 #define S3C_BANKCON1 0x08 /* Bank 1 Control register */
358 #define S3C_BANKCON2 0x0c /* Bank 2 Control register */
359 #define S3C_BANKCON3 0x10 /* Bank 3 Control register */
360 #define S3C_BANKCON4 0x14 /* Bank 4 Control register */
361 #define S3C_BANKCON5 0x18 /* Bank 5 Control register */
362 #define S3C_BANKCON6 0x1c /* Bank 6 Control register */
363 #define S3C_BANKCON7 0x20 /* Bank 7 Control register */
364 #define S3C_REFRESH 0x24 /* SDRAM Refresh Control register */
365 #define S3C_BANKSIZE 0x28 /* Flexible Bank Size register */
366 #define S3C_MRSRB6 0x2c /* Bank 6 Mode Set register */
367 #define S3C_MRSRB7 0x30 /* Bank 6 Mode Set register */
368
369 static void s3c_mc_reset(struct s3c_state_s *s)
370 {
371 s->mc_regs[S3C_BWSCON >> 2] = 0x0000000;
372 s->mc_regs[S3C_BANKCON0 >> 2] = 0x0700;
373 s->mc_regs[S3C_BANKCON1 >> 2] = 0x0700;
374 s->mc_regs[S3C_BANKCON2 >> 2] = 0x0700;
375 s->mc_regs[S3C_BANKCON3 >> 2] = 0x0700;
376 s->mc_regs[S3C_BANKCON4 >> 2] = 0x0700;
377 s->mc_regs[S3C_BANKCON5 >> 2] = 0x0700;
378 s->mc_regs[S3C_BANKCON6 >> 2] = 0x18008;
379 s->mc_regs[S3C_BANKCON7 >> 2] = 0x18008;
380 s->mc_regs[S3C_REFRESH >> 2] = 0xac0000;
381 s->mc_regs[S3C_BANKSIZE >> 2] = 0x2;
382 s->mc_regs[S3C_MRSRB6 >> 2] = 0x00;
383 s->mc_regs[S3C_MRSRB7 >> 2] = 0x00;
384 }
385
386 static uint32_t s3c_mc_read(void *opaque, target_phys_addr_t addr)
387 {
388 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
389
390 switch (addr >> 2) {
391 case S3C_BWSCON ... S3C_MRSRB7:
392 return s->mc_regs[addr >> 2];
393 default:
394 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
395 break;
396 }
397 return 0;
398 }
399
400 static void s3c_mc_write(void *opaque, target_phys_addr_t addr,
401 uint32_t value)
402 {
403 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
404
405 switch (addr >> 2) {
406 case S3C_BWSCON ... S3C_MRSRB7:
407 s->mc_regs[addr >> 2] = value;
408 break;
409 default:
410 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
411 }
412 }
413
414 static CPUReadMemoryFunc *s3c_mc_readfn[] = {
415 s3c_mc_read,
416 s3c_mc_read,
417 s3c_mc_read,
418 };
419
420 static CPUWriteMemoryFunc *s3c_mc_writefn[] = {
421 s3c_mc_write,
422 s3c_mc_write,
423 s3c_mc_write,
424 };
425
426 static void s3c_mc_save(QEMUFile *f, void *opaque)
427 {
428 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
429 int i;
430 for (i = 0; i < 13; i ++)
431 qemu_put_be32s(f, &s->mc_regs[i]);
432 }
433
434 static int s3c_mc_load(QEMUFile *f, void *opaque, int version_id)
435 {
436 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
437 int i;
438 for (i = 0; i < 13; i ++)
439 qemu_get_be32s(f, &s->mc_regs[i]);
440 return 0;
441 }
442
443 /* Clock & power management */
444 #define S3C_LOCKTIME 0x00 /* PLL Lock Time Count register */
445 #define S3C_MPLLCON 0x04 /* MPLL Configuration register */
446 #define S3C_UPLLCON 0x08 /* UPLL Configuration register */
447 #define S3C_CLKCON 0x0c /* Clock Generator Control register */
448 #define S3C_CLKSLOW 0x10 /* Slow Clock Control register */
449 #define S3C_CLKDIVN 0x14 /* Clock Divider Control register */
450
451 #define S3C2440_CAMDIVN 0x18 /* Camera Clock Divider register */
452
453 static void s3c_clkpwr_update(struct s3c_state_s *s)
454 {
455 uint32_t mpll = s->clkpwr_regs[S3C_MPLLCON >> 2],
456 ratio = s->clkpwr_regs[S3C_CLKDIVN >> 2];
457 uint32_t mdiv = (mpll >> 12) & 0xff,
458 pdiv = (mpll >> 4) & 0x3f,
459 sdiv = (mpll) & 0x3;
460
461 s->clock.clk = ((mdiv + 8) * s->clock.xtal * 2) /
462 ((pdiv + 2) * (1 << sdiv));
463
464 switch( (ratio & 0x6) >> 1 ) {
465 case 0:
466 s->clock.hclk = s->clock.clk;
467 break;
468 case 1:
469 s->clock.hclk = s->clock.clk/2;
470 break;
471 case 2:
472 s->clock.hclk = s->clock.clk/4;
473 break;
474 case 3:
475 s->clock.hclk = s->clock.clk/3;
476 break;
477 }
478 switch ( ratio&0x1) {
479 case 0:
480 s->clock.pclk = s->clock.hclk;
481 break;
482 case 1:
483 s->clock.pclk = s->clock.hclk/2;
484 break;
485 }
486 }
487
488 static void s3c_clkpwr_reset(struct s3c_state_s *s)
489 {
490 s->clkpwr_regs[S3C_LOCKTIME >> 2] = 0x00ffffff;
491 s->clkpwr_regs[S3C_MPLLCON >> 2] = 0x0005c080;
492 s->clkpwr_regs[S3C_UPLLCON >> 2] = 0x00028080;
493 s->clkpwr_regs[S3C_CLKCON >> 2] = 0x0007fff0;
494 s->clkpwr_regs[S3C_CLKSLOW >> 2] = 0x00000004;
495 s->clkpwr_regs[S3C_CLKDIVN >> 2] = 0x00000000;
496 s->clkpwr_regs[S3C2440_CAMDIVN >> 2] = 0x00000000;
497 s3c_clkpwr_update(s);
498 }
499
500 static uint32_t s3c_clkpwr_read(void *opaque, target_phys_addr_t addr)
501 {
502 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
503
504 switch (addr) {
505 case S3C_LOCKTIME ... S3C_CLKDIVN:
506 return s->clkpwr_regs[addr >> 2];
507 case S3C2440_CAMDIVN:
508 if (s->cpu_id == S3C_CPU_2440)
509 return s->clkpwr_regs[addr >> 2];
510 default:
511 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
512 break;
513 }
514 return 0;
515 }
516
517 static void s3c_clkpwr_write(void *opaque, target_phys_addr_t addr,
518 uint32_t value)
519 {
520 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
521
522 switch (addr) {
523 case S3C_LOCKTIME:
524 case S3C_MPLLCON:
525 case S3C_UPLLCON:
526 case S3C_CLKDIVN:
527 s->clkpwr_regs[addr >> 2] = value;
528 s3c_clkpwr_update(s);
529 break;
530 case S3C_CLKCON:
531 if (value & (1 << 3)) {
532 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
533 printf("%s: processor powered off\n", __FUNCTION__);
534 s3c_gpio_setpwrstat(s->io, 2);
535 #if 0
536 cpu_reset(s->env);
537 s->env->regs[15] = 0; /* XXX */
538 #endif
539 } else
540 if (value & (1 << 2)) /* Normal IDLE mode */
541 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
542 if ((s->clkpwr_regs[addr >> 2] ^ value) & 1)
543 printf("%s: SPECIAL mode %s\n", __FUNCTION__,
544 (value & 1) ? "on" : "off");
545 s->clkpwr_regs[addr >> 2] = value;
546 break;
547 case S3C_CLKSLOW:
548 if ((s->clkpwr_regs[addr >> 2] ^ value) & (1 << 4))
549 printf("%s: SLOW mode %s\n", __FUNCTION__,
550 (value & (1 << 4)) ? "on" : "off");
551 s->clkpwr_regs[addr >> 2] = value;
552 break;
553 case S3C2440_CAMDIVN:
554 if (s->cpu_id == S3C_CPU_2440) {
555 s->clkpwr_regs[addr >> 2] = value;
556 break;
557 }
558 default:
559 printf("%s: Bad register 0x%x (cpu %08x)\n", __FUNCTION__, /*(unsigned long)*/addr, s->cpu_id);
560 }
561 }
562
563 static CPUReadMemoryFunc *s3c_clkpwr_readfn[] = {
564 s3c_clkpwr_read,
565 s3c_clkpwr_read,
566 s3c_clkpwr_read,
567 };
568
569 static CPUWriteMemoryFunc *s3c_clkpwr_writefn[] = {
570 s3c_clkpwr_write,
571 s3c_clkpwr_write,
572 s3c_clkpwr_write,
573 };
574
575 static void s3c_clkpwr_save(QEMUFile *f, void *opaque)
576 {
577 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
578 int i;
579 for (i = 0; i < 7; i ++)
580 qemu_put_be32s(f, &s->clkpwr_regs[i]);
581 }
582
583 static int s3c_clkpwr_load(QEMUFile *f, void *opaque, int version_id)
584 {
585 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
586 int i;
587 for (i = 0; i < 7; i ++)
588 qemu_get_be32s(f, &s->clkpwr_regs[i]);
589 return 0;
590 }
591
592 /* DMA controller */
593 #define S3C_DMA_CH_N 4
594
595 struct s3c_dma_ch_state_s;
596 struct s3c_dma_state_s { /* Modelled as an interrupt controller */
597 target_phys_addr_t base;
598 qemu_irq *drqs;
599 struct s3c_dma_ch_state_s {
600 qemu_irq intr;
601 int curr_tc;
602 int req;
603 int running;
604 uint32_t con;
605 uint32_t isrc;
606 uint32_t isrcc;
607 uint32_t idst;
608 uint32_t idstc;
609 uint32_t csrc;
610 uint32_t cdst;
611 uint32_t mask;
612 } ch[S3C_DMA_CH_N];
613 };
614
615 static inline void s3c_dma_ch_run(struct s3c_dma_state_s *s,
616 struct s3c_dma_ch_state_s *ch)
617 {
618 int width, burst, t;
619 uint8_t buffer[4];
620 width = 1 << ((ch->con >> 20) & 3); /* DSZ */
621 burst = (ch->con & (1 << 28)) ? 4 : 1; /* TSZ */
622
623 while (!ch->running && ch->curr_tc > 0 && ch->req &&
624 (ch->mask & (1 << 1))) { /* ON_OFF */
625 if (width > sizeof(buffer)) {
626 printf("%s: wrong access width\n", __FUNCTION__);
627 return;
628 }
629 ch->running = 1;
630 while (ch->curr_tc --) {
631 for (t = 0; t < burst; t ++) {
632 cpu_physical_memory_read(ch->csrc, buffer, width);
633 cpu_physical_memory_write(ch->cdst, buffer, width);
634
635 if (!(ch->isrcc & 1)) /* INT */
636 ch->csrc += width;
637 if (!(ch->idstc & 1)) /* INT */
638 ch->cdst += width;
639 }
640
641 if (!(ch->con & (1 << 27)) && !ch->req) /* SERVMODE */
642 break;
643 }
644 ch->running = 0;
645
646 if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
647 ch->req = 0;
648 }
649
650 if (ch->curr_tc <= 0) {
651 if (ch->con & (1 << 22)) /* RELOAD */
652 ch->mask &= ~(1 << 1); /* ON_OFF */
653 else {
654 if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
655 printf("%s: auto-reload software controlled transfer\n",
656 __FUNCTION__);
657 break;
658 }
659 ch->csrc = ch->isrc; /* S_ADDR */
660 ch->cdst = ch->idst; /* D_ADDR */
661 ch->curr_tc = ch->con & 0xfffff; /* TC */
662 ch->con |= 1 << 22; /* ON_OFF */
663 }
664
665 if (ch->con & (1 << 31)) /* DMD_HS */
666 ch->req = 0;
667
668 if (ch->con & (1 << 29)) { /* INT */
669 qemu_irq_raise(ch->intr);
670 /* Give the system a chance to respond. */
671 break;
672 }
673 }
674 }
675 }
676
677 static void s3c_dma_reset(struct s3c_dma_state_s *s)
678 {
679 int i;
680 for (i = 0; i < S3C_DMA_CH_N; i ++) {
681 s->ch[i].curr_tc = 0;
682 s->ch[i].csrc = 0;
683 s->ch[i].isrc = 0;
684 s->ch[i].isrcc = 0;
685 s->ch[i].cdst = 0;
686 s->ch[i].idst = 0;
687 s->ch[i].idstc = 0;
688 s->ch[i].con = 0;
689 s->ch[i].csrc = 0;
690 s->ch[i].cdst = 0;
691 s->ch[i].mask = 0;
692 }
693 }
694
695 static void s3c_dma_dreq(void *opaque, int line, int req)
696 {
697 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
698 struct s3c_dma_ch_state_s *ch = &s->ch[line >> 4];
699
700 if (ch->con & (1 << 23)) /* SWHW_SEL */
701 if (((ch->con >> 24) & 7) == (line & 7)) { /* HWSRCSEL */
702 ch->req = req;
703 s3c_dma_ch_run(s, ch);
704 }
705 }
706
707 #define S3C_DISRC 0x00 /* DMA Initial Source register */
708 #define S3C_DISRCC 0x04 /* DMA Initial Source Control register */
709 #define S3C_DIDST 0x08 /* DMA Initial Destination register */
710 #define S3C_DIDSTC 0x0c /* DMA Initial Destination Control register */
711 #define S3C_DCON 0x10 /* DMA Control register */
712 #define S3C_DSTAT 0x14 /* DMA Count register */
713 #define S3C_DCSRC 0x18 /* DMA Current Source register */
714 #define S3C_DCDST 0x1c /* DMA Current Destination register */
715 #define S3C_DMASKTRIG 0x20 /* DMA Mask Trigger register */
716
717 static uint32_t s3c_dma_read(void *opaque, target_phys_addr_t addr)
718 {
719 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
720 struct s3c_dma_ch_state_s *ch = 0;
721
722 if (addr >= 0 && addr <= (S3C_DMA_CH_N << 6)) {
723 ch = &s->ch[addr >> 6];
724 addr &= 0x3f;
725 }
726
727 switch (addr) {
728 case S3C_DISRC:
729 return ch->isrc;
730 case S3C_DISRCC:
731 return ch->isrcc;
732 case S3C_DIDST:
733 return ch->idst;
734 case S3C_DIDSTC:
735 return ch->idstc;
736 case S3C_DCON:
737 return ch->con;
738 case S3C_DSTAT:
739 return ch->curr_tc;
740 case S3C_DCSRC:
741 return ch->csrc;
742 case S3C_DCDST:
743 return ch->cdst;
744 case S3C_DMASKTRIG:
745 return ch->mask;
746 default:
747 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
748 break;
749 }
750 return 0;
751 }
752
753 static void s3c_dma_write(void *opaque, target_phys_addr_t addr,
754 uint32_t value)
755 {
756 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
757 struct s3c_dma_ch_state_s *ch = 0;
758
759 if (addr >= 0 && addr <= (S3C_DMA_CH_N << 6)) {
760 ch = &s->ch[addr >> 6];
761 addr &= 0x3f;
762 }
763
764 switch (addr) {
765 case S3C_DCON:
766 ch->con = value;
767 break;
768 case S3C_DISRC:
769 ch->isrc = value;
770 break;
771 case S3C_DISRCC:
772 ch->isrcc = value;
773 break;
774 case S3C_DIDST:
775 ch->idst = value;
776 break;
777 case S3C_DIDSTC:
778 ch->idstc = value;
779 break;
780 case S3C_DMASKTRIG:
781 if (~ch->mask & value & (1 << 1)) { /* ON_OFF */
782 ch->curr_tc = ch->con & 0xfffff; /* TC */
783 ch->csrc = ch->isrc; /* S_ADDR */
784 ch->cdst = ch->idst; /* D_ADDR */
785 }
786
787 ch->mask = value;
788 if (value & (1 << 2)) { /* STOP */
789 ch->mask &= ~(3 << 1); /* ON_OFF */
790 } else if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
791 ch->req = value & 1; /* SW_TRIG */
792 s3c_dma_ch_run(s, ch);
793 }
794 break;
795 default:
796 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
797 }
798 }
799
800 static CPUReadMemoryFunc *s3c_dma_readfn[] = {
801 s3c_dma_read,
802 s3c_dma_read,
803 s3c_dma_read,
804 };
805
806 static CPUWriteMemoryFunc *s3c_dma_writefn[] = {
807 s3c_dma_write,
808 s3c_dma_write,
809 s3c_dma_write,
810 };
811
812 static void s3c_dma_save(QEMUFile *f, void *opaque)
813 {
814 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
815 int i;
816 for (i = 0; i < S3C_DMA_CH_N; i ++) {
817 qemu_put_be32(f, s->ch[i].curr_tc);
818 qemu_put_be32(f, s->ch[i].req);
819 qemu_put_be32s(f, &s->ch[i].con);
820 qemu_put_be32s(f, &s->ch[i].isrc);
821 qemu_put_be32s(f, &s->ch[i].isrcc);
822 qemu_put_be32s(f, &s->ch[i].idst);
823 qemu_put_be32s(f, &s->ch[i].idstc);
824 qemu_put_be32s(f, &s->ch[i].csrc);
825 qemu_put_be32s(f, &s->ch[i].cdst);
826 qemu_put_be32s(f, &s->ch[i].mask);
827 }
828 }
829
830 static int s3c_dma_load(QEMUFile *f, void *opaque, int version_id)
831 {
832 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
833 int i;
834 for (i = 0; i < S3C_DMA_CH_N; i ++) {
835 s->ch[i].curr_tc = qemu_get_be32(f);
836 s->ch[i].req = qemu_get_be32(f);
837 qemu_get_be32s(f, &s->ch[i].con);
838 qemu_get_be32s(f, &s->ch[i].isrc);
839 qemu_get_be32s(f, &s->ch[i].isrcc);
840 qemu_get_be32s(f, &s->ch[i].idst);
841 qemu_get_be32s(f, &s->ch[i].idstc);
842 qemu_get_be32s(f, &s->ch[i].csrc);
843 qemu_get_be32s(f, &s->ch[i].cdst);
844 qemu_get_be32s(f, &s->ch[i].mask);
845 }
846 return 0;
847 }
848
849 struct s3c_dma_state_s *s3c_dma_init(target_phys_addr_t base, qemu_irq *pic)
850 {
851 int iomemtype;
852 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *)
853 qemu_mallocz(sizeof(struct s3c_dma_state_s));
854
855 s->base = base;
856 s->ch[0].intr = pic[0];
857 s->ch[1].intr = pic[1];
858 s->ch[2].intr = pic[2];
859 s->ch[3].intr = pic[3];
860 s->drqs = qemu_allocate_irqs(s3c_dma_dreq, s, S3C_RQ_MAX);
861
862 s3c_dma_reset(s);
863
864 iomemtype = cpu_register_io_memory(0, s3c_dma_readfn,
865 s3c_dma_writefn, s);
866 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
867
868 register_savevm("s3c24xx_dma", 0, 0, s3c_dma_save, s3c_dma_load, s);
869
870 return s;
871 }
872
873 qemu_irq *s3c_dma_get(struct s3c_dma_state_s *s)
874 {
875 return s->drqs;
876 }
877
878 /* PWM timers controller */
879 struct s3c_timer_state_s;
880 struct s3c_timers_state_s {
881 struct s3c_freq_s * freq;
882 target_phys_addr_t base;
883 qemu_irq *dma;
884 DisplayState *ds;
885 struct s3c_timer_state_s {
886 QEMUTimer *t;
887 struct s3c_timers_state_s *s;
888 int n;
889 int running;
890 uint32_t divider;
891 uint16_t count;
892 int64_t reload;
893 qemu_irq irq;
894 gpio_handler_t cmp_cb;
895 void *cmp_opaque;
896 } timer[5];
897
898 uint16_t compareb[4];
899 uint16_t countb[5];
900 uint32_t config[2];
901 uint32_t control;
902 };
903
904 static const int s3c_tm_bits[] = { 0, 8, 12, 16, 20 };
905
906 static uint16_t s3c_timers_get(struct s3c_timers_state_s *s, int tm)
907 {
908 uint16_t elapsed;
909 if (!s->timer[tm].running)
910 return s->timer[tm].count;
911
912 elapsed = muldiv64(qemu_get_clock(vm_clock) - s->timer[tm].reload,
913 s->timer[tm].divider, ticks_per_sec);
914 if (unlikely(elapsed > s->timer[tm].count))
915 return s->timer[tm].count;
916
917 return s->timer[tm].count - elapsed;
918 }
919
920 static void s3c_timers_stop(struct s3c_timers_state_s *s, int tm)
921 {
922 s->timer[tm].count = s3c_timers_get(s, tm);
923 s->timer[tm].running = 0;
924 }
925
926 static void s3c_timers_start(struct s3c_timers_state_s *s, int tm)
927 {
928 if (s->timer[tm].running)
929 return;
930
931 s->timer[tm].divider = s->freq->pclk >>
932 (((s->config[1] >> (tm * 4)) & 3) + 1);
933 if (tm < 2)
934 s->timer[tm].divider /= ((s->config[0] >> 0) & 0xff) + 1;
935 else
936 s->timer[tm].divider /= ((s->config[0] >> 8) & 0xff) + 1;
937 s->timer[tm].running = 1;
938 s->timer[tm].reload = qemu_get_clock(vm_clock);
939 qemu_mod_timer(s->timer[tm].t,
940 s->timer[tm].reload + muldiv64(s->timer[tm].count,
941 ticks_per_sec, s->timer[tm].divider));
942 }
943
944 static void s3c_timers_reset(struct s3c_timers_state_s *s)
945 {
946 int i;
947 s->config[0] = 0x00000000;
948 s->config[1] = 0x00000000;
949 s->control = 0x00000000;
950
951 for (i = 0; i < 5; i ++) {
952 if (s->timer[i].running)
953 s3c_timers_stop(s, i);
954 s->countb[i] = 0x0000;
955 s->timer[i].count = 0;
956 }
957 for (i = 0; i < 4; i ++)
958 s->compareb[i] = 0x0000;
959 }
960
961 static void s3c_timers_tick(void *opaque)
962 {
963 struct s3c_timer_state_s *t = (struct s3c_timer_state_s *) opaque;
964 struct s3c_timers_state_s *s = t->s;
965 if (!t->running)
966 return;
967
968 if (((s->config[1] >> 20) & 0xf) == t->n + 1) {
969 qemu_irq_raise(s->dma[S3C_RQ_TIMER0]); /* TODO */
970 qemu_irq_raise(s->dma[S3C_RQ_TIMER1]);
971 qemu_irq_raise(s->dma[S3C_RQ_TIMER2]);
972 } else
973 qemu_irq_raise(t->irq);
974
975 t->running = 0;
976 t->count = 0;
977
978 if (s->control & (1 << ((t->n == 4) ? 22 : (s3c_tm_bits[t->n] + 3)))) {
979 /* Auto-reload */
980 t->count = s->countb[t->n];
981 s3c_timers_start(s, t->n);
982 } else
983 s->control &= ~(1 << s3c_tm_bits[t->n]);
984 }
985
986 #define S3C_TCFG0 0x00 /* Timer Configuration register 0 */
987 #define S3C_TCFG1 0x04 /* Timer Configuration register 1 */
988 #define S3C_TCON 0x08 /* Timer Control register */
989 #define S3C_TCNTB0 0x0c /* Timer 0 Count Buffer register */
990 #define S3C_TCMPB0 0x10 /* Timer 0 Compare Buffer register */
991 #define S3C_TCNTO0 0x14 /* Timer 0 Count Observation register */
992 #define S3C_TCNTB1 0x18 /* Timer 1 Count Buffer register */
993 #define S3C_TCMPB1 0x1c /* Timer 1 Compare Buffer register */
994 #define S3C_TCNTO1 0x20 /* Timer 1 Count Observation register */
995 #define S3C_TCNTB2 0x24 /* Timer 2 Count Buffer register */
996 #define S3C_TCMPB2 0x28 /* Timer 2 Compare Buffer register */
997 #define S3C_TCNTO2 0x2c /* Timer 2 Count Observation register */
998 #define S3C_TCNTB3 0x30 /* Timer 3 Count Buffer register */
999 #define S3C_TCMPB3 0x34 /* Timer 3 Compare Buffer register */
1000 #define S3C_TCNTO3 0x38 /* Timer 3 Count Observation register */
1001 #define S3C_TCNTB4 0x3c /* Timer 4 Count Buffer register */
1002 #define S3C_TCNTO4 0x40 /* Timer 4 Count Observation register */
1003
1004 static uint32_t s3c_timers_read(void *opaque, target_phys_addr_t addr)
1005 {
1006 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1007 int tm = 0;
1008
1009 switch (addr) {
1010 case S3C_TCFG0:
1011 return s->config[0];
1012 case S3C_TCFG1:
1013 return s->config[1];
1014 case S3C_TCON:
1015 return s->control;
1016 case S3C_TCMPB3: tm ++;
1017 case S3C_TCMPB2: tm ++;
1018 case S3C_TCMPB1: tm ++;
1019 case S3C_TCMPB0:
1020 return s->compareb[tm];
1021 case S3C_TCNTB4: tm ++;
1022 case S3C_TCNTB3: tm ++;
1023 case S3C_TCNTB2: tm ++;
1024 case S3C_TCNTB1: tm ++;
1025 case S3C_TCNTB0:
1026 return s->countb[tm];
1027 case S3C_TCNTO4: tm ++;
1028 case S3C_TCNTO3: tm ++;
1029 case S3C_TCNTO2: tm ++;
1030 case S3C_TCNTO1: tm ++;
1031 case S3C_TCNTO0:
1032 return s3c_timers_get(s, tm);
1033 default:
1034 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1035 break;
1036 }
1037 return 0;
1038 }
1039
1040 static void s3c_timers_write(void *opaque, target_phys_addr_t addr,
1041 uint32_t value)
1042 {
1043 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1044 int tm = 0;
1045
1046 switch (addr) {
1047 case S3C_TCFG0:
1048 s->config[0] = value & 0x00ffffff;
1049 break;
1050 case S3C_TCFG1:
1051 s->config[1] = value & 0x00ffffff;
1052 break;
1053 case S3C_TCON:
1054 for (tm = 0; tm < 5; tm ++) {
1055 if (value & (2 << (s3c_tm_bits[tm]))) {
1056 if (s->timer[tm].running) {
1057 s3c_timers_stop(s, tm);
1058 s->timer[tm].count = s->countb[tm];
1059 s3c_timers_start(s, tm);
1060 } else
1061 s->timer[tm].count = s->countb[tm];
1062 }
1063 if (((value >> s3c_tm_bits[tm]) & 1) ^ s->timer[tm].running) {
1064 if (s->timer[tm].running)
1065 s3c_timers_stop(s, tm);
1066 else
1067 s3c_timers_start(s, tm);
1068 }
1069 }
1070
1071 s->control = value & 0x007fff1f;
1072 break;
1073 case S3C_TCMPB3: tm ++;
1074 case S3C_TCMPB2: tm ++;
1075 case S3C_TCMPB1: tm ++;
1076 case S3C_TCMPB0:
1077 s->compareb[tm] = value & 0xffff;
1078 if (s->timer[tm].cmp_cb)
1079 s->timer[tm].cmp_cb(tm, s->compareb[tm], s->timer[tm].cmp_opaque);
1080 break;
1081 case S3C_TCNTB4: tm ++;
1082 case S3C_TCNTB3: tm ++;
1083 case S3C_TCNTB2: tm ++;
1084 case S3C_TCNTB1: tm ++;
1085 case S3C_TCNTB0:
1086 s->countb[tm] = value & 0xffff;
1087 break;
1088 default:
1089 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1090 }
1091 }
1092
1093 static CPUReadMemoryFunc *s3c_timers_readfn[] = {
1094 s3c_timers_read,
1095 s3c_timers_read,
1096 s3c_timers_read,
1097 };
1098
1099 static CPUWriteMemoryFunc *s3c_timers_writefn[] = {
1100 s3c_timers_write,
1101 s3c_timers_write,
1102 s3c_timers_write,
1103 };
1104
1105 static void s3c_timers_save(QEMUFile *f, void *opaque)
1106 {
1107 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1108 int i;
1109 for (i = 0; i < 5; i ++) {
1110 qemu_put_be32(f, s->timer[i].running);
1111 qemu_put_be32s(f, &s->timer[i].divider);
1112 qemu_put_be16(f, s3c_timers_get(s, i));
1113 qemu_put_sbe64s(f, &s->timer[i].reload);
1114 }
1115
1116 for (i = 0; i < 4; i ++)
1117 qemu_put_be16s(f, &s->compareb[i]);
1118 for (i = 0; i < 5; i ++)
1119 qemu_put_be16s(f, &s->countb[i]);
1120 for (i = 0; i < 2; i ++)
1121 qemu_put_be32s(f, &s->config[i]);
1122 qemu_put_be32s(f, &s->control);
1123 }
1124
1125 static int s3c_timers_load(QEMUFile *f, void *opaque, int version_id)
1126 {
1127 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1128 int i, running[5];
1129 for (i = 0; i < 5; i ++) {
1130 s->timer[i].running = 0;
1131 running[i] = qemu_get_be32(f);
1132 qemu_get_be32s(f, &s->timer[i].divider);
1133 qemu_get_be16s(f, &s->timer[i].count);
1134 qemu_get_sbe64s(f, &s->timer[i].reload);
1135 }
1136
1137 for (i = 0; i < 4; i ++)
1138 qemu_get_be16s(f, &s->compareb[i]);
1139 for (i = 0; i < 5; i ++)
1140 qemu_get_be16s(f, &s->countb[i]);
1141 for (i = 0; i < 2; i ++)
1142 qemu_get_be32s(f, &s->config[i]);
1143 qemu_get_be32s(f, &s->control);
1144
1145 for (i = 0; i < 5; i ++)
1146 if (running[i])
1147 s3c_timers_start(s, i);
1148
1149 return 0;
1150 }
1151
1152 struct s3c_timers_state_s *s3c_timers_init(struct s3c_freq_s * freq, target_phys_addr_t base,
1153 qemu_irq *pic, qemu_irq *dma)
1154 {
1155 int i, iomemtype;
1156 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *)
1157 qemu_mallocz(sizeof(struct s3c_timers_state_s));
1158
1159 s->freq = freq;
1160 s->base = base;
1161 s->dma = dma;
1162
1163 s3c_timers_reset(s);
1164
1165 for (i = 0; i < 5; i ++) {
1166 s->timer[i].t = qemu_new_timer(vm_clock,
1167 s3c_timers_tick, &s->timer[i]);
1168 s->timer[i].s = s;
1169 s->timer[i].n = i;
1170 s->timer[i].cmp_cb = 0;
1171 s->timer[i].irq = pic[i];
1172 }
1173
1174 iomemtype = cpu_register_io_memory(0, s3c_timers_readfn,
1175 s3c_timers_writefn, s);
1176 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1177
1178 register_savevm("s3c24xx_timers", 0, 0,
1179 s3c_timers_save, s3c_timers_load, s);
1180
1181 return s;
1182 }
1183
1184 void s3c_timers_cmp_handler_set(void *opaque, int line,
1185 gpio_handler_t handler, void *cmp_opaque)
1186 {
1187 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1188 if (line > 4 || line < 0) {
1189 printf("%s: Bad timer number %i.\n", __FUNCTION__, line);
1190 exit(-1);
1191 }
1192 s->timer[line].cmp_cb = handler;
1193 s->timer[line].cmp_opaque = cmp_opaque;
1194 }
1195
1196 /* UART */
1197 struct s3c_uart_state_s {
1198 struct s3c_freq_s * freq;
1199 target_phys_addr_t base;
1200 qemu_irq *irq;
1201 qemu_irq *dma;
1202 uint8_t data;
1203 uint8_t rxfifo[16];
1204 int rxstart;
1205 int rxlen;
1206 #define UART_MAX_CHR 4
1207 int chr_num;
1208 CharDriverState *chr[UART_MAX_CHR];
1209
1210 uint8_t lcontrol;
1211 uint8_t fcontrol;
1212 uint8_t mcontrol;
1213 uint16_t control;
1214 uint16_t brdiv;
1215 uint8_t errstat;
1216 };
1217
1218 static void s3c_uart_reset(struct s3c_uart_state_s *s)
1219 {
1220 s->lcontrol = 0x00;
1221 s->fcontrol = 0x00;
1222 s->mcontrol = 0x00;
1223 s->control = 0x0000;
1224 s->errstat = 0;
1225
1226 s->rxstart = 0;
1227 s->rxlen = 0;
1228 }
1229
1230 static void s3c_uart_err(struct s3c_uart_state_s *s, int err)
1231 {
1232 s->errstat |= err;
1233 if (s->control & (1 << 6))
1234 qemu_irq_raise(s->irq[2]);
1235 }
1236
1237 inline static void s3c_uart_full(struct s3c_uart_state_s *s, int pulse)
1238 {
1239 if (s->fcontrol & 1) /* FIFOEnable */
1240 if (s->rxlen < (((s->fcontrol >> 4) & 3) + 1) * 4) {
1241 if (((s->control >> 0) & 3) != 1 || /* ReceiveMode */
1242 !s->rxlen)
1243 return;
1244 if (!(s->control & (1 << 7))) /* RxTimeOutEnable */
1245 return;
1246 /* When the Rx FIFO trigger level is not reached, the interrupt
1247 * is generated anyway, just after a small timeout instead of
1248 * immediately. */
1249 }
1250
1251 switch ((s->control >> 0) & 3) { /* ReceiveMode */
1252 case 1:
1253 if ((s->control & (1 << 8)) || pulse) /* RxInterruptType */
1254 qemu_irq_raise(s->irq[0]);
1255 break;
1256 case 2:
1257 case 3:
1258 qemu_irq_raise(s->dma[0]);
1259 break;
1260 }
1261 }
1262
1263 inline static void s3c_uart_empty(struct s3c_uart_state_s *s, int pulse)
1264 {
1265 switch ((s->control >> 2) & 3) { /* TransmitMode */
1266 case 1:
1267 if ((s->control & (1 << 9)) || pulse) /* TxInterruptType */
1268 qemu_irq_raise(s->irq[1]);
1269 break;
1270 case 2:
1271 case 3:
1272 qemu_irq_raise(s->dma[0]);
1273 break;
1274 }
1275 }
1276
1277 inline static void s3c_uart_update(struct s3c_uart_state_s *s)
1278 {
1279 s3c_uart_empty(s, 0);
1280 s3c_uart_full(s, 0);
1281 }
1282
1283 static void s3c_uart_params_update(struct s3c_uart_state_s *s)
1284 {
1285 QEMUSerialSetParams ssp;
1286 int i;
1287 if (!s->chr)
1288 return;
1289
1290 /* XXX Calculate PCLK frequency from clock manager registers */
1291 ssp.speed = (s->freq->pclk >> 4) / (s->brdiv + 1);
1292
1293 switch ((s->lcontrol >> 3) & 7) {
1294 case 4:
1295 case 6:
1296 ssp.parity = 'O';
1297 break;
1298 case 5:
1299 case 7:
1300 ssp.parity = 'E';
1301 break;
1302 default:
1303 ssp.parity = 'N';
1304 }
1305
1306 ssp.data_bits = 5 + (s->lcontrol & 3);
1307
1308 ssp.stop_bits = (s->lcontrol & (1 << 2)) ? 2 : 1;
1309
1310 for (i = 0; i < s->chr_num; i ++)
1311 qemu_chr_ioctl(s->chr[i], CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1312 }
1313
1314 static int s3c_uart_is_empty(void *opaque)
1315 {
1316 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1317 if (s->fcontrol & 1) /* FIFOEnable */
1318 return 16 - s->rxlen;
1319 else
1320 return 1 - s->rxlen;
1321 }
1322
1323 static void s3c_uart_rx(void *opaque, const uint8_t *buf, int size)
1324 {
1325 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1326 int left;
1327 if (s->fcontrol & 1) { /* FIFOEnable */
1328 if (s->rxlen + size > 16) {
1329 size = 16 - s->rxlen;
1330 s3c_uart_err(s, 1);
1331 }
1332
1333 left = 16 - ((s->rxstart + s->rxlen) & 15);
1334 if (size > left) {
1335 memcpy(s->rxfifo + ((s->rxstart + s->rxlen) & 15), buf, left);
1336 memcpy(s->rxfifo, buf + left, size - left);
1337 } else
1338 memcpy(s->rxfifo + ((s->rxstart + s->rxlen) & 15), buf, size);
1339 s->rxlen += size;
1340 } else {
1341 if (s->rxlen + size > 1)
1342 s3c_uart_err(s, 1);
1343 s->rxlen = 1;
1344 s->data = buf[0];
1345 }
1346 s3c_uart_full(s, 1);
1347 }
1348
1349 /* S3C2410 UART doesn't seem to understand break conditions. */
1350 static void s3c_uart_event(void *opaque, int event)
1351 {
1352 }
1353
1354 #define S3C_ULCON 0x00 /* UART Line Control register */
1355 #define S3C_UCON 0x04 /* UART Control register */
1356 #define S3C_UFCON 0x08 /* UART FIFO Control register */
1357 #define S3C_UMCON 0x0c /* UART Modem Control register */
1358 #define S3C_UTRSTAT 0x10 /* UART Tx/Rx Status register */
1359 #define S3C_UERSTAT 0x14 /* UART Error Status register */
1360 #define S3C_UFSTAT 0x18 /* UART FIFO Status register */
1361 #define S3C_UMSTAT 0x1c /* UART Modem Status register */
1362 #define S3C_UTXH 0x20 /* UART Transmit Buffer register */
1363 #define S3C_URXH 0x24 /* UART Receive Buffer register */
1364 #define S3C_UBRDIV 0x28 /* UART Baud Rate Divisor register */
1365
1366 static uint32_t s3c_uart_read(void *opaque, target_phys_addr_t addr)
1367 {
1368 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1369 uint8_t ret;
1370
1371 switch (addr) {
1372 case S3C_ULCON:
1373 return s->lcontrol;
1374 case S3C_UCON:
1375 return s->control;
1376 case S3C_UFCON:
1377 return s->fcontrol;
1378 case S3C_UMCON:
1379 return s->mcontrol;
1380 case S3C_UTRSTAT:
1381 return 6 | !!s->rxlen;
1382 case S3C_UERSTAT:
1383 /* XXX: UERSTAT[3] is Reserved but Linux thinks it is BREAK */
1384 ret = s->errstat;
1385 s->errstat = 0;
1386 s3c_uart_update(s);
1387 return ret;
1388 case S3C_UFSTAT:
1389 s3c_uart_update(s);
1390 return s->rxlen ? s->rxlen | (1 << 8) : 0;
1391 case S3C_UMSTAT:
1392 s3c_uart_update(s);
1393 return 0x11;
1394 case S3C_UTXH: /* why this is called by u-boot is not clear */
1395 return 0;
1396 case S3C_URXH:
1397 s3c_uart_update(s);
1398 if (s->rxlen) {
1399 s->rxlen --;
1400 if (s->fcontrol & 1) { /* FIFOEnable */
1401 ret = s->rxfifo[s->rxstart ++];
1402 s->rxstart &= 15;
1403 } else
1404 ret = s->data;
1405 return ret;
1406 }
1407 return 0;
1408 case S3C_UBRDIV:
1409 return s->brdiv;
1410 default:
1411 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1412 break;
1413 }
1414 return 0;
1415 }
1416
1417 static void s3c_uart_write(void *opaque, target_phys_addr_t addr,
1418 uint32_t value)
1419 {
1420 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1421 uint8_t ch;
1422 int i;
1423
1424 switch (addr) {
1425 case S3C_ULCON:
1426 if ((s->lcontrol ^ value) & (1 << 6))
1427 printf("%s: UART Infra-red mode %s\n", __FUNCTION__,
1428 (value & (1 << 6)) ? "on" : "off");
1429 s->lcontrol = value;
1430 s3c_uart_params_update(s);
1431 s3c_uart_update(s);
1432 break;
1433 case S3C_UCON:
1434 /* XXX: UCON[4] is Reserved but Linux thinks it is BREAK */
1435 if ((s->control ^ value) & (1 << 5))
1436 printf("%s: UART loopback test mode %s\n", __FUNCTION__,
1437 (value & (1 << 5)) ? "on" : "off");
1438 s->control = value & 0x7ef;
1439 s3c_uart_update(s);
1440 break;
1441 case S3C_UFCON:
1442 if (value & (1 << 1)) /* RxReset */
1443 s->rxlen = 0;
1444 s->fcontrol = value & 0xf1;
1445 s3c_uart_update(s);
1446 break;
1447 case S3C_UMCON:
1448 #ifdef CONFIG_S3C_MODEM /* not handled, openmoko modem.c not imported */
1449 if ((s->mcontrol ^ value) & (1 << 4)) {
1450 int afc = (value >> 4) & 1;
1451 for (i = 0; i < s->chr_num; i ++)
1452 qemu_chr_ioctl(s->chr[i], CHR_IOCTL_MODEM_HANDSHAKE, &afc);
1453 }
1454 #endif
1455 s->mcontrol = value & 0x11;
1456 s3c_uart_update(s);
1457 break;
1458 case S3C_UTXH:
1459 ch = value & 0xff;
1460 for (i = 0; i < s->chr_num; i ++)
1461 qemu_chr_write(s->chr[i], &ch, 1);
1462 s3c_uart_empty(s, 1);
1463 s3c_uart_update(s);
1464 break;
1465 case S3C_UBRDIV:
1466 s->brdiv = value & 0xffff;
1467 s3c_uart_params_update(s);
1468 s3c_uart_update(s);
1469 break;
1470 default:
1471 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1472 }
1473 }
1474
1475 static CPUReadMemoryFunc *s3c_uart_readfn[] = {
1476 s3c_uart_read,
1477 s3c_uart_read,
1478 s3c_uart_read,
1479 };
1480
1481 static CPUWriteMemoryFunc *s3c_uart_writefn[] = {
1482 s3c_uart_write,
1483 s3c_uart_write,
1484 s3c_uart_write,
1485 };
1486
1487 static void s3c_uart_save(QEMUFile *f, void *opaque)
1488 {
1489 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1490 qemu_put_8s(f, &s->data);
1491 qemu_put_buffer(f, s->rxfifo, sizeof(s->rxfifo));
1492 qemu_put_be32(f, s->rxstart);
1493 qemu_put_be32(f, s->rxlen);
1494 qemu_put_8s(f, &s->lcontrol);
1495 qemu_put_8s(f, &s->fcontrol);
1496 qemu_put_8s(f, &s->mcontrol);
1497 qemu_put_be16s(f, &s->control);
1498 qemu_put_be16s(f, &s->brdiv);
1499 qemu_put_8s(f, &s->errstat);
1500 }
1501
1502 static int s3c_uart_load(QEMUFile *f, void *opaque, int version_id)
1503 {
1504 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1505 qemu_get_8s(f, &s->data);
1506 qemu_get_buffer(f, s->rxfifo, sizeof(s->rxfifo));
1507 s->rxstart = qemu_get_be32(f);
1508 s->rxlen = qemu_get_be32(f);
1509 qemu_get_8s(f, &s->lcontrol);
1510 qemu_get_8s(f, &s->fcontrol);
1511 qemu_get_8s(f, &s->mcontrol);
1512 qemu_get_be16s(f, &s->control);
1513 qemu_get_be16s(f, &s->brdiv);
1514 qemu_get_8s(f, &s->errstat);
1515
1516 return 0;
1517 }
1518
1519 struct s3c_uart_state_s *s3c_uart_init(struct s3c_freq_s * freq, target_phys_addr_t base,
1520 qemu_irq *irqs, qemu_irq *dma)
1521 {
1522 int iomemtype;
1523 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *)
1524 qemu_mallocz(sizeof(struct s3c_uart_state_s));
1525
1526 s->freq = freq;
1527 s->base = base;
1528 s->irq = irqs;
1529 s->dma = dma;
1530
1531 s3c_uart_reset(s);
1532
1533 iomemtype = cpu_register_io_memory(0, s3c_uart_readfn,
1534 s3c_uart_writefn, s);
1535 cpu_register_physical_memory(s->base, 0xfff, iomemtype);
1536
1537 register_savevm("s3c24xx_uart", base, 0, s3c_uart_save, s3c_uart_load, s);
1538
1539 return s;
1540 }
1541
1542 void s3c_uart_attach(struct s3c_uart_state_s *s, CharDriverState *chr)
1543 {
1544 if (s->chr_num >= UART_MAX_CHR)
1545 cpu_abort(cpu_single_env, "%s: Too many devices\n", __FUNCTION__);
1546 s->chr[s->chr_num ++] = chr;
1547
1548 qemu_chr_add_handlers(chr, s3c_uart_is_empty,
1549 s3c_uart_rx, s3c_uart_event, s);
1550 }
1551
1552 /* ADC & Touchscreen interface */
1553 struct s3c_adc_state_s {
1554 target_phys_addr_t base;
1555 qemu_irq irq;
1556 qemu_irq tcirq;
1557 QEMUTimer *convt;
1558 QEMUTimer *tst;
1559 int x;
1560 int y;
1561 int down;
1562 int enable;
1563 int input[8];
1564 int in_idx;
1565 int noise;
1566 int scale[6];
1567
1568 uint16_t control;
1569 uint16_t ts;
1570 uint16_t delay;
1571 int16_t xdata;
1572 int16_t ydata;
1573 };
1574
1575 static void s3c_adc_reset(struct s3c_adc_state_s *s)
1576 {
1577 s->down = 0;
1578 s->control = 0x3fc4;
1579 s->ts = 0x58;
1580 s->delay = 0xff;
1581 s->enable = 1;
1582 }
1583
1584 static void s3c_adc_start(struct s3c_adc_state_s *s)
1585 {
1586 if (!s->enable || (s->ts & 7) == 0)
1587 return;
1588 s->control &= ~(1 << 15);
1589 s->in_idx = (s->control >> 3) & 7;
1590 qemu_mod_timer(s->convt, qemu_get_clock(vm_clock) + (ticks_per_sec >> 5));
1591 }
1592
1593 static void s3c_adc_done(void *opaque)
1594 {
1595 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1596 s->xdata = s->input[s->in_idx] & 0x3ff;
1597 s->control |= 1 << 15;
1598 qemu_irq_raise(s->irq);
1599 }
1600
1601 static void s3c_adc_tick(void *opaque)
1602 {
1603 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1604 int sx, sy;
1605
1606 if (s->down) {
1607 if ((s->ts & 3) == 3 && s->enable)
1608 qemu_irq_raise(s->tcirq);
1609 else if (s->enable && ((s->ts & (1 << 2)) || (s->ts & 3))) {
1610 sx = s->x * s->scale[0] + s->y * s->scale[1] + s->scale[2];
1611 sy = s->x * s->scale[3] + s->y * s->scale[4] + s->scale[5];
1612 s->xdata = ((sx >> 13) & 0xfff) | (1 << 14) | ((s->ts & 3) << 12);
1613 s->ydata = ((sy >> 13) & 0xfff) | (1 << 14) | ((s->ts & 3) << 12);
1614 s->xdata ^= s->noise >> 1;
1615 s->ydata ^= s->noise >> 2;
1616 qemu_irq_raise(s->irq);
1617 s->noise ++;
1618 s->noise &= 7;
1619 }
1620 qemu_mod_timer(s->tst, qemu_get_clock(vm_clock) +
1621 (ticks_per_sec >> 5));
1622 }
1623 }
1624
1625 static void s3c_adc_event(void *opaque,
1626 int x, int y, int z, int buttons_state)
1627 {
1628 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1629 s->down = !!buttons_state;
1630 s->x = x;
1631 s->y = y;
1632 s3c_adc_tick(s);
1633 }
1634
1635 #define S3C_ADCCON 0x00 /* ADC Control register */
1636 #define S3C_ADCTSC 0x04 /* ADC Touchscreen Control register */
1637 #define S3C_ADCDLY 0x08 /* ADC Start or Interval Delay register */
1638 #define S3C_ADCDAT0 0x0c /* ADC Conversion Data register 0 */
1639 #define S3C_ADCDAT1 0x10 /* ADC Conversion Data register 1 */
1640
1641 static uint32_t s3c_adc_read(void *opaque, target_phys_addr_t addr)
1642 {
1643 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1644
1645 switch (addr) {
1646 case S3C_ADCCON:
1647 return s->control;
1648 case S3C_ADCTSC:
1649 return s->ts;
1650 case S3C_ADCDLY:
1651 return s->delay;
1652 case S3C_ADCDAT0:
1653 if (s->control & 2)
1654 s3c_adc_start(s);
1655 return ((!s->down) << 15) | s->xdata;
1656 case S3C_ADCDAT1:
1657 return ((!s->down) << 15) | s->ydata;
1658 default:
1659 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1660 break;
1661 }
1662 return 0;
1663 }
1664
1665 static void s3c_adc_write(void *opaque, target_phys_addr_t addr,
1666 uint32_t value)
1667 {
1668 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1669
1670 switch (addr) {
1671 case S3C_ADCCON:
1672 s->control = (s->control & 0x8000) | (value & 0x7ffe);
1673 s->enable = !(value & 4);
1674 if ((value & 1) && !(value & 2))
1675 s3c_adc_start(s);
1676 if (!s->enable)
1677 qemu_del_timer(s->convt);
1678 s3c_adc_tick(s);
1679 break;
1680
1681 case S3C_ADCTSC:
1682 s->ts = value & 0xff;
1683 break;
1684
1685 case S3C_ADCDLY:
1686 s->delay = value & 0xffff;
1687 break;
1688
1689 default:
1690 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1691 }
1692 }
1693
1694 static CPUReadMemoryFunc *s3c_adc_readfn[] = {
1695 s3c_adc_read,
1696 s3c_adc_read,
1697 s3c_adc_read,
1698 };
1699
1700 static CPUWriteMemoryFunc *s3c_adc_writefn[] = {
1701 s3c_adc_write,
1702 s3c_adc_write,
1703 s3c_adc_write,
1704 };
1705
1706 static void s3c_adc_save(QEMUFile *f, void *opaque)
1707 {
1708 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1709 int i;
1710 qemu_put_be32(f, s->enable);
1711 for (i = 0; i < 8; i ++)
1712 qemu_put_be32(f, s->input[i]);
1713 qemu_put_be32(f, s->in_idx);
1714 qemu_put_be32(f, s->noise);
1715
1716 qemu_put_be16s(f, &s->control);
1717 qemu_put_be16s(f, &s->ts);
1718 qemu_put_be16s(f, &s->delay);
1719 qemu_put_sbe16s(f, &s->xdata);
1720 qemu_put_sbe16s(f, &s->ydata);
1721 }
1722
1723 static int s3c_adc_load(QEMUFile *f, void *opaque, int version_id)
1724 {
1725 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1726 int i;
1727 s->enable = qemu_get_be32(f);
1728 for (i = 0; i < 8; i ++)
1729 s->input[i] = qemu_get_be32(f);
1730 s->in_idx = qemu_get_be32(f);
1731 s->noise = qemu_get_be32(f);
1732
1733 qemu_get_be16s(f, &s->control);
1734 qemu_get_be16s(f, &s->ts);
1735 qemu_get_be16s(f, &s->delay);
1736 qemu_get_sbe16s(f, &s->xdata);
1737 qemu_get_sbe16s(f, &s->ydata);
1738
1739 if (s->enable && (s->ts & 7) && !(s->control & (1 << 15)))
1740 s3c_adc_start(s);
1741
1742 return 0;
1743 }
1744
1745 struct s3c_adc_state_s *s3c_adc_init(target_phys_addr_t base, qemu_irq irq,
1746 qemu_irq tcirq)
1747 {
1748 int iomemtype;
1749 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *)
1750 qemu_mallocz(sizeof(struct s3c_adc_state_s));
1751
1752 s->base = base;
1753 s->irq = irq;
1754 s->tcirq = tcirq;
1755 s->convt = qemu_new_timer(vm_clock, s3c_adc_done, s);
1756 s->tst = qemu_new_timer(vm_clock, s3c_adc_tick, s);
1757
1758 s3c_adc_reset(s);
1759
1760 iomemtype = cpu_register_io_memory(0, s3c_adc_readfn,
1761 s3c_adc_writefn, s);
1762 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1763
1764 /* We want absolute coordinates */
1765 qemu_add_mouse_event_handler(s3c_adc_event, s, 1,
1766 "QEMU S3C2410-driven Touchscreen");
1767
1768 register_savevm("s3c24xx_adc", 0, 0, s3c_adc_save, s3c_adc_load, s);
1769
1770 return s;
1771 }
1772
1773 void s3c_adc_setscale(struct s3c_adc_state_s *adc, const int m[])
1774 {
1775 memcpy(adc->scale, m, 6 * sizeof(int));
1776 }
1777
1778 /* IIC-bus serial interface */
1779 struct s3c_i2c_state_s {
1780 i2c_slave slave;
1781 i2c_bus *bus;
1782 target_phys_addr_t base;
1783 qemu_irq irq;
1784
1785 uint8_t control;
1786 uint8_t status;
1787 uint8_t data;
1788 uint8_t addy;
1789 uint8_t mmaster;
1790 int busy;
1791 int newstart;
1792 };
1793
1794 static void s3c_i2c_irq(struct s3c_i2c_state_s *s)
1795 {
1796 s->control |= 1 << 4;
1797 if (s->control & (1 << 5))
1798 qemu_irq_raise(s->irq);
1799 }
1800
1801 static void s3c_i2c_reset(struct s3c_i2c_state_s *s)
1802 {
1803 s->control = 0x00;
1804 s->status = 0x00;
1805 s->busy = 0;
1806 s->newstart = 0;
1807 s->mmaster = 0;
1808 }
1809
1810 static void s3c_i2c_event(i2c_slave *i2c, enum i2c_event event)
1811 {
1812 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1813 if (!(s->status & (1 << 4)))
1814 return;
1815
1816 switch (event) {
1817 case I2C_START_RECV:
1818 case I2C_START_SEND:
1819 s->status |= 1 << 2;
1820 s3c_i2c_irq(s);
1821 break;
1822 case I2C_FINISH:
1823 s->status &= ~6;
1824 break;
1825 case I2C_NACK:
1826 s->status |= 1 << 0;
1827 break;
1828 default:
1829 break;
1830 }
1831 }
1832
1833 static int s3c_i2c_tx(i2c_slave *i2c, uint8_t data)
1834 {
1835 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1836 if (!(s->status & (1 << 4)))
1837 return 1;
1838
1839 if ((s->status >> 6) == 0)
1840 s->data = data; /* TODO */
1841 s->status &= ~(1 << 0);
1842 s3c_i2c_irq(s);
1843
1844 return !(s->control & (1 << 7));
1845 }
1846
1847 static int s3c_i2c_rx(i2c_slave *i2c)
1848 {
1849 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1850 if (!(s->status & (1 << 4)))
1851 return 1;
1852
1853 if ((s->status >> 6) == 1) {
1854 s->status &= ~(1 << 0);
1855 s3c_i2c_irq(s);
1856 return s->data;
1857 }
1858
1859 return 0x00;
1860 }
1861
1862 static void s3c_master_work(void *opaque)
1863 {
1864 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1865 int start = 0, stop = 0, ack = 1;
1866 if (s->control & (1 << 4)) /* Interrupt pending */
1867 return;
1868 if ((s->status & 0x90) != 0x90) /* Master */
1869 return;
1870 stop = ~s->status & (1 << 5);
1871 if (s->newstart && s->status & (1 << 5)) { /* START */
1872 s->busy = 1;
1873 start = 1;
1874 }
1875 s->newstart = 0;
1876 if (!s->busy)
1877 return;
1878
1879 if (start)
1880 ack = !i2c_start_transfer(s->bus, s->data >> 1, (~s->status >> 6) & 1);
1881 else if (stop)
1882 i2c_end_transfer(s->bus);
1883 else if (s->status & (1 << 6))
1884 ack = !i2c_send(s->bus, s->data);
1885 else {
1886 s->data = i2c_recv(s->bus);
1887
1888 if (!(s->control & (1 << 7))) /* ACK */
1889 i2c_nack(s->bus);
1890 }
1891
1892 if (!(s->status & (1 << 5))) {
1893 s->busy = 0;
1894 return;
1895 }
1896 s->status &= ~1;
1897 s->status |= !ack;
1898 if (!ack)
1899 s->busy = 0;
1900 s3c_i2c_irq(s);
1901 }
1902
1903 #define S3C_IICCON 0x00 /* IIC-Bus Control register */
1904 #define S3C_IICSTAT 0x04 /* IIC-Bus Control / Status register */
1905 #define S3C_IICADD 0x08 /* IIC-Bus Address register */
1906 #define S3C_IICDS 0x0c /* IIC-Bus Tx / Rx Data Shift register */
1907
1908 #define S3C2440_IICLC 0x10 /* IIC-Bus multi-master line control register */
1909
1910 static uint32_t s3c_i2c_read(void *opaque, target_phys_addr_t addr)
1911 {
1912 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1913
1914 switch (addr) {
1915 case S3C_IICCON:
1916 return s->control;
1917 case S3C_IICSTAT:
1918 return s->status & ~(1 << 5); /* Busy signal */
1919 case S3C_IICADD:
1920 return s->addy;
1921 case S3C_IICDS:
1922 return s->data;
1923 case S3C2440_IICLC: /* s3c2440 only ! */
1924 return s->mmaster;
1925 default:
1926 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1927 break;
1928 }
1929 return 0;
1930 }
1931
1932 static void s3c_i2c_write(void *opaque, target_phys_addr_t addr,
1933 uint32_t value)
1934 {
1935 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1936
1937 switch (addr) {
1938 case S3C_IICCON:
1939 s->control = (s->control | 0xef) & value;
1940 if (s->busy)
1941 s3c_master_work(s);
1942 break;
1943
1944 case S3C_IICSTAT:
1945 s->status &= 0x0f;
1946 s->status |= value & 0xf0;
1947 if (s->status & (1 << 5))
1948 s->newstart = 1;
1949 s3c_master_work(s);
1950 break;
1951
1952 case S3C_IICADD:
1953 s->addy = value & 0x7f;
1954 i2c_set_slave_address(&s->slave, s->addy);
1955 break;
1956
1957 case S3C_IICDS:
1958 s->data = value & 0xff;
1959 break;
1960
1961 case S3C2440_IICLC: /* s3c2440 only ! */
1962 s->mmaster = value & 0xff;
1963 break;
1964
1965 default:
1966 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1967 }
1968 }
1969
1970 static CPUReadMemoryFunc *s3c_i2c_readfn[] = {
1971 s3c_i2c_read,
1972 s3c_i2c_read,
1973 s3c_i2c_read,
1974 };
1975
1976 static CPUWriteMemoryFunc *s3c_i2c_writefn[] = {
1977 s3c_i2c_write,
1978 s3c_i2c_write,
1979 s3c_i2c_write,
1980 };
1981
1982 static void s3c_i2c_save(QEMUFile *f, void *opaque)
1983 {
1984 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1985 qemu_put_8s(f, &s->control);
1986 qemu_put_8s(f, &s->status);
1987 qemu_put_8s(f, &s->data);
1988 qemu_put_8s(f, &s->addy);
1989 qemu_put_8s(f, &s->mmaster);
1990
1991 qemu_put_be32(f, s->busy);
1992 qemu_put_be32(f, s->newstart);
1993
1994 i2c_slave_save(f, &s->slave);
1995 }
1996
1997 static int s3c_i2c_load(QEMUFile *f, void *opaque, int version_id)
1998 {
1999 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
2000 qemu_get_8s(f, &s->control);
2001 qemu_get_8s(f, &s->status);
2002 qemu_get_8s(f, &s->data);
2003 qemu_get_8s(f, &s->addy);
2004 qemu_get_8s(f, &s->mmaster);
2005
2006 s->busy = qemu_get_be32(f);
2007 s->newstart = qemu_get_be32(f);
2008
2009 i2c_slave_load(f, &s->slave);
2010 return 0;
2011 }
2012
2013 struct s3c_i2c_state_s *s3c_i2c_init(target_phys_addr_t base, qemu_irq irq)
2014 {
2015 int iomemtype;
2016 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *)
2017 qemu_mallocz(sizeof(struct s3c_i2c_state_s));
2018
2019 s->base = base;
2020 s->irq = irq;
2021 s->slave.event = s3c_i2c_event;
2022 s->slave.send = s3c_i2c_tx;
2023 s->slave.recv = s3c_i2c_rx;
2024 s->bus = i2c_init_bus();
2025
2026 s3c_i2c_reset(s);
2027
2028 iomemtype = cpu_register_io_memory(0, s3c_i2c_readfn,
2029 s3c_i2c_writefn, s);
2030 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2031
2032 register_savevm("s3c24xx_i2c", 0, 0, s3c_i2c_save, s3c_i2c_load, s);
2033
2034 return s;
2035 }
2036
2037 i2c_bus *s3c_i2c_bus(struct s3c_i2c_state_s *s)
2038 {
2039 return s->bus;
2040 }
2041
2042 /* Serial Peripheral Interface */
2043 struct s3c_spi_state_s {
2044 target_phys_addr_t base;
2045
2046 struct {
2047 qemu_irq irq;
2048 qemu_irq drq;
2049 qemu_irq miso;
2050
2051 uint8_t control;
2052 uint8_t pin;
2053 uint8_t pre;
2054
2055 int cs_pin;
2056 int clk_pin;
2057 int mosi_pin;
2058 uint8_t txbuf;
2059 uint8_t rxbuf;
2060 int bit;
2061 } chan[2];
2062
2063 uint8_t (*txrx[2])(void *opaque, uint8_t value);
2064 uint8_t (*btxrx[2])(void *opaque, uint8_t value);
2065 void *opaque[2];
2066 };
2067
2068 static void s3c_spi_update(struct s3c_spi_state_s *s)
2069 {
2070 int i;
2071 for (i = 0; i < 2; i ++) {
2072 switch ((s->chan[i].control >> 5) & 3) { /* SMOD */
2073 case 1:
2074 qemu_irq_raise(s->chan[i].irq);
2075 break;
2076 case 2:
2077 qemu_irq_raise(s->chan[i].drq);
2078 break;
2079 }
2080 }
2081 }
2082
2083 static void s3c_spi_reset(struct s3c_spi_state_s *s)
2084 {
2085 memset(s->chan, 0, sizeof(s->chan));
2086 s->chan[0].pin = 0x02;
2087 s->chan[1].pin = 0x02;
2088 s3c_spi_update(s);
2089 }
2090
2091 #define S3C_SPCON0 0x00 /* SPI channel 0 control register */
2092 #define S3C_SPSTA0 0x04 /* SPI channel 0 status register */
2093 #define S3C_SPPIN0 0x08 /* SPI channel 0 pin control register */
2094 #define S3C_SPPRE0 0x0c /* SPI channel 0 baudrate prescaler register */
2095 #define S3C_SPTDAT0 0x10 /* SPI channel 0 Tx data register */
2096 #define S3C_SPRDAT0 0x14 /* SPI channel 0 Rx data register */
2097 #define S3C_SPCON1 0x20 /* SPI channel 1 control register */
2098 #define S3C_SPSTA1 0x24 /* SPI channel 1 status register */
2099 #define S3C_SPPIN1 0x28 /* SPI channel 1 pin control register */
2100 #define S3C_SPPRE1 0x2c /* SPI channel 1 baudrate prescaler register */
2101 #define S3C_SPTDAT1 0x30 /* SPI channel 1 Tx data register */
2102 #define S3C_SPRDAT1 0x34 /* SPI channel 1 Rx data register */
2103
2104 static uint32_t s3c_spi_read(void *opaque, target_phys_addr_t addr)
2105 {
2106 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2107 int ch;
2108
2109 ch = addr >> 5;
2110
2111 switch (addr) {
2112 case S3C_SPCON0:
2113 case S3C_SPCON1:
2114 return s->chan[ch].control;
2115
2116 case S3C_SPSTA0:
2117 case S3C_SPSTA1:
2118 return 0x01;
2119
2120 case S3C_SPPIN0:
2121 case S3C_SPPIN1:
2122 return s->chan[ch].pin;
2123
2124 case S3C_SPPRE0:
2125 case S3C_SPPRE1:
2126 return s->chan[ch].pre;
2127
2128 case S3C_SPTDAT0:
2129 case S3C_SPTDAT1:
2130 return s->chan[ch + 2].txbuf;
2131
2132 case S3C_SPRDAT0:
2133 case S3C_SPRDAT1:
2134 if (s->txrx[ch] && (s->chan[ch].control & 0x19) == 0x19)
2135 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], 'Q');
2136 s3c_spi_update(s);
2137 return s->chan[ch].rxbuf;
2138
2139 default:
2140 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2141 break;
2142 }
2143 return 0;
2144 }
2145
2146 static void s3c_spi_write(void *opaque, target_phys_addr_t addr,
2147 uint32_t value)
2148 {
2149 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2150 int ch;
2151
2152 ch = addr >> 5;
2153
2154 switch (addr) {
2155 case S3C_SPCON0:
2156 case S3C_SPCON1:
2157 s->chan[ch].control = value & 0x7f;
2158 s3c_spi_update(s);
2159 break;
2160
2161 case S3C_SPPIN0:
2162 case S3C_SPPIN1:
2163 s->chan[ch].pin = value & 0x07;
2164 break;
2165
2166 case S3C_SPPRE0:
2167 case S3C_SPPRE1:
2168 s->chan[ch].pre = value & 0xff;
2169 break;
2170
2171 case S3C_SPTDAT0:
2172 case S3C_SPTDAT1:
2173 s->chan[ch].txbuf = value & 0xff;
2174 if (s->txrx[ch] && (s->chan[ch].control & 0x19) == 0x18)
2175 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], value & 0xff);
2176 s3c_spi_update(s);
2177 break;
2178
2179 default:
2180 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2181 }
2182 }
2183
2184 static CPUReadMemoryFunc *s3c_spi_readfn[] = {
2185 s3c_spi_read,
2186 s3c_spi_read,
2187 s3c_spi_read,
2188 };
2189
2190 static CPUWriteMemoryFunc *s3c_spi_writefn[] = {
2191 s3c_spi_write,
2192 s3c_spi_write,
2193 s3c_spi_write,
2194 };
2195
2196 static void s3c_spi_save(QEMUFile *f, void *opaque)
2197 {
2198 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2199 int i;
2200 for (i = 0; i < 2; i ++) {
2201 qemu_put_8s(f, &s->chan[i].control);
2202 qemu_put_8s(f, &s->chan[i].pin);
2203 qemu_put_8s(f, &s->chan[i].pre);
2204
2205 qemu_put_8s(f, &s->chan[i].txbuf);
2206 qemu_put_8s(f, &s->chan[i].rxbuf);
2207 qemu_put_be32(f, s->chan[i].cs_pin);
2208 qemu_put_be32(f, s->chan[i].clk_pin);
2209 qemu_put_be32(f, s->chan[i].mosi_pin);
2210 qemu_put_be32(f, s->chan[i].bit);
2211 }
2212 }
2213
2214 static int s3c_spi_load(QEMUFile *f, void *opaque, int version_id)
2215 {
2216 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2217 int i;
2218 for (i = 0; i < 2; i ++) {
2219 qemu_get_8s(f, &s->chan[i].control);
2220 qemu_get_8s(f, &s->chan[i].pin);
2221 qemu_get_8s(f, &s->chan[i].pre);
2222
2223 qemu_get_8s(f, &s->chan[i].txbuf);
2224 qemu_get_8s(f, &s->chan[i].rxbuf);
2225 s->chan[i].cs_pin = qemu_get_be32(f);
2226 s->chan[i].clk_pin = qemu_get_be32(f);
2227 s->chan[i].mosi_pin = qemu_get_be32(f);
2228 s->chan[i].bit = qemu_get_be32(f);
2229 }
2230
2231 return 0;
2232 }
2233
2234 static void s3c_spi_bitbang_cs(void *opaque, int line, int level)
2235 {
2236 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2237 int ch = line;
2238 if (s->chan[ch].cs_pin || level) {
2239 if (s->chan[ch].bit && s->txrx[ch] && !s->btxrx[ch]) {
2240 s->chan[ch].txbuf <<= 8 - s->chan[ch].bit;
2241 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], s->chan[ch].txbuf);
2242 }
2243 } else if (!s->chan[ch].cs_pin || !level)
2244 s->chan[ch].bit = 0;
2245
2246 /* SSn is active low. */
2247 s->chan[ch].cs_pin = !level;
2248 }
2249
2250 static void s3c_spi_bitbang_clk(void *opaque, int line, int level)
2251 {
2252 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2253 int ch = line;
2254 if (!s->chan[ch].cs_pin)
2255 goto done;
2256
2257 /* Detect CLK rising edge */
2258 if (s->chan[ch].clk_pin || !level)
2259 goto done;
2260
2261 if (s->btxrx[ch]) {
2262 qemu_set_irq(s->chan[ch].miso,
2263 s->btxrx[ch](s->opaque[ch], s->chan[ch].mosi_pin));
2264 goto done;
2265 }
2266
2267 s->chan[ch].txbuf <<= 1;
2268 s->chan[ch].txbuf |= s->chan[ch].mosi_pin;
2269
2270 qemu_set_irq(s->chan[ch].miso, (s->chan[ch].rxbuf >> 7) & 1);
2271 s->chan[ch].rxbuf <<= 1;
2272
2273 if (++ s->chan[ch].bit == 8) {
2274 if (s->txrx[ch])
2275 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], s->chan[ch].txbuf);
2276 s->chan[ch].bit = 0;
2277 }
2278
2279 done:
2280 s->chan[ch].clk_pin = level;
2281 }
2282
2283 static void s3c_spi_bitbang_mosi(void *opaque, int line, int level)
2284 {
2285 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2286 int ch = line;
2287 s->chan[ch].mosi_pin = level;
2288 }
2289
2290 static const struct {
2291 int cs, clk, miso, mosi;
2292 } s3c_spi_pins[2] = {
2293 { S3C_GPG(2), S3C_GPE(13), S3C_GPE(11), S3C_GPE(12) },
2294 { S3C_GPG(3), S3C_GPG(7), S3C_GPG(5), S3C_GPG(6) },
2295 };
2296
2297 static void s3c_spi_bitbang_init(struct s3c_spi_state_s *s,
2298 struct s3c_gpio_state_s *gpio)
2299 {
2300 int i;
2301 qemu_irq *cs = qemu_allocate_irqs(s3c_spi_bitbang_cs, s, 2);
2302 qemu_irq *clk = qemu_allocate_irqs(s3c_spi_bitbang_clk, s, 2);
2303 qemu_irq *mosi = qemu_allocate_irqs(s3c_spi_bitbang_mosi, s, 2);
2304
2305 for (i = 0; i < 2; i ++) {
2306 s3c_gpio_out_set(gpio, s3c_spi_pins[i].cs, cs[i]);
2307 s3c_gpio_out_set(gpio, s3c_spi_pins[i].clk, clk[i]);
2308 s->chan[i].miso = s3c_gpio_in_get(gpio)[s3c_spi_pins[i].miso];
2309 s3c_gpio_out_set(gpio, s3c_spi_pins[i].mosi, mosi[i]);
2310 }
2311 }
2312
2313 struct s3c_spi_state_s *s3c_spi_init(target_phys_addr_t base,
2314 qemu_irq irq0, qemu_irq drq0, qemu_irq irq1, qemu_irq drq1,
2315 struct s3c_gpio_state_s *gpio)
2316 {
2317 int iomemtype;
2318 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *)
2319 qemu_mallocz(sizeof(struct s3c_spi_state_s));
2320
2321 s->base = base;
2322 s->chan[0].irq = irq0;
2323 s->chan[0].drq = drq0;
2324 s->chan[1].irq = irq1;
2325 s->chan[1].drq = drq1;
2326
2327 s3c_spi_reset(s);
2328
2329 iomemtype = cpu_register_io_memory(0, s3c_spi_readfn,
2330 s3c_spi_writefn, s);
2331 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2332
2333 s3c_spi_bitbang_init(s, gpio);
2334
2335 register_savevm("s3c24xx_spi", 0, 0, s3c_spi_save, s3c_spi_load, s);
2336
2337 return s;
2338 }
2339
2340 void s3c_spi_attach(struct s3c_spi_state_s *s, int ch,
2341 uint8_t (*txrx)(void *opaque, uint8_t value),
2342 uint8_t (*btxrx)(void *opaque, uint8_t value), void *opaque)
2343 {
2344 if (ch & ~1)
2345 cpu_abort(cpu_single_env, "%s: No channel %i\n", __FUNCTION__, ch);
2346 s->txrx[ch] = txrx;
2347 s->btxrx[ch] = btxrx;
2348 s->opaque[ch] = opaque;
2349 }
2350
2351 /* IIS-BUS interface */
2352 static inline void s3c_i2s_update(struct s3c_i2s_state_s *s)
2353 {
2354 s->tx_en =
2355 (s->control & (1 << 0)) && !(s->control & (1 << 3)) &&
2356 (s->mode & (1 << 7)) && (s->fcontrol & (1 << 13));
2357 s->rx_en =
2358 (s->control & (1 << 0)) && !(s->control & (1 << 2)) &&
2359 (s->mode & (1 << 6)) && (s->fcontrol & (1 << 12));
2360 s->control &= ~0xc0;
2361 /* The specs are unclear about the FIFO-ready flags logic.
2362 * Implement semantics that make most sense. */
2363 if (s->tx_en && s->tx_len)
2364 s->control |= (1 << 7);
2365 if (s->rx_en && s->rx_len)
2366 s->control |= (1 << 6);
2367
2368 qemu_set_irq(s->dma[S3C_RQ_I2SSDO], (s->control >> 5) &
2369 (s->control >> 7) & (s->fcontrol >> 15) & 1);
2370 qemu_set_irq(s->dma[S3C_RQ_I2SSDI0], (s->control >> 4) &
2371 (s->control >> 6) & (s->fcontrol >> 14) & 1);
2372 qemu_set_irq(s->dma[S3C_RQ_I2SSDI1], (s->control >> 4) &
2373 (s->control >> 6) & (s->fcontrol >> 14) & 1);
2374 }
2375
2376 static void s3c_i2s_reset(struct s3c_i2s_state_s *s)
2377 {
2378 s->control = 0x100;
2379 s->mode = 0x000;
2380 s->prescaler = 0x000;
2381 s->fcontrol = 0x0000;
2382 s->tx_len = 0;
2383 s->rx_len = 0;
2384 s3c_i2s_update(s);
2385 }
2386
2387 #define S3C_IISCON 0x00 /* IIS Control register */
2388 #define S3C_IISMOD 0x04 /* IIS Mode register */
2389 #define S3C_IISPSR 0x08 /* IIS Prescaler register */
2390 #define S3C_IISFCON 0x0c /* IIS FIFO Interface register */
2391 #define S3C_IISFIFO 0x10 /* IIS FIFO register */
2392
2393 static uint32_t s3c_i2s_read(void *opaque, target_phys_addr_t addr)
2394 {
2395 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2396 uint32_t ret;
2397
2398 switch (addr) {
2399 case S3C_IISCON:
2400 return s->control;
2401 case S3C_IISMOD:
2402 return s->mode;
2403 case S3C_IISPSR:
2404 return s->prescaler;
2405 case S3C_IISFCON:
2406 return s->fcontrol |
2407 (MAX(32 - s->tx_len, 0) << 6) |
2408 MIN(s->rx_len, 32);
2409 case S3C_IISFIFO:
2410 if (s->rx_len > 0) {
2411 s->rx_len --;
2412 s3c_i2s_update(s);
2413 s->cycle ^= 1;
2414 if (s->cycle) {
2415 s->buffer = (uint16_t) (ret = s->codec_in(s->opaque));
2416 return ret >> 16;
2417 } else
2418 return s->buffer;
2419 }
2420 default:
2421 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2422 break;
2423 }
2424 return 0;
2425 }
2426
2427 static void s3c_i2s_write(void *opaque, target_phys_addr_t addr,
2428 uint32_t value)
2429 {
2430 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2431
2432 switch (addr) {
2433 case S3C_IISCON:
2434 s->control = (s->control & 0x100) | (value & 0x03f);
2435 s3c_i2s_update(s);
2436 break;
2437 case S3C_IISMOD:
2438 s->mode = value & 0x1ff;
2439 s3c_i2s_update(s);
2440 break;
2441 case S3C_IISPSR:
2442 s->prescaler = value & 0x3ff;
2443 break;
2444 case S3C_IISFCON:
2445 s->fcontrol = value & 0xf000;
2446 s3c_i2s_update(s);
2447 break;
2448 case S3C_IISFIFO:
2449 if (s->tx_len && s->tx_en) {
2450 s->tx_len --;
2451 s3c_i2s_update(s);
2452 if (s->cycle)
2453 s->codec_out(s->opaque, value | ((uint32_t) s->buffer << 16));
2454 else
2455 s->buffer = (uint16_t) value;
2456 s->cycle ^= 1;
2457 }
2458 break;
2459 default:
2460 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2461 }
2462 }
2463
2464 static CPUReadMemoryFunc *s3c_i2s_readfn[] = {
2465 s3c_i2s_read,
2466 s3c_i2s_read,
2467 s3c_i2s_read,
2468 };
2469
2470 static CPUWriteMemoryFunc *s3c_i2s_writefn[] = {
2471 s3c_i2s_write,
2472 s3c_i2s_write,
2473 s3c_i2s_write,
2474 };
2475
2476 static void s3c_i2s_save(QEMUFile *f, void *opaque)
2477 {
2478 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2479 qemu_put_be16s(f, &s->control);
2480 qemu_put_be16s(f, &s->mode);
2481 qemu_put_be16s(f, &s->prescaler);
2482 qemu_put_be16s(f, &s->fcontrol);
2483
2484 qemu_put_be32(f, s->tx_en);
2485 qemu_put_be32(f, s->rx_en);
2486 qemu_put_be32(f, s->tx_len);
2487 qemu_put_be32(f, s->rx_len);
2488 qemu_put_be16(f, s->buffer);
2489 qemu_put_be32(f, s->cycle);
2490 }
2491
2492 static int s3c_i2s_load(QEMUFile *f, void *opaque, int version_id)
2493 {
2494 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2495 qemu_get_be16s(f, &s->control);
2496 qemu_get_be16s(f, &s->mode);
2497 qemu_get_be16s(f, &s->prescaler);
2498 qemu_get_be16s(f, &s->fcontrol);
2499
2500 s->tx_en = qemu_get_be32(f);
2501 s->rx_en = qemu_get_be32(f);
2502 s->tx_len = qemu_get_be32(f);
2503 s->rx_len = qemu_get_be32(f);
2504 s->buffer = qemu_get_be16(f);
2505 s->cycle = qemu_get_be32(f);
2506
2507 return 0;
2508 }
2509
2510 static void s3c_i2s_data_req(void *opaque, int tx, int rx)
2511 {
2512 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2513 s->tx_len = tx;
2514 s->rx_len = rx;
2515 s3c_i2s_update(s);
2516 }
2517
2518 struct s3c_i2s_state_s *s3c_i2s_init(target_phys_addr_t base, qemu_irq *dma)
2519 {
2520 int iomemtype;
2521 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *)
2522 qemu_mallocz(sizeof(struct s3c_i2s_state_s));
2523
2524 s->base = base;
2525 s->dma = dma;
2526 s->data_req = s3c_i2s_data_req;
2527
2528 s3c_i2s_reset(s);
2529
2530 iomemtype = cpu_register_io_memory(0, s3c_i2s_readfn,
2531 s3c_i2s_writefn, s);
2532 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2533
2534 register_savevm("s3c24xx_iis", 0, 0, s3c_i2s_save, s3c_i2s_load, s);
2535
2536 return s;
2537 }
2538
2539 /* Watchdog Timer */
2540 struct s3c_wdt_state_s {
2541 struct s3c_freq_s * freq;
2542 target_phys_addr_t base;
2543 qemu_irq irq;
2544 uint16_t control;
2545 uint16_t data;
2546 uint16_t count;
2547 QEMUTimer *tm;
2548 int64_t timestamp;
2549 };
2550
2551 static void s3c_wdt_start(struct s3c_wdt_state_s *s)
2552 {
2553 int enable = s->control & (1 << 5);
2554 int prescaler = (s->control >> 8) + 1;
2555 int divider = prescaler << (((s->control >> 3) & 3) + 4);
2556 if (enable) {
2557 s->timestamp = qemu_get_clock(vm_clock);
2558 qemu_mod_timer(s->tm, s->timestamp + muldiv64(divider * s->count,
2559 ticks_per_sec, s->freq->pclk));
2560 } else
2561 qemu_del_timer(s->tm);
2562 }
2563
2564 static void s3c_wdt_stop(struct s3c_wdt_state_s *s)
2565 {
2566 int prescaler = (s->control >> 8) + 1;
2567 int divider = prescaler << (((s->control >> 3) & 3) + 4);
2568 int diff;
2569
2570 diff = muldiv64(qemu_get_clock(vm_clock) - s->timestamp, s->freq->pclk,
2571 ticks_per_sec) / divider;
2572 s->count -= MIN(s->count, diff);
2573 s->timestamp = qemu_get_clock(vm_clock);
2574 }
2575
2576 static void s3c_wdt_reset(struct s3c_wdt_state_s *s)
2577 {
2578 s->control = 0x8021;
2579 s->data = 0x8000;
2580 s->count = 0x8000;
2581 s3c_wdt_start(s);
2582 }
2583
2584 static void s3c_wdt_timeout(void *opaque)
2585 {
2586 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2587 if (s->control & (1 << 0)) {
2588 qemu_system_reset_request();
2589 return;
2590 }
2591 if (s->control & (1 << 2))
2592 qemu_irq_raise(s->irq);
2593 s->count = s->data;
2594 s3c_wdt_start(s);
2595 }
2596
2597 #define S3C_WTCON 0x00 /* Watchdog timer control register */
2598 #define S3C_WTDAT 0x04 /* Watchdog timer data register */
2599 #define S3C_WTCNT 0x08 /* Watchdog timer count register */
2600
2601 static uint32_t s3c_wdt_read(void *opaque, target_phys_addr_t addr)
2602 {
2603 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2604
2605 switch (addr) {
2606 case S3C_WTCON:
2607 return s->control;
2608 case S3C_WTDAT:
2609 return s->data;
2610 case S3C_WTCNT:
2611 s3c_wdt_stop(s);
2612 return s->count;
2613 default:
2614 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2615 break;
2616 }
2617 return 0;
2618 }
2619
2620 static void s3c_wdt_write(void *opaque, target_phys_addr_t addr,
2621 uint32_t value)
2622 {
2623 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2624
2625 switch (addr) {
2626 case S3C_WTCON:
2627 s3c_wdt_stop(s);
2628 s->control = value;
2629 s3c_wdt_start(s);
2630 break;
2631 case S3C_WTDAT:
2632 s->data = value;
2633 break;
2634 case S3C_WTCNT:
2635 s->count = value;
2636 s3c_wdt_start(s);
2637 break;
2638 default:
2639 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2640 }
2641 }
2642
2643 static CPUReadMemoryFunc *s3c_wdt_readfn[] = {
2644 s3c_wdt_read,
2645 s3c_wdt_read,
2646 s3c_wdt_read,
2647 };
2648
2649 static CPUWriteMemoryFunc *s3c_wdt_writefn[] = {
2650 s3c_wdt_write,
2651 s3c_wdt_write,
2652 s3c_wdt_write,
2653 };
2654
2655 static void s3c_wdt_save(QEMUFile *f, void *opaque)
2656 {
2657 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2658
2659 s3c_wdt_stop(s);
2660 qemu_put_be16s(f, &s->control);
2661 qemu_put_be16s(f, &s->data);
2662 qemu_put_be16s(f, &s->count);
2663 qemu_put_sbe64s(f, &s->timestamp);
2664 }
2665
2666 static int s3c_wdt_load(QEMUFile *f, void *opaque, int version_id)
2667 {
2668 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2669
2670 qemu_get_be16s(f, &s->control);
2671 qemu_get_be16s(f, &s->data);
2672 qemu_get_be16s(f, &s->count);
2673 qemu_get_sbe64s(f, &s->timestamp);
2674 s3c_wdt_start(s);
2675
2676 return 0;
2677 }
2678
2679 struct s3c_wdt_state_s *s3c_wdt_init(struct s3c_freq_s * freq, target_phys_addr_t base, qemu_irq irq)
2680 {
2681 int iomemtype;
2682 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *)
2683 qemu_mallocz(sizeof(struct s3c_wdt_state_s));
2684
2685 s->freq = freq;
2686 s->base = base;
2687 s->irq = irq;
2688 s->tm = qemu_new_timer(vm_clock, s3c_wdt_timeout, s);
2689
2690 s3c_wdt_reset(s);
2691
2692 iomemtype = cpu_register_io_memory(0, s3c_wdt_readfn,
2693 s3c_wdt_writefn, s);
2694 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2695
2696 register_savevm("s3c24xx_wdt", 0, 0, s3c_wdt_save, s3c_wdt_load, s);
2697
2698 return s;
2699 }
2700
2701 /* On-chip UARTs */
2702 static struct {
2703 target_phys_addr_t base;
2704 int irq[3];
2705 int dma[1];
2706 } s3c2410_uart[] = {
2707 {
2708 0x50000000,
2709 { S3C_PICS_RXD0, S3C_PICS_TXD0, S3C_PICS_ERR0 },
2710 { S3C_RQ_UART0 },
2711 },
2712 {
2713 0x50004000,
2714 { S3C_PICS_RXD1, S3C_PICS_TXD1, S3C_PICS_ERR1 },
2715 { S3C_RQ_UART1 },
2716 },
2717 {
2718 0x50008000,
2719 { S3C_PICS_RXD2, S3C_PICS_TXD2, S3C_PICS_ERR2 },
2720 { S3C_RQ_UART2 },
2721 },
2722 { 0, { 0, 0, 0 }, { 0 } }
2723 };
2724
2725 /* General CPU reset */
2726 static void s3c2410_reset(void *opaque)
2727 {
2728 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
2729 int i;
2730 s3c_mc_reset(s);
2731 s3c_pic_reset(s->pic);
2732 s3c_dma_reset(s->dma);
2733 s3c_gpio_reset(s->io);
2734 s3c_lcd_reset(s->lcd);
2735 s3c_timers_reset(s->timers);
2736 s3c_mmci_reset(s->mmci);
2737 s3c_adc_reset(s->adc);
2738 s3c_i2c_reset(s->i2c);
2739 s3c_i2s_reset(s->i2s);
2740 s3c_rtc_reset(s->rtc);
2741 s3c_spi_reset(s->spi);
2742 s3c_udc_reset(s->udc);
2743 s3c_wdt_reset(s->wdt);
2744 s3c_clkpwr_reset(s);
2745 s->nand->reset(s->nand);
2746 for (i = 0; s3c2410_uart[i].base; i ++)
2747 s3c_uart_reset(s->uart[i]);
2748 cpu_reset(s->env);
2749 }
2750
2751 struct s3c_state_s * g_s3c;
2752
2753 /* Initialise an S3C24XX microprocessor. */
2754 struct s3c_state_s *s3c24xx_init(
2755 uint32_t cpu_id,
2756 uint32_t xtal,
2757 unsigned int sdram_size,
2758 uint32_t sram_address,
2759 SDState *mmc)
2760 {
2761 struct s3c_state_s *s;
2762 int iomemtype, i;
2763 s = (struct s3c_state_s *) qemu_mallocz(sizeof(struct s3c_state_s));
2764
2765 g_s3c = s;
2766
2767 s->cpu_id = cpu_id;
2768 s->clock.xtal = xtal;
2769 s->clock.pclk = 66500000; // S3C_PCLK_FREQ; // TEMP
2770
2771 s->env = cpu_init("arm920t");
2772 if (!s->env) {
2773 fprintf(stderr, "Unable to initialize ARM920T\n");
2774 exit(2);
2775 }
2776 register_savevm("s3c24xx", 0, 0,
2777 cpu_save, cpu_load, s->env);
2778
2779 cpu_register_physical_memory(S3C_RAM_BASE, sdram_size,
2780 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2781
2782 /* If OM pins are 00, SRAM is mapped at 0x0 instead. */
2783 cpu_register_physical_memory(sram_address, S3C_SRAM_SIZE,
2784 qemu_ram_alloc(S3C_SRAM_SIZE) | IO_MEM_RAM);
2785
2786 s->mc_base = 0x48000000;
2787 s3c_mc_reset(s);
2788 iomemtype = cpu_register_io_memory(0, s3c_mc_readfn, s3c_mc_writefn, s);
2789 cpu_register_physical_memory(s->mc_base, 0xffffff, iomemtype);
2790 register_savevm("s3c24xx_mc", 0, 0, s3c_mc_save, s3c_mc_load, s);
2791
2792 s->pic = s3c_pic_init(0x4a000000, arm_pic_init_cpu(s->env));
2793 s->irq = s3c_pic_get(s->pic);
2794
2795 s->dma = s3c_dma_init(0x4b000000, &s->irq[S3C_PIC_DMA0]);
2796 s->drq = s3c_dma_get(s->dma);
2797
2798 s->clkpwr_base = 0x4c000000;
2799 s3c_clkpwr_reset(s);
2800
2801 iomemtype = cpu_register_io_memory(0, s3c_clkpwr_readfn,
2802 s3c_clkpwr_writefn, s);
2803 cpu_register_physical_memory(s->clkpwr_base, 0xffffff, iomemtype);
2804 register_savevm("s3c24xx_clkpwr", 0, 0,
2805 s3c_clkpwr_save, s3c_clkpwr_load, s);
2806
2807 s->lcd = s3c_lcd_init(0x4d000000, s->irq[S3C_PIC_LCD]);
2808
2809 if (s->cpu_id == S3C_CPU_2440)
2810 s->nand = s3c2440_nand_init();
2811 else
2812 s->nand = s3c2410_nand_init();
2813
2814 for (i = 0; s3c2410_uart[i].base; i ++) {
2815 s->uart[i] = s3c_uart_init(&s->clock,
2816 s3c2410_uart[i].base,
2817 &s->irq[s3c2410_uart[i].irq[0]],
2818 &s->drq[s3c2410_uart[i].dma[0]]);
2819 if (serial_hds[i])
2820 s3c_uart_attach(s->uart[i], serial_hds[i]);
2821 }
2822
2823 s->timers = s3c_timers_init(&s->clock, 0x51000000, &s->irq[S3C_PIC_TIMER0], s->drq);
2824
2825 s->udc = s3c_udc_init(0x52000000, s->irq[S3C_PIC_USBD], s->drq);
2826
2827 s->wdt = s3c_wdt_init(&s->clock, 0x53000000, s->irq[S3C_PIC_WDT]);
2828
2829 s->i2c = s3c_i2c_init(0x54000000, s->irq[S3C_PIC_IIC]);
2830
2831 s->i2s = s3c_i2s_init(0x55000000, s->drq);
2832
2833 s->io = s3c_gpio_init(0x56000000, s->irq, s->cpu_id);
2834
2835 s->rtc = s3c_rtc_init(0x57000000, s->irq[S3C_PIC_RTC]);
2836
2837 s->adc = s3c_adc_init(0x58000000, s->irq[S3C_PICS_ADC],
2838 s->irq[S3C_PICS_TC]);
2839
2840 s->spi = s3c_spi_init(0x59000000,
2841 s->irq[S3C_PIC_SPI0], s->drq[S3C_RQ_SPI0],
2842 s->irq[S3C_PIC_SPI1], s->drq[S3C_RQ_SPI1], s->io);
2843
2844 s->mmci = s3c_mmci_init(0x5a000000, s->cpu_id, mmc,
2845 s->irq[S3C_PIC_SDI], s->drq);
2846
2847 if (usb_enabled) {
2848 usb_ohci_init_pxa(0x49000000, 3, -1, s->irq[S3C_PIC_USBH]);
2849 }
2850
2851 qemu_register_reset(s3c2410_reset, s);
2852
2853 s->nand->setwp(s->nand, 1);
2854
2855 /* Power on reset */
2856 s3c_gpio_setpwrstat(s->io, 1);
2857 return s;
2858 }
Samsung s3c2440 and arm920t support for the mini2440 dev board