gdbstub.c

   1 /*
   2  * gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #ifdef CONFIG_USER_ONLY
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <stdarg.h>
  25 #include <string.h>
  26 #include <errno.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "qemu.h"
  31 #else
  32 #include "qemu-common.h"
  33 #include "qemu-char.h"
  34 #include "sysemu.h"
  35 #include "gdbstub.h"
  36 #endif
  37
  38 #include "qemu_socket.h"
  39 #ifdef _WIN32
  40 /* XXX: these constants may be independent of the host ones even for Unix */
  41 #ifndef SIGTRAP
  42 #define SIGTRAP 5
  43 #endif
  44 #ifndef SIGINT
  45 #define SIGINT 2
  46 #endif
  47 #else
  48 #include <signal.h>
  49 #endif
  50
  51 //#define DEBUG_GDB
  52
  53 enum RSState {
  54     RS_IDLE,
  55     RS_GETLINE,
  56     RS_CHKSUM1,
  57     RS_CHKSUM2,
  58     RS_SYSCALL,
  59 };
  60 typedef struct GDBState {
  61     CPUState *env; /* current CPU */
  62     enum RSState state; /* parsing state */
  63     char line_buf[4096];
  64     int line_buf_index;
  65     int line_csum;
  66     uint8_t last_packet[4100];
  67     int last_packet_len;
  68     int signal;
  69 #ifdef CONFIG_USER_ONLY
  70     int fd;
  71     int running_state;
  72 #else
  73     CharDriverState *chr;
  74 #endif
  75 } GDBState;
  76
  77 /* By default use no IRQs and no timers while single stepping so as to
  78  * make single stepping like an ICE HW step.
  79  */
  80 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
  81
  82 #ifdef CONFIG_USER_ONLY
  83 /* XXX: This is not thread safe.  Do we care?  */
  84 static int gdbserver_fd = -1;
  85
  86 /* XXX: remove this hack.  */
  87 static GDBState gdbserver_state;
  88
  89 static int get_char(GDBState *s)
  90 {
  91     uint8_t ch;
  92     int ret;
  93
  94     for(;;) {
  95         ret = recv(s->fd, &ch, 1, 0);
  96         if (ret < 0) {
  97             if (errno == ECONNRESET)
  98                 s->fd = -1;
  99             if (errno != EINTR && errno != EAGAIN)
 100                 return -1;
 101         } else if (ret == 0) {
 102             close(s->fd);
 103             s->fd = -1;
 104             return -1;
 105         } else {
 106             break;
 107         }
 108     }
 109     return ch;
 110 }
 111 #endif
 112
 113 /* GDB stub state for use by semihosting syscalls.  */
 114 static GDBState *gdb_syscall_state;
 115 static gdb_syscall_complete_cb gdb_current_syscall_cb;
 116
 117 enum {
 118     GDB_SYS_UNKNOWN,
 119     GDB_SYS_ENABLED,
 120     GDB_SYS_DISABLED,
 121 } gdb_syscall_mode;
 122
 123 /* If gdb is connected when the first semihosting syscall occurs then use
 124    remote gdb syscalls.  Otherwise use native file IO.  */
 125 int use_gdb_syscalls(void)
 126 {
 127     if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
 128         gdb_syscall_mode = (gdb_syscall_state ? GDB_SYS_ENABLED
 129                                               : GDB_SYS_DISABLED);
 130     }
 131     return gdb_syscall_mode == GDB_SYS_ENABLED;
 132 }
 133
 134 /* Resume execution.  */
 135 static inline void gdb_continue(GDBState *s)
 136 {
 137 #ifdef CONFIG_USER_ONLY
 138     s->running_state = 1;
 139 #else
 140     vm_start();
 141 #endif
 142 }
 143
 144 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
 145 {
 146 #ifdef CONFIG_USER_ONLY
 147     int ret;
 148
 149     while (len > 0) {
 150         ret = send(s->fd, buf, len, 0);
 151         if (ret < 0) {
 152             if (errno != EINTR && errno != EAGAIN)
 153                 return;
 154         } else {
 155             buf += ret;
 156             len -= ret;
 157         }
 158     }
 159 #else
 160     qemu_chr_write(s->chr, buf, len);
 161 #endif
 162 }
 163
 164 static inline int fromhex(int v)
 165 {
 166     if (v >= '0' && v <= '9')
 167         return v - '0';
 168     else if (v >= 'A' && v <= 'F')
 169         return v - 'A' + 10;
 170     else if (v >= 'a' && v <= 'f')
 171         return v - 'a' + 10;
 172     else
 173         return 0;
 174 }
 175
 176 static inline int tohex(int v)
 177 {
 178     if (v < 10)
 179         return v + '0';
 180     else
 181         return v - 10 + 'a';
 182 }
 183
 184 static void memtohex(char *buf, const uint8_t *mem, int len)
 185 {
 186     int i, c;
 187     char *q;
 188     q = buf;
 189     for(i = 0; i < len; i++) {
 190         c = mem[i];
 191         *q++ = tohex(c >> 4);
 192         *q++ = tohex(c & 0xf);
 193     }
 194     *q = '\0';
 195 }
 196
 197 static void hextomem(uint8_t *mem, const char *buf, int len)
 198 {
 199     int i;
 200
 201     for(i = 0; i < len; i++) {
 202         mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
 203         buf += 2;
 204     }
 205 }
 206
 207 /* return -1 if error, 0 if OK */
 208 static int put_packet(GDBState *s, char *buf)
 209 {
 210     int len, csum, i;
 211     uint8_t *p;
 212
 213 #ifdef DEBUG_GDB
 214     printf("reply='%s'\n", buf);
 215 #endif
 216
 217     for(;;) {
 218         p = s->last_packet;
 219         *(p++) = '$';
 220         len = strlen(buf);
 221         memcpy(p, buf, len);
 222         p += len;
 223         csum = 0;
 224         for(i = 0; i < len; i++) {
 225             csum += buf[i];
 226         }
 227         *(p++) = '#';
 228         *(p++) = tohex((csum >> 4) & 0xf);
 229         *(p++) = tohex((csum) & 0xf);
 230
 231         s->last_packet_len = p - s->last_packet;
 232         put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
 233
 234 #ifdef CONFIG_USER_ONLY
 235         i = get_char(s);
 236         if (i < 0)
 237             return -1;
 238         if (i == '+')
 239             break;
 240 #else
 241         break;
 242 #endif
 243     }
 244     return 0;
 245 }
 246
 247 #if defined(TARGET_I386)
 248
 249 #ifdef TARGET_X86_64
 250 static const uint8_t gdb_x86_64_regs[16] = {
 251     R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
 252     8, 9, 10, 11, 12, 13, 14, 15,
 253 };
 254 #endif
 255
 256 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 257 {
 258     int i, fpus, nb_regs;
 259     uint8_t *p;
 260
 261     p = mem_buf;
 262 #ifdef TARGET_X86_64
 263     if (env->hflags & HF_CS64_MASK) {
 264         nb_regs = 16;
 265         for(i = 0; i < 16; i++) {
 266             *(uint64_t *)p = tswap64(env->regs[gdb_x86_64_regs[i]]);
 267             p += 8;
 268         }
 269         *(uint64_t *)p = tswap64(env->eip);
 270         p += 8;
 271     } else
 272 #endif
 273     {
 274         nb_regs = 8;
 275         for(i = 0; i < 8; i++) {
 276             *(uint32_t *)p = tswap32(env->regs[i]);
 277             p += 4;
 278         }
 279         *(uint32_t *)p = tswap32(env->eip);
 280         p += 4;
 281     }
 282
 283     *(uint32_t *)p = tswap32(env->eflags);
 284     p += 4;
 285     *(uint32_t *)p = tswap32(env->segs[R_CS].selector);
 286     p += 4;
 287     *(uint32_t *)p = tswap32(env->segs[R_SS].selector);
 288     p += 4;
 289     *(uint32_t *)p = tswap32(env->segs[R_DS].selector);
 290     p += 4;
 291     *(uint32_t *)p = tswap32(env->segs[R_ES].selector);
 292     p += 4;
 293     *(uint32_t *)p = tswap32(env->segs[R_FS].selector);
 294     p += 4;
 295     *(uint32_t *)p = tswap32(env->segs[R_GS].selector);
 296     p += 4;
 297     for(i = 0; i < 8; i++) {
 298         /* XXX: convert floats */
 299 #ifdef USE_X86LDOUBLE
 300         memcpy(p, &env->fpregs[i], 10);
 301 #else
 302         memset(p, 0, 10);
 303 #endif
 304         p += 10;
 305     }
 306     *(uint32_t *)p = tswap32(env->fpuc); /* fctrl */
 307     p += 4;
 308     fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 309     *(uint32_t *)p = tswap32(fpus); /* fstat */
 310     p += 4;
 311     *(uint32_t *)p = 0; /* ftag */
 312     p += 4;
 313     *(uint32_t *)p = 0; /* fiseg */
 314     p += 4;
 315     *(uint32_t *)p = 0; /* fioff */
 316     p += 4;
 317     *(uint32_t *)p = 0; /* foseg */
 318     p += 4;
 319     *(uint32_t *)p = 0; /* fooff */
 320     p += 4;
 321     *(uint32_t *)p = 0; /* fop */
 322     p += 4;
 323     for(i = 0; i < nb_regs; i++) {
 324         *(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(0));
 325         p += 8;
 326         *(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(1));
 327         p += 8;
 328     }
 329     *(uint32_t *)p = tswap32(env->mxcsr);
 330     p += 4;
 331     return p - mem_buf;
 332 }
 333
 334 static inline void cpu_gdb_load_seg(CPUState *env, const uint8_t **pp,
 335                                     int sreg)
 336 {
 337     const uint8_t *p;
 338     uint32_t sel;
 339     p = *pp;
 340     sel = tswap32(*(uint32_t *)p);
 341     p += 4;
 342     if (sel != env->segs[sreg].selector) {
 343 #if defined(CONFIG_USER_ONLY)
 344         cpu_x86_load_seg(env, sreg, sel);
 345 #else
 346         /* XXX: do it with a debug function which does not raise an
 347            exception */
 348 #endif
 349     }
 350     *pp = p;
 351 }
 352
 353 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 354 {
 355     const uint8_t *p = mem_buf;
 356     int i, nb_regs;
 357     uint16_t fpus;
 358
 359 #ifdef TARGET_X86_64
 360     if (env->hflags & HF_CS64_MASK) {
 361         nb_regs = 16;
 362         for(i = 0; i < 16; i++) {
 363             env->regs[gdb_x86_64_regs[i]] = tswap64(*(uint64_t *)p);
 364             p += 8;
 365         }
 366         env->eip = tswap64(*(uint64_t *)p);
 367         p += 8;
 368     } else
 369 #endif
 370     {
 371         nb_regs = 8;
 372         for(i = 0; i < 8; i++) {
 373             env->regs[i] = tswap32(*(uint32_t *)p);
 374             p += 4;
 375         }
 376         env->eip = tswap32(*(uint32_t *)p);
 377         p += 4;
 378     }
 379     env->eflags = tswap32(*(uint32_t *)p);
 380     p += 4;
 381     cpu_gdb_load_seg(env, &p, R_CS);
 382     cpu_gdb_load_seg(env, &p, R_SS);
 383     cpu_gdb_load_seg(env, &p, R_DS);
 384     cpu_gdb_load_seg(env, &p, R_ES);
 385     cpu_gdb_load_seg(env, &p, R_FS);
 386     cpu_gdb_load_seg(env, &p, R_GS);
 387
 388     /* FPU state */
 389     for(i = 0; i < 8; i++) {
 390         /* XXX: convert floats */
 391 #ifdef USE_X86LDOUBLE
 392         memcpy(&env->fpregs[i], p, 10);
 393 #endif
 394         p += 10;
 395     }
 396     env->fpuc = tswap32(*(uint32_t *)p); /* fctrl */
 397     p += 4;
 398     fpus = tswap32(*(uint32_t *)p);
 399     p += 4;
 400     env->fpstt = (fpus >> 11) & 7;
 401     env->fpus = fpus & ~0x3800;
 402     p += 4 * 6;
 403
 404     if (size >= ((p - mem_buf) + 16 * nb_regs + 4)) {
 405         /* SSE state */
 406         for(i = 0; i < nb_regs; i++) {
 407             env->xmm_regs[i].XMM_Q(0) = tswap64(*(uint64_t *)p);
 408             p += 8;
 409             env->xmm_regs[i].XMM_Q(1) = tswap64(*(uint64_t *)p);
 410             p += 8;
 411         }
 412         env->mxcsr = tswap32(*(uint32_t *)p);
 413         p += 4;
 414     }
 415 }
 416
 417 #elif defined (TARGET_PPC)
 418 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 419 {
 420     uint32_t *registers = (uint32_t *)mem_buf, tmp;
 421     int i;
 422
 423     /* fill in gprs */
 424     for(i = 0; i < 32; i++) {
 425         registers[i] = tswapl(env->gpr[i]);
 426     }
 427     /* fill in fprs */
 428     for (i = 0; i < 32; i++) {
 429         registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
 430         registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1));
 431     }
 432     /* nip, msr, ccr, lnk, ctr, xer, mq */
 433     registers[96] = tswapl(env->nip);
 434     registers[97] = tswapl(env->msr);
 435     tmp = 0;
 436     for (i = 0; i < 8; i++)
 437         tmp |= env->crf[i] << (32 - ((i + 1) * 4));
 438     registers[98] = tswapl(tmp);
 439     registers[99] = tswapl(env->lr);
 440     registers[100] = tswapl(env->ctr);
 441     registers[101] = tswapl(ppc_load_xer(env));
 442     registers[102] = 0;
 443
 444     return 103 * 4;
 445 }
 446
 447 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 448 {
 449     uint32_t *registers = (uint32_t *)mem_buf;
 450     int i;
 451
 452     /* fill in gprs */
 453     for (i = 0; i < 32; i++) {
 454         env->gpr[i] = tswapl(registers[i]);
 455     }
 456     /* fill in fprs */
 457     for (i = 0; i < 32; i++) {
 458         *((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]);
 459         *((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]);
 460     }
 461     /* nip, msr, ccr, lnk, ctr, xer, mq */
 462     env->nip = tswapl(registers[96]);
 463     ppc_store_msr(env, tswapl(registers[97]));
 464     registers[98] = tswapl(registers[98]);
 465     for (i = 0; i < 8; i++)
 466         env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
 467     env->lr = tswapl(registers[99]);
 468     env->ctr = tswapl(registers[100]);
 469     ppc_store_xer(env, tswapl(registers[101]));
 470 }
 471 #elif defined (TARGET_SPARC)
 472 #ifdef TARGET_ABI32
 473 #define tswap_abi(val) tswap32(val &0xffffffff)
 474 #else
 475 #define tswap_abi(val) tswapl(val)
 476 #endif
 477 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 478 {
 479 #ifdef TARGET_ABI32
 480     abi_ulong *registers = (abi_ulong *)mem_buf;
 481 #else
 482     target_ulong *registers = (target_ulong *)mem_buf;
 483 #endif
 484     int i;
 485
 486     /* fill in g0..g7 */
 487     for(i = 0; i < 8; i++) {
 488         registers[i] = tswap_abi(env->gregs[i]);
 489     }
 490     /* fill in register window */
 491     for(i = 0; i < 24; i++) {
 492         registers[i + 8] = tswap_abi(env->regwptr[i]);
 493     }
 494 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
 495     /* fill in fprs */
 496     for (i = 0; i < 32; i++) {
 497         registers[i + 32] = tswap_abi(*((uint32_t *)&env->fpr[i]));
 498     }
 499     /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 500     registers[64] = tswap_abi(env->y);
 501     {
 502         uint32_t tmp;
 503
 504         tmp = GET_PSR(env);
 505         registers[65] = tswap32(tmp);
 506     }
 507     registers[66] = tswap_abi(env->wim);
 508     registers[67] = tswap_abi(env->tbr);
 509     registers[68] = tswap_abi(env->pc);
 510     registers[69] = tswap_abi(env->npc);
 511     registers[70] = tswap_abi(env->fsr);
 512     registers[71] = 0; /* csr */
 513     registers[72] = 0;
 514     return 73 * sizeof(uint32_t);
 515 #else
 516     /* fill in fprs */
 517     for (i = 0; i < 64; i += 2) {
 518         uint64_t tmp;
 519
 520         tmp = ((uint64_t)*(uint32_t *)&env->fpr[i]) << 32;
 521         tmp |= *(uint32_t *)&env->fpr[i + 1];
 522         registers[i / 2 + 32] = tswap64(tmp);
 523     }
 524     registers[64] = tswapl(env->pc);
 525     registers[65] = tswapl(env->npc);
 526     registers[66] = tswapl(((uint64_t)GET_CCR(env) << 32) |
 527                            ((env->asi & 0xff) << 24) |
 528                            ((env->pstate & 0xfff) << 8) |
 529                            GET_CWP64(env));
 530     registers[67] = tswapl(env->fsr);
 531     registers[68] = tswapl(env->fprs);
 532     registers[69] = tswapl(env->y);
 533     return 70 * sizeof(target_ulong);
 534 #endif
 535 }
 536
 537 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 538 {
 539 #ifdef TARGET_ABI32
 540     abi_ulong *registers = (abi_ulong *)mem_buf;
 541 #else
 542     target_ulong *registers = (target_ulong *)mem_buf;
 543 #endif
 544     int i;
 545
 546     /* fill in g0..g7 */
 547     for(i = 0; i < 7; i++) {
 548         env->gregs[i] = tswap_abi(registers[i]);
 549     }
 550     /* fill in register window */
 551     for(i = 0; i < 24; i++) {
 552         env->regwptr[i] = tswap_abi(registers[i + 8]);
 553     }
 554 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
 555     /* fill in fprs */
 556     for (i = 0; i < 32; i++) {
 557         *((uint32_t *)&env->fpr[i]) = tswap_abi(registers[i + 32]);
 558     }
 559     /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 560     env->y = tswap_abi(registers[64]);
 561     PUT_PSR(env, tswap_abi(registers[65]));
 562     env->wim = tswap_abi(registers[66]);
 563     env->tbr = tswap_abi(registers[67]);
 564     env->pc = tswap_abi(registers[68]);
 565     env->npc = tswap_abi(registers[69]);
 566     env->fsr = tswap_abi(registers[70]);
 567 #else
 568     for (i = 0; i < 64; i += 2) {
 569         uint64_t tmp;
 570
 571         tmp = tswap64(registers[i / 2 + 32]);
 572         *((uint32_t *)&env->fpr[i]) = tmp >> 32;
 573         *((uint32_t *)&env->fpr[i + 1]) = tmp & 0xffffffff;
 574     }
 575     env->pc = tswapl(registers[64]);
 576     env->npc = tswapl(registers[65]);
 577     {
 578         uint64_t tmp = tswapl(registers[66]);
 579
 580         PUT_CCR(env, tmp >> 32);
 581         env->asi = (tmp >> 24) & 0xff;
 582         env->pstate = (tmp >> 8) & 0xfff;
 583         PUT_CWP64(env, tmp & 0xff);
 584     }
 585     env->fsr = tswapl(registers[67]);
 586     env->fprs = tswapl(registers[68]);
 587     env->y = tswapl(registers[69]);
 588 #endif
 589 }
 590 #undef tswap_abi
 591 #elif defined (TARGET_ARM)
 592 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 593 {
 594     int i;
 595     uint8_t *ptr;
 596
 597     ptr = mem_buf;
 598     /* 16 core integer registers (4 bytes each).  */
 599     for (i = 0; i < 16; i++)
 600       {
 601         *(uint32_t *)ptr = tswapl(env->regs[i]);
 602         ptr += 4;
 603       }
 604     /* 8 FPA registers (12 bytes each), FPS (4 bytes).
 605        Not yet implemented.  */
 606     memset (ptr, 0, 8 * 12 + 4);
 607     ptr += 8 * 12 + 4;
 608     /* CPSR (4 bytes).  */
 609     *(uint32_t *)ptr = tswapl (cpsr_read(env));
 610     ptr += 4;
 611
 612     return ptr - mem_buf;
 613 }
 614
 615 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 616 {
 617     int i;
 618     uint8_t *ptr;
 619
 620     ptr = mem_buf;
 621     /* Core integer registers.  */
 622     for (i = 0; i < 16; i++)
 623       {
 624         env->regs[i] = tswapl(*(uint32_t *)ptr);
 625         ptr += 4;
 626       }
 627     /* Ignore FPA regs and scr.  */
 628     ptr += 8 * 12 + 4;
 629     cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
 630 }
 631 #elif defined (TARGET_M68K)
 632 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 633 {
 634     int i;
 635     uint8_t *ptr;
 636     CPU_DoubleU u;
 637
 638     ptr = mem_buf;
 639     /* D0-D7 */
 640     for (i = 0; i < 8; i++) {
 641         *(uint32_t *)ptr = tswapl(env->dregs[i]);
 642         ptr += 4;
 643     }
 644     /* A0-A7 */
 645     for (i = 0; i < 8; i++) {
 646         *(uint32_t *)ptr = tswapl(env->aregs[i]);
 647         ptr += 4;
 648     }
 649     *(uint32_t *)ptr = tswapl(env->sr);
 650     ptr += 4;
 651     *(uint32_t *)ptr = tswapl(env->pc);
 652     ptr += 4;
 653     /* F0-F7.  The 68881/68040 have 12-bit extended precision registers.
 654        ColdFire has 8-bit double precision registers.  */
 655     for (i = 0; i < 8; i++) {
 656         u.d = env->fregs[i];
 657         *(uint32_t *)ptr = tswap32(u.l.upper);
 658         *(uint32_t *)ptr = tswap32(u.l.lower);
 659     }
 660     /* FP control regs (not implemented).  */
 661     memset (ptr, 0, 3 * 4);
 662     ptr += 3 * 4;
 663
 664     return ptr - mem_buf;
 665 }
 666
 667 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 668 {
 669     int i;
 670     uint8_t *ptr;
 671     CPU_DoubleU u;
 672
 673     ptr = mem_buf;
 674     /* D0-D7 */
 675     for (i = 0; i < 8; i++) {
 676         env->dregs[i] = tswapl(*(uint32_t *)ptr);
 677         ptr += 4;
 678     }
 679     /* A0-A7 */
 680     for (i = 0; i < 8; i++) {
 681         env->aregs[i] = tswapl(*(uint32_t *)ptr);
 682         ptr += 4;
 683     }
 684     env->sr = tswapl(*(uint32_t *)ptr);
 685     ptr += 4;
 686     env->pc = tswapl(*(uint32_t *)ptr);
 687     ptr += 4;
 688     /* F0-F7.  The 68881/68040 have 12-bit extended precision registers.
 689        ColdFire has 8-bit double precision registers.  */
 690     for (i = 0; i < 8; i++) {
 691         u.l.upper = tswap32(*(uint32_t *)ptr);
 692         u.l.lower = tswap32(*(uint32_t *)ptr);
 693         env->fregs[i] = u.d;
 694     }
 695     /* FP control regs (not implemented).  */
 696     ptr += 3 * 4;
 697 }
 698 #elif defined (TARGET_MIPS)
 699 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 700 {
 701     int i;
 702     uint8_t *ptr;
 703
 704     ptr = mem_buf;
 705     for (i = 0; i < 32; i++)
 706       {
 707         *(target_ulong *)ptr = tswapl(env->active_tc.gpr[i]);
 708         ptr += sizeof(target_ulong);
 709       }
 710
 711     *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status);
 712     ptr += sizeof(target_ulong);
 713
 714     *(target_ulong *)ptr = tswapl(env->active_tc.LO[0]);
 715     ptr += sizeof(target_ulong);
 716
 717     *(target_ulong *)ptr = tswapl(env->active_tc.HI[0]);
 718     ptr += sizeof(target_ulong);
 719
 720     *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
 721     ptr += sizeof(target_ulong);
 722
 723     *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause);
 724     ptr += sizeof(target_ulong);
 725
 726     *(target_ulong *)ptr = tswapl(env->active_tc.PC);
 727     ptr += sizeof(target_ulong);
 728
 729     if (env->CP0_Config1 & (1 << CP0C1_FP))
 730       {
 731         for (i = 0; i < 32; i++)
 732           {
 733             if (env->CP0_Status & (1 << CP0St_FR))
 734               *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d);
 735             else
 736               *(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]);
 737             ptr += sizeof(target_ulong);
 738           }
 739
 740         *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31);
 741         ptr += sizeof(target_ulong);
 742
 743         *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0);
 744         ptr += sizeof(target_ulong);
 745       }
 746
 747     /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
 748     *(target_ulong *)ptr = 0;
 749     ptr += sizeof(target_ulong);
 750
 751     /* Registers for embedded use, we just pad them. */
 752     for (i = 0; i < 16; i++)
 753       {
 754         *(target_ulong *)ptr = 0;
 755         ptr += sizeof(target_ulong);
 756       }
 757
 758     /* Processor ID. */
 759     *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid);
 760     ptr += sizeof(target_ulong);
 761
 762     return ptr - mem_buf;
 763 }
 764
 765 /* convert MIPS rounding mode in FCR31 to IEEE library */
 766 static unsigned int ieee_rm[] =
 767   {
 768     float_round_nearest_even,
 769     float_round_to_zero,
 770     float_round_up,
 771     float_round_down
 772   };
 773 #define RESTORE_ROUNDING_MODE \
 774     set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
 775
 776 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 777 {
 778     int i;
 779     uint8_t *ptr;
 780
 781     ptr = mem_buf;
 782     for (i = 0; i < 32; i++)
 783       {
 784         env->active_tc.gpr[i] = tswapl(*(target_ulong *)ptr);
 785         ptr += sizeof(target_ulong);
 786       }
 787
 788     env->CP0_Status = tswapl(*(target_ulong *)ptr);
 789     ptr += sizeof(target_ulong);
 790
 791     env->active_tc.LO[0] = tswapl(*(target_ulong *)ptr);
 792     ptr += sizeof(target_ulong);
 793
 794     env->active_tc.HI[0] = tswapl(*(target_ulong *)ptr);
 795     ptr += sizeof(target_ulong);
 796
 797     env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);
 798     ptr += sizeof(target_ulong);
 799
 800     env->CP0_Cause = tswapl(*(target_ulong *)ptr);
 801     ptr += sizeof(target_ulong);
 802
 803     env->active_tc.PC = tswapl(*(target_ulong *)ptr);
 804     ptr += sizeof(target_ulong);
 805
 806     if (env->CP0_Config1 & (1 << CP0C1_FP))
 807       {
 808         for (i = 0; i < 32; i++)
 809           {
 810             if (env->CP0_Status & (1 << CP0St_FR))
 811               env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr);
 812             else
 813               env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
 814             ptr += sizeof(target_ulong);
 815           }
 816
 817         env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
 818         ptr += sizeof(target_ulong);
 819
 820         /* The remaining registers are assumed to be read-only. */
 821
 822         /* set rounding mode */
 823         RESTORE_ROUNDING_MODE;
 824
 825 #ifndef CONFIG_SOFTFLOAT
 826         /* no floating point exception for native float */
 827         SET_FP_ENABLE(env->fcr31, 0);
 828 #endif
 829       }
 830 }
 831 #elif defined (TARGET_SH4)
 832
 833 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
 834
 835 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 836 {
 837   uint32_t *ptr = (uint32_t *)mem_buf;
 838   int i;
 839
 840 #define SAVE(x) *ptr++=tswapl(x)
 841   if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
 842       for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
 843   } else {
 844       for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
 845   }
 846   for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
 847   SAVE (env->pc);
 848   SAVE (env->pr);
 849   SAVE (env->gbr);
 850   SAVE (env->vbr);
 851   SAVE (env->mach);
 852   SAVE (env->macl);
 853   SAVE (env->sr);
 854   SAVE (env->fpul);
 855   SAVE (env->fpscr);
 856   for (i = 0; i < 16; i++)
 857       SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
 858   SAVE (env->ssr);
 859   SAVE (env->spc);
 860   for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
 861   for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
 862   return ((uint8_t *)ptr - mem_buf);
 863 }
 864
 865 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 866 {
 867   uint32_t *ptr = (uint32_t *)mem_buf;
 868   int i;
 869
 870 #define LOAD(x) (x)=*ptr++;
 871   if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
 872       for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
 873   } else {
 874       for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
 875   }
 876   for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
 877   LOAD (env->pc);
 878   LOAD (env->pr);
 879   LOAD (env->gbr);
 880   LOAD (env->vbr);
 881   LOAD (env->mach);
 882   LOAD (env->macl);
 883   LOAD (env->sr);
 884   LOAD (env->fpul);
 885   LOAD (env->fpscr);
 886   for (i = 0; i < 16; i++)
 887       LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
 888   LOAD (env->ssr);
 889   LOAD (env->spc);
 890   for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
 891   for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
 892 }
 893 #elif defined (TARGET_CRIS)
 894
 895 static int cris_save_32 (unsigned char *d, uint32_t value)
 896 {
 897         *d++ = (value);
 898         *d++ = (value >>= 8);
 899         *d++ = (value >>= 8);
 900         *d++ = (value >>= 8);
 901         return 4;
 902 }
 903 static int cris_save_16 (unsigned char *d, uint32_t value)
 904 {
 905         *d++ = (value);
 906         *d++ = (value >>= 8);
 907         return 2;
 908 }
 909 static int cris_save_8 (unsigned char *d, uint32_t value)
 910 {
 911         *d++ = (value);
 912         return 1;
 913 }
 914
 915 /* FIXME: this will bug on archs not supporting unaligned word accesses.  */
 916 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 917 {
 918   uint8_t *ptr = mem_buf;
 919   uint8_t srs;
 920   int i;
 921
 922   for (i = 0; i < 16; i++)
 923           ptr += cris_save_32 (ptr, env->regs[i]);
 924
 925   srs = env->pregs[PR_SRS];
 926
 927   ptr += cris_save_8 (ptr, env->pregs[0]);
 928   ptr += cris_save_8 (ptr, env->pregs[1]);
 929   ptr += cris_save_32 (ptr, env->pregs[2]);
 930   ptr += cris_save_8 (ptr, srs);
 931   ptr += cris_save_16 (ptr, env->pregs[4]);
 932
 933   for (i = 5; i < 16; i++)
 934           ptr += cris_save_32 (ptr, env->pregs[i]);
 935
 936   ptr += cris_save_32 (ptr, env->pc);
 937
 938   for (i = 0; i < 16; i++)
 939           ptr += cris_save_32 (ptr, env->sregs[srs][i]);
 940
 941   return ((uint8_t *)ptr - mem_buf);
 942 }
 943
 944 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 945 {
 946   uint32_t *ptr = (uint32_t *)mem_buf;
 947   int i;
 948
 949 #define LOAD(x) (x)=*ptr++;
 950   for (i = 0; i < 16; i++) LOAD(env->regs[i]);
 951   LOAD (env->pc);
 952 }
 953 #else
 954 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 955 {
 956     return 0;
 957 }
 958
 959 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 960 {
 961 }
 962
 963 #endif
 964
 965 static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
 966 {
 967     const char *p;
 968     int ch, reg_size, type;
 969     char buf[4096];
 970     uint8_t mem_buf[4096];
 971     uint32_t *registers;
 972     target_ulong addr, len;
 973
 974 #ifdef DEBUG_GDB
 975     printf("command='%s'\n", line_buf);
 976 #endif
 977     p = line_buf;
 978     ch = *p++;
 979     switch(ch) {
 980     case '?':
 981         /* TODO: Make this return the correct value for user-mode.  */
 982         snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
 983         put_packet(s, buf);
 984         /* Remove all the breakpoints when this query is issued,
 985          * because gdb is doing and initial connect and the state
 986          * should be cleaned up.
 987          */
 988         cpu_breakpoint_remove_all(env);
 989         cpu_watchpoint_remove_all(env);
 990         break;
 991     case 'c':
 992         if (*p != '\0') {
 993             addr = strtoull(p, (char **)&p, 16);
 994 #if defined(TARGET_I386)
 995             env->eip = addr;
 996 #elif defined (TARGET_PPC)
 997             env->nip = addr;
 998 #elif defined (TARGET_SPARC)
 999             env->pc = addr;
1000             env->npc = addr + 4;
1001 #elif defined (TARGET_ARM)
1002             env->regs[15] = addr;
1003 #elif defined (TARGET_SH4)
1004             env->pc = addr;
1005 #elif defined (TARGET_MIPS)
1006             env->active_tc.PC = addr;
1007 #elif defined (TARGET_CRIS)
1008             env->pc = addr;
1009 #endif
1010         }
1011         gdb_continue(s);
1012         return RS_IDLE;
1013     case 'C':
1014         s->signal = strtoul(p, (char **)&p, 16);
1015         gdb_continue(s);
1016         return RS_IDLE;
1017     case 'k':
1018         /* Kill the target */
1019         fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1020         exit(0);
1021     case 'D':
1022         /* Detach packet */
1023         cpu_breakpoint_remove_all(env);
1024         cpu_watchpoint_remove_all(env);
1025         gdb_continue(s);
1026         put_packet(s, "OK");
1027         break;
1028     case 's':
1029         if (*p != '\0') {
1030             addr = strtoull(p, (char **)&p, 16);
1031 #if defined(TARGET_I386)
1032             env->eip = addr;
1033 #elif defined (TARGET_PPC)
1034             env->nip = addr;
1035 #elif defined (TARGET_SPARC)
1036             env->pc = addr;
1037             env->npc = addr + 4;
1038 #elif defined (TARGET_ARM)
1039             env->regs[15] = addr;
1040 #elif defined (TARGET_SH4)
1041             env->pc = addr;
1042 #elif defined (TARGET_MIPS)
1043             env->active_tc.PC = addr;
1044 #elif defined (TARGET_CRIS)
1045             env->pc = addr;
1046 #endif
1047         }
1048         cpu_single_step(env, sstep_flags);
1049         gdb_continue(s);
1050         return RS_IDLE;
1051     case 'F':
1052         {
1053             target_ulong ret;
1054             target_ulong err;
1055
1056             ret = strtoull(p, (char **)&p, 16);
1057             if (*p == ',') {
1058                 p++;
1059                 err = strtoull(p, (char **)&p, 16);
1060             } else {
1061                 err = 0;
1062             }
1063             if (*p == ',')
1064                 p++;
1065             type = *p;
1066             if (gdb_current_syscall_cb)
1067                 gdb_current_syscall_cb(s->env, ret, err);
1068             if (type == 'C') {
1069                 put_packet(s, "T02");
1070             } else {
1071                 gdb_continue(s);
1072             }
1073         }
1074         break;
1075     case 'g':
1076         reg_size = cpu_gdb_read_registers(env, mem_buf);
1077         memtohex(buf, mem_buf, reg_size);
1078         put_packet(s, buf);
1079         break;
1080     case 'G':
1081         registers = (void *)mem_buf;
1082         len = strlen(p) / 2;
1083         hextomem((uint8_t *)registers, p, len);
1084         cpu_gdb_write_registers(env, mem_buf, len);
1085         put_packet(s, "OK");
1086         break;
1087     case 'm':
1088         addr = strtoull(p, (char **)&p, 16);
1089         if (*p == ',')
1090             p++;
1091         len = strtoull(p, NULL, 16);
1092         if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) {
1093             put_packet (s, "E14");
1094         } else {
1095             memtohex(buf, mem_buf, len);
1096             put_packet(s, buf);
1097         }
1098         break;
1099     case 'M':
1100         addr = strtoull(p, (char **)&p, 16);
1101         if (*p == ',')
1102             p++;
1103         len = strtoull(p, (char **)&p, 16);
1104         if (*p == ':')
1105             p++;
1106         hextomem(mem_buf, p, len);
1107         if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0)
1108             put_packet(s, "E14");
1109         else
1110             put_packet(s, "OK");
1111         break;
1112     case 'Z':
1113         type = strtoul(p, (char **)&p, 16);
1114         if (*p == ',')
1115             p++;
1116         addr = strtoull(p, (char **)&p, 16);
1117         if (*p == ',')
1118             p++;
1119         len = strtoull(p, (char **)&p, 16);
1120         switch (type) {
1121         case 0:
1122         case 1:
1123             if (cpu_breakpoint_insert(env, addr) < 0)
1124                 goto breakpoint_error;
1125             put_packet(s, "OK");
1126             break;
1127 #ifndef CONFIG_USER_ONLY
1128         case 2:
1129             type = PAGE_WRITE;
1130             goto insert_watchpoint;
1131         case 3:
1132             type = PAGE_READ;
1133             goto insert_watchpoint;
1134         case 4:
1135             type = PAGE_READ | PAGE_WRITE;
1136         insert_watchpoint:
1137             if (cpu_watchpoint_insert(env, addr, type) < 0)
1138                 goto breakpoint_error;
1139             put_packet(s, "OK");
1140             break;
1141 #endif
1142         default:
1143             put_packet(s, "");
1144             break;
1145         }
1146         break;
1147     breakpoint_error:
1148         put_packet(s, "E22");
1149         break;
1150
1151     case 'z':
1152         type = strtoul(p, (char **)&p, 16);
1153         if (*p == ',')
1154             p++;
1155         addr = strtoull(p, (char **)&p, 16);
1156         if (*p == ',')
1157             p++;
1158         len = strtoull(p, (char **)&p, 16);
1159         if (type == 0 || type == 1) {
1160             cpu_breakpoint_remove(env, addr);
1161             put_packet(s, "OK");
1162 #ifndef CONFIG_USER_ONLY
1163         } else if (type >= 2 || type <= 4) {
1164             cpu_watchpoint_remove(env, addr);
1165             put_packet(s, "OK");
1166 #endif
1167         } else {
1168             put_packet(s, "");
1169         }
1170         break;
1171     case 'q':
1172     case 'Q':
1173         /* parse any 'q' packets here */
1174         if (!strcmp(p,"qemu.sstepbits")) {
1175             /* Query Breakpoint bit definitions */
1176             sprintf(buf,"ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1177                     SSTEP_ENABLE,
1178                     SSTEP_NOIRQ,
1179                     SSTEP_NOTIMER);
1180             put_packet(s, buf);
1181             break;
1182         } else if (strncmp(p,"qemu.sstep",10) == 0) {
1183             /* Display or change the sstep_flags */
1184             p += 10;
1185             if (*p != '=') {
1186                 /* Display current setting */
1187                 sprintf(buf,"0x%x", sstep_flags);
1188                 put_packet(s, buf);
1189                 break;
1190             }
1191             p++;
1192             type = strtoul(p, (char **)&p, 16);
1193             sstep_flags = type;
1194             put_packet(s, "OK");
1195             break;
1196         }
1197 #ifdef CONFIG_LINUX_USER
1198         else if (strncmp(p, "Offsets", 7) == 0) {
1199             TaskState *ts = env->opaque;
1200
1201             sprintf(buf,
1202                     "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
1203                     ";Bss=" TARGET_ABI_FMT_lx,
1204                     ts->info->code_offset,
1205                     ts->info->data_offset,
1206                     ts->info->data_offset);
1207             put_packet(s, buf);
1208             break;
1209         }
1210 #endif
1211         /* Fall through.  */
1212     default:
1213         /* put empty packet */
1214         buf[0] = '\0';
1215         put_packet(s, buf);
1216         break;
1217     }
1218     return RS_IDLE;
1219 }
1220
1221 extern void tb_flush(CPUState *env);
1222
1223 #ifndef CONFIG_USER_ONLY
1224 static void gdb_vm_stopped(void *opaque, int reason)
1225 {
1226     GDBState *s = opaque;
1227     char buf[256];
1228     int ret;
1229
1230     if (s->state == RS_SYSCALL)
1231         return;
1232
1233     /* disable single step if it was enable */
1234     cpu_single_step(s->env, 0);
1235
1236     if (reason == EXCP_DEBUG) {
1237         if (s->env->watchpoint_hit) {
1238             snprintf(buf, sizeof(buf), "T%02xwatch:" TARGET_FMT_lx ";",
1239                      SIGTRAP,
1240                      s->env->watchpoint[s->env->watchpoint_hit - 1].vaddr);
1241             put_packet(s, buf);
1242             s->env->watchpoint_hit = 0;
1243             return;
1244         }
1245         tb_flush(s->env);
1246         ret = SIGTRAP;
1247     } else if (reason == EXCP_INTERRUPT) {
1248         ret = SIGINT;
1249     } else {
1250         ret = 0;
1251     }
1252     snprintf(buf, sizeof(buf), "S%02x", ret);
1253     put_packet(s, buf);
1254 }
1255 #endif
1256
1257 /* Send a gdb syscall request.
1258    This accepts limited printf-style format specifiers, specifically:
1259     %x  - target_ulong argument printed in hex.
1260     %lx - 64-bit argument printed in hex.
1261     %s  - string pointer (target_ulong) and length (int) pair.  */
1262 void gdb_do_syscall(gdb_syscall_complete_cb cb, char *fmt, ...)
1263 {
1264     va_list va;
1265     char buf[256];
1266     char *p;
1267     target_ulong addr;
1268     uint64_t i64;
1269     GDBState *s;
1270
1271     s = gdb_syscall_state;
1272     if (!s)
1273         return;
1274     gdb_current_syscall_cb = cb;
1275     s->state = RS_SYSCALL;
1276 #ifndef CONFIG_USER_ONLY
1277     vm_stop(EXCP_DEBUG);
1278 #endif
1279     s->state = RS_IDLE;
1280     va_start(va, fmt);
1281     p = buf;
1282     *(p++) = 'F';
1283     while (*fmt) {
1284         if (*fmt == '%') {
1285             fmt++;
1286             switch (*fmt++) {
1287             case 'x':
1288                 addr = va_arg(va, target_ulong);
1289                 p += sprintf(p, TARGET_FMT_lx, addr);
1290                 break;
1291             case 'l':
1292                 if (*(fmt++) != 'x')
1293                     goto bad_format;
1294                 i64 = va_arg(va, uint64_t);
1295                 p += sprintf(p, "%" PRIx64, i64);
1296                 break;
1297             case 's':
1298                 addr = va_arg(va, target_ulong);
1299                 p += sprintf(p, TARGET_FMT_lx "/%x", addr, va_arg(va, int));
1300                 break;
1301             default:
1302             bad_format:
1303                 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
1304                         fmt - 1);
1305                 break;
1306             }
1307         } else {
1308             *(p++) = *(fmt++);
1309         }
1310     }
1311     *p = 0;
1312     va_end(va);
1313     put_packet(s, buf);
1314 #ifdef CONFIG_USER_ONLY
1315     gdb_handlesig(s->env, 0);
1316 #else
1317     cpu_interrupt(s->env, CPU_INTERRUPT_EXIT);
1318 #endif
1319 }
1320
1321 static void gdb_read_byte(GDBState *s, int ch)
1322 {
1323     CPUState *env = s->env;
1324     int i, csum;
1325     uint8_t reply;
1326
1327 #ifndef CONFIG_USER_ONLY
1328     if (s->last_packet_len) {
1329         /* Waiting for a response to the last packet.  If we see the start
1330            of a new command then abandon the previous response.  */
1331         if (ch == '-') {
1332 #ifdef DEBUG_GDB
1333             printf("Got NACK, retransmitting\n");
1334 #endif
1335             put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
1336         }
1337 #ifdef DEBUG_GDB
1338         else if (ch == '+')
1339             printf("Got ACK\n");
1340         else
1341             printf("Got '%c' when expecting ACK/NACK\n", ch);
1342 #endif
1343         if (ch == '+' || ch == '$')
1344             s->last_packet_len = 0;
1345         if (ch != '$')
1346             return;
1347     }
1348     if (vm_running) {
1349         /* when the CPU is running, we cannot do anything except stop
1350            it when receiving a char */
1351         vm_stop(EXCP_INTERRUPT);
1352     } else
1353 #endif
1354     {
1355         switch(s->state) {
1356         case RS_IDLE:
1357             if (ch == '$') {
1358                 s->line_buf_index = 0;
1359                 s->state = RS_GETLINE;
1360             }
1361             break;
1362         case RS_GETLINE:
1363             if (ch == '#') {
1364             s->state = RS_CHKSUM1;
1365             } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
1366                 s->state = RS_IDLE;
1367             } else {
1368             s->line_buf[s->line_buf_index++] = ch;
1369             }
1370             break;
1371         case RS_CHKSUM1:
1372             s->line_buf[s->line_buf_index] = '\0';
1373             s->line_csum = fromhex(ch) << 4;
1374             s->state = RS_CHKSUM2;
1375             break;
1376         case RS_CHKSUM2:
1377             s->line_csum |= fromhex(ch);
1378             csum = 0;
1379             for(i = 0; i < s->line_buf_index; i++) {
1380                 csum += s->line_buf[i];
1381             }
1382             if (s->line_csum != (csum & 0xff)) {
1383                 reply = '-';
1384                 put_buffer(s, &reply, 1);
1385                 s->state = RS_IDLE;
1386             } else {
1387                 reply = '+';
1388                 put_buffer(s, &reply, 1);
1389                 s->state = gdb_handle_packet(s, env, s->line_buf);
1390             }
1391             break;
1392         default:
1393             abort();
1394         }
1395     }
1396 }
1397
1398 #ifdef CONFIG_USER_ONLY
1399 int
1400 gdb_handlesig (CPUState *env, int sig)
1401 {
1402   GDBState *s;
1403   char buf[256];
1404   int n;
1405
1406   s = &gdbserver_state;
1407   if (gdbserver_fd < 0 || s->fd < 0)
1408     return sig;
1409
1410   /* disable single step if it was enabled */
1411   cpu_single_step(env, 0);
1412   tb_flush(env);
1413
1414   if (sig != 0)
1415     {
1416       snprintf(buf, sizeof(buf), "S%02x", sig);
1417       put_packet(s, buf);
1418     }
1419   /* put_packet() might have detected that the peer terminated the
1420      connection.  */
1421   if (s->fd < 0)
1422       return sig;
1423
1424   sig = 0;
1425   s->state = RS_IDLE;
1426   s->running_state = 0;
1427   while (s->running_state == 0) {
1428       n = read (s->fd, buf, 256);
1429       if (n > 0)
1430         {
1431           int i;
1432
1433           for (i = 0; i < n; i++)
1434             gdb_read_byte (s, buf[i]);
1435         }
1436       else if (n == 0 || errno != EAGAIN)
1437         {
1438           /* XXX: Connection closed.  Should probably wait for annother
1439              connection before continuing.  */
1440           return sig;
1441         }
1442   }
1443   sig = s->signal;
1444   s->signal = 0;
1445   return sig;
1446 }
1447
1448 /* Tell the remote gdb that the process has exited.  */
1449 void gdb_exit(CPUState *env, int code)
1450 {
1451   GDBState *s;
1452   char buf[4];
1453
1454   s = &gdbserver_state;
1455   if (gdbserver_fd < 0 || s->fd < 0)
1456     return;
1457
1458   snprintf(buf, sizeof(buf), "W%02x", code);
1459   put_packet(s, buf);
1460 }
1461
1462
1463 static void gdb_accept(void *opaque)
1464 {
1465     GDBState *s;
1466     struct sockaddr_in sockaddr;
1467     socklen_t len;
1468     int val, fd;
1469
1470     for(;;) {
1471         len = sizeof(sockaddr);
1472         fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
1473         if (fd < 0 && errno != EINTR) {
1474             perror("accept");
1475             return;
1476         } else if (fd >= 0) {
1477             break;
1478         }
1479     }
1480
1481     /* set short latency */
1482     val = 1;
1483     setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
1484
1485     s = &gdbserver_state;
1486     memset (s, 0, sizeof (GDBState));
1487     s->env = first_cpu; /* XXX: allow to change CPU */
1488     s->fd = fd;
1489
1490     gdb_syscall_state = s;
1491
1492     fcntl(fd, F_SETFL, O_NONBLOCK);
1493 }
1494
1495 static int gdbserver_open(int port)
1496 {
1497     struct sockaddr_in sockaddr;
1498     int fd, val, ret;
1499
1500     fd = socket(PF_INET, SOCK_STREAM, 0);
1501     if (fd < 0) {
1502         perror("socket");
1503         return -1;
1504     }
1505
1506     /* allow fast reuse */
1507     val = 1;
1508     setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
1509
1510     sockaddr.sin_family = AF_INET;
1511     sockaddr.sin_port = htons(port);
1512     sockaddr.sin_addr.s_addr = 0;
1513     ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1514     if (ret < 0) {
1515         perror("bind");
1516         return -1;
1517     }
1518     ret = listen(fd, 0);
1519     if (ret < 0) {
1520         perror("listen");
1521         return -1;
1522     }
1523     return fd;
1524 }
1525
1526 int gdbserver_start(int port)
1527 {
1528     gdbserver_fd = gdbserver_open(port);
1529     if (gdbserver_fd < 0)
1530         return -1;
1531     /* accept connections */
1532     gdb_accept (NULL);
1533     return 0;
1534 }
1535 #else
1536 static int gdb_chr_can_receive(void *opaque)
1537 {
1538   return 1;
1539 }
1540
1541 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
1542 {
1543     GDBState *s = opaque;
1544     int i;
1545
1546     for (i = 0; i < size; i++) {
1547         gdb_read_byte(s, buf[i]);
1548     }
1549 }
1550
1551 static void gdb_chr_event(void *opaque, int event)
1552 {
1553     switch (event) {
1554     case CHR_EVENT_RESET:
1555         vm_stop(EXCP_INTERRUPT);
1556         gdb_syscall_state = opaque;
1557         break;
1558     default:
1559         break;
1560     }
1561 }
1562
1563 int gdbserver_start(const char *port)
1564 {
1565     GDBState *s;
1566     char gdbstub_port_name[128];
1567     int port_num;
1568     char *p;
1569     CharDriverState *chr;
1570
1571     if (!port || !*port)
1572       return -1;
1573
1574     port_num = strtol(port, &p, 10);
1575     if (*p == 0) {
1576         /* A numeric value is interpreted as a port number.  */
1577         snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
1578                  "tcp::%d,nowait,nodelay,server", port_num);
1579         port = gdbstub_port_name;
1580     }
1581
1582     chr = qemu_chr_open(port);
1583     if (!chr)
1584         return -1;
1585
1586     s = qemu_mallocz(sizeof(GDBState));
1587     if (!s) {
1588         return -1;
1589     }
1590     s->env = first_cpu; /* XXX: allow to change CPU */
1591     s->chr = chr;
1592     qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
1593                           gdb_chr_event, s);
1594     qemu_add_vm_stop_handler(gdb_vm_stopped, s);
1595     return 0;
1596 }
1597 #endif