target-sh4/helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <signal.h>
  26
  27 #include "cpu.h"
  28 #include "exec-all.h"
  29 #include "hw/sh_intc.h"
  30
  31 #if defined(CONFIG_USER_ONLY)
  32
  33 void do_interrupt (CPUState *env)
  34 {
  35   env->exception_index = -1;
  36 }
  37
  38 int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
  39                              int mmu_idx, int is_softmmu)
  40 {
  41     env->tea = address;
  42     env->exception_index = 0;
  43     switch (rw) {
  44     case 0:
  45         env->exception_index = 0x0a0;
  46         break;
  47     case 1:
  48         env->exception_index = 0x0c0;
  49         break;
  50     case 2:
  51         env->exception_index = 0x0a0;
  52         break;
  53     }
  54     return 1;
  55 }
  56
  57 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
  58 {
  59     return addr;
  60 }
  61
  62 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
  63 {
  64     /* For user mode, only U0 area is cachable. */
  65     return !(addr & 0x80000000);
  66 }
  67
  68 #else /* !CONFIG_USER_ONLY */
  69
  70 #define MMU_OK                   0
  71 #define MMU_ITLB_MISS            (-1)
  72 #define MMU_ITLB_MULTIPLE        (-2)
  73 #define MMU_ITLB_VIOLATION       (-3)
  74 #define MMU_DTLB_MISS_READ       (-4)
  75 #define MMU_DTLB_MISS_WRITE      (-5)
  76 #define MMU_DTLB_INITIAL_WRITE   (-6)
  77 #define MMU_DTLB_VIOLATION_READ  (-7)
  78 #define MMU_DTLB_VIOLATION_WRITE (-8)
  79 #define MMU_DTLB_MULTIPLE        (-9)
  80 #define MMU_DTLB_MISS            (-10)
  81 #define MMU_IADDR_ERROR          (-11)
  82 #define MMU_DADDR_ERROR_READ     (-12)
  83 #define MMU_DADDR_ERROR_WRITE    (-13)
  84
  85 void do_interrupt(CPUState * env)
  86 {
  87     int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
  88     int do_exp, irq_vector = env->exception_index;
  89
  90     /* prioritize exceptions over interrupts */
  91
  92     do_exp = env->exception_index != -1;
  93     do_irq = do_irq && (env->exception_index == -1);
  94
  95     if (env->sr & SR_BL) {
  96         if (do_exp && env->exception_index != 0x1e0) {
  97             env->exception_index = 0x000; /* masked exception -> reset */
  98         }
  99         if (do_irq && !env->intr_at_halt) {
 100             return; /* masked */
 101         }
 102         env->intr_at_halt = 0;
 103     }
 104
 105     if (do_irq) {
 106         irq_vector = sh_intc_get_pending_vector(env->intc_handle,
 107                                                 (env->sr >> 4) & 0xf);
 108         if (irq_vector == -1) {
 109             return; /* masked */
 110         }
 111     }
 112
 113     if (qemu_loglevel_mask(CPU_LOG_INT)) {
 114         const char *expname;
 115         switch (env->exception_index) {
 116         case 0x0e0:
 117             expname = "addr_error";
 118             break;
 119         case 0x040:
 120             expname = "tlb_miss";
 121             break;
 122         case 0x0a0:
 123             expname = "tlb_violation";
 124             break;
 125         case 0x180:
 126             expname = "illegal_instruction";
 127             break;
 128         case 0x1a0:
 129             expname = "slot_illegal_instruction";
 130             break;
 131         case 0x800:
 132             expname = "fpu_disable";
 133             break;
 134         case 0x820:
 135             expname = "slot_fpu";
 136             break;
 137         case 0x100:
 138             expname = "data_write";
 139             break;
 140         case 0x060:
 141             expname = "dtlb_miss_write";
 142             break;
 143         case 0x0c0:
 144             expname = "dtlb_violation_write";
 145             break;
 146         case 0x120:
 147             expname = "fpu_exception";
 148             break;
 149         case 0x080:
 150             expname = "initial_page_write";
 151             break;
 152         case 0x160:
 153             expname = "trapa";
 154             break;
 155         default:
 156             expname = do_irq ? "interrupt" : "???";
 157             break;
 158         }
 159         qemu_log("exception 0x%03x [%s] raised\n",
 160                   irq_vector, expname);
 161         log_cpu_state(env, 0);
 162     }
 163
 164     env->ssr = env->sr;
 165     env->spc = env->pc;
 166     env->sgr = env->gregs[15];
 167     env->sr |= SR_BL | SR_MD | SR_RB;
 168
 169     if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
 170         /* Branch instruction should be executed again before delay slot. */
 171         env->spc -= 2;
 172         /* Clear flags for exception/interrupt routine. */
 173         env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
 174     }
 175     if (env->flags & DELAY_SLOT_CLEARME)
 176         env->flags = 0;
 177
 178     if (do_exp) {
 179         env->expevt = env->exception_index;
 180         switch (env->exception_index) {
 181         case 0x000:
 182         case 0x020:
 183         case 0x140:
 184             env->sr &= ~SR_FD;
 185             env->sr |= 0xf << 4; /* IMASK */
 186             env->pc = 0xa0000000;
 187             break;
 188         case 0x040:
 189         case 0x060:
 190             env->pc = env->vbr + 0x400;
 191             break;
 192         case 0x160:
 193             env->spc += 2; /* special case for TRAPA */
 194             /* fall through */
 195         default:
 196             env->pc = env->vbr + 0x100;
 197             break;
 198         }
 199         return;
 200     }
 201
 202     if (do_irq) {
 203         env->intevt = irq_vector;
 204         env->pc = env->vbr + 0x600;
 205         return;
 206     }
 207 }
 208
 209 static void update_itlb_use(CPUState * env, int itlbnb)
 210 {
 211     uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
 212
 213     switch (itlbnb) {
 214     case 0:
 215         and_mask = 0x1f;
 216         break;
 217     case 1:
 218         and_mask = 0xe7;
 219         or_mask = 0x80;
 220         break;
 221     case 2:
 222         and_mask = 0xfb;
 223         or_mask = 0x50;
 224         break;
 225     case 3:
 226         or_mask = 0x2c;
 227         break;
 228     }
 229
 230     env->mmucr &= (and_mask << 24) | 0x00ffffff;
 231     env->mmucr |= (or_mask << 24);
 232 }
 233
 234 static int itlb_replacement(CPUState * env)
 235 {
 236     if ((env->mmucr & 0xe0000000) == 0xe0000000)
 237         return 0;
 238     if ((env->mmucr & 0x98000000) == 0x18000000)
 239         return 1;
 240     if ((env->mmucr & 0x54000000) == 0x04000000)
 241         return 2;
 242     if ((env->mmucr & 0x2c000000) == 0x00000000)
 243         return 3;
 244     assert(0);
 245 }
 246
 247 /* Find the corresponding entry in the right TLB
 248    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
 249 */
 250 static int find_tlb_entry(CPUState * env, target_ulong address,
 251                           tlb_t * entries, uint8_t nbtlb, int use_asid)
 252 {
 253     int match = MMU_DTLB_MISS;
 254     uint32_t start, end;
 255     uint8_t asid;
 256     int i;
 257
 258     asid = env->pteh & 0xff;
 259
 260     for (i = 0; i < nbtlb; i++) {
 261         if (!entries[i].v)
 262             continue;           /* Invalid entry */
 263         if (!entries[i].sh && use_asid && entries[i].asid != asid)
 264             continue;           /* Bad ASID */
 265 #if 0
 266         switch (entries[i].sz) {
 267         case 0:
 268             size = 1024;        /* 1kB */
 269             break;
 270         case 1:
 271             size = 4 * 1024;    /* 4kB */
 272             break;
 273         case 2:
 274             size = 64 * 1024;   /* 64kB */
 275             break;
 276         case 3:
 277             size = 1024 * 1024; /* 1MB */
 278             break;
 279         default:
 280             assert(0);
 281         }
 282 #endif
 283         start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
 284         end = start + entries[i].size - 1;
 285         if (address >= start && address <= end) {       /* Match */
 286             if (match != MMU_DTLB_MISS)
 287                 return MMU_DTLB_MULTIPLE;       /* Multiple match */
 288             match = i;
 289         }
 290     }
 291     return match;
 292 }
 293
 294 static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
 295                                  const tlb_t * needle)
 296 {
 297     int i;
 298     for (i = 0; i < nbtlb; i++)
 299         if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
 300             return 1;
 301     return 0;
 302 }
 303
 304 static void increment_urc(CPUState * env)
 305 {
 306     uint8_t urb, urc;
 307
 308     /* Increment URC */
 309     urb = ((env->mmucr) >> 18) & 0x3f;
 310     urc = ((env->mmucr) >> 10) & 0x3f;
 311     urc++;
 312     if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
 313         urc = 0;
 314     env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
 315 }
 316
 317 /* Find itlb entry - update itlb from utlb if necessary and asked for
 318    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
 319    Update the itlb from utlb if update is not 0
 320 */
 321 static int find_itlb_entry(CPUState * env, target_ulong address,
 322                            int use_asid, int update)
 323 {
 324     int e, n;
 325
 326     e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
 327     if (e == MMU_DTLB_MULTIPLE)
 328         e = MMU_ITLB_MULTIPLE;
 329     else if (e == MMU_DTLB_MISS && update) {
 330         e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
 331         if (e >= 0) {
 332             tlb_t * ientry;
 333             n = itlb_replacement(env);
 334             ientry = &env->itlb[n];
 335             if (ientry->v) {
 336                 if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
 337                     tlb_flush_page(env, ientry->vpn << 10);
 338             }
 339             *ientry = env->utlb[e];
 340             e = n;
 341         } else if (e == MMU_DTLB_MISS)
 342             e = MMU_ITLB_MISS;
 343     } else if (e == MMU_DTLB_MISS)
 344         e = MMU_ITLB_MISS;
 345     if (e >= 0)
 346         update_itlb_use(env, e);
 347     return e;
 348 }
 349
 350 /* Find utlb entry
 351    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
 352 static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
 353 {
 354     /* per utlb access */
 355     increment_urc(env);
 356
 357     /* Return entry */
 358     return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
 359 }
 360
 361 /* Match address against MMU
 362    Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
 363    MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
 364    MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
 365    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
 366    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
 367 */
 368 static int get_mmu_address(CPUState * env, target_ulong * physical,
 369                            int *prot, target_ulong address,
 370                            int rw, int access_type)
 371 {
 372     int use_asid, n;
 373     tlb_t *matching = NULL;
 374
 375     use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
 376
 377     if (rw == 2) {
 378         n = find_itlb_entry(env, address, use_asid, 1);
 379         if (n >= 0) {
 380             matching = &env->itlb[n];
 381             if ((env->sr & SR_MD) & !(matching->pr & 2))
 382                 n = MMU_ITLB_VIOLATION;
 383             else
 384                 *prot = PAGE_READ;
 385         }
 386     } else {
 387         n = find_utlb_entry(env, address, use_asid);
 388         if (n >= 0) {
 389             matching = &env->utlb[n];
 390             switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
 391             case 0:             /* 000 */
 392             case 2:             /* 010 */
 393                 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
 394                     MMU_DTLB_VIOLATION_READ;
 395                 break;
 396             case 1:             /* 001 */
 397             case 4:             /* 100 */
 398             case 5:             /* 101 */
 399                 if (rw == 1)
 400                     n = MMU_DTLB_VIOLATION_WRITE;
 401                 else
 402                     *prot = PAGE_READ;
 403                 break;
 404             case 3:             /* 011 */
 405             case 6:             /* 110 */
 406             case 7:             /* 111 */
 407                 *prot = (rw == 1)? PAGE_WRITE : PAGE_READ;
 408                 break;
 409             }
 410         } else if (n == MMU_DTLB_MISS) {
 411             n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
 412                 MMU_DTLB_MISS_READ;
 413         }
 414     }
 415     if (n >= 0) {
 416         *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
 417             (address & (matching->size - 1));
 418         if ((rw == 1) & !matching->d)
 419             n = MMU_DTLB_INITIAL_WRITE;
 420         else
 421             n = MMU_OK;
 422     }
 423     return n;
 424 }
 425
 426 static int get_physical_address(CPUState * env, target_ulong * physical,
 427                                 int *prot, target_ulong address,
 428                                 int rw, int access_type)
 429 {
 430     /* P1, P2 and P4 areas do not use translation */
 431     if ((address >= 0x80000000 && address < 0xc0000000) ||
 432         address >= 0xe0000000) {
 433         if (!(env->sr & SR_MD)
 434             && (address < 0xe0000000 || address > 0xe4000000)) {
 435             /* Unauthorized access in user mode (only store queues are available) */
 436             fprintf(stderr, "Unauthorized access\n");
 437             if (rw == 0)
 438                 return MMU_DADDR_ERROR_READ;
 439             else if (rw == 1)
 440                 return MMU_DADDR_ERROR_WRITE;
 441             else
 442                 return MMU_IADDR_ERROR;
 443         }
 444         if (address >= 0x80000000 && address < 0xc0000000) {
 445             /* Mask upper 3 bits for P1 and P2 areas */
 446             *physical = address & 0x1fffffff;
 447         } else {
 448             *physical = address;
 449         }
 450         *prot = PAGE_READ | PAGE_WRITE;
 451         return MMU_OK;
 452     }
 453
 454     /* If MMU is disabled, return the corresponding physical page */
 455     if (!env->mmucr & MMUCR_AT) {
 456         *physical = address & 0x1FFFFFFF;
 457         *prot = PAGE_READ | PAGE_WRITE;
 458         return MMU_OK;
 459     }
 460
 461     /* We need to resort to the MMU */
 462     return get_mmu_address(env, physical, prot, address, rw, access_type);
 463 }
 464
 465 int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
 466                              int mmu_idx, int is_softmmu)
 467 {
 468     target_ulong physical, page_offset, page_size;
 469     int prot, ret, access_type;
 470
 471     access_type = ACCESS_INT;
 472     ret =
 473         get_physical_address(env, &physical, &prot, address, rw,
 474                              access_type);
 475
 476     if (ret != MMU_OK) {
 477         env->tea = address;
 478         switch (ret) {
 479         case MMU_ITLB_MISS:
 480         case MMU_DTLB_MISS_READ:
 481             env->exception_index = 0x040;
 482             break;
 483         case MMU_DTLB_MULTIPLE:
 484         case MMU_ITLB_MULTIPLE:
 485             env->exception_index = 0x140;
 486             break;
 487         case MMU_ITLB_VIOLATION:
 488             env->exception_index = 0x0a0;
 489             break;
 490         case MMU_DTLB_MISS_WRITE:
 491             env->exception_index = 0x060;
 492             break;
 493         case MMU_DTLB_INITIAL_WRITE:
 494             env->exception_index = 0x080;
 495             break;
 496         case MMU_DTLB_VIOLATION_READ:
 497             env->exception_index = 0x0a0;
 498             break;
 499         case MMU_DTLB_VIOLATION_WRITE:
 500             env->exception_index = 0x0c0;
 501             break;
 502         case MMU_IADDR_ERROR:
 503         case MMU_DADDR_ERROR_READ:
 504             env->exception_index = 0x0c0;
 505             break;
 506         case MMU_DADDR_ERROR_WRITE:
 507             env->exception_index = 0x100;
 508             break;
 509         default:
 510             assert(0);
 511         }
 512         return 1;
 513     }
 514
 515     page_size = TARGET_PAGE_SIZE;
 516     page_offset =
 517         (address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
 518     address = (address & TARGET_PAGE_MASK) + page_offset;
 519     physical = (physical & TARGET_PAGE_MASK) + page_offset;
 520
 521     return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
 522 }
 523
 524 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
 525 {
 526     target_ulong physical;
 527     int prot;
 528
 529     get_physical_address(env, &physical, &prot, addr, 0, 0);
 530     return physical;
 531 }
 532
 533 void cpu_load_tlb(CPUSH4State * env)
 534 {
 535     int n = cpu_mmucr_urc(env->mmucr);
 536     tlb_t * entry = &env->utlb[n];
 537
 538     if (entry->v) {
 539         /* Overwriting valid entry in utlb. */
 540         target_ulong address = entry->vpn << 10;
 541         if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
 542             tlb_flush_page(env, address);
 543         }
 544     }
 545
 546     /* Take values into cpu status from registers. */
 547     entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
 548     entry->vpn  = cpu_pteh_vpn(env->pteh);
 549     entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
 550     entry->ppn  = cpu_ptel_ppn(env->ptel);
 551     entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
 552     switch (entry->sz) {
 553     case 0: /* 00 */
 554         entry->size = 1024; /* 1K */
 555         break;
 556     case 1: /* 01 */
 557         entry->size = 1024 * 4; /* 4K */
 558         break;
 559     case 2: /* 10 */
 560         entry->size = 1024 * 64; /* 64K */
 561         break;
 562     case 3: /* 11 */
 563         entry->size = 1024 * 1024; /* 1M */
 564         break;
 565     default:
 566         assert(0);
 567         break;
 568     }
 569     entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
 570     entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
 571     entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
 572     entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
 573     entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
 574     entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
 575     entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
 576 }
 577
 578 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
 579                                     uint32_t mem_value)
 580 {
 581     int associate = addr & 0x0000080;
 582     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 583     uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
 584     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 585     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 586     int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;
 587
 588     if (associate) {
 589         int i;
 590         tlb_t * utlb_match_entry = NULL;
 591         int needs_tlb_flush = 0;
 592
 593         /* search UTLB */
 594         for (i = 0; i < UTLB_SIZE; i++) {
 595             tlb_t * entry = &s->utlb[i];
 596             if (!entry->v)
 597                 continue;
 598
 599             if (entry->vpn == vpn
 600                 && (!use_asid || entry->asid == asid || entry->sh)) {
 601                 if (utlb_match_entry) {
 602                     /* Multiple TLB Exception */
 603                     s->exception_index = 0x140;
 604                     s->tea = addr;
 605                     break;
 606                 }
 607                 if (entry->v && !v)
 608                     needs_tlb_flush = 1;
 609                 entry->v = v;
 610                 entry->d = d;
 611                 utlb_match_entry = entry;
 612             }
 613             increment_urc(s); /* per utlb access */
 614         }
 615
 616         /* search ITLB */
 617         for (i = 0; i < ITLB_SIZE; i++) {
 618             tlb_t * entry = &s->itlb[i];
 619             if (entry->vpn == vpn
 620                 && (!use_asid || entry->asid == asid || entry->sh)) {
 621                 if (entry->v && !v)
 622                     needs_tlb_flush = 1;
 623                 if (utlb_match_entry)
 624                     *entry = *utlb_match_entry;
 625                 else
 626                     entry->v = v;
 627                 break;
 628             }
 629         }
 630
 631         if (needs_tlb_flush)
 632             tlb_flush_page(s, vpn << 10);
 633
 634     } else {
 635         int index = (addr & 0x00003f00) >> 8;
 636         tlb_t * entry = &s->utlb[index];
 637         if (entry->v) {
 638             /* Overwriting valid entry in utlb. */
 639             target_ulong address = entry->vpn << 10;
 640             if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
 641                 tlb_flush_page(s, address);
 642             }
 643         }
 644         entry->asid = asid;
 645         entry->vpn = vpn;
 646         entry->d = d;
 647         entry->v = v;
 648         increment_urc(s);
 649     }
 650 }
 651
 652 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
 653 {
 654     int n;
 655     int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
 656
 657     /* check area */
 658     if (env->sr & SR_MD) {
 659         /* For previledged mode, P2 and P4 area is not cachable. */
 660         if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
 661             return 0;
 662     } else {
 663         /* For user mode, only U0 area is cachable. */
 664         if (0x80000000 <= addr)
 665             return 0;
 666     }
 667
 668     /*
 669      * TODO : Evaluate CCR and check if the cache is on or off.
 670      *        Now CCR is not in CPUSH4State, but in SH7750State.
 671      *        When you move the ccr inot CPUSH4State, the code will be
 672      *        as follows.
 673      */
 674 #if 0
 675     /* check if operand cache is enabled or not. */
 676     if (!(env->ccr & 1))
 677         return 0;
 678 #endif
 679
 680     /* if MMU is off, no check for TLB. */
 681     if (env->mmucr & MMUCR_AT)
 682         return 1;
 683
 684     /* check TLB */
 685     n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
 686     if (n >= 0)
 687         return env->itlb[n].c;
 688
 689     n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
 690     if (n >= 0)
 691         return env->utlb[n].c;
 692
 693     return 0;
 694 }
 695
 696 #endif