9 #include "qemu-common.h"
11 static uint32_t cortexa8_cp15_c0_c1
[8] =
12 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
14 static uint32_t cortexa8_cp15_c0_c2
[8] =
15 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
17 static uint32_t mpcore_cp15_c0_c1
[8] =
18 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
20 static uint32_t mpcore_cp15_c0_c2
[8] =
21 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
23 static uint32_t arm1136_cp15_c0_c1
[8] =
24 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
26 static uint32_t arm1136_cp15_c0_c2
[8] =
27 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
29 static uint32_t cpu_arm_find_by_name(const char *name
);
31 static inline void set_feature(CPUARMState
*env
, int feature
)
33 env
->features
|= 1u << feature
;
36 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
38 env
->cp15
.c0_cpuid
= id
;
40 case ARM_CPUID_ARM920T
:
41 set_feature(env
, ARM_FEATURE_S3C
);
42 env
->cp15
.c0_cachetype
= 0xd172172;
43 env
->cp15
.c1_sys
= 0x00000078;
45 case ARM_CPUID_ARM926
:
46 set_feature(env
, ARM_FEATURE_VFP
);
47 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
48 env
->cp15
.c0_cachetype
= 0x1dd20d2;
49 env
->cp15
.c1_sys
= 0x00090078;
51 case ARM_CPUID_ARM946
:
52 set_feature(env
, ARM_FEATURE_MPU
);
53 env
->cp15
.c0_cachetype
= 0x0f004006;
54 env
->cp15
.c1_sys
= 0x00000078;
56 case ARM_CPUID_ARM1026
:
57 set_feature(env
, ARM_FEATURE_VFP
);
58 set_feature(env
, ARM_FEATURE_AUXCR
);
59 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
60 env
->cp15
.c0_cachetype
= 0x1dd20d2;
61 env
->cp15
.c1_sys
= 0x00090078;
63 case ARM_CPUID_ARM1136_R2
:
64 case ARM_CPUID_ARM1136
:
65 set_feature(env
, ARM_FEATURE_V6
);
66 set_feature(env
, ARM_FEATURE_VFP
);
67 set_feature(env
, ARM_FEATURE_AUXCR
);
68 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
69 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
70 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
71 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
72 memcpy(env
->cp15
.c0_c2
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
73 env
->cp15
.c0_cachetype
= 0x1dd20d2;
75 case ARM_CPUID_ARM11MPCORE
:
76 set_feature(env
, ARM_FEATURE_V6
);
77 set_feature(env
, ARM_FEATURE_V6K
);
78 set_feature(env
, ARM_FEATURE_VFP
);
79 set_feature(env
, ARM_FEATURE_AUXCR
);
80 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
81 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
82 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
83 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
84 memcpy(env
->cp15
.c0_c2
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
85 env
->cp15
.c0_cachetype
= 0x1dd20d2;
87 case ARM_CPUID_CORTEXA8
:
88 set_feature(env
, ARM_FEATURE_V6
);
89 set_feature(env
, ARM_FEATURE_V6K
);
90 set_feature(env
, ARM_FEATURE_V7
);
91 set_feature(env
, ARM_FEATURE_AUXCR
);
92 set_feature(env
, ARM_FEATURE_THUMB2
);
93 set_feature(env
, ARM_FEATURE_VFP
);
94 set_feature(env
, ARM_FEATURE_VFP3
);
95 set_feature(env
, ARM_FEATURE_NEON
);
96 set_feature(env
, ARM_FEATURE_THUMB2EE
);
97 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
98 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
99 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
100 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
101 memcpy(env
->cp15
.c0_c2
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
102 env
->cp15
.c0_cachetype
= 0x82048004;
103 env
->cp15
.c0_clid
= (1 << 27) | (2 << 24) | 3;
104 env
->cp15
.c0_ccsid
[0] = 0xe007e01a; /* 16k L1 dcache. */
105 env
->cp15
.c0_ccsid
[1] = 0x2007e01a; /* 16k L1 icache. */
106 env
->cp15
.c0_ccsid
[2] = 0xf0000000; /* No L2 icache. */
108 case ARM_CPUID_CORTEXM3
:
109 set_feature(env
, ARM_FEATURE_V6
);
110 set_feature(env
, ARM_FEATURE_THUMB2
);
111 set_feature(env
, ARM_FEATURE_V7
);
112 set_feature(env
, ARM_FEATURE_M
);
113 set_feature(env
, ARM_FEATURE_DIV
);
115 case ARM_CPUID_ANY
: /* For userspace emulation. */
116 set_feature(env
, ARM_FEATURE_V6
);
117 set_feature(env
, ARM_FEATURE_V6K
);
118 set_feature(env
, ARM_FEATURE_V7
);
119 set_feature(env
, ARM_FEATURE_THUMB2
);
120 set_feature(env
, ARM_FEATURE_VFP
);
121 set_feature(env
, ARM_FEATURE_VFP3
);
122 set_feature(env
, ARM_FEATURE_NEON
);
123 set_feature(env
, ARM_FEATURE_THUMB2EE
);
124 set_feature(env
, ARM_FEATURE_DIV
);
126 case ARM_CPUID_TI915T
:
127 case ARM_CPUID_TI925T
:
128 set_feature(env
, ARM_FEATURE_OMAPCP
);
129 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
130 env
->cp15
.c0_cachetype
= 0x5109149;
131 env
->cp15
.c1_sys
= 0x00000070;
132 env
->cp15
.c15_i_max
= 0x000;
133 env
->cp15
.c15_i_min
= 0xff0;
135 case ARM_CPUID_PXA250
:
136 case ARM_CPUID_PXA255
:
137 case ARM_CPUID_PXA260
:
138 case ARM_CPUID_PXA261
:
139 case ARM_CPUID_PXA262
:
140 set_feature(env
, ARM_FEATURE_XSCALE
);
141 /* JTAG_ID is ((id << 28) | 0x09265013) */
142 env
->cp15
.c0_cachetype
= 0xd172172;
143 env
->cp15
.c1_sys
= 0x00000078;
145 case ARM_CPUID_PXA270_A0
:
146 case ARM_CPUID_PXA270_A1
:
147 case ARM_CPUID_PXA270_B0
:
148 case ARM_CPUID_PXA270_B1
:
149 case ARM_CPUID_PXA270_C0
:
150 case ARM_CPUID_PXA270_C5
:
151 set_feature(env
, ARM_FEATURE_XSCALE
);
152 /* JTAG_ID is ((id << 28) | 0x09265013) */
153 set_feature(env
, ARM_FEATURE_IWMMXT
);
154 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
155 env
->cp15
.c0_cachetype
= 0xd172172;
156 env
->cp15
.c1_sys
= 0x00000078;
159 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
164 void cpu_reset(CPUARMState
*env
)
168 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
169 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
170 log_cpu_state(env
, 0);
173 id
= env
->cp15
.c0_cpuid
;
174 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
176 cpu_reset_model_id(env
, id
);
177 #if defined (CONFIG_USER_ONLY)
178 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
179 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
181 /* SVC mode with interrupts disabled. */
182 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
183 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
186 env
->uncached_cpsr
&= ~CPSR_I
;
187 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
188 env
->cp15
.c2_base_mask
= 0xffffc000u
;
194 static int vfp_gdb_get_reg(CPUState
*env
, uint8_t *buf
, int reg
)
198 /* VFP data registers are always little-endian. */
199 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
201 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
204 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
205 /* Aliases for Q regs. */
208 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
209 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
213 switch (reg
- nregs
) {
214 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
215 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
216 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
221 static int vfp_gdb_set_reg(CPUState
*env
, uint8_t *buf
, int reg
)
225 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
227 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
230 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
233 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
234 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
238 switch (reg
- nregs
) {
239 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
240 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
241 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
); return 4;
246 CPUARMState
*cpu_arm_init(const char *cpu_model
)
250 static int inited
= 0;
252 id
= cpu_arm_find_by_name(cpu_model
);
255 env
= qemu_mallocz(sizeof(CPUARMState
));
259 arm_translate_init();
262 env
->cpu_model_str
= cpu_model
;
263 env
->cp15
.c0_cpuid
= id
;
265 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
266 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
267 51, "arm-neon.xml", 0);
268 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
269 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
270 35, "arm-vfp3.xml", 0);
271 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
272 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
273 19, "arm-vfp.xml", 0);
284 static const struct arm_cpu_t arm_cpu_names
[] = {
285 { ARM_CPUID_ARM920T
, "arm920t"},
286 { ARM_CPUID_ARM926
, "arm926"},
287 { ARM_CPUID_ARM946
, "arm946"},
288 { ARM_CPUID_ARM1026
, "arm1026"},
289 { ARM_CPUID_ARM1136
, "arm1136"},
290 { ARM_CPUID_ARM1136_R2
, "arm1136-r2"},
291 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
292 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
293 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
294 { ARM_CPUID_TI925T
, "ti925t" },
295 { ARM_CPUID_PXA250
, "pxa250" },
296 { ARM_CPUID_PXA255
, "pxa255" },
297 { ARM_CPUID_PXA260
, "pxa260" },
298 { ARM_CPUID_PXA261
, "pxa261" },
299 { ARM_CPUID_PXA262
, "pxa262" },
300 { ARM_CPUID_PXA270
, "pxa270" },
301 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
302 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
303 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
304 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
305 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
306 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
307 { ARM_CPUID_ANY
, "any"},
311 void arm_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
315 (*cpu_fprintf
)(f
, "Available CPUs:\n");
316 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
317 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
321 /* return 0 if not found */
322 static uint32_t cpu_arm_find_by_name(const char *name
)
328 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
329 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
330 id
= arm_cpu_names
[i
].id
;
337 void cpu_arm_close(CPUARMState
*env
)
342 uint32_t cpsr_read(CPUARMState
*env
)
346 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
347 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
348 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
349 | ((env
->condexec_bits
& 0xfc) << 8)
353 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
355 if (mask
& CPSR_NZCV
) {
356 env
->ZF
= (~val
) & CPSR_Z
;
358 env
->CF
= (val
>> 29) & 1;
359 env
->VF
= (val
<< 3) & 0x80000000;
362 env
->QF
= ((val
& CPSR_Q
) != 0);
364 env
->thumb
= ((val
& CPSR_T
) != 0);
365 if (mask
& CPSR_IT_0_1
) {
366 env
->condexec_bits
&= ~3;
367 env
->condexec_bits
|= (val
>> 25) & 3;
369 if (mask
& CPSR_IT_2_7
) {
370 env
->condexec_bits
&= 3;
371 env
->condexec_bits
|= (val
>> 8) & 0xfc;
373 if (mask
& CPSR_GE
) {
374 env
->GE
= (val
>> 16) & 0xf;
377 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
378 switch_mode(env
, val
& CPSR_M
);
380 mask
&= ~CACHED_CPSR_BITS
;
381 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
384 /* Sign/zero extend */
385 uint32_t HELPER(sxtb16
)(uint32_t x
)
388 res
= (uint16_t)(int8_t)x
;
389 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
393 uint32_t HELPER(uxtb16
)(uint32_t x
)
396 res
= (uint16_t)(uint8_t)x
;
397 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
401 uint32_t HELPER(clz
)(uint32_t x
)
404 for (count
= 32; x
; count
--)
409 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
416 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
423 uint32_t HELPER(rbit
)(uint32_t x
)
425 x
= ((x
& 0xff000000) >> 24)
426 | ((x
& 0x00ff0000) >> 8)
427 | ((x
& 0x0000ff00) << 8)
428 | ((x
& 0x000000ff) << 24);
429 x
= ((x
& 0xf0f0f0f0) >> 4)
430 | ((x
& 0x0f0f0f0f) << 4);
431 x
= ((x
& 0x88888888) >> 3)
432 | ((x
& 0x44444444) >> 1)
433 | ((x
& 0x22222222) << 1)
434 | ((x
& 0x11111111) << 3);
438 uint32_t HELPER(abs
)(uint32_t x
)
440 return ((int32_t)x
< 0) ? -x
: x
;
443 #if defined(CONFIG_USER_ONLY)
445 void do_interrupt (CPUState
*env
)
447 env
->exception_index
= -1;
450 /* Structure used to record exclusive memory locations. */
451 typedef struct mmon_state
{
452 struct mmon_state
*next
;
453 CPUARMState
*cpu_env
;
457 /* Chain of current locks. */
458 static mmon_state
* mmon_head
= NULL
;
460 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
461 int mmu_idx
, int is_softmmu
)
464 env
->exception_index
= EXCP_PREFETCH_ABORT
;
465 env
->cp15
.c6_insn
= address
;
467 env
->exception_index
= EXCP_DATA_ABORT
;
468 env
->cp15
.c6_data
= address
;
473 static void allocate_mmon_state(CPUState
*env
)
475 env
->mmon_entry
= malloc(sizeof (mmon_state
));
476 memset (env
->mmon_entry
, 0, sizeof (mmon_state
));
477 env
->mmon_entry
->cpu_env
= env
;
478 mmon_head
= env
->mmon_entry
;
481 /* Flush any monitor locks for the specified address. */
482 static void flush_mmon(uint32_t addr
)
486 for (mon
= mmon_head
; mon
; mon
= mon
->next
)
488 if (mon
->addr
!= addr
)
496 /* Mark an address for exclusive access. */
497 void HELPER(mark_exclusive
)(CPUState
*env
, uint32_t addr
)
499 if (!env
->mmon_entry
)
500 allocate_mmon_state(env
);
501 /* Clear any previous locks. */
503 env
->mmon_entry
->addr
= addr
;
506 /* Test if an exclusive address is still exclusive. Returns zero
507 if the address is still exclusive. */
508 uint32_t HELPER(test_exclusive
)(CPUState
*env
, uint32_t addr
)
512 if (!env
->mmon_entry
)
514 if (env
->mmon_entry
->addr
== addr
)
522 void HELPER(clrex
)(CPUState
*env
)
524 if (!(env
->mmon_entry
&& env
->mmon_entry
->addr
))
526 flush_mmon(env
->mmon_entry
->addr
);
529 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
534 /* These should probably raise undefined insn exceptions. */
535 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
537 int op1
= (insn
>> 8) & 0xf;
538 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
542 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
544 int op1
= (insn
>> 8) & 0xf;
545 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
549 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
551 cpu_abort(env
, "cp15 insn %08x\n", insn
);
554 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
556 cpu_abort(env
, "cp15 insn %08x\n", insn
);
560 /* These should probably raise undefined insn exceptions. */
561 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
563 cpu_abort(env
, "v7m_mrs %d\n", reg
);
566 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
568 cpu_abort(env
, "v7m_mrs %d\n", reg
);
572 void switch_mode(CPUState
*env
, int mode
)
574 if (mode
!= ARM_CPU_MODE_USR
)
575 cpu_abort(env
, "Tried to switch out of user mode\n");
578 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
580 cpu_abort(env
, "banked r13 write\n");
583 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
585 cpu_abort(env
, "banked r13 read\n");
591 extern int semihosting_enabled
;
593 /* Map CPU modes onto saved register banks. */
594 static inline int bank_number (int mode
)
597 case ARM_CPU_MODE_USR
:
598 case ARM_CPU_MODE_SYS
:
600 case ARM_CPU_MODE_SVC
:
602 case ARM_CPU_MODE_ABT
:
604 case ARM_CPU_MODE_UND
:
606 case ARM_CPU_MODE_IRQ
:
608 case ARM_CPU_MODE_FIQ
:
611 cpu_abort(cpu_single_env
, "Bad mode %x\n", mode
);
615 void switch_mode(CPUState
*env
, int mode
)
620 old_mode
= env
->uncached_cpsr
& CPSR_M
;
621 if (mode
== old_mode
)
624 if (old_mode
== ARM_CPU_MODE_FIQ
) {
625 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
626 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
627 } else if (mode
== ARM_CPU_MODE_FIQ
) {
628 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
629 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
632 i
= bank_number(old_mode
);
633 env
->banked_r13
[i
] = env
->regs
[13];
634 env
->banked_r14
[i
] = env
->regs
[14];
635 env
->banked_spsr
[i
] = env
->spsr
;
637 i
= bank_number(mode
);
638 env
->regs
[13] = env
->banked_r13
[i
];
639 env
->regs
[14] = env
->banked_r14
[i
];
640 env
->spsr
= env
->banked_spsr
[i
];
643 static void v7m_push(CPUARMState
*env
, uint32_t val
)
646 stl_phys(env
->regs
[13], val
);
649 static uint32_t v7m_pop(CPUARMState
*env
)
652 val
= ldl_phys(env
->regs
[13]);
657 /* Switch to V7M main or process stack pointer. */
658 static void switch_v7m_sp(CPUARMState
*env
, int process
)
661 if (env
->v7m
.current_sp
!= process
) {
662 tmp
= env
->v7m
.other_sp
;
663 env
->v7m
.other_sp
= env
->regs
[13];
665 env
->v7m
.current_sp
= process
;
669 static void do_v7m_exception_exit(CPUARMState
*env
)
674 type
= env
->regs
[15];
675 if (env
->v7m
.exception
!= 0)
676 armv7m_nvic_complete_irq(env
->v7m
.nvic
, env
->v7m
.exception
);
678 /* Switch to the target stack. */
679 switch_v7m_sp(env
, (type
& 4) != 0);
681 env
->regs
[0] = v7m_pop(env
);
682 env
->regs
[1] = v7m_pop(env
);
683 env
->regs
[2] = v7m_pop(env
);
684 env
->regs
[3] = v7m_pop(env
);
685 env
->regs
[12] = v7m_pop(env
);
686 env
->regs
[14] = v7m_pop(env
);
687 env
->regs
[15] = v7m_pop(env
);
689 xpsr_write(env
, xpsr
, 0xfffffdff);
690 /* Undo stack alignment. */
693 /* ??? The exception return type specifies Thread/Handler mode. However
694 this is also implied by the xPSR value. Not sure what to do
695 if there is a mismatch. */
696 /* ??? Likewise for mismatches between the CONTROL register and the stack
700 static void do_interrupt_v7m(CPUARMState
*env
)
702 uint32_t xpsr
= xpsr_read(env
);
707 if (env
->v7m
.current_sp
)
709 if (env
->v7m
.exception
== 0)
712 /* For exceptions we just mark as pending on the NVIC, and let that
714 /* TODO: Need to escalate if the current priority is higher than the
715 one we're raising. */
716 switch (env
->exception_index
) {
718 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_USAGE
);
722 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_SVC
);
724 case EXCP_PREFETCH_ABORT
:
725 case EXCP_DATA_ABORT
:
726 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_MEM
);
729 if (semihosting_enabled
) {
731 nr
= lduw_code(env
->regs
[15]) & 0xff;
734 env
->regs
[0] = do_arm_semihosting(env
);
738 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_DEBUG
);
741 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->v7m
.nvic
);
743 case EXCP_EXCEPTION_EXIT
:
744 do_v7m_exception_exit(env
);
747 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
748 return; /* Never happens. Keep compiler happy. */
751 /* Align stack pointer. */
752 /* ??? Should only do this if Configuration Control Register
753 STACKALIGN bit is set. */
754 if (env
->regs
[13] & 4) {
758 /* Switch to the handler mode. */
760 v7m_push(env
, env
->regs
[15]);
761 v7m_push(env
, env
->regs
[14]);
762 v7m_push(env
, env
->regs
[12]);
763 v7m_push(env
, env
->regs
[3]);
764 v7m_push(env
, env
->regs
[2]);
765 v7m_push(env
, env
->regs
[1]);
766 v7m_push(env
, env
->regs
[0]);
767 switch_v7m_sp(env
, 0);
768 env
->uncached_cpsr
&= ~CPSR_IT
;
770 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
771 env
->regs
[15] = addr
& 0xfffffffe;
772 env
->thumb
= addr
& 1;
775 /* Handle a CPU exception. */
776 void do_interrupt(CPUARMState
*env
)
784 do_interrupt_v7m(env
);
787 /* TODO: Vectored interrupt controller. */
788 switch (env
->exception_index
) {
790 new_mode
= ARM_CPU_MODE_UND
;
799 if (semihosting_enabled
) {
800 /* Check for semihosting interrupt. */
802 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
804 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
806 /* Only intercept calls from privileged modes, to provide some
807 semblance of security. */
808 if (((mask
== 0x123456 && !env
->thumb
)
809 || (mask
== 0xab && env
->thumb
))
810 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
811 env
->regs
[0] = do_arm_semihosting(env
);
815 new_mode
= ARM_CPU_MODE_SVC
;
818 /* The PC already points to the next instruction. */
822 /* See if this is a semihosting syscall. */
823 if (env
->thumb
&& semihosting_enabled
) {
824 mask
= lduw_code(env
->regs
[15]) & 0xff;
826 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
828 env
->regs
[0] = do_arm_semihosting(env
);
832 /* Fall through to prefetch abort. */
833 case EXCP_PREFETCH_ABORT
:
834 new_mode
= ARM_CPU_MODE_ABT
;
836 mask
= CPSR_A
| CPSR_I
;
839 case EXCP_DATA_ABORT
:
840 new_mode
= ARM_CPU_MODE_ABT
;
842 mask
= CPSR_A
| CPSR_I
;
846 new_mode
= ARM_CPU_MODE_IRQ
;
848 /* Disable IRQ and imprecise data aborts. */
849 mask
= CPSR_A
| CPSR_I
;
853 new_mode
= ARM_CPU_MODE_FIQ
;
855 /* Disable FIQ, IRQ and imprecise data aborts. */
856 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
860 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
861 return; /* Never happens. Keep compiler happy. */
864 if (env
->cp15
.c1_sys
& (1 << 13)) {
867 switch_mode (env
, new_mode
);
868 env
->spsr
= cpsr_read(env
);
870 env
->condexec_bits
= 0;
871 /* Switch to the new mode, and switch to Arm mode. */
872 /* ??? Thumb interrupt handlers not implemented. */
873 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
874 env
->uncached_cpsr
|= mask
;
876 env
->regs
[14] = env
->regs
[15] + offset
;
877 env
->regs
[15] = addr
;
878 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
881 /* Check section/page access permissions.
882 Returns the page protection flags, or zero if the access is not
884 static inline int check_ap(CPUState
*env
, int ap
, int domain
, int access_type
,
890 return PAGE_READ
| PAGE_WRITE
;
892 if (access_type
== 1)
899 if (access_type
== 1)
901 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
903 return is_user
? 0 : PAGE_READ
;
910 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
915 return PAGE_READ
| PAGE_WRITE
;
917 return PAGE_READ
| PAGE_WRITE
;
918 case 4: /* Reserved. */
921 return is_user
? 0 : prot_ro
;
925 if (!arm_feature (env
, ARM_FEATURE_V7
))
933 static uint32_t get_level1_table_address(CPUState
*env
, uint32_t address
)
937 if (address
& env
->cp15
.c2_mask
)
938 table
= env
->cp15
.c2_base1
& 0xffffc000;
940 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
942 table
|= (address
>> 18) & 0x3ffc;
946 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
947 int is_user
, uint32_t *phys_ptr
, int *prot
)
957 /* Pagetable walk. */
958 /* Lookup l1 descriptor. */
959 table
= get_level1_table_address(env
, address
);
960 desc
= ldl_phys(table
);
962 domain
= (env
->cp15
.c3
>> ((desc
>> 4) & 0x1e)) & 3;
964 /* Section translation fault. */
968 if (domain
== 0 || domain
== 2) {
970 code
= 9; /* Section domain fault. */
972 code
= 11; /* Page domain fault. */
977 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
978 ap
= (desc
>> 10) & 3;
981 /* Lookup l2 entry. */
983 /* Coarse pagetable. */
984 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
986 /* Fine pagetable. */
987 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
989 desc
= ldl_phys(table
);
991 case 0: /* Page translation fault. */
994 case 1: /* 64k page. */
995 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
996 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
998 case 2: /* 4k page. */
999 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1000 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1002 case 3: /* 1k page. */
1004 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1005 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1007 /* Page translation fault. */
1012 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1014 ap
= (desc
>> 4) & 3;
1017 /* Never happens, but compiler isn't smart enough to tell. */
1022 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1024 /* Access permission fault. */
1027 *phys_ptr
= phys_addr
;
1030 return code
| (domain
<< 4);
1033 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
1034 int is_user
, uint32_t *phys_ptr
, int *prot
)
1045 /* Pagetable walk. */
1046 /* Lookup l1 descriptor. */
1047 table
= get_level1_table_address(env
, address
);
1048 desc
= ldl_phys(table
);
1051 /* Section translation fault. */
1055 } else if (type
== 2 && (desc
& (1 << 18))) {
1059 /* Section or page. */
1060 domain
= (desc
>> 4) & 0x1e;
1062 domain
= (env
->cp15
.c3
>> domain
) & 3;
1063 if (domain
== 0 || domain
== 2) {
1065 code
= 9; /* Section domain fault. */
1067 code
= 11; /* Page domain fault. */
1071 if (desc
& (1 << 18)) {
1073 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1076 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1078 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1079 xn
= desc
& (1 << 4);
1082 /* Lookup l2 entry. */
1083 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1084 desc
= ldl_phys(table
);
1085 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1087 case 0: /* Page translation fault. */
1090 case 1: /* 64k page. */
1091 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1092 xn
= desc
& (1 << 15);
1094 case 2: case 3: /* 4k page. */
1095 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1099 /* Never happens, but compiler isn't smart enough to tell. */
1104 if (xn
&& access_type
== 2)
1107 /* The simplified model uses AP[0] as an access control bit. */
1108 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1109 /* Access flag fault. */
1110 code
= (code
== 15) ? 6 : 3;
1113 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1115 /* Access permission fault. */
1118 *phys_ptr
= phys_addr
;
1121 return code
| (domain
<< 4);
1124 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
1125 int is_user
, uint32_t *phys_ptr
, int *prot
)
1131 *phys_ptr
= address
;
1132 for (n
= 7; n
>= 0; n
--) {
1133 base
= env
->cp15
.c6_region
[n
];
1134 if ((base
& 1) == 0)
1136 mask
= 1 << ((base
>> 1) & 0x1f);
1137 /* Keep this shift separate from the above to avoid an
1138 (undefined) << 32. */
1139 mask
= (mask
<< 1) - 1;
1140 if (((base
^ address
) & ~mask
) == 0)
1146 if (access_type
== 2) {
1147 mask
= env
->cp15
.c5_insn
;
1149 mask
= env
->cp15
.c5_data
;
1151 mask
= (mask
>> (n
* 4)) & 0xf;
1158 *prot
= PAGE_READ
| PAGE_WRITE
;
1163 *prot
|= PAGE_WRITE
;
1166 *prot
= PAGE_READ
| PAGE_WRITE
;
1177 /* Bad permission. */
1183 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1184 int access_type
, int is_user
,
1185 uint32_t *phys_ptr
, int *prot
)
1187 /* Fast Context Switch Extension. */
1188 if (address
< 0x02000000)
1189 address
+= env
->cp15
.c13_fcse
;
1191 if ((env
->cp15
.c1_sys
& 1) == 0) {
1192 /* MMU/MPU disabled. */
1193 *phys_ptr
= address
;
1194 *prot
= PAGE_READ
| PAGE_WRITE
;
1196 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1197 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1199 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1200 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1203 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1208 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1209 int access_type
, int mmu_idx
, int is_softmmu
)
1215 is_user
= mmu_idx
== MMU_USER_IDX
;
1216 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
);
1218 /* Map a single [sub]page. */
1219 phys_addr
&= ~(uint32_t)0x3ff;
1220 address
&= ~(uint32_t)0x3ff;
1221 return tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
,
1225 if (access_type
== 2) {
1226 env
->cp15
.c5_insn
= ret
;
1227 env
->cp15
.c6_insn
= address
;
1228 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1230 env
->cp15
.c5_data
= ret
;
1231 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1232 env
->cp15
.c5_data
|= (1 << 11);
1233 env
->cp15
.c6_data
= address
;
1234 env
->exception_index
= EXCP_DATA_ABORT
;
1239 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1245 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
);
1253 /* Not really implemented. Need to figure out a sane way of doing this.
1254 Maybe add generic watchpoint support and use that. */
1256 void HELPER(mark_exclusive
)(CPUState
*env
, uint32_t addr
)
1258 env
->mmon_addr
= addr
;
1261 uint32_t HELPER(test_exclusive
)(CPUState
*env
, uint32_t addr
)
1263 return (env
->mmon_addr
!= addr
);
1266 void HELPER(clrex
)(CPUState
*env
)
1268 env
->mmon_addr
= -1;
1271 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1273 int cp_num
= (insn
>> 8) & 0xf;
1274 int cp_info
= (insn
>> 5) & 7;
1275 int src
= (insn
>> 16) & 0xf;
1276 int operand
= insn
& 0xf;
1278 if (env
->cp
[cp_num
].cp_write
)
1279 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1280 cp_info
, src
, operand
, val
);
1283 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
1285 int cp_num
= (insn
>> 8) & 0xf;
1286 int cp_info
= (insn
>> 5) & 7;
1287 int dest
= (insn
>> 16) & 0xf;
1288 int operand
= insn
& 0xf;
1290 if (env
->cp
[cp_num
].cp_read
)
1291 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1292 cp_info
, dest
, operand
);
1296 /* Return basic MPU access permission bits. */
1297 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1304 for (i
= 0; i
< 16; i
+= 2) {
1305 ret
|= (val
>> i
) & mask
;
1311 /* Pad basic MPU access permission bits to extended format. */
1312 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1319 for (i
= 0; i
< 16; i
+= 2) {
1320 ret
|= (val
& mask
) << i
;
1326 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1332 op1
= (insn
>> 21) & 7;
1333 op2
= (insn
>> 5) & 7;
1335 switch ((insn
>> 16) & 0xf) {
1338 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1340 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1342 if (arm_feature(env
, ARM_FEATURE_V7
)
1343 && op1
== 2 && crm
== 0 && op2
== 0) {
1344 env
->cp15
.c0_cssel
= val
& 0xf;
1348 case 1: /* System configuration. */
1349 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1353 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1354 env
->cp15
.c1_sys
= val
;
1355 /* ??? Lots of these bits are not implemented. */
1356 /* This may enable/disable the MMU, so do a TLB flush. */
1359 case 1: /* Auxiliary cotrol register. */
1360 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1361 env
->cp15
.c1_xscaleauxcr
= val
;
1364 /* Not implemented. */
1367 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1369 if (env
->cp15
.c1_coproc
!= val
) {
1370 env
->cp15
.c1_coproc
= val
;
1371 /* ??? Is this safe when called from within a TB? */
1379 case 2: /* MMU Page table control / MPU cache control. */
1380 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1383 env
->cp15
.c2_data
= val
;
1386 env
->cp15
.c2_insn
= val
;
1394 env
->cp15
.c2_base0
= val
;
1397 env
->cp15
.c2_base1
= val
;
1401 env
->cp15
.c2_control
= val
;
1402 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1403 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> val
);
1410 case 3: /* MMU Domain access control / MPU write buffer control. */
1412 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1414 case 4: /* Reserved. */
1416 case 5: /* MMU Fault status / MPU access permission. */
1417 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1421 if (arm_feature(env
, ARM_FEATURE_MPU
))
1422 val
= extended_mpu_ap_bits(val
);
1423 env
->cp15
.c5_data
= val
;
1426 if (arm_feature(env
, ARM_FEATURE_MPU
))
1427 val
= extended_mpu_ap_bits(val
);
1428 env
->cp15
.c5_insn
= val
;
1431 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1433 env
->cp15
.c5_data
= val
;
1436 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1438 env
->cp15
.c5_insn
= val
;
1444 case 6: /* MMU Fault address / MPU base/size. */
1445 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1448 env
->cp15
.c6_region
[crm
] = val
;
1450 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1454 env
->cp15
.c6_data
= val
;
1456 case 1: /* ??? This is WFAR on armv6 */
1458 env
->cp15
.c6_insn
= val
;
1465 case 7: /* Cache control. */
1466 env
->cp15
.c15_i_max
= 0x000;
1467 env
->cp15
.c15_i_min
= 0xff0;
1468 /* No cache, so nothing to do. */
1469 /* ??? MPCore has VA to PA translation functions. */
1471 case 8: /* MMU TLB control. */
1473 case 0: /* Invalidate all. */
1476 case 1: /* Invalidate single TLB entry. */
1478 /* ??? This is wrong for large pages and sections. */
1479 /* As an ugly hack to make linux work we always flush a 4K
1482 tlb_flush_page(env
, val
);
1483 tlb_flush_page(env
, val
+ 0x400);
1484 tlb_flush_page(env
, val
+ 0x800);
1485 tlb_flush_page(env
, val
+ 0xc00);
1490 case 2: /* Invalidate on ASID. */
1491 tlb_flush(env
, val
== 0);
1493 case 3: /* Invalidate single entry on MVA. */
1494 /* ??? This is like case 1, but ignores ASID. */
1502 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1505 case 0: /* Cache lockdown. */
1507 case 0: /* L1 cache. */
1510 env
->cp15
.c9_data
= val
;
1513 env
->cp15
.c9_insn
= val
;
1519 case 1: /* L2 cache. */
1520 /* Ignore writes to L2 lockdown/auxiliary registers. */
1526 case 1: /* TCM memory region registers. */
1527 /* Not implemented. */
1533 case 10: /* MMU TLB lockdown. */
1534 /* ??? TLB lockdown not implemented. */
1536 case 12: /* Reserved. */
1538 case 13: /* Process ID. */
1539 if (arm_feature(env
, ARM_FEATURE_S3C
))
1543 /* Unlike real hardware the qemu TLB uses virtual addresses,
1544 not modified virtual addresses, so this causes a TLB flush.
1546 if (env
->cp15
.c13_fcse
!= val
)
1548 env
->cp15
.c13_fcse
= val
;
1551 /* This changes the ASID, so do a TLB flush. */
1552 if (env
->cp15
.c13_context
!= val
1553 && !arm_feature(env
, ARM_FEATURE_MPU
))
1555 env
->cp15
.c13_context
= val
;
1558 env
->cp15
.c13_tls1
= val
;
1561 env
->cp15
.c13_tls2
= val
;
1564 env
->cp15
.c13_tls3
= val
;
1570 case 14: /* Reserved. */
1572 case 15: /* Implementation specific. */
1573 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1574 if (op2
== 0 && crm
== 1) {
1575 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1576 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1578 env
->cp15
.c15_cpar
= val
& 0x3fff;
1584 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1588 case 1: /* Set TI925T configuration. */
1589 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1590 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1591 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1593 case 2: /* Set I_max. */
1594 env
->cp15
.c15_i_max
= val
;
1596 case 3: /* Set I_min. */
1597 env
->cp15
.c15_i_min
= val
;
1599 case 4: /* Set thread-ID. */
1600 env
->cp15
.c15_threadid
= val
& 0xffff;
1602 case 8: /* Wait-for-interrupt (deprecated). */
1603 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1613 /* ??? For debugging only. Should raise illegal instruction exception. */
1614 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1615 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1618 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
1624 op1
= (insn
>> 21) & 7;
1625 op2
= (insn
>> 5) & 7;
1627 switch ((insn
>> 16) & 0xf) {
1628 case 0: /* ID codes. */
1634 case 0: /* Device ID. */
1635 return env
->cp15
.c0_cpuid
;
1636 case 1: /* Cache Type. */
1637 return env
->cp15
.c0_cachetype
;
1638 case 2: /* TCM status. */
1639 if (arm_feature(env
, ARM_FEATURE_S3C
))
1640 return env
->cp15
.c0_cpuid
;
1642 case 3: /* TLB type register. */
1643 return 0; /* No lockable TLB entries. */
1644 case 5: /* CPU ID */
1645 return env
->cpu_index
;
1650 if (!arm_feature(env
, ARM_FEATURE_V6
))
1652 return env
->cp15
.c0_c1
[op2
];
1654 if (!arm_feature(env
, ARM_FEATURE_V6
))
1656 return env
->cp15
.c0_c2
[op2
];
1657 case 3: case 4: case 5: case 6: case 7:
1663 /* These registers aren't documented on arm11 cores. However
1664 Linux looks at them anyway. */
1665 if (!arm_feature(env
, ARM_FEATURE_V6
))
1669 if (!arm_feature(env
, ARM_FEATURE_V7
))
1674 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1676 return env
->cp15
.c0_clid
;
1682 if (op2
!= 0 || crm
!= 0)
1684 return env
->cp15
.c0_cssel
;
1688 case 1: /* System configuration. */
1689 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1692 case 0: /* Control register. */
1693 return env
->cp15
.c1_sys
;
1694 case 1: /* Auxiliary control register. */
1695 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1696 return env
->cp15
.c1_xscaleauxcr
;
1697 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1699 switch (ARM_CPUID(env
)) {
1700 case ARM_CPUID_ARM1026
:
1702 case ARM_CPUID_ARM1136
:
1703 case ARM_CPUID_ARM1136_R2
:
1705 case ARM_CPUID_ARM11MPCORE
:
1707 case ARM_CPUID_CORTEXA8
:
1712 case 2: /* Coprocessor access register. */
1713 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1715 return env
->cp15
.c1_coproc
;
1719 case 2: /* MMU Page table control / MPU cache control. */
1720 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1723 return env
->cp15
.c2_data
;
1726 return env
->cp15
.c2_insn
;
1734 return env
->cp15
.c2_base0
;
1736 return env
->cp15
.c2_base1
;
1738 return env
->cp15
.c2_control
;
1743 case 3: /* MMU Domain access control / MPU write buffer control. */
1744 return env
->cp15
.c3
;
1745 case 4: /* Reserved. */
1747 case 5: /* MMU Fault status / MPU access permission. */
1748 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1752 if (arm_feature(env
, ARM_FEATURE_MPU
))
1753 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1754 return env
->cp15
.c5_data
;
1756 if (arm_feature(env
, ARM_FEATURE_MPU
))
1757 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1758 return env
->cp15
.c5_insn
;
1760 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1762 return env
->cp15
.c5_data
;
1764 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1766 return env
->cp15
.c5_insn
;
1770 case 6: /* MMU Fault address. */
1771 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1774 return env
->cp15
.c6_region
[crm
];
1776 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1780 return env
->cp15
.c6_data
;
1782 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1783 /* Watchpoint Fault Adrress. */
1784 return 0; /* Not implemented. */
1786 /* Instruction Fault Adrress. */
1787 /* Arm9 doesn't have an IFAR, but implementing it anyway
1788 shouldn't do any harm. */
1789 return env
->cp15
.c6_insn
;
1792 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1793 /* Instruction Fault Adrress. */
1794 return env
->cp15
.c6_insn
;
1802 case 7: /* Cache control. */
1803 /* FIXME: Should only clear Z flag if destination is r15. */
1806 case 8: /* MMU TLB control. */
1808 case 9: /* Cache lockdown. */
1810 case 0: /* L1 cache. */
1811 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1815 return env
->cp15
.c9_data
;
1817 return env
->cp15
.c9_insn
;
1821 case 1: /* L2 cache */
1824 /* L2 Lockdown and Auxiliary control. */
1829 case 10: /* MMU TLB lockdown. */
1830 /* ??? TLB lockdown not implemented. */
1832 case 11: /* TCM DMA control. */
1833 case 12: /* Reserved. */
1835 case 13: /* Process ID. */
1838 return env
->cp15
.c13_fcse
;
1840 return env
->cp15
.c13_context
;
1842 return env
->cp15
.c13_tls1
;
1844 return env
->cp15
.c13_tls2
;
1846 return env
->cp15
.c13_tls3
;
1850 case 14: /* Reserved. */
1852 case 15: /* Implementation specific. */
1853 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1854 if (op2
== 0 && crm
== 1)
1855 return env
->cp15
.c15_cpar
;
1859 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1863 case 1: /* Read TI925T configuration. */
1864 return env
->cp15
.c15_ticonfig
;
1865 case 2: /* Read I_max. */
1866 return env
->cp15
.c15_i_max
;
1867 case 3: /* Read I_min. */
1868 return env
->cp15
.c15_i_min
;
1869 case 4: /* Read thread-ID. */
1870 return env
->cp15
.c15_threadid
;
1871 case 8: /* TI925T_status */
1874 /* TODO: Peripheral port remap register:
1875 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1876 * controller base address at $rn & ~0xfff and map size of
1877 * 0x200 << ($rn & 0xfff), when MMU is off. */
1883 /* ??? For debugging only. Should raise illegal instruction exception. */
1884 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1885 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1889 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
1891 env
->banked_r13
[bank_number(mode
)] = val
;
1894 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
1896 return env
->banked_r13
[bank_number(mode
)];
1899 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
1903 return xpsr_read(env
) & 0xf8000000;
1905 return xpsr_read(env
) & 0xf80001ff;
1907 return xpsr_read(env
) & 0xff00fc00;
1909 return xpsr_read(env
) & 0xff00fdff;
1911 return xpsr_read(env
) & 0x000001ff;
1913 return xpsr_read(env
) & 0x0700fc00;
1915 return xpsr_read(env
) & 0x0700edff;
1917 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
1919 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
1920 case 16: /* PRIMASK */
1921 return (env
->uncached_cpsr
& CPSR_I
) != 0;
1922 case 17: /* FAULTMASK */
1923 return (env
->uncached_cpsr
& CPSR_F
) != 0;
1924 case 18: /* BASEPRI */
1925 case 19: /* BASEPRI_MAX */
1926 return env
->v7m
.basepri
;
1927 case 20: /* CONTROL */
1928 return env
->v7m
.control
;
1930 /* ??? For debugging only. */
1931 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
1936 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
1940 xpsr_write(env
, val
, 0xf8000000);
1943 xpsr_write(env
, val
, 0xf8000000);
1946 xpsr_write(env
, val
, 0xfe00fc00);
1949 xpsr_write(env
, val
, 0xfe00fc00);
1952 /* IPSR bits are readonly. */
1955 xpsr_write(env
, val
, 0x0600fc00);
1958 xpsr_write(env
, val
, 0x0600fc00);
1961 if (env
->v7m
.current_sp
)
1962 env
->v7m
.other_sp
= val
;
1964 env
->regs
[13] = val
;
1967 if (env
->v7m
.current_sp
)
1968 env
->regs
[13] = val
;
1970 env
->v7m
.other_sp
= val
;
1972 case 16: /* PRIMASK */
1974 env
->uncached_cpsr
|= CPSR_I
;
1976 env
->uncached_cpsr
&= ~CPSR_I
;
1978 case 17: /* FAULTMASK */
1980 env
->uncached_cpsr
|= CPSR_F
;
1982 env
->uncached_cpsr
&= ~CPSR_F
;
1984 case 18: /* BASEPRI */
1985 env
->v7m
.basepri
= val
& 0xff;
1987 case 19: /* BASEPRI_MAX */
1989 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
1990 env
->v7m
.basepri
= val
;
1992 case 20: /* CONTROL */
1993 env
->v7m
.control
= val
& 3;
1994 switch_v7m_sp(env
, (val
& 2) != 0);
1997 /* ??? For debugging only. */
1998 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2003 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
2004 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
2007 if (cpnum
< 0 || cpnum
> 14) {
2008 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
2012 env
->cp
[cpnum
].cp_read
= cp_read
;
2013 env
->cp
[cpnum
].cp_write
= cp_write
;
2014 env
->cp
[cpnum
].opaque
= opaque
;
2019 /* Note that signed overflow is undefined in C. The following routines are
2020 careful to use unsigned types where modulo arithmetic is required.
2021 Failure to do so _will_ break on newer gcc. */
2023 /* Signed saturating arithmetic. */
2025 /* Perform 16-bit signed saturating addition. */
2026 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2031 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2040 /* Perform 8-bit signed saturating addition. */
2041 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2046 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2055 /* Perform 16-bit signed saturating subtraction. */
2056 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2061 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2070 /* Perform 8-bit signed saturating subtraction. */
2071 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2076 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2085 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2086 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2087 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2088 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2091 #include "op_addsub.h"
2093 /* Unsigned saturating arithmetic. */
2094 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2103 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2111 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2120 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2128 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2129 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2130 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2131 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2134 #include "op_addsub.h"
2136 /* Signed modulo arithmetic. */
2137 #define SARITH16(a, b, n, op) do { \
2139 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2140 RESULT(sum, n, 16); \
2142 ge |= 3 << (n * 2); \
2145 #define SARITH8(a, b, n, op) do { \
2147 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2148 RESULT(sum, n, 8); \
2154 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2155 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2156 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2157 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2161 #include "op_addsub.h"
2163 /* Unsigned modulo arithmetic. */
2164 #define ADD16(a, b, n) do { \
2166 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2167 RESULT(sum, n, 16); \
2168 if ((sum >> 16) == 1) \
2169 ge |= 3 << (n * 2); \
2172 #define ADD8(a, b, n) do { \
2174 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2175 RESULT(sum, n, 8); \
2176 if ((sum >> 8) == 1) \
2180 #define SUB16(a, b, n) do { \
2182 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2183 RESULT(sum, n, 16); \
2184 if ((sum >> 16) == 0) \
2185 ge |= 3 << (n * 2); \
2188 #define SUB8(a, b, n) do { \
2190 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2191 RESULT(sum, n, 8); \
2192 if ((sum >> 8) == 0) \
2199 #include "op_addsub.h"
2201 /* Halved signed arithmetic. */
2202 #define ADD16(a, b, n) \
2203 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2204 #define SUB16(a, b, n) \
2205 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2206 #define ADD8(a, b, n) \
2207 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2208 #define SUB8(a, b, n) \
2209 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2212 #include "op_addsub.h"
2214 /* Halved unsigned arithmetic. */
2215 #define ADD16(a, b, n) \
2216 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2217 #define SUB16(a, b, n) \
2218 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2219 #define ADD8(a, b, n) \
2220 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2221 #define SUB8(a, b, n) \
2222 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2225 #include "op_addsub.h"
2227 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2235 /* Unsigned sum of absolute byte differences. */
2236 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2239 sum
= do_usad(a
, b
);
2240 sum
+= do_usad(a
>> 8, b
>> 8);
2241 sum
+= do_usad(a
>> 16, b
>>16);
2242 sum
+= do_usad(a
>> 24, b
>> 24);
2246 /* For ARMv6 SEL instruction. */
2247 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2260 return (a
& mask
) | (b
& ~mask
);
2263 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2265 return (val
>> 32) | (val
!= 0);
2268 /* VFP support. We follow the convention used for VFP instrunctions:
2269 Single precition routines have a "s" suffix, double precision a
2272 /* Convert host exception flags to vfp form. */
2273 static inline int vfp_exceptbits_from_host(int host_bits
)
2275 int target_bits
= 0;
2277 if (host_bits
& float_flag_invalid
)
2279 if (host_bits
& float_flag_divbyzero
)
2281 if (host_bits
& float_flag_overflow
)
2283 if (host_bits
& float_flag_underflow
)
2285 if (host_bits
& float_flag_inexact
)
2286 target_bits
|= 0x10;
2290 uint32_t HELPER(vfp_get_fpscr
)(CPUState
*env
)
2295 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2296 | (env
->vfp
.vec_len
<< 16)
2297 | (env
->vfp
.vec_stride
<< 20);
2298 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2299 fpscr
|= vfp_exceptbits_from_host(i
);
2303 /* Convert vfp exception flags to target form. */
2304 static inline int vfp_exceptbits_to_host(int target_bits
)
2308 if (target_bits
& 1)
2309 host_bits
|= float_flag_invalid
;
2310 if (target_bits
& 2)
2311 host_bits
|= float_flag_divbyzero
;
2312 if (target_bits
& 4)
2313 host_bits
|= float_flag_overflow
;
2314 if (target_bits
& 8)
2315 host_bits
|= float_flag_underflow
;
2316 if (target_bits
& 0x10)
2317 host_bits
|= float_flag_inexact
;
2321 void HELPER(vfp_set_fpscr
)(CPUState
*env
, uint32_t val
)
2326 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2327 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2328 env
->vfp
.vec_len
= (val
>> 16) & 7;
2329 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2332 if (changed
& (3 << 22)) {
2333 i
= (val
>> 22) & 3;
2336 i
= float_round_nearest_even
;
2342 i
= float_round_down
;
2345 i
= float_round_to_zero
;
2348 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2350 if (changed
& (1 << 24))
2351 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2352 if (changed
& (1 << 25))
2353 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2355 i
= vfp_exceptbits_to_host((val
>> 8) & 0x1f);
2356 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2359 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2361 #define VFP_BINOP(name) \
2362 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2364 return float32_ ## name (a, b, &env->vfp.fp_status); \
2366 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2368 return float64_ ## name (a, b, &env->vfp.fp_status); \
2376 float32
VFP_HELPER(neg
, s
)(float32 a
)
2378 return float32_chs(a
);
2381 float64
VFP_HELPER(neg
, d
)(float64 a
)
2383 return float64_chs(a
);
2386 float32
VFP_HELPER(abs
, s
)(float32 a
)
2388 return float32_abs(a
);
2391 float64
VFP_HELPER(abs
, d
)(float64 a
)
2393 return float64_abs(a
);
2396 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUState
*env
)
2398 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2401 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUState
*env
)
2403 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2406 /* XXX: check quiet/signaling case */
2407 #define DO_VFP_cmp(p, type) \
2408 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2411 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2412 case 0: flags = 0x6; break; \
2413 case -1: flags = 0x8; break; \
2414 case 1: flags = 0x2; break; \
2415 default: case 2: flags = 0x3; break; \
2417 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2418 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2420 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2423 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2424 case 0: flags = 0x6; break; \
2425 case -1: flags = 0x8; break; \
2426 case 1: flags = 0x2; break; \
2427 default: case 2: flags = 0x3; break; \
2429 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2430 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2432 DO_VFP_cmp(s
, float32
)
2433 DO_VFP_cmp(d
, float64
)
2436 /* Helper routines to perform bitwise copies between float and int. */
2437 static inline float32
vfp_itos(uint32_t i
)
2448 static inline uint32_t vfp_stoi(float32 s
)
2459 static inline float64
vfp_itod(uint64_t i
)
2470 static inline uint64_t vfp_dtoi(float64 d
)
2481 /* Integer to float conversion. */
2482 float32
VFP_HELPER(uito
, s
)(float32 x
, CPUState
*env
)
2484 return uint32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2487 float64
VFP_HELPER(uito
, d
)(float32 x
, CPUState
*env
)
2489 return uint32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2492 float32
VFP_HELPER(sito
, s
)(float32 x
, CPUState
*env
)
2494 return int32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2497 float64
VFP_HELPER(sito
, d
)(float32 x
, CPUState
*env
)
2499 return int32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2502 /* Float to integer conversion. */
2503 float32
VFP_HELPER(toui
, s
)(float32 x
, CPUState
*env
)
2505 return vfp_itos(float32_to_uint32(x
, &env
->vfp
.fp_status
));
2508 float32
VFP_HELPER(toui
, d
)(float64 x
, CPUState
*env
)
2510 return vfp_itos(float64_to_uint32(x
, &env
->vfp
.fp_status
));
2513 float32
VFP_HELPER(tosi
, s
)(float32 x
, CPUState
*env
)
2515 return vfp_itos(float32_to_int32(x
, &env
->vfp
.fp_status
));
2518 float32
VFP_HELPER(tosi
, d
)(float64 x
, CPUState
*env
)
2520 return vfp_itos(float64_to_int32(x
, &env
->vfp
.fp_status
));
2523 float32
VFP_HELPER(touiz
, s
)(float32 x
, CPUState
*env
)
2525 return vfp_itos(float32_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2528 float32
VFP_HELPER(touiz
, d
)(float64 x
, CPUState
*env
)
2530 return vfp_itos(float64_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2533 float32
VFP_HELPER(tosiz
, s
)(float32 x
, CPUState
*env
)
2535 return vfp_itos(float32_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2538 float32
VFP_HELPER(tosiz
, d
)(float64 x
, CPUState
*env
)
2540 return vfp_itos(float64_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2543 /* floating point conversion */
2544 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUState
*env
)
2546 return float32_to_float64(x
, &env
->vfp
.fp_status
);
2549 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUState
*env
)
2551 return float64_to_float32(x
, &env
->vfp
.fp_status
);
2554 /* VFP3 fixed point conversion. */
2555 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2556 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2559 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2560 &env->vfp.fp_status); \
2561 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
2563 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2566 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2567 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2568 &env->vfp.fp_status)); \
2571 VFP_CONV_FIX(sh
, d
, float64
, int16
, )
2572 VFP_CONV_FIX(sl
, d
, float64
, int32
, )
2573 VFP_CONV_FIX(uh
, d
, float64
, uint16
, u
)
2574 VFP_CONV_FIX(ul
, d
, float64
, uint32
, u
)
2575 VFP_CONV_FIX(sh
, s
, float32
, int16
, )
2576 VFP_CONV_FIX(sl
, s
, float32
, int32
, )
2577 VFP_CONV_FIX(uh
, s
, float32
, uint16
, u
)
2578 VFP_CONV_FIX(ul
, s
, float32
, uint32
, u
)
2581 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUState
*env
)
2583 float_status
*s
= &env
->vfp
.fp_status
;
2584 float32 two
= int32_to_float32(2, s
);
2585 return float32_sub(two
, float32_mul(a
, b
, s
), s
);
2588 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUState
*env
)
2590 float_status
*s
= &env
->vfp
.fp_status
;
2591 float32 three
= int32_to_float32(3, s
);
2592 return float32_sub(three
, float32_mul(a
, b
, s
), s
);
2597 /* TODO: The architecture specifies the value that the estimate functions
2598 should return. We return the exact reciprocal/root instead. */
2599 float32
HELPER(recpe_f32
)(float32 a
, CPUState
*env
)
2601 float_status
*s
= &env
->vfp
.fp_status
;
2602 float32 one
= int32_to_float32(1, s
);
2603 return float32_div(one
, a
, s
);
2606 float32
HELPER(rsqrte_f32
)(float32 a
, CPUState
*env
)
2608 float_status
*s
= &env
->vfp
.fp_status
;
2609 float32 one
= int32_to_float32(1, s
);
2610 return float32_div(one
, float32_sqrt(a
, s
), s
);
2613 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUState
*env
)
2615 float_status
*s
= &env
->vfp
.fp_status
;
2617 tmp
= int32_to_float32(a
, s
);
2618 tmp
= float32_scalbn(tmp
, -32, s
);
2619 tmp
= helper_recpe_f32(tmp
, env
);
2620 tmp
= float32_scalbn(tmp
, 31, s
);
2621 return float32_to_int32(tmp
, s
);
2624 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUState
*env
)
2626 float_status
*s
= &env
->vfp
.fp_status
;
2628 tmp
= int32_to_float32(a
, s
);
2629 tmp
= float32_scalbn(tmp
, -32, s
);
2630 tmp
= helper_rsqrte_f32(tmp
, env
);
2631 tmp
= float32_scalbn(tmp
, 31, s
);
2632 return float32_to_int32(tmp
, s
);
2635 void HELPER(set_teecr
)(CPUState
*env
, uint32_t val
)
2638 if (env
->teecr
!= val
) {