target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26
  27 //#define DEBUG_KVM
  28
  29 #ifdef DEBUG_KVM
  30 #define dprintf(fmt, ...) \
  31     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  32 #else
  33 #define dprintf(fmt, ...) \
  34     do { } while (0)
  35 #endif
  36
  37 int kvm_arch_init_vcpu(CPUState *env)
  38 {
  39     struct {
  40         struct kvm_cpuid2 cpuid;
  41         struct kvm_cpuid_entry2 entries[100];
  42     } __attribute__((packed)) cpuid_data;
  43     uint32_t limit, i, j, cpuid_i;
  44     uint32_t unused;
  45
  46     cpuid_i = 0;
  47
  48     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
  49
  50     for (i = 0; i <= limit; i++) {
  51         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
  52
  53         switch (i) {
  54         case 2: {
  55             /* Keep reading function 2 till all the input is received */
  56             int times;
  57
  58             c->function = i;
  59             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
  60                        KVM_CPUID_FLAG_STATE_READ_NEXT;
  61             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
  62             times = c->eax & 0xff;
  63
  64             for (j = 1; j < times; ++j) {
  65                 c = &cpuid_data.entries[cpuid_i++];
  66                 c->function = i;
  67                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
  68                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
  69             }
  70             break;
  71         }
  72         case 4:
  73         case 0xb:
  74         case 0xd:
  75             for (j = 0; ; j++) {
  76                 c->function = i;
  77                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
  78                 c->index = j;
  79                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
  80
  81                 if (i == 4 && c->eax == 0)
  82                     break;
  83                 if (i == 0xb && !(c->ecx & 0xff00))
  84                     break;
  85                 if (i == 0xd && c->eax == 0)
  86                     break;
  87
  88                 c = &cpuid_data.entries[cpuid_i++];
  89             }
  90             break;
  91         default:
  92             c->function = i;
  93             c->flags = 0;
  94             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
  95             break;
  96         }
  97     }
  98     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
  99
 100     for (i = 0x80000000; i <= limit; i++) {
 101         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 102
 103         c->function = i;
 104         c->flags = 0;
 105         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 106     }
 107
 108     cpuid_data.cpuid.nent = cpuid_i;
 109
 110     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 111 }
 112
 113 static int kvm_has_msr_star(CPUState *env)
 114 {
 115     static int has_msr_star;
 116     int ret;
 117
 118     /* first time */
 119     if (has_msr_star == 0) {
 120         struct kvm_msr_list msr_list, *kvm_msr_list;
 121
 122         has_msr_star = -1;
 123
 124         /* Obtain MSR list from KVM.  These are the MSRs that we must
 125          * save/restore */
 126         msr_list.nmsrs = 0;
 127         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 128         if (ret < 0)
 129             return 0;
 130
 131         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
 132                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 133
 134         kvm_msr_list->nmsrs = msr_list.nmsrs;
 135         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 136         if (ret >= 0) {
 137             int i;
 138
 139             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 140                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 141                     has_msr_star = 1;
 142                     break;
 143                 }
 144             }
 145         }
 146
 147         free(kvm_msr_list);
 148     }
 149
 150     if (has_msr_star == 1)
 151         return 1;
 152     return 0;
 153 }
 154
 155 int kvm_arch_init(KVMState *s, int smp_cpus)
 156 {
 157     int ret;
 158
 159     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 160      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 161      * must be part of guest physical memory, we need to allocate it.  Older
 162      * versions of KVM just assumed that it would be at the end of physical
 163      * memory but that doesn't work with more than 4GB of memory.  We simply
 164      * refuse to work with those older versions of KVM. */
 165     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 166     if (ret <= 0) {
 167         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 168         return ret;
 169     }
 170
 171     /* this address is 3 pages before the bios, and the bios should present
 172      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 173      * this?
 174      */
 175     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 176 }
 177
 178 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 179 {
 180     lhs->selector = rhs->selector;
 181     lhs->base = rhs->base;
 182     lhs->limit = rhs->limit;
 183     lhs->type = 3;
 184     lhs->present = 1;
 185     lhs->dpl = 3;
 186     lhs->db = 0;
 187     lhs->s = 1;
 188     lhs->l = 0;
 189     lhs->g = 0;
 190     lhs->avl = 0;
 191     lhs->unusable = 0;
 192 }
 193
 194 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 195 {
 196     unsigned flags = rhs->flags;
 197     lhs->selector = rhs->selector;
 198     lhs->base = rhs->base;
 199     lhs->limit = rhs->limit;
 200     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 201     lhs->present = (flags & DESC_P_MASK) != 0;
 202     lhs->dpl = rhs->selector & 3;
 203     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 204     lhs->s = (flags & DESC_S_MASK) != 0;
 205     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 206     lhs->g = (flags & DESC_G_MASK) != 0;
 207     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 208     lhs->unusable = 0;
 209 }
 210
 211 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 212 {
 213     lhs->selector = rhs->selector;
 214     lhs->base = rhs->base;
 215     lhs->limit = rhs->limit;
 216     lhs->flags =
 217         (rhs->type << DESC_TYPE_SHIFT)
 218         | (rhs->present * DESC_P_MASK)
 219         | (rhs->dpl << DESC_DPL_SHIFT)
 220         | (rhs->db << DESC_B_SHIFT)
 221         | (rhs->s * DESC_S_MASK)
 222         | (rhs->l << DESC_L_SHIFT)
 223         | (rhs->g * DESC_G_MASK)
 224         | (rhs->avl * DESC_AVL_MASK);
 225 }
 226
 227 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 228 {
 229     if (set)
 230         *kvm_reg = *qemu_reg;
 231     else
 232         *qemu_reg = *kvm_reg;
 233 }
 234
 235 static int kvm_getput_regs(CPUState *env, int set)
 236 {
 237     struct kvm_regs regs;
 238     int ret = 0;
 239
 240     if (!set) {
 241         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 242         if (ret < 0)
 243             return ret;
 244     }
 245
 246     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 247     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 248     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 249     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 250     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 251     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 252     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 253     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 254 #ifdef TARGET_X86_64
 255     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 256     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 257     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 258     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 259     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 260     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 261     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 262     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 263 #endif
 264
 265     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 266     kvm_getput_reg(&regs.rip, &env->eip, set);
 267
 268     if (set)
 269         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 270
 271     return ret;
 272 }
 273
 274 static int kvm_put_fpu(CPUState *env)
 275 {
 276     struct kvm_fpu fpu;
 277     int i;
 278
 279     memset(&fpu, 0, sizeof fpu);
 280     fpu.fsw = env->fpus & ~(7 << 11);
 281     fpu.fsw |= (env->fpstt & 7) << 11;
 282     fpu.fcw = env->fpuc;
 283     for (i = 0; i < 8; ++i)
 284         fpu.ftwx |= (!env->fptags[i]) << i;
 285     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 286     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 287     fpu.mxcsr = env->mxcsr;
 288
 289     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 290 }
 291
 292 static int kvm_put_sregs(CPUState *env)
 293 {
 294     struct kvm_sregs sregs;
 295
 296     memcpy(sregs.interrupt_bitmap,
 297            env->interrupt_bitmap,
 298            sizeof(sregs.interrupt_bitmap));
 299
 300     if ((env->eflags & VM_MASK)) {
 301             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 302             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 303             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 304             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 305             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 306             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 307     } else {
 308             set_seg(&sregs.cs, &env->segs[R_CS]);
 309             set_seg(&sregs.ds, &env->segs[R_DS]);
 310             set_seg(&sregs.es, &env->segs[R_ES]);
 311             set_seg(&sregs.fs, &env->segs[R_FS]);
 312             set_seg(&sregs.gs, &env->segs[R_GS]);
 313             set_seg(&sregs.ss, &env->segs[R_SS]);
 314
 315             if (env->cr[0] & CR0_PE_MASK) {
 316                 /* force ss cpl to cs cpl */
 317                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 318                         (sregs.cs.selector & 3);
 319                 sregs.ss.dpl = sregs.ss.selector & 3;
 320             }
 321     }
 322
 323     set_seg(&sregs.tr, &env->tr);
 324     set_seg(&sregs.ldt, &env->ldt);
 325
 326     sregs.idt.limit = env->idt.limit;
 327     sregs.idt.base = env->idt.base;
 328     sregs.gdt.limit = env->gdt.limit;
 329     sregs.gdt.base = env->gdt.base;
 330
 331     sregs.cr0 = env->cr[0];
 332     sregs.cr2 = env->cr[2];
 333     sregs.cr3 = env->cr[3];
 334     sregs.cr4 = env->cr[4];
 335
 336     sregs.cr8 = cpu_get_apic_tpr(env);
 337     sregs.apic_base = cpu_get_apic_base(env);
 338
 339     sregs.efer = env->efer;
 340
 341     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 342 }
 343
 344 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 345                               uint32_t index, uint64_t value)
 346 {
 347     entry->index = index;
 348     entry->data = value;
 349 }
 350
 351 static int kvm_put_msrs(CPUState *env)
 352 {
 353     struct {
 354         struct kvm_msrs info;
 355         struct kvm_msr_entry entries[100];
 356     } msr_data;
 357     struct kvm_msr_entry *msrs = msr_data.entries;
 358     int n = 0;
 359
 360     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 361     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 362     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 363     if (kvm_has_msr_star(env))
 364         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 365     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 366 #ifdef TARGET_X86_64
 367     /* FIXME if lm capable */
 368     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 369     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 370     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 371     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 372 #endif
 373     msr_data.info.nmsrs = n;
 374
 375     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 376
 377 }
 378
 379
 380 static int kvm_get_fpu(CPUState *env)
 381 {
 382     struct kvm_fpu fpu;
 383     int i, ret;
 384
 385     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 386     if (ret < 0)
 387         return ret;
 388
 389     env->fpstt = (fpu.fsw >> 11) & 7;
 390     env->fpus = fpu.fsw;
 391     env->fpuc = fpu.fcw;
 392     for (i = 0; i < 8; ++i)
 393         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 394     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 395     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 396     env->mxcsr = fpu.mxcsr;
 397
 398     return 0;
 399 }
 400
 401 static int kvm_get_sregs(CPUState *env)
 402 {
 403     struct kvm_sregs sregs;
 404     uint32_t hflags;
 405     int ret;
 406
 407     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 408     if (ret < 0)
 409         return ret;
 410
 411     memcpy(env->interrupt_bitmap,
 412            sregs.interrupt_bitmap,
 413            sizeof(sregs.interrupt_bitmap));
 414
 415     get_seg(&env->segs[R_CS], &sregs.cs);
 416     get_seg(&env->segs[R_DS], &sregs.ds);
 417     get_seg(&env->segs[R_ES], &sregs.es);
 418     get_seg(&env->segs[R_FS], &sregs.fs);
 419     get_seg(&env->segs[R_GS], &sregs.gs);
 420     get_seg(&env->segs[R_SS], &sregs.ss);
 421
 422     get_seg(&env->tr, &sregs.tr);
 423     get_seg(&env->ldt, &sregs.ldt);
 424
 425     env->idt.limit = sregs.idt.limit;
 426     env->idt.base = sregs.idt.base;
 427     env->gdt.limit = sregs.gdt.limit;
 428     env->gdt.base = sregs.gdt.base;
 429
 430     env->cr[0] = sregs.cr0;
 431     env->cr[2] = sregs.cr2;
 432     env->cr[3] = sregs.cr3;
 433     env->cr[4] = sregs.cr4;
 434
 435     cpu_set_apic_base(env, sregs.apic_base);
 436
 437     env->efer = sregs.efer;
 438     //cpu_set_apic_tpr(env, sregs.cr8);
 439
 440 #define HFLAG_COPY_MASK ~( \
 441                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 442                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 443                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 444                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 445
 446
 447
 448     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 449     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 450     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 451             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 452     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 453     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 454             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 455
 456     if (env->efer & MSR_EFER_LMA) {
 457         hflags |= HF_LMA_MASK;
 458     }
 459
 460     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 461         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 462     } else {
 463         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 464                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 465         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 466                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 467         if (!(env->cr[0] & CR0_PE_MASK) ||
 468                    (env->eflags & VM_MASK) ||
 469                    !(hflags & HF_CS32_MASK)) {
 470                 hflags |= HF_ADDSEG_MASK;
 471             } else {
 472                 hflags |= ((env->segs[R_DS].base |
 473                                 env->segs[R_ES].base |
 474                                 env->segs[R_SS].base) != 0) <<
 475                     HF_ADDSEG_SHIFT;
 476             }
 477     }
 478     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 479
 480     return 0;
 481 }
 482
 483 static int kvm_get_msrs(CPUState *env)
 484 {
 485     struct {
 486         struct kvm_msrs info;
 487         struct kvm_msr_entry entries[100];
 488     } msr_data;
 489     struct kvm_msr_entry *msrs = msr_data.entries;
 490     int ret, i, n;
 491
 492     n = 0;
 493     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 494     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 495     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 496     if (kvm_has_msr_star(env))
 497         msrs[n++].index = MSR_STAR;
 498     msrs[n++].index = MSR_IA32_TSC;
 499 #ifdef TARGET_X86_64
 500     /* FIXME lm_capable_kernel */
 501     msrs[n++].index = MSR_CSTAR;
 502     msrs[n++].index = MSR_KERNELGSBASE;
 503     msrs[n++].index = MSR_FMASK;
 504     msrs[n++].index = MSR_LSTAR;
 505 #endif
 506     msr_data.info.nmsrs = n;
 507     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 508     if (ret < 0)
 509         return ret;
 510
 511     for (i = 0; i < ret; i++) {
 512         switch (msrs[i].index) {
 513         case MSR_IA32_SYSENTER_CS:
 514             env->sysenter_cs = msrs[i].data;
 515             break;
 516         case MSR_IA32_SYSENTER_ESP:
 517             env->sysenter_esp = msrs[i].data;
 518             break;
 519         case MSR_IA32_SYSENTER_EIP:
 520             env->sysenter_eip = msrs[i].data;
 521             break;
 522         case MSR_STAR:
 523             env->star = msrs[i].data;
 524             break;
 525 #ifdef TARGET_X86_64
 526         case MSR_CSTAR:
 527             env->cstar = msrs[i].data;
 528             break;
 529         case MSR_KERNELGSBASE:
 530             env->kernelgsbase = msrs[i].data;
 531             break;
 532         case MSR_FMASK:
 533             env->fmask = msrs[i].data;
 534             break;
 535         case MSR_LSTAR:
 536             env->lstar = msrs[i].data;
 537             break;
 538 #endif
 539         case MSR_IA32_TSC:
 540             env->tsc = msrs[i].data;
 541             break;
 542         }
 543     }
 544
 545     return 0;
 546 }
 547
 548 int kvm_arch_put_registers(CPUState *env)
 549 {
 550     int ret;
 551
 552     ret = kvm_getput_regs(env, 1);
 553     if (ret < 0)
 554         return ret;
 555
 556     ret = kvm_put_fpu(env);
 557     if (ret < 0)
 558         return ret;
 559
 560     ret = kvm_put_sregs(env);
 561     if (ret < 0)
 562         return ret;
 563
 564     ret = kvm_put_msrs(env);
 565     if (ret < 0)
 566         return ret;
 567
 568     return 0;
 569 }
 570
 571 int kvm_arch_get_registers(CPUState *env)
 572 {
 573     int ret;
 574
 575     ret = kvm_getput_regs(env, 0);
 576     if (ret < 0)
 577         return ret;
 578
 579     ret = kvm_get_fpu(env);
 580     if (ret < 0)
 581         return ret;
 582
 583     ret = kvm_get_sregs(env);
 584     if (ret < 0)
 585         return ret;
 586
 587     ret = kvm_get_msrs(env);
 588     if (ret < 0)
 589         return ret;
 590
 591     return 0;
 592 }
 593
 594 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 595 {
 596     /* Try to inject an interrupt if the guest can accept it */
 597     if (run->ready_for_interrupt_injection &&
 598         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 599         (env->eflags & IF_MASK)) {
 600         int irq;
 601
 602         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 603         irq = cpu_get_pic_interrupt(env);
 604         if (irq >= 0) {
 605             struct kvm_interrupt intr;
 606             intr.irq = irq;
 607             /* FIXME: errors */
 608             dprintf("injected interrupt %d\n", irq);
 609             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 610         }
 611     }
 612
 613     /* If we have an interrupt but the guest is not ready to receive an
 614      * interrupt, request an interrupt window exit.  This will
 615      * cause a return to userspace as soon as the guest is ready to
 616      * receive interrupts. */
 617     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 618         run->request_interrupt_window = 1;
 619     else
 620         run->request_interrupt_window = 0;
 621
 622     dprintf("setting tpr\n");
 623     run->cr8 = cpu_get_apic_tpr(env);
 624
 625     return 0;
 626 }
 627
 628 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 629 {
 630     if (run->if_flag)
 631         env->eflags |= IF_MASK;
 632     else
 633         env->eflags &= ~IF_MASK;
 634
 635     cpu_set_apic_tpr(env, run->cr8);
 636     cpu_set_apic_base(env, run->apic_base);
 637
 638     return 0;
 639 }
 640
 641 static int kvm_handle_halt(CPUState *env)
 642 {
 643     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 644           (env->eflags & IF_MASK)) &&
 645         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 646         env->halted = 1;
 647         env->exception_index = EXCP_HLT;
 648         return 0;
 649     }
 650
 651     return 1;
 652 }
 653
 654 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 655 {
 656     int ret = 0;
 657
 658     switch (run->exit_reason) {
 659     case KVM_EXIT_HLT:
 660         dprintf("handle_hlt\n");
 661         ret = kvm_handle_halt(env);
 662         break;
 663     }
 664
 665     return ret;
 666 }
 667
 668 #ifdef KVM_CAP_SET_GUEST_DEBUG
 669 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 670 {
 671     const static uint8_t int3 = 0xcc;
 672
 673     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 674         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
 675         return -EINVAL;
 676     return 0;
 677 }
 678
 679 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 680 {
 681     uint8_t int3;
 682
 683     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 684         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 685         return -EINVAL;
 686     return 0;
 687 }
 688
 689 static struct {
 690     target_ulong addr;
 691     int len;
 692     int type;
 693 } hw_breakpoint[4];
 694
 695 static int nb_hw_breakpoint;
 696
 697 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 698 {
 699     int n;
 700
 701     for (n = 0; n < nb_hw_breakpoint; n++)
 702         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 703             (hw_breakpoint[n].len == len || len == -1))
 704             return n;
 705     return -1;
 706 }
 707
 708 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 709                                   target_ulong len, int type)
 710 {
 711     switch (type) {
 712     case GDB_BREAKPOINT_HW:
 713         len = 1;
 714         break;
 715     case GDB_WATCHPOINT_WRITE:
 716     case GDB_WATCHPOINT_ACCESS:
 717         switch (len) {
 718         case 1:
 719             break;
 720         case 2:
 721         case 4:
 722         case 8:
 723             if (addr & (len - 1))
 724                 return -EINVAL;
 725             break;
 726         default:
 727             return -EINVAL;
 728         }
 729         break;
 730     default:
 731         return -ENOSYS;
 732     }
 733
 734     if (nb_hw_breakpoint == 4)
 735         return -ENOBUFS;
 736
 737     if (find_hw_breakpoint(addr, len, type) >= 0)
 738         return -EEXIST;
 739
 740     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 741     hw_breakpoint[nb_hw_breakpoint].len = len;
 742     hw_breakpoint[nb_hw_breakpoint].type = type;
 743     nb_hw_breakpoint++;
 744
 745     return 0;
 746 }
 747
 748 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 749                                   target_ulong len, int type)
 750 {
 751     int n;
 752
 753     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
 754     if (n < 0)
 755         return -ENOENT;
 756
 757     nb_hw_breakpoint--;
 758     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
 759
 760     return 0;
 761 }
 762
 763 void kvm_arch_remove_all_hw_breakpoints(void)
 764 {
 765     nb_hw_breakpoint = 0;
 766 }
 767
 768 static CPUWatchpoint hw_watchpoint;
 769
 770 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
 771 {
 772     int handle = 0;
 773     int n;
 774
 775     if (arch_info->exception == 1) {
 776         if (arch_info->dr6 & (1 << 14)) {
 777             if (cpu_single_env->singlestep_enabled)
 778                 handle = 1;
 779         } else {
 780             for (n = 0; n < 4; n++)
 781                 if (arch_info->dr6 & (1 << n))
 782                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
 783                     case 0x0:
 784                         handle = 1;
 785                         break;
 786                     case 0x1:
 787                         handle = 1;
 788                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 789                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 790                         hw_watchpoint.flags = BP_MEM_WRITE;
 791                         break;
 792                     case 0x3:
 793                         handle = 1;
 794                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 795                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 796                         hw_watchpoint.flags = BP_MEM_ACCESS;
 797                         break;
 798                     }
 799         }
 800     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
 801         handle = 1;
 802
 803     if (!handle)
 804         kvm_update_guest_debug(cpu_single_env,
 805                         (arch_info->exception == 1) ?
 806                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
 807
 808     return handle;
 809 }
 810
 811 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
 812 {
 813     const uint8_t type_code[] = {
 814         [GDB_BREAKPOINT_HW] = 0x0,
 815         [GDB_WATCHPOINT_WRITE] = 0x1,
 816         [GDB_WATCHPOINT_ACCESS] = 0x3
 817     };
 818     const uint8_t len_code[] = {
 819         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
 820     };
 821     int n;
 822
 823     if (kvm_sw_breakpoints_active(env))
 824         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
 825
 826     if (nb_hw_breakpoint > 0) {
 827         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
 828         dbg->arch.debugreg[7] = 0x0600;
 829         for (n = 0; n < nb_hw_breakpoint; n++) {
 830             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
 831             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
 832                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
 833                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
 834         }
 835     }
 836 }
 837 #endif /* KVM_CAP_SET_GUEST_DEBUG */