hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34
  35 #define KERNEL_LOAD_ADDR     0x00404000
  36 #define CMDLINE_ADDR         0x003ff000
  37 #define INITRD_LOAD_ADDR     0x00300000
  38 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  39 #define PROM_ADDR            0x1fff0000000ULL
  40 #define PROM_VADDR           0x000ffd00000ULL
  41 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  42 #define APB_MEM_BASE         0x1ff00000000ULL
  43 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  44 #define PROM_FILENAME        "openbios-sparc64"
  45 #define NVRAM_SIZE           0x2000
  46 #define MAX_IDE_BUS          2
  47
  48 struct hwdef {
  49     const char * const default_cpu_model;
  50 };
  51
  52 int DMA_get_channel_mode (int nchan)
  53 {
  54     return 0;
  55 }
  56 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  57 {
  58     return 0;
  59 }
  60 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  61 {
  62     return 0;
  63 }
  64 void DMA_hold_DREQ (int nchan) {}
  65 void DMA_release_DREQ (int nchan) {}
  66 void DMA_schedule(int nchan) {}
  67 void DMA_run (void) {}
  68 void DMA_init (int high_page_enable) {}
  69 void DMA_register_channel (int nchan,
  70                            DMA_transfer_handler transfer_handler,
  71                            void *opaque)
  72 {
  73 }
  74
  75 static int nvram_boot_set(void *opaque, const char *boot_device)
  76 {
  77     unsigned int i;
  78     uint8_t image[sizeof(ohwcfg_v3_t)];
  79     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
  80     m48t59_t *nvram = (m48t59_t *)opaque;
  81
  82     for (i = 0; i < sizeof(image); i++)
  83         image[i] = m48t59_read(nvram, i) & 0xff;
  84
  85     strcpy((char *)header->boot_devices, boot_device);
  86     header->nboot_devices = strlen(boot_device) & 0xff;
  87     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
  88
  89     for (i = 0; i < sizeof(image); i++)
  90         m48t59_write(nvram, i, image[i]);
  91
  92     return 0;
  93 }
  94
  95 extern int nographic;
  96
  97 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
  98                                    const char *arch,
  99                                    ram_addr_t RAM_size,
 100                                    const char *boot_devices,
 101                                    uint32_t kernel_image, uint32_t kernel_size,
 102                                    const char *cmdline,
 103                                    uint32_t initrd_image, uint32_t initrd_size,
 104                                    uint32_t NVRAM_image,
 105                                    int width, int height, int depth,
 106                                    const uint8_t *macaddr)
 107 {
 108     unsigned int i;
 109     uint32_t start, end;
 110     uint8_t image[0x1ff0];
 111     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
 112     struct sparc_arch_cfg *sparc_header;
 113     struct OpenBIOS_nvpart_v1 *part_header;
 114
 115     memset(image, '\0', sizeof(image));
 116
 117     // Try to match PPC NVRAM
 118     strcpy((char *)header->struct_ident, "QEMU_BIOS");
 119     header->struct_version = cpu_to_be32(3); /* structure v3 */
 120
 121     header->nvram_size = cpu_to_be16(NVRAM_size);
 122     header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
 123     header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
 124     strcpy((char *)header->arch, arch);
 125     header->nb_cpus = smp_cpus & 0xff;
 126     header->RAM0_base = 0;
 127     header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
 128     strcpy((char *)header->boot_devices, boot_devices);
 129     header->nboot_devices = strlen(boot_devices) & 0xff;
 130     header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
 131     header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
 132     if (cmdline) {
 133         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
 134         header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
 135         header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
 136     }
 137     header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
 138     header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
 139     header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
 140
 141     header->width = cpu_to_be16(width);
 142     header->height = cpu_to_be16(height);
 143     header->depth = cpu_to_be16(depth);
 144     if (nographic)
 145         header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
 146
 147     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
 148
 149     // Architecture specific header
 150     start = sizeof(ohwcfg_v3_t);
 151     sparc_header = (struct sparc_arch_cfg *)&image[start];
 152     sparc_header->valid = 0;
 153     start += sizeof(struct sparc_arch_cfg);
 154
 155     // OpenBIOS nvram variables
 156     // Variable partition
 157     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 158     part_header->signature = OPENBIOS_PART_SYSTEM;
 159     strcpy(part_header->name, "system");
 160
 161     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 162     for (i = 0; i < nb_prom_envs; i++)
 163         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 164
 165     // End marker
 166     image[end++] = '\0';
 167
 168     end = start + ((end - start + 15) & ~15);
 169     OpenBIOS_finish_partition(part_header, end - start);
 170
 171     // free partition
 172     start = end;
 173     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 174     part_header->signature = OPENBIOS_PART_FREE;
 175     strcpy(part_header->name, "free");
 176
 177     end = 0x1fd0;
 178     OpenBIOS_finish_partition(part_header, end - start);
 179
 180     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 181
 182     for (i = 0; i < sizeof(image); i++)
 183         m48t59_write(nvram, i, image[i]);
 184
 185     qemu_register_boot_set(nvram_boot_set, nvram);
 186
 187     return 0;
 188 }
 189
 190 void pic_info(void)
 191 {
 192 }
 193
 194 void irq_info(void)
 195 {
 196 }
 197
 198 void qemu_system_powerdown(void)
 199 {
 200 }
 201
 202 static void main_cpu_reset(void *opaque)
 203 {
 204     CPUState *env = opaque;
 205
 206     cpu_reset(env);
 207     ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
 208     ptimer_run(env->tick, 0);
 209     ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
 210     ptimer_run(env->stick, 0);
 211     ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
 212     ptimer_run(env->hstick, 0);
 213 }
 214
 215 static void tick_irq(void *opaque)
 216 {
 217     CPUState *env = opaque;
 218
 219     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 220 }
 221
 222 static void stick_irq(void *opaque)
 223 {
 224     CPUState *env = opaque;
 225
 226     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 227 }
 228
 229 static void hstick_irq(void *opaque)
 230 {
 231     CPUState *env = opaque;
 232
 233     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 234 }
 235
 236 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
 237 {
 238 }
 239
 240 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 241 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 242 static const int ide_irq[2] = { 14, 15 };
 243
 244 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 245 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 246
 247 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 248 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 249
 250 static fdctrl_t *floppy_controller;
 251
 252 static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
 253                         const char *boot_devices, DisplayState *ds,
 254                         const char *kernel_filename, const char *kernel_cmdline,
 255                         const char *initrd_filename, const char *cpu_model,
 256                         const struct hwdef *hwdef)
 257 {
 258     CPUState *env;
 259     char buf[1024];
 260     m48t59_t *nvram;
 261     int ret, linux_boot;
 262     unsigned int i;
 263     long prom_offset, initrd_size, kernel_size;
 264     PCIBus *pci_bus;
 265     QEMUBH *bh;
 266     qemu_irq *irq;
 267     int drive_index;
 268     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 269     BlockDriverState *fd[MAX_FD];
 270
 271     linux_boot = (kernel_filename != NULL);
 272
 273     /* init CPUs */
 274     if (!cpu_model)
 275         cpu_model = hwdef->default_cpu_model;
 276
 277     env = cpu_init(cpu_model);
 278     if (!env) {
 279         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 280         exit(1);
 281     }
 282     bh = qemu_bh_new(tick_irq, env);
 283     env->tick = ptimer_init(bh);
 284     ptimer_set_period(env->tick, 1ULL);
 285
 286     bh = qemu_bh_new(stick_irq, env);
 287     env->stick = ptimer_init(bh);
 288     ptimer_set_period(env->stick, 1ULL);
 289
 290     bh = qemu_bh_new(hstick_irq, env);
 291     env->hstick = ptimer_init(bh);
 292     ptimer_set_period(env->hstick, 1ULL);
 293     qemu_register_reset(main_cpu_reset, env);
 294     main_cpu_reset(env);
 295
 296     /* allocate RAM */
 297     cpu_register_physical_memory(0, RAM_size, 0);
 298
 299     prom_offset = RAM_size + vga_ram_size;
 300     cpu_register_physical_memory(PROM_ADDR,
 301                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
 302                                  TARGET_PAGE_MASK,
 303                                  prom_offset | IO_MEM_ROM);
 304
 305     if (bios_name == NULL)
 306         bios_name = PROM_FILENAME;
 307     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 308     ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
 309     if (ret < 0) {
 310         fprintf(stderr, "qemu: could not load prom '%s'\n",
 311                 buf);
 312         exit(1);
 313     }
 314
 315     kernel_size = 0;
 316     initrd_size = 0;
 317     if (linux_boot) {
 318         /* XXX: put correct offset */
 319         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 320         if (kernel_size < 0)
 321             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 322                                     ram_size - KERNEL_LOAD_ADDR);
 323         if (kernel_size < 0)
 324             kernel_size = load_image_targphys(kernel_filename,
 325                                               KERNEL_LOAD_ADDR,
 326                                               ram_size - KERNEL_LOAD_ADDR);
 327         if (kernel_size < 0) {
 328             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 329                     kernel_filename);
 330             exit(1);
 331         }
 332
 333         /* load initrd */
 334         if (initrd_filename) {
 335             initrd_size = load_image_targphys(initrd_filename,
 336                                               INITRD_LOAD_ADDR,
 337                                               ram_size - INITRD_LOAD_ADDR);
 338             if (initrd_size < 0) {
 339                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 340                         initrd_filename);
 341                 exit(1);
 342             }
 343         }
 344         if (initrd_size > 0) {
 345             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 346                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 347                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 348                     stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
 349                     break;
 350                 }
 351             }
 352         }
 353     }
 354     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
 355     isa_mem_base = VGA_BASE;
 356     pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
 357                         vga_ram_size);
 358
 359     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 360         if (serial_hds[i]) {
 361             serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
 362                         serial_hds[i]);
 363         }
 364     }
 365
 366     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 367         if (parallel_hds[i]) {
 368             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
 369                           parallel_hds[i]);
 370         }
 371     }
 372
 373     for(i = 0; i < nb_nics; i++) {
 374         if (!nd_table[i].model)
 375             nd_table[i].model = "ne2k_pci";
 376         pci_nic_init(pci_bus, &nd_table[i], -1);
 377     }
 378
 379     irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
 380     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 381         fprintf(stderr, "qemu: too many IDE bus\n");
 382         exit(1);
 383     }
 384     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 385         drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
 386                                       i % MAX_IDE_DEVS);
 387        if (drive_index != -1)
 388            hd[i] = drives_table[drive_index].bdrv;
 389        else
 390            hd[i] = NULL;
 391     }
 392
 393     // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
 394     pci_piix3_ide_init(pci_bus, hd, -1, irq);
 395     /* FIXME: wire up interrupts.  */
 396     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 397     for(i = 0; i < MAX_FD; i++) {
 398         drive_index = drive_get_index(IF_FLOPPY, 0, i);
 399        if (drive_index != -1)
 400            fd[i] = drives_table[drive_index].bdrv;
 401        else
 402            fd[i] = NULL;
 403     }
 404     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
 405     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 406     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 407                            KERNEL_LOAD_ADDR, kernel_size,
 408                            kernel_cmdline,
 409                            INITRD_LOAD_ADDR, initrd_size,
 410                            /* XXX: need an option to load a NVRAM image */
 411                            0,
 412                            graphic_width, graphic_height, graphic_depth,
 413                            (uint8_t *)&nd_table[0].macaddr);
 414
 415 }
 416
 417 static const struct hwdef hwdefs[] = {
 418     /* Sun4u generic PC-like machine */
 419     {
 420         .default_cpu_model = "TI UltraSparc II",
 421     },
 422     /* Sun4v generic PC-like machine */
 423     {
 424         .default_cpu_model = "Sun UltraSparc T1",
 425     },
 426 };
 427
 428 /* Sun4u hardware initialisation */
 429 static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
 430                        const char *boot_devices, DisplayState *ds,
 431                        const char *kernel_filename, const char *kernel_cmdline,
 432                        const char *initrd_filename, const char *cpu_model)
 433 {
 434     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 435                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 436 }
 437
 438 /* Sun4v hardware initialisation */
 439 static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
 440                        const char *boot_devices, DisplayState *ds,
 441                        const char *kernel_filename, const char *kernel_cmdline,
 442                        const char *initrd_filename, const char *cpu_model)
 443 {
 444     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 445                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 446 }
 447
 448 QEMUMachine sun4u_machine = {
 449     "sun4u",
 450     "Sun4u platform",
 451     sun4u_init,
 452     PROM_SIZE_MAX + VGA_RAM_SIZE,
 453 };
 454
 455 QEMUMachine sun4v_machine = {
 456     "sun4v",
 457     "Sun4v platform",
 458     sun4v_init,
 459     PROM_SIZE_MAX + VGA_RAM_SIZE,
 460 };