hw/sbi.c

   1 /*
   2  * QEMU Sparc SBI interrupt controller emulation
   3  *
   4  * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "console.h"
  27
  28 //#define DEBUG_IRQ
  29
  30 #ifdef DEBUG_IRQ
  31 #define DPRINTF(fmt, args...) \
  32 do { printf("IRQ: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 #define MAX_CPUS 16
  38
  39 #define SBI_NREGS 16
  40
  41 typedef struct SBIState {
  42     uint32_t regs[SBI_NREGS];
  43     uint32_t intreg_pending[MAX_CPUS];
  44     qemu_irq *cpu_irqs[MAX_CPUS];
  45     uint32_t pil_out[MAX_CPUS];
  46 } SBIState;
  47
  48 #define SBI_SIZE (SBI_NREGS * 4)
  49 #define SBI_MASK (SBI_SIZE - 1)
  50
  51 static void sbi_check_interrupts(void *opaque)
  52 {
  53 }
  54
  55 static void sbi_set_irq(void *opaque, int irq, int level)
  56 {
  57 }
  58
  59 static void sbi_set_timer_irq_cpu(void *opaque, int cpu, int level)
  60 {
  61 }
  62
  63 static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
  64 {
  65     SBIState *s = opaque;
  66     uint32_t saddr, ret;
  67
  68     saddr = (addr & SBI_MASK) >> 2;
  69     switch (saddr) {
  70     default:
  71         ret = s->regs[saddr];
  72         break;
  73     }
  74     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
  75
  76     return ret;
  77 }
  78
  79 static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  80 {
  81     SBIState *s = opaque;
  82     uint32_t saddr;
  83
  84     saddr = (addr & SBI_MASK) >> 2;
  85     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
  86     switch (saddr) {
  87     default:
  88         s->regs[saddr] = val;
  89         break;
  90     }
  91 }
  92
  93 static CPUReadMemoryFunc *sbi_mem_read[3] = {
  94     NULL,
  95     NULL,
  96     sbi_mem_readl,
  97 };
  98
  99 static CPUWriteMemoryFunc *sbi_mem_write[3] = {
 100     NULL,
 101     NULL,
 102     sbi_mem_writel,
 103 };
 104
 105 static void sbi_save(QEMUFile *f, void *opaque)
 106 {
 107     SBIState *s = opaque;
 108     unsigned int i;
 109
 110     for (i = 0; i < MAX_CPUS; i++) {
 111         qemu_put_be32s(f, &s->intreg_pending[i]);
 112     }
 113 }
 114
 115 static int sbi_load(QEMUFile *f, void *opaque, int version_id)
 116 {
 117     SBIState *s = opaque;
 118     unsigned int i;
 119
 120     if (version_id != 1)
 121         return -EINVAL;
 122
 123     for (i = 0; i < MAX_CPUS; i++) {
 124         qemu_get_be32s(f, &s->intreg_pending[i]);
 125     }
 126     sbi_check_interrupts(s);
 127
 128     return 0;
 129 }
 130
 131 static void sbi_reset(void *opaque)
 132 {
 133     SBIState *s = opaque;
 134     unsigned int i;
 135
 136     for (i = 0; i < MAX_CPUS; i++) {
 137         s->intreg_pending[i] = 0;
 138     }
 139     sbi_check_interrupts(s);
 140 }
 141
 142 void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
 143                qemu_irq **parent_irq)
 144 {
 145     unsigned int i;
 146     int sbi_io_memory;
 147     SBIState *s;
 148
 149     s = qemu_mallocz(sizeof(SBIState));
 150     if (!s)
 151         return NULL;
 152
 153     for (i = 0; i < MAX_CPUS; i++) {
 154         s->cpu_irqs[i] = parent_irq[i];
 155     }
 156
 157     sbi_io_memory = cpu_register_io_memory(0, sbi_mem_read, sbi_mem_write, s);
 158     cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);
 159
 160     register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);
 161     qemu_register_reset(sbi_reset, s);
 162     *irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
 163     *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);
 164     sbi_reset(s);
 165
 166     return s;
 167 }