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On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64
[qemu/mini2440.git] / hw / omap1.c
blob58545007643f038a98e218f9123e85ad4417ea86
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21 #include "hw.h"
22 #include "arm-misc.h"
23 #include "omap.h"
24 #include "sysemu.h"
25 #include "qemu-timer.h"
26 #include "qemu-char.h"
27 #include "soc_dma.h"
28 /* We use pc-style serial ports. */
29 #include "pc.h"
30
31 /* Should signal the TCMI/GPMC */
32 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
33 {
34 uint8_t ret;
35
36 OMAP_8B_REG(addr);
37 cpu_physical_memory_read(addr, (void *) &ret, 1);
38 return ret;
39 }
40
41 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
42 uint32_t value)
43 {
44 uint8_t val8 = value;
45
46 OMAP_8B_REG(addr);
47 cpu_physical_memory_write(addr, (void *) &val8, 1);
48 }
49
50 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
51 {
52 uint16_t ret;
53
54 OMAP_16B_REG(addr);
55 cpu_physical_memory_read(addr, (void *) &ret, 2);
56 return ret;
57 }
58
59 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
60 uint32_t value)
61 {
62 uint16_t val16 = value;
63
64 OMAP_16B_REG(addr);
65 cpu_physical_memory_write(addr, (void *) &val16, 2);
66 }
67
68 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
69 {
70 uint32_t ret;
71
72 OMAP_32B_REG(addr);
73 cpu_physical_memory_read(addr, (void *) &ret, 4);
74 return ret;
75 }
76
77 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
78 uint32_t value)
79 {
80 OMAP_32B_REG(addr);
81 cpu_physical_memory_write(addr, (void *) &value, 4);
82 }
83
84 /* Interrupt Handlers */
85 struct omap_intr_handler_bank_s {
86 uint32_t irqs;
87 uint32_t inputs;
88 uint32_t mask;
89 uint32_t fiq;
90 uint32_t sens_edge;
91 uint32_t swi;
92 unsigned char priority[32];
93 };
94
95 struct omap_intr_handler_s {
96 qemu_irq *pins;
97 qemu_irq parent_intr[2];
98 target_phys_addr_t base;
99 unsigned char nbanks;
100 int level_only;
101
102 /* state */
103 uint32_t new_agr[2];
104 int sir_intr[2];
105 int autoidle;
106 uint32_t mask;
107 struct omap_intr_handler_bank_s bank[];
108 };
109
110 static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
111 {
112 int i, j, sir_intr, p_intr, p, f;
113 uint32_t level;
114 sir_intr = 0;
115 p_intr = 255;
116
117 /* Find the interrupt line with the highest dynamic priority.
118 * Note: 0 denotes the hightest priority.
119 * If all interrupts have the same priority, the default order is IRQ_N,
120 * IRQ_N-1,...,IRQ_0. */
121 for (j = 0; j < s->nbanks; ++j) {
122 level = s->bank[j].irqs & ~s->bank[j].mask &
123 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
124 for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
125 level >>= f) {
126 p = s->bank[j].priority[i];
127 if (p <= p_intr) {
128 p_intr = p;
129 sir_intr = 32 * j + i;
130 }
131 f = ffs(level >> 1);
132 }
133 }
134 s->sir_intr[is_fiq] = sir_intr;
135 }
136
137 static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
138 {
139 int i;
140 uint32_t has_intr = 0;
141
142 for (i = 0; i < s->nbanks; ++i)
143 has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
144 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
145
146 if (s->new_agr[is_fiq] & has_intr & s->mask) {
147 s->new_agr[is_fiq] = 0;
148 omap_inth_sir_update(s, is_fiq);
149 qemu_set_irq(s->parent_intr[is_fiq], 1);
150 }
151 }
152
153 #define INT_FALLING_EDGE 0
154 #define INT_LOW_LEVEL 1
155
156 static void omap_set_intr(void *opaque, int irq, int req)
157 {
158 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
159 uint32_t rise;
160
161 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
162 int n = irq & 31;
163
164 if (req) {
165 rise = ~bank->irqs & (1 << n);
166 if (~bank->sens_edge & (1 << n))
167 rise &= ~bank->inputs;
168
169 bank->inputs |= (1 << n);
170 if (rise) {
171 bank->irqs |= rise;
172 omap_inth_update(ih, 0);
173 omap_inth_update(ih, 1);
174 }
175 } else {
176 rise = bank->sens_edge & bank->irqs & (1 << n);
177 bank->irqs &= ~rise;
178 bank->inputs &= ~(1 << n);
179 }
180 }
181
182 /* Simplified version with no edge detection */
183 static void omap_set_intr_noedge(void *opaque, int irq, int req)
184 {
185 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
186 uint32_t rise;
187
188 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
189 int n = irq & 31;
190
191 if (req) {
192 rise = ~bank->inputs & (1 << n);
193 if (rise) {
194 bank->irqs |= bank->inputs |= rise;
195 omap_inth_update(ih, 0);
196 omap_inth_update(ih, 1);
197 }
198 } else
199 bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
200 }
201
202 static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
203 {
204 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
205 int i, offset = addr - s->base;
206 int bank_no = offset >> 8;
207 int line_no;
208 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
209 offset &= 0xff;
210
211 switch (offset) {
212 case 0x00: /* ITR */
213 return bank->irqs;
214
215 case 0x04: /* MIR */
216 return bank->mask;
217
218 case 0x10: /* SIR_IRQ_CODE */
219 case 0x14: /* SIR_FIQ_CODE */
220 if (bank_no != 0)
221 break;
222 line_no = s->sir_intr[(offset - 0x10) >> 2];
223 bank = &s->bank[line_no >> 5];
224 i = line_no & 31;
225 if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
226 bank->irqs &= ~(1 << i);
227 return line_no;
228
229 case 0x18: /* CONTROL_REG */
230 if (bank_no != 0)
231 break;
232 return 0;
233
234 case 0x1c: /* ILR0 */
235 case 0x20: /* ILR1 */
236 case 0x24: /* ILR2 */
237 case 0x28: /* ILR3 */
238 case 0x2c: /* ILR4 */
239 case 0x30: /* ILR5 */
240 case 0x34: /* ILR6 */
241 case 0x38: /* ILR7 */
242 case 0x3c: /* ILR8 */
243 case 0x40: /* ILR9 */
244 case 0x44: /* ILR10 */
245 case 0x48: /* ILR11 */
246 case 0x4c: /* ILR12 */
247 case 0x50: /* ILR13 */
248 case 0x54: /* ILR14 */
249 case 0x58: /* ILR15 */
250 case 0x5c: /* ILR16 */
251 case 0x60: /* ILR17 */
252 case 0x64: /* ILR18 */
253 case 0x68: /* ILR19 */
254 case 0x6c: /* ILR20 */
255 case 0x70: /* ILR21 */
256 case 0x74: /* ILR22 */
257 case 0x78: /* ILR23 */
258 case 0x7c: /* ILR24 */
259 case 0x80: /* ILR25 */
260 case 0x84: /* ILR26 */
261 case 0x88: /* ILR27 */
262 case 0x8c: /* ILR28 */
263 case 0x90: /* ILR29 */
264 case 0x94: /* ILR30 */
265 case 0x98: /* ILR31 */
266 i = (offset - 0x1c) >> 2;
267 return (bank->priority[i] << 2) |
268 (((bank->sens_edge >> i) & 1) << 1) |
269 ((bank->fiq >> i) & 1);
270
271 case 0x9c: /* ISR */
272 return 0x00000000;
273
274 }
275 OMAP_BAD_REG(addr);
276 return 0;
277 }
278
279 static void omap_inth_write(void *opaque, target_phys_addr_t addr,
280 uint32_t value)
281 {
282 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
283 int i, offset = addr - s->base;
284 int bank_no = offset >> 8;
285 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
286 offset &= 0xff;
287
288 switch (offset) {
289 case 0x00: /* ITR */
290 /* Important: ignore the clearing if the IRQ is level-triggered and
291 the input bit is 1 */
292 bank->irqs &= value | (bank->inputs & bank->sens_edge);
293 return;
294
295 case 0x04: /* MIR */
296 bank->mask = value;
297 omap_inth_update(s, 0);
298 omap_inth_update(s, 1);
299 return;
300
301 case 0x10: /* SIR_IRQ_CODE */
302 case 0x14: /* SIR_FIQ_CODE */
303 OMAP_RO_REG(addr);
304 break;
305
306 case 0x18: /* CONTROL_REG */
307 if (bank_no != 0)
308 break;
309 if (value & 2) {
310 qemu_set_irq(s->parent_intr[1], 0);
311 s->new_agr[1] = ~0;
312 omap_inth_update(s, 1);
313 }
314 if (value & 1) {
315 qemu_set_irq(s->parent_intr[0], 0);
316 s->new_agr[0] = ~0;
317 omap_inth_update(s, 0);
318 }
319 return;
320
321 case 0x1c: /* ILR0 */
322 case 0x20: /* ILR1 */
323 case 0x24: /* ILR2 */
324 case 0x28: /* ILR3 */
325 case 0x2c: /* ILR4 */
326 case 0x30: /* ILR5 */
327 case 0x34: /* ILR6 */
328 case 0x38: /* ILR7 */
329 case 0x3c: /* ILR8 */
330 case 0x40: /* ILR9 */
331 case 0x44: /* ILR10 */
332 case 0x48: /* ILR11 */
333 case 0x4c: /* ILR12 */
334 case 0x50: /* ILR13 */
335 case 0x54: /* ILR14 */
336 case 0x58: /* ILR15 */
337 case 0x5c: /* ILR16 */
338 case 0x60: /* ILR17 */
339 case 0x64: /* ILR18 */
340 case 0x68: /* ILR19 */
341 case 0x6c: /* ILR20 */
342 case 0x70: /* ILR21 */
343 case 0x74: /* ILR22 */
344 case 0x78: /* ILR23 */
345 case 0x7c: /* ILR24 */
346 case 0x80: /* ILR25 */
347 case 0x84: /* ILR26 */
348 case 0x88: /* ILR27 */
349 case 0x8c: /* ILR28 */
350 case 0x90: /* ILR29 */
351 case 0x94: /* ILR30 */
352 case 0x98: /* ILR31 */
353 i = (offset - 0x1c) >> 2;
354 bank->priority[i] = (value >> 2) & 0x1f;
355 bank->sens_edge &= ~(1 << i);
356 bank->sens_edge |= ((value >> 1) & 1) << i;
357 bank->fiq &= ~(1 << i);
358 bank->fiq |= (value & 1) << i;
359 return;
360
361 case 0x9c: /* ISR */
362 for (i = 0; i < 32; i ++)
363 if (value & (1 << i)) {
364 omap_set_intr(s, 32 * bank_no + i, 1);
365 return;
366 }
367 return;
368 }
369 OMAP_BAD_REG(addr);
370 }
371
372 static CPUReadMemoryFunc *omap_inth_readfn[] = {
373 omap_badwidth_read32,
374 omap_badwidth_read32,
375 omap_inth_read,
376 };
377
378 static CPUWriteMemoryFunc *omap_inth_writefn[] = {
379 omap_inth_write,
380 omap_inth_write,
381 omap_inth_write,
382 };
383
384 void omap_inth_reset(struct omap_intr_handler_s *s)
385 {
386 int i;
387
388 for (i = 0; i < s->nbanks; ++i){
389 s->bank[i].irqs = 0x00000000;
390 s->bank[i].mask = 0xffffffff;
391 s->bank[i].sens_edge = 0x00000000;
392 s->bank[i].fiq = 0x00000000;
393 s->bank[i].inputs = 0x00000000;
394 s->bank[i].swi = 0x00000000;
395 memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
396
397 if (s->level_only)
398 s->bank[i].sens_edge = 0xffffffff;
399 }
400
401 s->new_agr[0] = ~0;
402 s->new_agr[1] = ~0;
403 s->sir_intr[0] = 0;
404 s->sir_intr[1] = 0;
405 s->autoidle = 0;
406 s->mask = ~0;
407
408 qemu_set_irq(s->parent_intr[0], 0);
409 qemu_set_irq(s->parent_intr[1], 0);
410 }
411
412 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
413 unsigned long size, unsigned char nbanks, qemu_irq **pins,
414 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
415 {
416 int iomemtype;
417 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
418 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
419 sizeof(struct omap_intr_handler_bank_s) * nbanks);
420
421 s->parent_intr[0] = parent_irq;
422 s->parent_intr[1] = parent_fiq;
423 s->base = base;
424 s->nbanks = nbanks;
425 s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
426 if (pins)
427 *pins = s->pins;
428
429 omap_inth_reset(s);
430
431 iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
432 omap_inth_writefn, s);
433 cpu_register_physical_memory(s->base, size, iomemtype);
434
435 return s;
436 }
437
438 static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
439 {
440 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
441 int offset = addr - s->base;
442 int bank_no, line_no;
443 struct omap_intr_handler_bank_s *bank = 0;
444
445 if ((offset & 0xf80) == 0x80) {
446 bank_no = (offset & 0x60) >> 5;
447 if (bank_no < s->nbanks) {
448 offset &= ~0x60;
449 bank = &s->bank[bank_no];
450 }
451 }
452
453 switch (offset) {
454 case 0x00: /* INTC_REVISION */
455 return 0x21;
456
457 case 0x10: /* INTC_SYSCONFIG */
458 return (s->autoidle >> 2) & 1;
459
460 case 0x14: /* INTC_SYSSTATUS */
461 return 1; /* RESETDONE */
462
463 case 0x40: /* INTC_SIR_IRQ */
464 return s->sir_intr[0];
465
466 case 0x44: /* INTC_SIR_FIQ */
467 return s->sir_intr[1];
468
469 case 0x48: /* INTC_CONTROL */
470 return (!s->mask) << 2; /* GLOBALMASK */
471
472 case 0x4c: /* INTC_PROTECTION */
473 return 0;
474
475 case 0x50: /* INTC_IDLE */
476 return s->autoidle & 3;
477
478 /* Per-bank registers */
479 case 0x80: /* INTC_ITR */
480 return bank->inputs;
481
482 case 0x84: /* INTC_MIR */
483 return bank->mask;
484
485 case 0x88: /* INTC_MIR_CLEAR */
486 case 0x8c: /* INTC_MIR_SET */
487 return 0;
488
489 case 0x90: /* INTC_ISR_SET */
490 return bank->swi;
491
492 case 0x94: /* INTC_ISR_CLEAR */
493 return 0;
494
495 case 0x98: /* INTC_PENDING_IRQ */
496 return bank->irqs & ~bank->mask & ~bank->fiq;
497
498 case 0x9c: /* INTC_PENDING_FIQ */
499 return bank->irqs & ~bank->mask & bank->fiq;
500
501 /* Per-line registers */
502 case 0x100 ... 0x300: /* INTC_ILR */
503 bank_no = (offset - 0x100) >> 7;
504 if (bank_no > s->nbanks)
505 break;
506 bank = &s->bank[bank_no];
507 line_no = (offset & 0x7f) >> 2;
508 return (bank->priority[line_no] << 2) |
509 ((bank->fiq >> line_no) & 1);
510 }
511 OMAP_BAD_REG(addr);
512 return 0;
513 }
514
515 static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
516 uint32_t value)
517 {
518 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
519 int offset = addr - s->base;
520 int bank_no, line_no;
521 struct omap_intr_handler_bank_s *bank = 0;
522
523 if ((offset & 0xf80) == 0x80) {
524 bank_no = (offset & 0x60) >> 5;
525 if (bank_no < s->nbanks) {
526 offset &= ~0x60;
527 bank = &s->bank[bank_no];
528 }
529 }
530
531 switch (offset) {
532 case 0x10: /* INTC_SYSCONFIG */
533 s->autoidle &= 4;
534 s->autoidle |= (value & 1) << 2;
535 if (value & 2) /* SOFTRESET */
536 omap_inth_reset(s);
537 return;
538
539 case 0x48: /* INTC_CONTROL */
540 s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */
541 if (value & 2) { /* NEWFIQAGR */
542 qemu_set_irq(s->parent_intr[1], 0);
543 s->new_agr[1] = ~0;
544 omap_inth_update(s, 1);
545 }
546 if (value & 1) { /* NEWIRQAGR */
547 qemu_set_irq(s->parent_intr[0], 0);
548 s->new_agr[0] = ~0;
549 omap_inth_update(s, 0);
550 }
551 return;
552
553 case 0x4c: /* INTC_PROTECTION */
554 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
555 * for every register, see Chapter 3 and 4 for privileged mode. */
556 if (value & 1)
557 fprintf(stderr, "%s: protection mode enable attempt\n",
558 __FUNCTION__);
559 return;
560
561 case 0x50: /* INTC_IDLE */
562 s->autoidle &= ~3;
563 s->autoidle |= value & 3;
564 return;
565
566 /* Per-bank registers */
567 case 0x84: /* INTC_MIR */
568 bank->mask = value;
569 omap_inth_update(s, 0);
570 omap_inth_update(s, 1);
571 return;
572
573 case 0x88: /* INTC_MIR_CLEAR */
574 bank->mask &= ~value;
575 omap_inth_update(s, 0);
576 omap_inth_update(s, 1);
577 return;
578
579 case 0x8c: /* INTC_MIR_SET */
580 bank->mask |= value;
581 return;
582
583 case 0x90: /* INTC_ISR_SET */
584 bank->irqs |= bank->swi |= value;
585 omap_inth_update(s, 0);
586 omap_inth_update(s, 1);
587 return;
588
589 case 0x94: /* INTC_ISR_CLEAR */
590 bank->swi &= ~value;
591 bank->irqs = bank->swi & bank->inputs;
592 return;
593
594 /* Per-line registers */
595 case 0x100 ... 0x300: /* INTC_ILR */
596 bank_no = (offset - 0x100) >> 7;
597 if (bank_no > s->nbanks)
598 break;
599 bank = &s->bank[bank_no];
600 line_no = (offset & 0x7f) >> 2;
601 bank->priority[line_no] = (value >> 2) & 0x3f;
602 bank->fiq &= ~(1 << line_no);
603 bank->fiq |= (value & 1) << line_no;
604 return;
605
606 case 0x00: /* INTC_REVISION */
607 case 0x14: /* INTC_SYSSTATUS */
608 case 0x40: /* INTC_SIR_IRQ */
609 case 0x44: /* INTC_SIR_FIQ */
610 case 0x80: /* INTC_ITR */
611 case 0x98: /* INTC_PENDING_IRQ */
612 case 0x9c: /* INTC_PENDING_FIQ */
613 OMAP_RO_REG(addr);
614 return;
615 }
616 OMAP_BAD_REG(addr);
617 }
618
619 static CPUReadMemoryFunc *omap2_inth_readfn[] = {
620 omap_badwidth_read32,
621 omap_badwidth_read32,
622 omap2_inth_read,
623 };
624
625 static CPUWriteMemoryFunc *omap2_inth_writefn[] = {
626 omap2_inth_write,
627 omap2_inth_write,
628 omap2_inth_write,
629 };
630
631 struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
632 int size, int nbanks, qemu_irq **pins,
633 qemu_irq parent_irq, qemu_irq parent_fiq,
634 omap_clk fclk, omap_clk iclk)
635 {
636 int iomemtype;
637 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
638 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
639 sizeof(struct omap_intr_handler_bank_s) * nbanks);
640
641 s->parent_intr[0] = parent_irq;
642 s->parent_intr[1] = parent_fiq;
643 s->base = base;
644 s->nbanks = nbanks;
645 s->level_only = 1;
646 s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
647 if (pins)
648 *pins = s->pins;
649
650 omap_inth_reset(s);
651
652 iomemtype = cpu_register_io_memory(0, omap2_inth_readfn,
653 omap2_inth_writefn, s);
654 cpu_register_physical_memory(s->base, size, iomemtype);
655
656 return s;
657 }
658
659 /* MPU OS timers */
660 struct omap_mpu_timer_s {
661 qemu_irq irq;
662 omap_clk clk;
663 target_phys_addr_t base;
664 uint32_t val;
665 int64_t time;
666 QEMUTimer *timer;
667 int64_t rate;
668 int it_ena;
669
670 int enable;
671 int ptv;
672 int ar;
673 int st;
674 uint32_t reset_val;
675 };
676
677 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
678 {
679 uint64_t distance = qemu_get_clock(vm_clock) - timer->time;
680
681 if (timer->st && timer->enable && timer->rate)
682 return timer->val - muldiv64(distance >> (timer->ptv + 1),
683 timer->rate, ticks_per_sec);
684 else
685 return timer->val;
686 }
687
688 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
689 {
690 timer->val = omap_timer_read(timer);
691 timer->time = qemu_get_clock(vm_clock);
692 }
693
694 static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
695 {
696 int64_t expires;
697
698 if (timer->enable && timer->st && timer->rate) {
699 timer->val = timer->reset_val; /* Should skip this on clk enable */
700 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
701 ticks_per_sec, timer->rate);
702
703 /* If timer expiry would be sooner than in about 1 ms and
704 * auto-reload isn't set, then fire immediately. This is a hack
705 * to make systems like PalmOS run in acceptable time. PalmOS
706 * sets the interval to a very low value and polls the status bit
707 * in a busy loop when it wants to sleep just a couple of CPU
708 * ticks. */
709 if (expires > (ticks_per_sec >> 10) || timer->ar)
710 qemu_mod_timer(timer->timer, timer->time + expires);
711 else {
712 timer->val = 0;
713 timer->st = 0;
714 if (timer->it_ena)
715 /* Edge-triggered irq */
716 qemu_irq_pulse(timer->irq);
717 }
718 } else
719 qemu_del_timer(timer->timer);
720 }
721
722 static void omap_timer_tick(void *opaque)
723 {
724 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
725 omap_timer_sync(timer);
726
727 if (!timer->ar) {
728 timer->val = 0;
729 timer->st = 0;
730 }
731
732 if (timer->it_ena)
733 /* Edge-triggered irq */
734 qemu_irq_pulse(timer->irq);
735 omap_timer_update(timer);
736 }
737
738 static void omap_timer_clk_update(void *opaque, int line, int on)
739 {
740 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
741
742 omap_timer_sync(timer);
743 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
744 omap_timer_update(timer);
745 }
746
747 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
748 {
749 omap_clk_adduser(timer->clk,
750 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
751 timer->rate = omap_clk_getrate(timer->clk);
752 }
753
754 static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
755 {
756 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
757 int offset = addr - s->base;
758
759 switch (offset) {
760 case 0x00: /* CNTL_TIMER */
761 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
762
763 case 0x04: /* LOAD_TIM */
764 break;
765
766 case 0x08: /* READ_TIM */
767 return omap_timer_read(s);
768 }
769
770 OMAP_BAD_REG(addr);
771 return 0;
772 }
773
774 static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
775 uint32_t value)
776 {
777 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
778 int offset = addr - s->base;
779
780 switch (offset) {
781 case 0x00: /* CNTL_TIMER */
782 omap_timer_sync(s);
783 s->enable = (value >> 5) & 1;
784 s->ptv = (value >> 2) & 7;
785 s->ar = (value >> 1) & 1;
786 s->st = value & 1;
787 omap_timer_update(s);
788 return;
789
790 case 0x04: /* LOAD_TIM */
791 s->reset_val = value;
792 return;
793
794 case 0x08: /* READ_TIM */
795 OMAP_RO_REG(addr);
796 break;
797
798 default:
799 OMAP_BAD_REG(addr);
800 }
801 }
802
803 static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
804 omap_badwidth_read32,
805 omap_badwidth_read32,
806 omap_mpu_timer_read,
807 };
808
809 static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
810 omap_badwidth_write32,
811 omap_badwidth_write32,
812 omap_mpu_timer_write,
813 };
814
815 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
816 {
817 qemu_del_timer(s->timer);
818 s->enable = 0;
819 s->reset_val = 31337;
820 s->val = 0;
821 s->ptv = 0;
822 s->ar = 0;
823 s->st = 0;
824 s->it_ena = 1;
825 }
826
827 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
828 qemu_irq irq, omap_clk clk)
829 {
830 int iomemtype;
831 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
832 qemu_mallocz(sizeof(struct omap_mpu_timer_s));
833
834 s->irq = irq;
835 s->clk = clk;
836 s->base = base;
837 s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s);
838 omap_mpu_timer_reset(s);
839 omap_timer_clk_setup(s);
840
841 iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
842 omap_mpu_timer_writefn, s);
843 cpu_register_physical_memory(s->base, 0x100, iomemtype);
844
845 return s;
846 }
847
848 /* Watchdog timer */
849 struct omap_watchdog_timer_s {
850 struct omap_mpu_timer_s timer;
851 uint8_t last_wr;
852 int mode;
853 int free;
854 int reset;
855 };
856
857 static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
858 {
859 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
860 int offset = addr - s->timer.base;
861
862 switch (offset) {
863 case 0x00: /* CNTL_TIMER */
864 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
865 (s->timer.st << 7) | (s->free << 1);
866
867 case 0x04: /* READ_TIMER */
868 return omap_timer_read(&s->timer);
869
870 case 0x08: /* TIMER_MODE */
871 return s->mode << 15;
872 }
873
874 OMAP_BAD_REG(addr);
875 return 0;
876 }
877
878 static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
879 uint32_t value)
880 {
881 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
882 int offset = addr - s->timer.base;
883
884 switch (offset) {
885 case 0x00: /* CNTL_TIMER */
886 omap_timer_sync(&s->timer);
887 s->timer.ptv = (value >> 9) & 7;
888 s->timer.ar = (value >> 8) & 1;
889 s->timer.st = (value >> 7) & 1;
890 s->free = (value >> 1) & 1;
891 omap_timer_update(&s->timer);
892 break;
893
894 case 0x04: /* LOAD_TIMER */
895 s->timer.reset_val = value & 0xffff;
896 break;
897
898 case 0x08: /* TIMER_MODE */
899 if (!s->mode && ((value >> 15) & 1))
900 omap_clk_get(s->timer.clk);
901 s->mode |= (value >> 15) & 1;
902 if (s->last_wr == 0xf5) {
903 if ((value & 0xff) == 0xa0) {
904 if (s->mode) {
905 s->mode = 0;
906 omap_clk_put(s->timer.clk);
907 }
908 } else {
909 /* XXX: on T|E hardware somehow this has no effect,
910 * on Zire 71 it works as specified. */
911 s->reset = 1;
912 qemu_system_reset_request();
913 }
914 }
915 s->last_wr = value & 0xff;
916 break;
917
918 default:
919 OMAP_BAD_REG(addr);
920 }
921 }
922
923 static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
924 omap_badwidth_read16,
925 omap_wd_timer_read,
926 omap_badwidth_read16,
927 };
928
929 static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
930 omap_badwidth_write16,
931 omap_wd_timer_write,
932 omap_badwidth_write16,
933 };
934
935 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
936 {
937 qemu_del_timer(s->timer.timer);
938 if (!s->mode)
939 omap_clk_get(s->timer.clk);
940 s->mode = 1;
941 s->free = 1;
942 s->reset = 0;
943 s->timer.enable = 1;
944 s->timer.it_ena = 1;
945 s->timer.reset_val = 0xffff;
946 s->timer.val = 0;
947 s->timer.st = 0;
948 s->timer.ptv = 0;
949 s->timer.ar = 0;
950 omap_timer_update(&s->timer);
951 }
952
953 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
954 qemu_irq irq, omap_clk clk)
955 {
956 int iomemtype;
957 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
958 qemu_mallocz(sizeof(struct omap_watchdog_timer_s));
959
960 s->timer.irq = irq;
961 s->timer.clk = clk;
962 s->timer.base = base;
963 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
964 omap_wd_timer_reset(s);
965 omap_timer_clk_setup(&s->timer);
966
967 iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
968 omap_wd_timer_writefn, s);
969 cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
970
971 return s;
972 }
973
974 /* 32-kHz timer */
975 struct omap_32khz_timer_s {
976 struct omap_mpu_timer_s timer;
977 };
978
979 static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
980 {
981 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
982 int offset = addr & OMAP_MPUI_REG_MASK;
983
984 switch (offset) {
985 case 0x00: /* TVR */
986 return s->timer.reset_val;
987
988 case 0x04: /* TCR */
989 return omap_timer_read(&s->timer);
990
991 case 0x08: /* CR */
992 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
993
994 default:
995 break;
996 }
997 OMAP_BAD_REG(addr);
998 return 0;
999 }
1000
1001 static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
1002 uint32_t value)
1003 {
1004 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
1005 int offset = addr & OMAP_MPUI_REG_MASK;
1006
1007 switch (offset) {
1008 case 0x00: /* TVR */
1009 s->timer.reset_val = value & 0x00ffffff;
1010 break;
1011
1012 case 0x04: /* TCR */
1013 OMAP_RO_REG(addr);
1014 break;
1015
1016 case 0x08: /* CR */
1017 s->timer.ar = (value >> 3) & 1;
1018 s->timer.it_ena = (value >> 2) & 1;
1019 if (s->timer.st != (value & 1) || (value & 2)) {
1020 omap_timer_sync(&s->timer);
1021 s->timer.enable = value & 1;
1022 s->timer.st = value & 1;
1023 omap_timer_update(&s->timer);
1024 }
1025 break;
1026
1027 default:
1028 OMAP_BAD_REG(addr);
1029 }
1030 }
1031
1032 static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
1033 omap_badwidth_read32,
1034 omap_badwidth_read32,
1035 omap_os_timer_read,
1036 };
1037
1038 static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
1039 omap_badwidth_write32,
1040 omap_badwidth_write32,
1041 omap_os_timer_write,
1042 };
1043
1044 static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
1045 {
1046 qemu_del_timer(s->timer.timer);
1047 s->timer.enable = 0;
1048 s->timer.it_ena = 0;
1049 s->timer.reset_val = 0x00ffffff;
1050 s->timer.val = 0;
1051 s->timer.st = 0;
1052 s->timer.ptv = 0;
1053 s->timer.ar = 1;
1054 }
1055
1056 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
1057 qemu_irq irq, omap_clk clk)
1058 {
1059 int iomemtype;
1060 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
1061 qemu_mallocz(sizeof(struct omap_32khz_timer_s));
1062
1063 s->timer.irq = irq;
1064 s->timer.clk = clk;
1065 s->timer.base = base;
1066 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
1067 omap_os_timer_reset(s);
1068 omap_timer_clk_setup(&s->timer);
1069
1070 iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
1071 omap_os_timer_writefn, s);
1072 cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
1073
1074 return s;
1075 }
1076
1077 /* Ultra Low-Power Device Module */
1078 static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
1079 {
1080 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1081 int offset = addr - s->ulpd_pm_base;
1082 uint16_t ret;
1083
1084 switch (offset) {
1085 case 0x14: /* IT_STATUS */
1086 ret = s->ulpd_pm_regs[offset >> 2];
1087 s->ulpd_pm_regs[offset >> 2] = 0;
1088 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
1089 return ret;
1090
1091 case 0x18: /* Reserved */
1092 case 0x1c: /* Reserved */
1093 case 0x20: /* Reserved */
1094 case 0x28: /* Reserved */
1095 case 0x2c: /* Reserved */
1096 OMAP_BAD_REG(addr);
1097 case 0x00: /* COUNTER_32_LSB */
1098 case 0x04: /* COUNTER_32_MSB */
1099 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1100 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1101 case 0x10: /* GAUGING_CTRL */
1102 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1103 case 0x30: /* CLOCK_CTRL */
1104 case 0x34: /* SOFT_REQ */
1105 case 0x38: /* COUNTER_32_FIQ */
1106 case 0x3c: /* DPLL_CTRL */
1107 case 0x40: /* STATUS_REQ */
1108 /* XXX: check clk::usecount state for every clock */
1109 case 0x48: /* LOCL_TIME */
1110 case 0x4c: /* APLL_CTRL */
1111 case 0x50: /* POWER_CTRL */
1112 return s->ulpd_pm_regs[offset >> 2];
1113 }
1114
1115 OMAP_BAD_REG(addr);
1116 return 0;
1117 }
1118
1119 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
1120 uint16_t diff, uint16_t value)
1121 {
1122 if (diff & (1 << 4)) /* USB_MCLK_EN */
1123 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
1124 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
1125 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
1126 }
1127
1128 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
1129 uint16_t diff, uint16_t value)
1130 {
1131 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
1132 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
1133 if (diff & (1 << 1)) /* SOFT_COM_REQ */
1134 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
1135 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
1136 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
1137 if (diff & (1 << 3)) /* SOFT_USB_REQ */
1138 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
1139 }
1140
1141 static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
1142 uint32_t value)
1143 {
1144 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1145 int offset = addr - s->ulpd_pm_base;
1146 int64_t now, ticks;
1147 int div, mult;
1148 static const int bypass_div[4] = { 1, 2, 4, 4 };
1149 uint16_t diff;
1150
1151 switch (offset) {
1152 case 0x00: /* COUNTER_32_LSB */
1153 case 0x04: /* COUNTER_32_MSB */
1154 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1155 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1156 case 0x14: /* IT_STATUS */
1157 case 0x40: /* STATUS_REQ */
1158 OMAP_RO_REG(addr);
1159 break;
1160
1161 case 0x10: /* GAUGING_CTRL */
1162 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
1163 if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) {
1164 now = qemu_get_clock(vm_clock);
1165
1166 if (value & 1)
1167 s->ulpd_gauge_start = now;
1168 else {
1169 now -= s->ulpd_gauge_start;
1170
1171 /* 32-kHz ticks */
1172 ticks = muldiv64(now, 32768, ticks_per_sec);
1173 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
1174 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
1175 if (ticks >> 32) /* OVERFLOW_32K */
1176 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
1177
1178 /* High frequency ticks */
1179 ticks = muldiv64(now, 12000000, ticks_per_sec);
1180 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
1181 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
1182 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
1183 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
1184
1185 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
1186 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
1187 }
1188 }
1189 s->ulpd_pm_regs[offset >> 2] = value;
1190 break;
1191
1192 case 0x18: /* Reserved */
1193 case 0x1c: /* Reserved */
1194 case 0x20: /* Reserved */
1195 case 0x28: /* Reserved */
1196 case 0x2c: /* Reserved */
1197 OMAP_BAD_REG(addr);
1198 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1199 case 0x38: /* COUNTER_32_FIQ */
1200 case 0x48: /* LOCL_TIME */
1201 case 0x50: /* POWER_CTRL */
1202 s->ulpd_pm_regs[offset >> 2] = value;
1203 break;
1204
1205 case 0x30: /* CLOCK_CTRL */
1206 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1207 s->ulpd_pm_regs[offset >> 2] = value & 0x3f;
1208 omap_ulpd_clk_update(s, diff, value);
1209 break;
1210
1211 case 0x34: /* SOFT_REQ */
1212 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1213 s->ulpd_pm_regs[offset >> 2] = value & 0x1f;
1214 omap_ulpd_req_update(s, diff, value);
1215 break;
1216
1217 case 0x3c: /* DPLL_CTRL */
1218 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
1219 * omitted altogether, probably a typo. */
1220 /* This register has identical semantics with DPLL(1:3) control
1221 * registers, see omap_dpll_write() */
1222 diff = s->ulpd_pm_regs[offset >> 2] & value;
1223 s->ulpd_pm_regs[offset >> 2] = value & 0x2fff;
1224 if (diff & (0x3ff << 2)) {
1225 if (value & (1 << 4)) { /* PLL_ENABLE */
1226 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1227 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1228 } else {
1229 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1230 mult = 1;
1231 }
1232 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
1233 }
1234
1235 /* Enter the desired mode. */
1236 s->ulpd_pm_regs[offset >> 2] =
1237 (s->ulpd_pm_regs[offset >> 2] & 0xfffe) |
1238 ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1);
1239
1240 /* Act as if the lock is restored. */
1241 s->ulpd_pm_regs[offset >> 2] |= 2;
1242 break;
1243
1244 case 0x4c: /* APLL_CTRL */
1245 diff = s->ulpd_pm_regs[offset >> 2] & value;
1246 s->ulpd_pm_regs[offset >> 2] = value & 0xf;
1247 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
1248 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
1249 (value & (1 << 0)) ? "apll" : "dpll4"));
1250 break;
1251
1252 default:
1253 OMAP_BAD_REG(addr);
1254 }
1255 }
1256
1257 static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
1258 omap_badwidth_read16,
1259 omap_ulpd_pm_read,
1260 omap_badwidth_read16,
1261 };
1262
1263 static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
1264 omap_badwidth_write16,
1265 omap_ulpd_pm_write,
1266 omap_badwidth_write16,
1267 };
1268
1269 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
1270 {
1271 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
1272 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
1273 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
1274 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
1275 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
1276 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
1277 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
1278 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
1279 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
1280 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
1281 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
1282 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
1283 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
1284 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
1285 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
1286 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
1287 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
1288 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
1289 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
1290 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
1291 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
1292 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
1293 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
1294 }
1295
1296 static void omap_ulpd_pm_init(target_phys_addr_t base,
1297 struct omap_mpu_state_s *mpu)
1298 {
1299 int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn,
1300 omap_ulpd_pm_writefn, mpu);
1301
1302 mpu->ulpd_pm_base = base;
1303 cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
1304 omap_ulpd_pm_reset(mpu);
1305 }
1306
1307 /* OMAP Pin Configuration */
1308 static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
1309 {
1310 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1311 int offset = addr - s->pin_cfg_base;
1312
1313 switch (offset) {
1314 case 0x00: /* FUNC_MUX_CTRL_0 */
1315 case 0x04: /* FUNC_MUX_CTRL_1 */
1316 case 0x08: /* FUNC_MUX_CTRL_2 */
1317 return s->func_mux_ctrl[offset >> 2];
1318
1319 case 0x0c: /* COMP_MODE_CTRL_0 */
1320 return s->comp_mode_ctrl[0];
1321
1322 case 0x10: /* FUNC_MUX_CTRL_3 */
1323 case 0x14: /* FUNC_MUX_CTRL_4 */
1324 case 0x18: /* FUNC_MUX_CTRL_5 */
1325 case 0x1c: /* FUNC_MUX_CTRL_6 */
1326 case 0x20: /* FUNC_MUX_CTRL_7 */
1327 case 0x24: /* FUNC_MUX_CTRL_8 */
1328 case 0x28: /* FUNC_MUX_CTRL_9 */
1329 case 0x2c: /* FUNC_MUX_CTRL_A */
1330 case 0x30: /* FUNC_MUX_CTRL_B */
1331 case 0x34: /* FUNC_MUX_CTRL_C */
1332 case 0x38: /* FUNC_MUX_CTRL_D */
1333 return s->func_mux_ctrl[(offset >> 2) - 1];
1334
1335 case 0x40: /* PULL_DWN_CTRL_0 */
1336 case 0x44: /* PULL_DWN_CTRL_1 */
1337 case 0x48: /* PULL_DWN_CTRL_2 */
1338 case 0x4c: /* PULL_DWN_CTRL_3 */
1339 return s->pull_dwn_ctrl[(offset & 0xf) >> 2];
1340
1341 case 0x50: /* GATE_INH_CTRL_0 */
1342 return s->gate_inh_ctrl[0];
1343
1344 case 0x60: /* VOLTAGE_CTRL_0 */
1345 return s->voltage_ctrl[0];
1346
1347 case 0x70: /* TEST_DBG_CTRL_0 */
1348 return s->test_dbg_ctrl[0];
1349
1350 case 0x80: /* MOD_CONF_CTRL_0 */
1351 return s->mod_conf_ctrl[0];
1352 }
1353
1354 OMAP_BAD_REG(addr);
1355 return 0;
1356 }
1357
1358 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
1359 uint32_t diff, uint32_t value)
1360 {
1361 if (s->compat1509) {
1362 if (diff & (1 << 9)) /* BLUETOOTH */
1363 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
1364 (~value >> 9) & 1);
1365 if (diff & (1 << 7)) /* USB.CLKO */
1366 omap_clk_onoff(omap_findclk(s, "usb.clko"),
1367 (value >> 7) & 1);
1368 }
1369 }
1370
1371 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
1372 uint32_t diff, uint32_t value)
1373 {
1374 if (s->compat1509) {
1375 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
1376 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
1377 (value >> 31) & 1);
1378 if (diff & (1 << 1)) /* CLK32K */
1379 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
1380 (~value >> 1) & 1);
1381 }
1382 }
1383
1384 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
1385 uint32_t diff, uint32_t value)
1386 {
1387 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
1388 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
1389 omap_findclk(s, ((value >> 31) & 1) ?
1390 "ck_48m" : "armper_ck"));
1391 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
1392 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
1393 omap_findclk(s, ((value >> 30) & 1) ?
1394 "ck_48m" : "armper_ck"));
1395 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
1396 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
1397 omap_findclk(s, ((value >> 29) & 1) ?
1398 "ck_48m" : "armper_ck"));
1399 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
1400 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
1401 omap_findclk(s, ((value >> 23) & 1) ?
1402 "ck_48m" : "armper_ck"));
1403 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
1404 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
1405 omap_findclk(s, ((value >> 12) & 1) ?
1406 "ck_48m" : "armper_ck"));
1407 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
1408 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
1409 }
1410
1411 static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
1412 uint32_t value)
1413 {
1414 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1415 int offset = addr - s->pin_cfg_base;
1416 uint32_t diff;
1417
1418 switch (offset) {
1419 case 0x00: /* FUNC_MUX_CTRL_0 */
1420 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1421 s->func_mux_ctrl[offset >> 2] = value;
1422 omap_pin_funcmux0_update(s, diff, value);
1423 return;
1424
1425 case 0x04: /* FUNC_MUX_CTRL_1 */
1426 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1427 s->func_mux_ctrl[offset >> 2] = value;
1428 omap_pin_funcmux1_update(s, diff, value);
1429 return;
1430
1431 case 0x08: /* FUNC_MUX_CTRL_2 */
1432 s->func_mux_ctrl[offset >> 2] = value;
1433 return;
1434
1435 case 0x0c: /* COMP_MODE_CTRL_0 */
1436 s->comp_mode_ctrl[0] = value;
1437 s->compat1509 = (value != 0x0000eaef);
1438 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
1439 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
1440 return;
1441
1442 case 0x10: /* FUNC_MUX_CTRL_3 */
1443 case 0x14: /* FUNC_MUX_CTRL_4 */
1444 case 0x18: /* FUNC_MUX_CTRL_5 */
1445 case 0x1c: /* FUNC_MUX_CTRL_6 */
1446 case 0x20: /* FUNC_MUX_CTRL_7 */
1447 case 0x24: /* FUNC_MUX_CTRL_8 */
1448 case 0x28: /* FUNC_MUX_CTRL_9 */
1449 case 0x2c: /* FUNC_MUX_CTRL_A */
1450 case 0x30: /* FUNC_MUX_CTRL_B */
1451 case 0x34: /* FUNC_MUX_CTRL_C */
1452 case 0x38: /* FUNC_MUX_CTRL_D */
1453 s->func_mux_ctrl[(offset >> 2) - 1] = value;
1454 return;
1455
1456 case 0x40: /* PULL_DWN_CTRL_0 */
1457 case 0x44: /* PULL_DWN_CTRL_1 */
1458 case 0x48: /* PULL_DWN_CTRL_2 */
1459 case 0x4c: /* PULL_DWN_CTRL_3 */
1460 s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value;
1461 return;
1462
1463 case 0x50: /* GATE_INH_CTRL_0 */
1464 s->gate_inh_ctrl[0] = value;
1465 return;
1466
1467 case 0x60: /* VOLTAGE_CTRL_0 */
1468 s->voltage_ctrl[0] = value;
1469 return;
1470
1471 case 0x70: /* TEST_DBG_CTRL_0 */
1472 s->test_dbg_ctrl[0] = value;
1473 return;
1474
1475 case 0x80: /* MOD_CONF_CTRL_0 */
1476 diff = s->mod_conf_ctrl[0] ^ value;
1477 s->mod_conf_ctrl[0] = value;
1478 omap_pin_modconf1_update(s, diff, value);
1479 return;
1480
1481 default:
1482 OMAP_BAD_REG(addr);
1483 }
1484 }
1485
1486 static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
1487 omap_badwidth_read32,
1488 omap_badwidth_read32,
1489 omap_pin_cfg_read,
1490 };
1491
1492 static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
1493 omap_badwidth_write32,
1494 omap_badwidth_write32,
1495 omap_pin_cfg_write,
1496 };
1497
1498 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
1499 {
1500 /* Start in Compatibility Mode. */
1501 mpu->compat1509 = 1;
1502 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
1503 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
1504 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
1505 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
1506 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
1507 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
1508 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
1509 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
1510 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
1511 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
1512 }
1513
1514 static void omap_pin_cfg_init(target_phys_addr_t base,
1515 struct omap_mpu_state_s *mpu)
1516 {
1517 int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn,
1518 omap_pin_cfg_writefn, mpu);
1519
1520 mpu->pin_cfg_base = base;
1521 cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
1522 omap_pin_cfg_reset(mpu);
1523 }
1524
1525 /* Device Identification, Die Identification */
1526 static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
1527 {
1528 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1529
1530 switch (addr) {
1531 case 0xfffe1800: /* DIE_ID_LSB */
1532 return 0xc9581f0e;
1533 case 0xfffe1804: /* DIE_ID_MSB */
1534 return 0xa8858bfa;
1535
1536 case 0xfffe2000: /* PRODUCT_ID_LSB */
1537 return 0x00aaaafc;
1538 case 0xfffe2004: /* PRODUCT_ID_MSB */
1539 return 0xcafeb574;
1540
1541 case 0xfffed400: /* JTAG_ID_LSB */
1542 switch (s->mpu_model) {
1543 case omap310:
1544 return 0x03310315;
1545 case omap1510:
1546 return 0x03310115;
1547 default:
1548 cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
1549 }
1550 break;
1551
1552 case 0xfffed404: /* JTAG_ID_MSB */
1553 switch (s->mpu_model) {
1554 case omap310:
1555 return 0xfb57402f;
1556 case omap1510:
1557 return 0xfb47002f;
1558 default:
1559 cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
1560 }
1561 break;
1562 }
1563
1564 OMAP_BAD_REG(addr);
1565 return 0;
1566 }
1567
1568 static void omap_id_write(void *opaque, target_phys_addr_t addr,
1569 uint32_t value)
1570 {
1571 OMAP_BAD_REG(addr);
1572 }
1573
1574 static CPUReadMemoryFunc *omap_id_readfn[] = {
1575 omap_badwidth_read32,
1576 omap_badwidth_read32,
1577 omap_id_read,
1578 };
1579
1580 static CPUWriteMemoryFunc *omap_id_writefn[] = {
1581 omap_badwidth_write32,
1582 omap_badwidth_write32,
1583 omap_id_write,
1584 };
1585
1586 static void omap_id_init(struct omap_mpu_state_s *mpu)
1587 {
1588 int iomemtype = cpu_register_io_memory(0, omap_id_readfn,
1589 omap_id_writefn, mpu);
1590 cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype);
1591 cpu_register_physical_memory(0xfffed400, 0x100, iomemtype);
1592 if (!cpu_is_omap15xx(mpu))
1593 cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype);
1594 }
1595
1596 /* MPUI Control (Dummy) */
1597 static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
1598 {
1599 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1600 int offset = addr - s->mpui_base;
1601
1602 switch (offset) {
1603 case 0x00: /* CTRL */
1604 return s->mpui_ctrl;
1605 case 0x04: /* DEBUG_ADDR */
1606 return 0x01ffffff;
1607 case 0x08: /* DEBUG_DATA */
1608 return 0xffffffff;
1609 case 0x0c: /* DEBUG_FLAG */
1610 return 0x00000800;
1611 case 0x10: /* STATUS */
1612 return 0x00000000;
1613
1614 /* Not in OMAP310 */
1615 case 0x14: /* DSP_STATUS */
1616 case 0x18: /* DSP_BOOT_CONFIG */
1617 return 0x00000000;
1618 case 0x1c: /* DSP_MPUI_CONFIG */
1619 return 0x0000ffff;
1620 }
1621
1622 OMAP_BAD_REG(addr);
1623 return 0;
1624 }
1625
1626 static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
1627 uint32_t value)
1628 {
1629 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1630 int offset = addr - s->mpui_base;
1631
1632 switch (offset) {
1633 case 0x00: /* CTRL */
1634 s->mpui_ctrl = value & 0x007fffff;
1635 break;
1636
1637 case 0x04: /* DEBUG_ADDR */
1638 case 0x08: /* DEBUG_DATA */
1639 case 0x0c: /* DEBUG_FLAG */
1640 case 0x10: /* STATUS */
1641 /* Not in OMAP310 */
1642 case 0x14: /* DSP_STATUS */
1643 OMAP_RO_REG(addr);
1644 case 0x18: /* DSP_BOOT_CONFIG */
1645 case 0x1c: /* DSP_MPUI_CONFIG */
1646 break;
1647
1648 default:
1649 OMAP_BAD_REG(addr);
1650 }
1651 }
1652
1653 static CPUReadMemoryFunc *omap_mpui_readfn[] = {
1654 omap_badwidth_read32,
1655 omap_badwidth_read32,
1656 omap_mpui_read,
1657 };
1658
1659 static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
1660 omap_badwidth_write32,
1661 omap_badwidth_write32,
1662 omap_mpui_write,
1663 };
1664
1665 static void omap_mpui_reset(struct omap_mpu_state_s *s)
1666 {
1667 s->mpui_ctrl = 0x0003ff1b;
1668 }
1669
1670 static void omap_mpui_init(target_phys_addr_t base,
1671 struct omap_mpu_state_s *mpu)
1672 {
1673 int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn,
1674 omap_mpui_writefn, mpu);
1675
1676 mpu->mpui_base = base;
1677 cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
1678
1679 omap_mpui_reset(mpu);
1680 }
1681
1682 /* TIPB Bridges */
1683 struct omap_tipb_bridge_s {
1684 target_phys_addr_t base;
1685 qemu_irq abort;
1686
1687 int width_intr;
1688 uint16_t control;
1689 uint16_t alloc;
1690 uint16_t buffer;
1691 uint16_t enh_control;
1692 };
1693
1694 static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
1695 {
1696 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1697 int offset = addr - s->base;
1698
1699 switch (offset) {
1700 case 0x00: /* TIPB_CNTL */
1701 return s->control;
1702 case 0x04: /* TIPB_BUS_ALLOC */
1703 return s->alloc;
1704 case 0x08: /* MPU_TIPB_CNTL */
1705 return s->buffer;
1706 case 0x0c: /* ENHANCED_TIPB_CNTL */
1707 return s->enh_control;
1708 case 0x10: /* ADDRESS_DBG */
1709 case 0x14: /* DATA_DEBUG_LOW */
1710 case 0x18: /* DATA_DEBUG_HIGH */
1711 return 0xffff;
1712 case 0x1c: /* DEBUG_CNTR_SIG */
1713 return 0x00f8;
1714 }
1715
1716 OMAP_BAD_REG(addr);
1717 return 0;
1718 }
1719
1720 static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
1721 uint32_t value)
1722 {
1723 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1724 int offset = addr - s->base;
1725
1726 switch (offset) {
1727 case 0x00: /* TIPB_CNTL */
1728 s->control = value & 0xffff;
1729 break;
1730
1731 case 0x04: /* TIPB_BUS_ALLOC */
1732 s->alloc = value & 0x003f;
1733 break;
1734
1735 case 0x08: /* MPU_TIPB_CNTL */
1736 s->buffer = value & 0x0003;
1737 break;
1738
1739 case 0x0c: /* ENHANCED_TIPB_CNTL */
1740 s->width_intr = !(value & 2);
1741 s->enh_control = value & 0x000f;
1742 break;
1743
1744 case 0x10: /* ADDRESS_DBG */
1745 case 0x14: /* DATA_DEBUG_LOW */
1746 case 0x18: /* DATA_DEBUG_HIGH */
1747 case 0x1c: /* DEBUG_CNTR_SIG */
1748 OMAP_RO_REG(addr);
1749 break;
1750
1751 default:
1752 OMAP_BAD_REG(addr);
1753 }
1754 }
1755
1756 static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
1757 omap_badwidth_read16,
1758 omap_tipb_bridge_read,
1759 omap_tipb_bridge_read,
1760 };
1761
1762 static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
1763 omap_badwidth_write16,
1764 omap_tipb_bridge_write,
1765 omap_tipb_bridge_write,
1766 };
1767
1768 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1769 {
1770 s->control = 0xffff;
1771 s->alloc = 0x0009;
1772 s->buffer = 0x0000;
1773 s->enh_control = 0x000f;
1774 }
1775
1776 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
1777 qemu_irq abort_irq, omap_clk clk)
1778 {
1779 int iomemtype;
1780 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
1781 qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
1782
1783 s->abort = abort_irq;
1784 s->base = base;
1785 omap_tipb_bridge_reset(s);
1786
1787 iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
1788 omap_tipb_bridge_writefn, s);
1789 cpu_register_physical_memory(s->base, 0x100, iomemtype);
1790
1791 return s;
1792 }
1793
1794 /* Dummy Traffic Controller's Memory Interface */
1795 static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
1796 {
1797 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1798 int offset = addr - s->tcmi_base;
1799 uint32_t ret;
1800
1801 switch (offset) {
1802 case 0x00: /* IMIF_PRIO */
1803 case 0x04: /* EMIFS_PRIO */
1804 case 0x08: /* EMIFF_PRIO */
1805 case 0x0c: /* EMIFS_CONFIG */
1806 case 0x10: /* EMIFS_CS0_CONFIG */
1807 case 0x14: /* EMIFS_CS1_CONFIG */
1808 case 0x18: /* EMIFS_CS2_CONFIG */
1809 case 0x1c: /* EMIFS_CS3_CONFIG */
1810 case 0x24: /* EMIFF_MRS */
1811 case 0x28: /* TIMEOUT1 */
1812 case 0x2c: /* TIMEOUT2 */
1813 case 0x30: /* TIMEOUT3 */
1814 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1815 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1816 return s->tcmi_regs[offset >> 2];
1817
1818 case 0x20: /* EMIFF_SDRAM_CONFIG */
1819 ret = s->tcmi_regs[offset >> 2];
1820 s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1821 /* XXX: We can try using the VGA_DIRTY flag for this */
1822 return ret;
1823 }
1824
1825 OMAP_BAD_REG(addr);
1826 return 0;
1827 }
1828
1829 static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
1830 uint32_t value)
1831 {
1832 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1833 int offset = addr - s->tcmi_base;
1834
1835 switch (offset) {
1836 case 0x00: /* IMIF_PRIO */
1837 case 0x04: /* EMIFS_PRIO */
1838 case 0x08: /* EMIFF_PRIO */
1839 case 0x10: /* EMIFS_CS0_CONFIG */
1840 case 0x14: /* EMIFS_CS1_CONFIG */
1841 case 0x18: /* EMIFS_CS2_CONFIG */
1842 case 0x1c: /* EMIFS_CS3_CONFIG */
1843 case 0x20: /* EMIFF_SDRAM_CONFIG */
1844 case 0x24: /* EMIFF_MRS */
1845 case 0x28: /* TIMEOUT1 */
1846 case 0x2c: /* TIMEOUT2 */
1847 case 0x30: /* TIMEOUT3 */
1848 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1849 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1850 s->tcmi_regs[offset >> 2] = value;
1851 break;
1852 case 0x0c: /* EMIFS_CONFIG */
1853 s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4);
1854 break;
1855
1856 default:
1857 OMAP_BAD_REG(addr);
1858 }
1859 }
1860
1861 static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
1862 omap_badwidth_read32,
1863 omap_badwidth_read32,
1864 omap_tcmi_read,
1865 };
1866
1867 static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
1868 omap_badwidth_write32,
1869 omap_badwidth_write32,
1870 omap_tcmi_write,
1871 };
1872
1873 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1874 {
1875 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1876 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1877 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1878 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1879 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1880 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1881 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1882 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1883 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1884 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1885 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1886 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1887 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1888 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1889 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1890 }
1891
1892 static void omap_tcmi_init(target_phys_addr_t base,
1893 struct omap_mpu_state_s *mpu)
1894 {
1895 int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn,
1896 omap_tcmi_writefn, mpu);
1897
1898 mpu->tcmi_base = base;
1899 cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
1900 omap_tcmi_reset(mpu);
1901 }
1902
1903 /* Digital phase-locked loops control */
1904 static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
1905 {
1906 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1907 int offset = addr - s->base;
1908
1909 if (offset == 0x00) /* CTL_REG */
1910 return s->mode;
1911
1912 OMAP_BAD_REG(addr);
1913 return 0;
1914 }
1915
1916 static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
1917 uint32_t value)
1918 {
1919 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1920 uint16_t diff;
1921 int offset = addr - s->base;
1922 static const int bypass_div[4] = { 1, 2, 4, 4 };
1923 int div, mult;
1924
1925 if (offset == 0x00) { /* CTL_REG */
1926 /* See omap_ulpd_pm_write() too */
1927 diff = s->mode & value;
1928 s->mode = value & 0x2fff;
1929 if (diff & (0x3ff << 2)) {
1930 if (value & (1 << 4)) { /* PLL_ENABLE */
1931 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1932 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1933 } else {
1934 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1935 mult = 1;
1936 }
1937 omap_clk_setrate(s->dpll, div, mult);
1938 }
1939
1940 /* Enter the desired mode. */
1941 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1942
1943 /* Act as if the lock is restored. */
1944 s->mode |= 2;
1945 } else {
1946 OMAP_BAD_REG(addr);
1947 }
1948 }
1949
1950 static CPUReadMemoryFunc *omap_dpll_readfn[] = {
1951 omap_badwidth_read16,
1952 omap_dpll_read,
1953 omap_badwidth_read16,
1954 };
1955
1956 static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
1957 omap_badwidth_write16,
1958 omap_dpll_write,
1959 omap_badwidth_write16,
1960 };
1961
1962 static void omap_dpll_reset(struct dpll_ctl_s *s)
1963 {
1964 s->mode = 0x2002;
1965 omap_clk_setrate(s->dpll, 1, 1);
1966 }
1967
1968 static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
1969 omap_clk clk)
1970 {
1971 int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn,
1972 omap_dpll_writefn, s);
1973
1974 s->base = base;
1975 s->dpll = clk;
1976 omap_dpll_reset(s);
1977
1978 cpu_register_physical_memory(s->base, 0x100, iomemtype);
1979 }
1980
1981 /* UARTs */
1982 struct omap_uart_s {
1983 SerialState *serial; /* TODO */
1984 struct omap_target_agent_s *ta;
1985 target_phys_addr_t base;
1986
1987 uint8_t eblr;
1988 uint8_t syscontrol;
1989 uint8_t wkup;
1990 uint8_t cfps;
1991 uint8_t mdr[2];
1992 uint8_t scr;
1993 };
1994
1995 void omap_uart_reset(struct omap_uart_s *s)
1996 {
1997 s->eblr = 0x00;
1998 s->syscontrol = 0;
1999 s->wkup = 0x3f;
2000 s->cfps = 0x69;
2001 }
2002
2003 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
2004 qemu_irq irq, omap_clk fclk, omap_clk iclk,
2005 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
2006 {
2007 struct omap_uart_s *s = (struct omap_uart_s *)
2008 qemu_mallocz(sizeof(struct omap_uart_s));
2009
2010 s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
2011 chr ?: qemu_chr_open("null"), 1);
2012
2013 return s;
2014 }
2015
2016 static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
2017 {
2018 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
2019 int offset = addr - s->base;
2020
2021 switch (offset) {
2022 case 0x20: /* MDR1 */
2023 return s->mdr[0];
2024 case 0x24: /* MDR2 */
2025 return s->mdr[1];
2026 case 0x40: /* SCR */
2027 return s->scr;
2028 case 0x44: /* SSR */
2029 return 0x0;
2030 case 0x48: /* EBLR */
2031 return s->eblr;
2032 case 0x50: /* MVR */
2033 return 0x30;
2034 case 0x54: /* SYSC */
2035 return s->syscontrol;
2036 case 0x58: /* SYSS */
2037 return 1;
2038 case 0x5c: /* WER */
2039 return s->wkup;
2040 case 0x60: /* CFPS */
2041 return s->cfps;
2042 }
2043
2044 OMAP_BAD_REG(addr);
2045 return 0;
2046 }
2047
2048 static void omap_uart_write(void *opaque, target_phys_addr_t addr,
2049 uint32_t value)
2050 {
2051 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
2052 int offset = addr - s->base;
2053
2054 switch (offset) {
2055 case 0x20: /* MDR1 */
2056 s->mdr[0] = value & 0x7f;
2057 break;
2058 case 0x24: /* MDR2 */
2059 s->mdr[1] = value & 0xff;
2060 break;
2061 case 0x40: /* SCR */
2062 s->scr = value & 0xff;
2063 break;
2064 case 0x48: /* EBLR */
2065 s->eblr = value & 0xff;
2066 break;
2067 case 0x44: /* SSR */
2068 case 0x50: /* MVR */
2069 case 0x58: /* SYSS */
2070 OMAP_RO_REG(addr);
2071 break;
2072 case 0x54: /* SYSC */
2073 s->syscontrol = value & 0x1d;
2074 if (value & 2)
2075 omap_uart_reset(s);
2076 break;
2077 case 0x5c: /* WER */
2078 s->wkup = value & 0x7f;
2079 break;
2080 case 0x60: /* CFPS */
2081 s->cfps = value & 0xff;
2082 break;
2083 default:
2084 OMAP_BAD_REG(addr);
2085 }
2086 }
2087
2088 static CPUReadMemoryFunc *omap_uart_readfn[] = {
2089 omap_uart_read,
2090 omap_uart_read,
2091 omap_badwidth_read8,
2092 };
2093
2094 static CPUWriteMemoryFunc *omap_uart_writefn[] = {
2095 omap_uart_write,
2096 omap_uart_write,
2097 omap_badwidth_write8,
2098 };
2099
2100 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
2101 qemu_irq irq, omap_clk fclk, omap_clk iclk,
2102 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
2103 {
2104 target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
2105 struct omap_uart_s *s = omap_uart_init(base, irq,
2106 fclk, iclk, txdma, rxdma, chr);
2107 int iomemtype = cpu_register_io_memory(0, omap_uart_readfn,
2108 omap_uart_writefn, s);
2109
2110 s->ta = ta;
2111 s->base = base;
2112
2113 cpu_register_physical_memory(s->base + 0x20, 0x100, iomemtype);
2114
2115 return s;
2116 }
2117
2118 /* MPU Clock/Reset/Power Mode Control */
2119 static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
2120 {
2121 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2122 int offset = addr - s->clkm.mpu_base;
2123
2124 switch (offset) {
2125 case 0x00: /* ARM_CKCTL */
2126 return s->clkm.arm_ckctl;
2127
2128 case 0x04: /* ARM_IDLECT1 */
2129 return s->clkm.arm_idlect1;
2130
2131 case 0x08: /* ARM_IDLECT2 */
2132 return s->clkm.arm_idlect2;
2133
2134 case 0x0c: /* ARM_EWUPCT */
2135 return s->clkm.arm_ewupct;
2136
2137 case 0x10: /* ARM_RSTCT1 */
2138 return s->clkm.arm_rstct1;
2139
2140 case 0x14: /* ARM_RSTCT2 */
2141 return s->clkm.arm_rstct2;
2142
2143 case 0x18: /* ARM_SYSST */
2144 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
2145
2146 case 0x1c: /* ARM_CKOUT1 */
2147 return s->clkm.arm_ckout1;
2148
2149 case 0x20: /* ARM_CKOUT2 */
2150 break;
2151 }
2152
2153 OMAP_BAD_REG(addr);
2154 return 0;
2155 }
2156
2157 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
2158 uint16_t diff, uint16_t value)
2159 {
2160 omap_clk clk;
2161
2162 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
2163 if (value & (1 << 14))
2164 /* Reserved */;
2165 else {
2166 clk = omap_findclk(s, "arminth_ck");
2167 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2168 }
2169 }
2170 if (diff & (1 << 12)) { /* ARM_TIMXO */
2171 clk = omap_findclk(s, "armtim_ck");
2172 if (value & (1 << 12))
2173 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
2174 else
2175 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2176 }
2177 /* XXX: en_dspck */
2178 if (diff & (3 << 10)) { /* DSPMMUDIV */
2179 clk = omap_findclk(s, "dspmmu_ck");
2180 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
2181 }
2182 if (diff & (3 << 8)) { /* TCDIV */
2183 clk = omap_findclk(s, "tc_ck");
2184 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
2185 }
2186 if (diff & (3 << 6)) { /* DSPDIV */
2187 clk = omap_findclk(s, "dsp_ck");
2188 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
2189 }
2190 if (diff & (3 << 4)) { /* ARMDIV */
2191 clk = omap_findclk(s, "arm_ck");
2192 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
2193 }
2194 if (diff & (3 << 2)) { /* LCDDIV */
2195 clk = omap_findclk(s, "lcd_ck");
2196 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
2197 }
2198 if (diff & (3 << 0)) { /* PERDIV */
2199 clk = omap_findclk(s, "armper_ck");
2200 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
2201 }
2202 }
2203
2204 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
2205 uint16_t diff, uint16_t value)
2206 {
2207 omap_clk clk;
2208
2209 if (value & (1 << 11)) /* SETARM_IDLE */
2210 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
2211 if (!(value & (1 << 10))) /* WKUP_MODE */
2212 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
2213
2214 #define SET_CANIDLE(clock, bit) \
2215 if (diff & (1 << bit)) { \
2216 clk = omap_findclk(s, clock); \
2217 omap_clk_canidle(clk, (value >> bit) & 1); \
2218 }
2219 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
2220 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
2221 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
2222 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
2223 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
2224 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
2225 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
2226 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
2227 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
2228 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
2229 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
2230 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
2231 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
2232 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
2233 }
2234
2235 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
2236 uint16_t diff, uint16_t value)
2237 {
2238 omap_clk clk;
2239
2240 #define SET_ONOFF(clock, bit) \
2241 if (diff & (1 << bit)) { \
2242 clk = omap_findclk(s, clock); \
2243 omap_clk_onoff(clk, (value >> bit) & 1); \
2244 }
2245 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
2246 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
2247 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
2248 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
2249 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
2250 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
2251 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
2252 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
2253 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
2254 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
2255 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
2256 }
2257
2258 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
2259 uint16_t diff, uint16_t value)
2260 {
2261 omap_clk clk;
2262
2263 if (diff & (3 << 4)) { /* TCLKOUT */
2264 clk = omap_findclk(s, "tclk_out");
2265 switch ((value >> 4) & 3) {
2266 case 1:
2267 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
2268 omap_clk_onoff(clk, 1);
2269 break;
2270 case 2:
2271 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2272 omap_clk_onoff(clk, 1);
2273 break;
2274 default:
2275 omap_clk_onoff(clk, 0);
2276 }
2277 }
2278 if (diff & (3 << 2)) { /* DCLKOUT */
2279 clk = omap_findclk(s, "dclk_out");
2280 switch ((value >> 2) & 3) {
2281 case 0:
2282 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
2283 break;
2284 case 1:
2285 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
2286 break;
2287 case 2:
2288 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
2289 break;
2290 case 3:
2291 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2292 break;
2293 }
2294 }
2295 if (diff & (3 << 0)) { /* ACLKOUT */
2296 clk = omap_findclk(s, "aclk_out");
2297 switch ((value >> 0) & 3) {
2298 case 1:
2299 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2300 omap_clk_onoff(clk, 1);
2301 break;
2302 case 2:
2303 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
2304 omap_clk_onoff(clk, 1);
2305 break;
2306 case 3:
2307 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2308 omap_clk_onoff(clk, 1);
2309 break;
2310 default:
2311 omap_clk_onoff(clk, 0);
2312 }
2313 }
2314 }
2315
2316 static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
2317 uint32_t value)
2318 {
2319 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2320 int offset = addr - s->clkm.mpu_base;
2321 uint16_t diff;
2322 omap_clk clk;
2323 static const char *clkschemename[8] = {
2324 "fully synchronous", "fully asynchronous", "synchronous scalable",
2325 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
2326 };
2327
2328 switch (offset) {
2329 case 0x00: /* ARM_CKCTL */
2330 diff = s->clkm.arm_ckctl ^ value;
2331 s->clkm.arm_ckctl = value & 0x7fff;
2332 omap_clkm_ckctl_update(s, diff, value);
2333 return;
2334
2335 case 0x04: /* ARM_IDLECT1 */
2336 diff = s->clkm.arm_idlect1 ^ value;
2337 s->clkm.arm_idlect1 = value & 0x0fff;
2338 omap_clkm_idlect1_update(s, diff, value);
2339 return;
2340
2341 case 0x08: /* ARM_IDLECT2 */
2342 diff = s->clkm.arm_idlect2 ^ value;
2343 s->clkm.arm_idlect2 = value & 0x07ff;
2344 omap_clkm_idlect2_update(s, diff, value);
2345 return;
2346
2347 case 0x0c: /* ARM_EWUPCT */
2348 diff = s->clkm.arm_ewupct ^ value;
2349 s->clkm.arm_ewupct = value & 0x003f;
2350 return;
2351
2352 case 0x10: /* ARM_RSTCT1 */
2353 diff = s->clkm.arm_rstct1 ^ value;
2354 s->clkm.arm_rstct1 = value & 0x0007;
2355 if (value & 9) {
2356 qemu_system_reset_request();
2357 s->clkm.cold_start = 0xa;
2358 }
2359 if (diff & ~value & 4) { /* DSP_RST */
2360 omap_mpui_reset(s);
2361 omap_tipb_bridge_reset(s->private_tipb);
2362 omap_tipb_bridge_reset(s->public_tipb);
2363 }
2364 if (diff & 2) { /* DSP_EN */
2365 clk = omap_findclk(s, "dsp_ck");
2366 omap_clk_canidle(clk, (~value >> 1) & 1);
2367 }
2368 return;
2369
2370 case 0x14: /* ARM_RSTCT2 */
2371 s->clkm.arm_rstct2 = value & 0x0001;
2372 return;
2373
2374 case 0x18: /* ARM_SYSST */
2375 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
2376 s->clkm.clocking_scheme = (value >> 11) & 7;
2377 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
2378 clkschemename[s->clkm.clocking_scheme]);
2379 }
2380 s->clkm.cold_start &= value & 0x3f;
2381 return;
2382
2383 case 0x1c: /* ARM_CKOUT1 */
2384 diff = s->clkm.arm_ckout1 ^ value;
2385 s->clkm.arm_ckout1 = value & 0x003f;
2386 omap_clkm_ckout1_update(s, diff, value);
2387 return;
2388
2389 case 0x20: /* ARM_CKOUT2 */
2390 default:
2391 OMAP_BAD_REG(addr);
2392 }
2393 }
2394
2395 static CPUReadMemoryFunc *omap_clkm_readfn[] = {
2396 omap_badwidth_read16,
2397 omap_clkm_read,
2398 omap_badwidth_read16,
2399 };
2400
2401 static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
2402 omap_badwidth_write16,
2403 omap_clkm_write,
2404 omap_badwidth_write16,
2405 };
2406
2407 static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
2408 {
2409 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2410 int offset = addr - s->clkm.dsp_base;
2411
2412 switch (offset) {
2413 case 0x04: /* DSP_IDLECT1 */
2414 return s->clkm.dsp_idlect1;
2415
2416 case 0x08: /* DSP_IDLECT2 */
2417 return s->clkm.dsp_idlect2;
2418
2419 case 0x14: /* DSP_RSTCT2 */
2420 return s->clkm.dsp_rstct2;
2421
2422 case 0x18: /* DSP_SYSST */
2423 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
2424 (s->env->halted << 6); /* Quite useless... */
2425 }
2426
2427 OMAP_BAD_REG(addr);
2428 return 0;
2429 }
2430
2431 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
2432 uint16_t diff, uint16_t value)
2433 {
2434 omap_clk clk;
2435
2436 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
2437 }
2438
2439 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
2440 uint16_t diff, uint16_t value)
2441 {
2442 omap_clk clk;
2443
2444 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
2445 }
2446
2447 static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
2448 uint32_t value)
2449 {
2450 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2451 int offset = addr - s->clkm.dsp_base;
2452 uint16_t diff;
2453
2454 switch (offset) {
2455 case 0x04: /* DSP_IDLECT1 */
2456 diff = s->clkm.dsp_idlect1 ^ value;
2457 s->clkm.dsp_idlect1 = value & 0x01f7;
2458 omap_clkdsp_idlect1_update(s, diff, value);
2459 break;
2460
2461 case 0x08: /* DSP_IDLECT2 */
2462 s->clkm.dsp_idlect2 = value & 0x0037;
2463 diff = s->clkm.dsp_idlect1 ^ value;
2464 omap_clkdsp_idlect2_update(s, diff, value);
2465 break;
2466
2467 case 0x14: /* DSP_RSTCT2 */
2468 s->clkm.dsp_rstct2 = value & 0x0001;
2469 break;
2470
2471 case 0x18: /* DSP_SYSST */
2472 s->clkm.cold_start &= value & 0x3f;
2473 break;
2474
2475 default:
2476 OMAP_BAD_REG(addr);
2477 }
2478 }
2479
2480 static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
2481 omap_badwidth_read16,
2482 omap_clkdsp_read,
2483 omap_badwidth_read16,
2484 };
2485
2486 static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
2487 omap_badwidth_write16,
2488 omap_clkdsp_write,
2489 omap_badwidth_write16,
2490 };
2491
2492 static void omap_clkm_reset(struct omap_mpu_state_s *s)
2493 {
2494 if (s->wdt && s->wdt->reset)
2495 s->clkm.cold_start = 0x6;
2496 s->clkm.clocking_scheme = 0;
2497 omap_clkm_ckctl_update(s, ~0, 0x3000);
2498 s->clkm.arm_ckctl = 0x3000;
2499 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
2500 s->clkm.arm_idlect1 = 0x0400;
2501 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
2502 s->clkm.arm_idlect2 = 0x0100;
2503 s->clkm.arm_ewupct = 0x003f;
2504 s->clkm.arm_rstct1 = 0x0000;
2505 s->clkm.arm_rstct2 = 0x0000;
2506 s->clkm.arm_ckout1 = 0x0015;
2507 s->clkm.dpll1_mode = 0x2002;
2508 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
2509 s->clkm.dsp_idlect1 = 0x0040;
2510 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
2511 s->clkm.dsp_idlect2 = 0x0000;
2512 s->clkm.dsp_rstct2 = 0x0000;
2513 }
2514
2515 static void omap_clkm_init(target_phys_addr_t mpu_base,
2516 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
2517 {
2518 int iomemtype[2] = {
2519 cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
2520 cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
2521 };
2522
2523 s->clkm.mpu_base = mpu_base;
2524 s->clkm.dsp_base = dsp_base;
2525 s->clkm.arm_idlect1 = 0x03ff;
2526 s->clkm.arm_idlect2 = 0x0100;
2527 s->clkm.dsp_idlect1 = 0x0002;
2528 omap_clkm_reset(s);
2529 s->clkm.cold_start = 0x3a;
2530
2531 cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]);
2532 cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]);
2533 }
2534
2535 /* MPU I/O */
2536 struct omap_mpuio_s {
2537 target_phys_addr_t base;
2538 qemu_irq irq;
2539 qemu_irq kbd_irq;
2540 qemu_irq *in;
2541 qemu_irq handler[16];
2542 qemu_irq wakeup;
2543
2544 uint16_t inputs;
2545 uint16_t outputs;
2546 uint16_t dir;
2547 uint16_t edge;
2548 uint16_t mask;
2549 uint16_t ints;
2550
2551 uint16_t debounce;
2552 uint16_t latch;
2553 uint8_t event;
2554
2555 uint8_t buttons[5];
2556 uint8_t row_latch;
2557 uint8_t cols;
2558 int kbd_mask;
2559 int clk;
2560 };
2561
2562 static void omap_mpuio_set(void *opaque, int line, int level)
2563 {
2564 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2565 uint16_t prev = s->inputs;
2566
2567 if (level)
2568 s->inputs |= 1 << line;
2569 else
2570 s->inputs &= ~(1 << line);
2571
2572 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
2573 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
2574 s->ints |= 1 << line;
2575 qemu_irq_raise(s->irq);
2576 /* TODO: wakeup */
2577 }
2578 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
2579 (s->event >> 1) == line) /* PIN_SELECT */
2580 s->latch = s->inputs;
2581 }
2582 }
2583
2584 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
2585 {
2586 int i;
2587 uint8_t *row, rows = 0, cols = ~s->cols;
2588
2589 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
2590 if (*row & cols)
2591 rows |= i;
2592
2593 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
2594 s->row_latch = ~rows;
2595 }
2596
2597 static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
2598 {
2599 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2600 int offset = addr & OMAP_MPUI_REG_MASK;
2601 uint16_t ret;
2602
2603 switch (offset) {
2604 case 0x00: /* INPUT_LATCH */
2605 return s->inputs;
2606
2607 case 0x04: /* OUTPUT_REG */
2608 return s->outputs;
2609
2610 case 0x08: /* IO_CNTL */
2611 return s->dir;
2612
2613 case 0x10: /* KBR_LATCH */
2614 return s->row_latch;
2615
2616 case 0x14: /* KBC_REG */
2617 return s->cols;
2618
2619 case 0x18: /* GPIO_EVENT_MODE_REG */
2620 return s->event;
2621
2622 case 0x1c: /* GPIO_INT_EDGE_REG */
2623 return s->edge;
2624
2625 case 0x20: /* KBD_INT */
2626 return (~s->row_latch & 0x1f) && !s->kbd_mask;
2627
2628 case 0x24: /* GPIO_INT */
2629 ret = s->ints;
2630 s->ints &= s->mask;
2631 if (ret)
2632 qemu_irq_lower(s->irq);
2633 return ret;
2634
2635 case 0x28: /* KBD_MASKIT */
2636 return s->kbd_mask;
2637
2638 case 0x2c: /* GPIO_MASKIT */
2639 return s->mask;
2640
2641 case 0x30: /* GPIO_DEBOUNCING_REG */
2642 return s->debounce;
2643
2644 case 0x34: /* GPIO_LATCH_REG */
2645 return s->latch;
2646 }
2647
2648 OMAP_BAD_REG(addr);
2649 return 0;
2650 }
2651
2652 static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
2653 uint32_t value)
2654 {
2655 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2656 int offset = addr & OMAP_MPUI_REG_MASK;
2657 uint16_t diff;
2658 int ln;
2659
2660 switch (offset) {
2661 case 0x04: /* OUTPUT_REG */
2662 diff = (s->outputs ^ value) & ~s->dir;
2663 s->outputs = value;
2664 while ((ln = ffs(diff))) {
2665 ln --;
2666 if (s->handler[ln])
2667 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2668 diff &= ~(1 << ln);
2669 }
2670 break;
2671
2672 case 0x08: /* IO_CNTL */
2673 diff = s->outputs & (s->dir ^ value);
2674 s->dir = value;
2675
2676 value = s->outputs & ~s->dir;
2677 while ((ln = ffs(diff))) {
2678 ln --;
2679 if (s->handler[ln])
2680 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2681 diff &= ~(1 << ln);
2682 }
2683 break;
2684
2685 case 0x14: /* KBC_REG */
2686 s->cols = value;
2687 omap_mpuio_kbd_update(s);
2688 break;
2689
2690 case 0x18: /* GPIO_EVENT_MODE_REG */
2691 s->event = value & 0x1f;
2692 break;
2693
2694 case 0x1c: /* GPIO_INT_EDGE_REG */
2695 s->edge = value;
2696 break;
2697
2698 case 0x28: /* KBD_MASKIT */
2699 s->kbd_mask = value & 1;
2700 omap_mpuio_kbd_update(s);
2701 break;
2702
2703 case 0x2c: /* GPIO_MASKIT */
2704 s->mask = value;
2705 break;
2706
2707 case 0x30: /* GPIO_DEBOUNCING_REG */
2708 s->debounce = value & 0x1ff;
2709 break;
2710
2711 case 0x00: /* INPUT_LATCH */
2712 case 0x10: /* KBR_LATCH */
2713 case 0x20: /* KBD_INT */
2714 case 0x24: /* GPIO_INT */
2715 case 0x34: /* GPIO_LATCH_REG */
2716 OMAP_RO_REG(addr);
2717 return;
2718
2719 default:
2720 OMAP_BAD_REG(addr);
2721 return;
2722 }
2723 }
2724
2725 static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
2726 omap_badwidth_read16,
2727 omap_mpuio_read,
2728 omap_badwidth_read16,
2729 };
2730
2731 static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
2732 omap_badwidth_write16,
2733 omap_mpuio_write,
2734 omap_badwidth_write16,
2735 };
2736
2737 static void omap_mpuio_reset(struct omap_mpuio_s *s)
2738 {
2739 s->inputs = 0;
2740 s->outputs = 0;
2741 s->dir = ~0;
2742 s->event = 0;
2743 s->edge = 0;
2744 s->kbd_mask = 0;
2745 s->mask = 0;
2746 s->debounce = 0;
2747 s->latch = 0;
2748 s->ints = 0;
2749 s->row_latch = 0x1f;
2750 s->clk = 1;
2751 }
2752
2753 static void omap_mpuio_onoff(void *opaque, int line, int on)
2754 {
2755 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2756
2757 s->clk = on;
2758 if (on)
2759 omap_mpuio_kbd_update(s);
2760 }
2761
2762 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
2763 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2764 omap_clk clk)
2765 {
2766 int iomemtype;
2767 struct omap_mpuio_s *s = (struct omap_mpuio_s *)
2768 qemu_mallocz(sizeof(struct omap_mpuio_s));
2769
2770 s->base = base;
2771 s->irq = gpio_int;
2772 s->kbd_irq = kbd_int;
2773 s->wakeup = wakeup;
2774 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2775 omap_mpuio_reset(s);
2776
2777 iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
2778 omap_mpuio_writefn, s);
2779 cpu_register_physical_memory(s->base, 0x800, iomemtype);
2780
2781 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
2782
2783 return s;
2784 }
2785
2786 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2787 {
2788 return s->in;
2789 }
2790
2791 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2792 {
2793 if (line >= 16 || line < 0)
2794 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
2795 s->handler[line] = handler;
2796 }
2797
2798 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2799 {
2800 if (row >= 5 || row < 0)
2801 cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
2802 __FUNCTION__, col, row);
2803
2804 if (down)
2805 s->buttons[row] |= 1 << col;
2806 else
2807 s->buttons[row] &= ~(1 << col);
2808
2809 omap_mpuio_kbd_update(s);
2810 }
2811
2812 /* General-Purpose I/O */
2813 struct omap_gpio_s {
2814 target_phys_addr_t base;
2815 qemu_irq irq;
2816 qemu_irq *in;
2817 qemu_irq handler[16];
2818
2819 uint16_t inputs;
2820 uint16_t outputs;
2821 uint16_t dir;
2822 uint16_t edge;
2823 uint16_t mask;
2824 uint16_t ints;
2825 uint16_t pins;
2826 };
2827
2828 static void omap_gpio_set(void *opaque, int line, int level)
2829 {
2830 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
2831 uint16_t prev = s->inputs;
2832
2833 if (level)
2834 s->inputs |= 1 << line;
2835 else
2836 s->inputs &= ~(1 << line);
2837
2838 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
2839 (1 << line) & s->dir & ~s->mask) {
2840 s->ints |= 1 << line;
2841 qemu_irq_raise(s->irq);
2842 }
2843 }
2844
2845 static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
2846 {
2847 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
2848 int offset = addr & OMAP_MPUI_REG_MASK;
2849
2850 switch (offset) {
2851 case 0x00: /* DATA_INPUT */
2852 return s->inputs & s->pins;
2853
2854 case 0x04: /* DATA_OUTPUT */
2855 return s->outputs;
2856
2857 case 0x08: /* DIRECTION_CONTROL */
2858 return s->dir;
2859
2860 case 0x0c: /* INTERRUPT_CONTROL */
2861 return s->edge;
2862
2863 case 0x10: /* INTERRUPT_MASK */
2864 return s->mask;
2865
2866 case 0x14: /* INTERRUPT_STATUS */
2867 return s->ints;
2868
2869 case 0x18: /* PIN_CONTROL (not in OMAP310) */
2870 OMAP_BAD_REG(addr);
2871 return s->pins;
2872 }
2873
2874 OMAP_BAD_REG(addr);
2875 return 0;
2876 }
2877
2878 static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
2879 uint32_t value)
2880 {
2881 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
2882 int offset = addr & OMAP_MPUI_REG_MASK;
2883 uint16_t diff;
2884 int ln;
2885
2886 switch (offset) {
2887 case 0x00: /* DATA_INPUT */
2888 OMAP_RO_REG(addr);
2889 return;
2890
2891 case 0x04: /* DATA_OUTPUT */
2892 diff = (s->outputs ^ value) & ~s->dir;
2893 s->outputs = value;
2894 while ((ln = ffs(diff))) {
2895 ln --;
2896 if (s->handler[ln])
2897 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2898 diff &= ~(1 << ln);
2899 }
2900 break;
2901
2902 case 0x08: /* DIRECTION_CONTROL */
2903 diff = s->outputs & (s->dir ^ value);
2904 s->dir = value;
2905
2906 value = s->outputs & ~s->dir;
2907 while ((ln = ffs(diff))) {
2908 ln --;
2909 if (s->handler[ln])
2910 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2911 diff &= ~(1 << ln);
2912 }
2913 break;
2914
2915 case 0x0c: /* INTERRUPT_CONTROL */
2916 s->edge = value;
2917 break;
2918
2919 case 0x10: /* INTERRUPT_MASK */
2920 s->mask = value;
2921 break;
2922
2923 case 0x14: /* INTERRUPT_STATUS */
2924 s->ints &= ~value;
2925 if (!s->ints)
2926 qemu_irq_lower(s->irq);
2927 break;
2928
2929 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
2930 OMAP_BAD_REG(addr);
2931 s->pins = value;
2932 break;
2933
2934 default:
2935 OMAP_BAD_REG(addr);
2936 return;
2937 }
2938 }
2939
2940 /* *Some* sources say the memory region is 32-bit. */
2941 static CPUReadMemoryFunc *omap_gpio_readfn[] = {
2942 omap_badwidth_read16,
2943 omap_gpio_read,
2944 omap_badwidth_read16,
2945 };
2946
2947 static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
2948 omap_badwidth_write16,
2949 omap_gpio_write,
2950 omap_badwidth_write16,
2951 };
2952
2953 static void omap_gpio_reset(struct omap_gpio_s *s)
2954 {
2955 s->inputs = 0;
2956 s->outputs = ~0;
2957 s->dir = ~0;
2958 s->edge = ~0;
2959 s->mask = ~0;
2960 s->ints = 0;
2961 s->pins = ~0;
2962 }
2963
2964 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
2965 qemu_irq irq, omap_clk clk)
2966 {
2967 int iomemtype;
2968 struct omap_gpio_s *s = (struct omap_gpio_s *)
2969 qemu_mallocz(sizeof(struct omap_gpio_s));
2970
2971 s->base = base;
2972 s->irq = irq;
2973 s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
2974 omap_gpio_reset(s);
2975
2976 iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
2977 omap_gpio_writefn, s);
2978 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
2979
2980 return s;
2981 }
2982
2983 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
2984 {
2985 return s->in;
2986 }
2987
2988 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler)
2989 {
2990 if (line >= 16 || line < 0)
2991 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
2992 s->handler[line] = handler;
2993 }
2994
2995 /* MicroWire Interface */
2996 struct omap_uwire_s {
2997 target_phys_addr_t base;
2998 qemu_irq txirq;
2999 qemu_irq rxirq;
3000 qemu_irq txdrq;
3001
3002 uint16_t txbuf;
3003 uint16_t rxbuf;
3004 uint16_t control;
3005 uint16_t setup[5];
3006
3007 struct uwire_slave_s *chip[4];
3008 };
3009
3010 static void omap_uwire_transfer_start(struct omap_uwire_s *s)
3011 {
3012 int chipselect = (s->control >> 10) & 3; /* INDEX */
3013 struct uwire_slave_s *slave = s->chip[chipselect];
3014
3015 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
3016 if (s->control & (1 << 12)) /* CS_CMD */
3017 if (slave && slave->send)
3018 slave->send(slave->opaque,
3019 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
3020 s->control &= ~(1 << 14); /* CSRB */
3021 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3022 * a DRQ. When is the level IRQ supposed to be reset? */
3023 }
3024
3025 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
3026 if (s->control & (1 << 12)) /* CS_CMD */
3027 if (slave && slave->receive)
3028 s->rxbuf = slave->receive(slave->opaque);
3029 s->control |= 1 << 15; /* RDRB */
3030 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3031 * a DRQ. When is the level IRQ supposed to be reset? */
3032 }
3033 }
3034
3035 static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
3036 {
3037 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
3038 int offset = addr & OMAP_MPUI_REG_MASK;
3039
3040 switch (offset) {
3041 case 0x00: /* RDR */
3042 s->control &= ~(1 << 15); /* RDRB */
3043 return s->rxbuf;
3044
3045 case 0x04: /* CSR */
3046 return s->control;
3047
3048 case 0x08: /* SR1 */
3049 return s->setup[0];
3050 case 0x0c: /* SR2 */
3051 return s->setup[1];
3052 case 0x10: /* SR3 */
3053 return s->setup[2];
3054 case 0x14: /* SR4 */
3055 return s->setup[3];
3056 case 0x18: /* SR5 */
3057 return s->setup[4];
3058 }
3059
3060 OMAP_BAD_REG(addr);
3061 return 0;
3062 }
3063
3064 static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
3065 uint32_t value)
3066 {
3067 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
3068 int offset = addr & OMAP_MPUI_REG_MASK;
3069
3070 switch (offset) {
3071 case 0x00: /* TDR */
3072 s->txbuf = value; /* TD */
3073 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
3074 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
3075 (s->control & (1 << 12)))) { /* CS_CMD */
3076 s->control |= 1 << 14; /* CSRB */
3077 omap_uwire_transfer_start(s);
3078 }
3079 break;
3080
3081 case 0x04: /* CSR */
3082 s->control = value & 0x1fff;
3083 if (value & (1 << 13)) /* START */
3084 omap_uwire_transfer_start(s);
3085 break;
3086
3087 case 0x08: /* SR1 */
3088 s->setup[0] = value & 0x003f;
3089 break;
3090
3091 case 0x0c: /* SR2 */
3092 s->setup[1] = value & 0x0fc0;
3093 break;
3094
3095 case 0x10: /* SR3 */
3096 s->setup[2] = value & 0x0003;
3097 break;
3098
3099 case 0x14: /* SR4 */
3100 s->setup[3] = value & 0x0001;
3101 break;
3102
3103 case 0x18: /* SR5 */
3104 s->setup[4] = value & 0x000f;
3105 break;
3106
3107 default:
3108 OMAP_BAD_REG(addr);
3109 return;
3110 }
3111 }
3112
3113 static CPUReadMemoryFunc *omap_uwire_readfn[] = {
3114 omap_badwidth_read16,
3115 omap_uwire_read,
3116 omap_badwidth_read16,
3117 };
3118
3119 static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
3120 omap_badwidth_write16,
3121 omap_uwire_write,
3122 omap_badwidth_write16,
3123 };
3124
3125 static void omap_uwire_reset(struct omap_uwire_s *s)
3126 {
3127 s->control = 0;
3128 s->setup[0] = 0;
3129 s->setup[1] = 0;
3130 s->setup[2] = 0;
3131 s->setup[3] = 0;
3132 s->setup[4] = 0;
3133 }
3134
3135 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
3136 qemu_irq *irq, qemu_irq dma, omap_clk clk)
3137 {
3138 int iomemtype;
3139 struct omap_uwire_s *s = (struct omap_uwire_s *)
3140 qemu_mallocz(sizeof(struct omap_uwire_s));
3141
3142 s->base = base;
3143 s->txirq = irq[0];
3144 s->rxirq = irq[1];
3145 s->txdrq = dma;
3146 omap_uwire_reset(s);
3147
3148 iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
3149 omap_uwire_writefn, s);
3150 cpu_register_physical_memory(s->base, 0x800, iomemtype);
3151
3152 return s;
3153 }
3154
3155 void omap_uwire_attach(struct omap_uwire_s *s,
3156 struct uwire_slave_s *slave, int chipselect)
3157 {
3158 if (chipselect < 0 || chipselect > 3) {
3159 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
3160 exit(-1);
3161 }
3162
3163 s->chip[chipselect] = slave;
3164 }
3165
3166 /* Pseudonoise Pulse-Width Light Modulator */
3167 static void omap_pwl_update(struct omap_mpu_state_s *s)
3168 {
3169 int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
3170
3171 if (output != s->pwl.output) {
3172 s->pwl.output = output;
3173 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
3174 }
3175 }
3176
3177 static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
3178 {
3179 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3180 int offset = addr & OMAP_MPUI_REG_MASK;
3181
3182 switch (offset) {
3183 case 0x00: /* PWL_LEVEL */
3184 return s->pwl.level;
3185 case 0x04: /* PWL_CTRL */
3186 return s->pwl.enable;
3187 }
3188 OMAP_BAD_REG(addr);
3189 return 0;
3190 }
3191
3192 static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
3193 uint32_t value)
3194 {
3195 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3196 int offset = addr & OMAP_MPUI_REG_MASK;
3197
3198 switch (offset) {
3199 case 0x00: /* PWL_LEVEL */
3200 s->pwl.level = value;
3201 omap_pwl_update(s);
3202 break;
3203 case 0x04: /* PWL_CTRL */
3204 s->pwl.enable = value & 1;
3205 omap_pwl_update(s);
3206 break;
3207 default:
3208 OMAP_BAD_REG(addr);
3209 return;
3210 }
3211 }
3212
3213 static CPUReadMemoryFunc *omap_pwl_readfn[] = {
3214 omap_pwl_read,
3215 omap_badwidth_read8,
3216 omap_badwidth_read8,
3217 };
3218
3219 static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
3220 omap_pwl_write,
3221 omap_badwidth_write8,
3222 omap_badwidth_write8,
3223 };
3224
3225 static void omap_pwl_reset(struct omap_mpu_state_s *s)
3226 {
3227 s->pwl.output = 0;
3228 s->pwl.level = 0;
3229 s->pwl.enable = 0;
3230 s->pwl.clk = 1;
3231 omap_pwl_update(s);
3232 }
3233
3234 static void omap_pwl_clk_update(void *opaque, int line, int on)
3235 {
3236 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3237
3238 s->pwl.clk = on;
3239 omap_pwl_update(s);
3240 }
3241
3242 static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
3243 omap_clk clk)
3244 {
3245 int iomemtype;
3246
3247 omap_pwl_reset(s);
3248
3249 iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
3250 omap_pwl_writefn, s);
3251 cpu_register_physical_memory(base, 0x800, iomemtype);
3252
3253 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
3254 }
3255
3256 /* Pulse-Width Tone module */
3257 static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
3258 {
3259 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3260 int offset = addr & OMAP_MPUI_REG_MASK;
3261
3262 switch (offset) {
3263 case 0x00: /* FRC */
3264 return s->pwt.frc;
3265 case 0x04: /* VCR */
3266 return s->pwt.vrc;
3267 case 0x08: /* GCR */
3268 return s->pwt.gcr;
3269 }
3270 OMAP_BAD_REG(addr);
3271 return 0;
3272 }
3273
3274 static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
3275 uint32_t value)
3276 {
3277 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3278 int offset = addr & OMAP_MPUI_REG_MASK;
3279
3280 switch (offset) {
3281 case 0x00: /* FRC */
3282 s->pwt.frc = value & 0x3f;
3283 break;
3284 case 0x04: /* VRC */
3285 if ((value ^ s->pwt.vrc) & 1) {
3286 if (value & 1)
3287 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
3288 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
3289 ((omap_clk_getrate(s->pwt.clk) >> 3) /
3290 /* Pre-multiplexer divider */
3291 ((s->pwt.gcr & 2) ? 1 : 154) /
3292 /* Octave multiplexer */
3293 (2 << (value & 3)) *
3294 /* 101/107 divider */
3295 ((value & (1 << 2)) ? 101 : 107) *
3296 /* 49/55 divider */
3297 ((value & (1 << 3)) ? 49 : 55) *
3298 /* 50/63 divider */
3299 ((value & (1 << 4)) ? 50 : 63) *
3300 /* 80/127 divider */
3301 ((value & (1 << 5)) ? 80 : 127) /
3302 (107 * 55 * 63 * 127)));
3303 else
3304 printf("%s: silence!\n", __FUNCTION__);
3305 }
3306 s->pwt.vrc = value & 0x7f;
3307 break;
3308 case 0x08: /* GCR */
3309 s->pwt.gcr = value & 3;
3310 break;
3311 default:
3312 OMAP_BAD_REG(addr);
3313 return;
3314 }
3315 }
3316
3317 static CPUReadMemoryFunc *omap_pwt_readfn[] = {
3318 omap_pwt_read,
3319 omap_badwidth_read8,
3320 omap_badwidth_read8,
3321 };
3322
3323 static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
3324 omap_pwt_write,
3325 omap_badwidth_write8,
3326 omap_badwidth_write8,
3327 };
3328
3329 static void omap_pwt_reset(struct omap_mpu_state_s *s)
3330 {
3331 s->pwt.frc = 0;
3332 s->pwt.vrc = 0;
3333 s->pwt.gcr = 0;
3334 }
3335
3336 static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
3337 omap_clk clk)
3338 {
3339 int iomemtype;
3340
3341 s->pwt.clk = clk;
3342 omap_pwt_reset(s);
3343
3344 iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
3345 omap_pwt_writefn, s);
3346 cpu_register_physical_memory(base, 0x800, iomemtype);
3347 }
3348
3349 /* Real-time Clock module */
3350 struct omap_rtc_s {
3351 target_phys_addr_t base;
3352 qemu_irq irq;
3353 qemu_irq alarm;
3354 QEMUTimer *clk;
3355
3356 uint8_t interrupts;
3357 uint8_t status;
3358 int16_t comp_reg;
3359 int running;
3360 int pm_am;
3361 int auto_comp;
3362 int round;
3363 struct tm alarm_tm;
3364 time_t alarm_ti;
3365
3366 struct tm current_tm;
3367 time_t ti;
3368 uint64_t tick;
3369 };
3370
3371 static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
3372 {
3373 /* s->alarm is level-triggered */
3374 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
3375 }
3376
3377 static void omap_rtc_alarm_update(struct omap_rtc_s *s)
3378 {
3379 s->alarm_ti = mktime(&s->alarm_tm);
3380 if (s->alarm_ti == -1)
3381 printf("%s: conversion failed\n", __FUNCTION__);
3382 }
3383
3384 static inline uint8_t omap_rtc_bcd(int num)
3385 {
3386 return ((num / 10) << 4) | (num % 10);
3387 }
3388
3389 static inline int omap_rtc_bin(uint8_t num)
3390 {
3391 return (num & 15) + 10 * (num >> 4);
3392 }
3393
3394 static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
3395 {
3396 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
3397 int offset = addr & OMAP_MPUI_REG_MASK;
3398 uint8_t i;
3399
3400 switch (offset) {
3401 case 0x00: /* SECONDS_REG */
3402 return omap_rtc_bcd(s->current_tm.tm_sec);
3403
3404 case 0x04: /* MINUTES_REG */
3405 return omap_rtc_bcd(s->current_tm.tm_min);
3406
3407 case 0x08: /* HOURS_REG */
3408 if (s->pm_am)
3409 return ((s->current_tm.tm_hour > 11) << 7) |
3410 omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
3411 else
3412 return omap_rtc_bcd(s->current_tm.tm_hour);
3413
3414 case 0x0c: /* DAYS_REG */
3415 return omap_rtc_bcd(s->current_tm.tm_mday);
3416
3417 case 0x10: /* MONTHS_REG */
3418 return omap_rtc_bcd(s->current_tm.tm_mon + 1);
3419
3420 case 0x14: /* YEARS_REG */
3421 return omap_rtc_bcd(s->current_tm.tm_year % 100);
3422
3423 case 0x18: /* WEEK_REG */
3424 return s->current_tm.tm_wday;
3425
3426 case 0x20: /* ALARM_SECONDS_REG */
3427 return omap_rtc_bcd(s->alarm_tm.tm_sec);
3428
3429 case 0x24: /* ALARM_MINUTES_REG */
3430 return omap_rtc_bcd(s->alarm_tm.tm_min);
3431
3432 case 0x28: /* ALARM_HOURS_REG */
3433 if (s->pm_am)
3434 return ((s->alarm_tm.tm_hour > 11) << 7) |
3435 omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
3436 else
3437 return omap_rtc_bcd(s->alarm_tm.tm_hour);
3438
3439 case 0x2c: /* ALARM_DAYS_REG */
3440 return omap_rtc_bcd(s->alarm_tm.tm_mday);
3441
3442 case 0x30: /* ALARM_MONTHS_REG */
3443 return omap_rtc_bcd(s->alarm_tm.tm_mon + 1);
3444
3445 case 0x34: /* ALARM_YEARS_REG */
3446 return omap_rtc_bcd(s->alarm_tm.tm_year % 100);
3447
3448 case 0x40: /* RTC_CTRL_REG */
3449 return (s->pm_am << 3) | (s->auto_comp << 2) |
3450 (s->round << 1) | s->running;
3451
3452 case 0x44: /* RTC_STATUS_REG */
3453 i = s->status;
3454 s->status &= ~0x3d;
3455 return i;
3456
3457 case 0x48: /* RTC_INTERRUPTS_REG */
3458 return s->interrupts;
3459
3460 case 0x4c: /* RTC_COMP_LSB_REG */
3461 return ((uint16_t) s->comp_reg) & 0xff;
3462
3463 case 0x50: /* RTC_COMP_MSB_REG */
3464 return ((uint16_t) s->comp_reg) >> 8;
3465 }
3466
3467 OMAP_BAD_REG(addr);
3468 return 0;
3469 }
3470
3471 static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
3472 uint32_t value)
3473 {
3474 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
3475 int offset = addr & OMAP_MPUI_REG_MASK;
3476 struct tm new_tm;
3477 time_t ti[2];
3478
3479 switch (offset) {
3480 case 0x00: /* SECONDS_REG */
3481 #if ALMDEBUG
3482 printf("RTC SEC_REG <-- %02x\n", value);
3483 #endif
3484 s->ti -= s->current_tm.tm_sec;
3485 s->ti += omap_rtc_bin(value);
3486 return;
3487
3488 case 0x04: /* MINUTES_REG */
3489 #if ALMDEBUG
3490 printf("RTC MIN_REG <-- %02x\n", value);
3491 #endif
3492 s->ti -= s->current_tm.tm_min * 60;
3493 s->ti += omap_rtc_bin(value) * 60;
3494 return;
3495
3496 case 0x08: /* HOURS_REG */
3497 #if ALMDEBUG
3498 printf("RTC HRS_REG <-- %02x\n", value);
3499 #endif
3500 s->ti -= s->current_tm.tm_hour * 3600;
3501 if (s->pm_am) {
3502 s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600;
3503 s->ti += ((value >> 7) & 1) * 43200;
3504 } else
3505 s->ti += omap_rtc_bin(value & 0x3f) * 3600;
3506 return;
3507
3508 case 0x0c: /* DAYS_REG */
3509 #if ALMDEBUG
3510 printf("RTC DAY_REG <-- %02x\n", value);
3511 #endif
3512 s->ti -= s->current_tm.tm_mday * 86400;
3513 s->ti += omap_rtc_bin(value) * 86400;
3514 return;
3515
3516 case 0x10: /* MONTHS_REG */
3517 #if ALMDEBUG
3518 printf("RTC MTH_REG <-- %02x\n", value);
3519 #endif
3520 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
3521 new_tm.tm_mon = omap_rtc_bin(value);
3522 ti[0] = mktime(&s->current_tm);
3523 ti[1] = mktime(&new_tm);
3524
3525 if (ti[0] != -1 && ti[1] != -1) {
3526 s->ti -= ti[0];
3527 s->ti += ti[1];
3528 } else {
3529 /* A less accurate version */
3530 s->ti -= s->current_tm.tm_mon * 2592000;
3531 s->ti += omap_rtc_bin(value) * 2592000;
3532 }
3533 return;
3534
3535 case 0x14: /* YEARS_REG */
3536 #if ALMDEBUG
3537 printf("RTC YRS_REG <-- %02x\n", value);
3538 #endif
3539 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
3540 new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100);
3541 ti[0] = mktime(&s->current_tm);
3542 ti[1] = mktime(&new_tm);
3543
3544 if (ti[0] != -1 && ti[1] != -1) {
3545 s->ti -= ti[0];
3546 s->ti += ti[1];
3547 } else {
3548 /* A less accurate version */
3549 s->ti -= (s->current_tm.tm_year % 100) * 31536000;
3550 s->ti += omap_rtc_bin(value) * 31536000;
3551 }
3552 return;
3553
3554 case 0x18: /* WEEK_REG */
3555 return; /* Ignored */
3556
3557 case 0x20: /* ALARM_SECONDS_REG */
3558 #if ALMDEBUG
3559 printf("ALM SEC_REG <-- %02x\n", value);
3560 #endif
3561 s->alarm_tm.tm_sec = omap_rtc_bin(value);
3562 omap_rtc_alarm_update(s);
3563 return;
3564
3565 case 0x24: /* ALARM_MINUTES_REG */
3566 #if ALMDEBUG
3567 printf("ALM MIN_REG <-- %02x\n", value);
3568 #endif
3569 s->alarm_tm.tm_min = omap_rtc_bin(value);
3570 omap_rtc_alarm_update(s);
3571 return;
3572
3573 case 0x28: /* ALARM_HOURS_REG */
3574 #if ALMDEBUG
3575 printf("ALM HRS_REG <-- %02x\n", value);
3576 #endif
3577 if (s->pm_am)
3578 s->alarm_tm.tm_hour =
3579 ((omap_rtc_bin(value & 0x3f)) % 12) +
3580 ((value >> 7) & 1) * 12;
3581 else
3582 s->alarm_tm.tm_hour = omap_rtc_bin(value);
3583 omap_rtc_alarm_update(s);
3584 return;
3585
3586 case 0x2c: /* ALARM_DAYS_REG */
3587 #if ALMDEBUG
3588 printf("ALM DAY_REG <-- %02x\n", value);
3589 #endif
3590 s->alarm_tm.tm_mday = omap_rtc_bin(value);
3591 omap_rtc_alarm_update(s);
3592 return;
3593
3594 case 0x30: /* ALARM_MONTHS_REG */
3595 #if ALMDEBUG
3596 printf("ALM MON_REG <-- %02x\n", value);
3597 #endif
3598 s->alarm_tm.tm_mon = omap_rtc_bin(value);
3599 omap_rtc_alarm_update(s);
3600 return;
3601
3602 case 0x34: /* ALARM_YEARS_REG */
3603 #if ALMDEBUG
3604 printf("ALM YRS_REG <-- %02x\n", value);
3605 #endif
3606 s->alarm_tm.tm_year = omap_rtc_bin(value);
3607 omap_rtc_alarm_update(s);
3608 return;
3609
3610 case 0x40: /* RTC_CTRL_REG */
3611 #if ALMDEBUG
3612 printf("RTC CONTROL <-- %02x\n", value);
3613 #endif
3614 s->pm_am = (value >> 3) & 1;
3615 s->auto_comp = (value >> 2) & 1;
3616 s->round = (value >> 1) & 1;
3617 s->running = value & 1;
3618 s->status &= 0xfd;
3619 s->status |= s->running << 1;
3620 return;
3621
3622 case 0x44: /* RTC_STATUS_REG */
3623 #if ALMDEBUG
3624 printf("RTC STATUSL <-- %02x\n", value);
3625 #endif
3626 s->status &= ~((value & 0xc0) ^ 0x80);
3627 omap_rtc_interrupts_update(s);
3628 return;
3629
3630 case 0x48: /* RTC_INTERRUPTS_REG */
3631 #if ALMDEBUG
3632 printf("RTC INTRS <-- %02x\n", value);
3633 #endif
3634 s->interrupts = value;
3635 return;
3636
3637 case 0x4c: /* RTC_COMP_LSB_REG */
3638 #if ALMDEBUG
3639 printf("RTC COMPLSB <-- %02x\n", value);
3640 #endif
3641 s->comp_reg &= 0xff00;
3642 s->comp_reg |= 0x00ff & value;
3643 return;
3644
3645 case 0x50: /* RTC_COMP_MSB_REG */
3646 #if ALMDEBUG
3647 printf("RTC COMPMSB <-- %02x\n", value);
3648 #endif
3649 s->comp_reg &= 0x00ff;
3650 s->comp_reg |= 0xff00 & (value << 8);
3651 return;
3652
3653 default:
3654 OMAP_BAD_REG(addr);
3655 return;
3656 }
3657 }
3658
3659 static CPUReadMemoryFunc *omap_rtc_readfn[] = {
3660 omap_rtc_read,
3661 omap_badwidth_read8,
3662 omap_badwidth_read8,
3663 };
3664
3665 static CPUWriteMemoryFunc *omap_rtc_writefn[] = {
3666 omap_rtc_write,
3667 omap_badwidth_write8,
3668 omap_badwidth_write8,
3669 };
3670
3671 static void omap_rtc_tick(void *opaque)
3672 {
3673 struct omap_rtc_s *s = opaque;
3674
3675 if (s->round) {
3676 /* Round to nearest full minute. */
3677 if (s->current_tm.tm_sec < 30)
3678 s->ti -= s->current_tm.tm_sec;
3679 else
3680 s->ti += 60 - s->current_tm.tm_sec;
3681
3682 s->round = 0;
3683 }
3684
3685 memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
3686
3687 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
3688 s->status |= 0x40;
3689 omap_rtc_interrupts_update(s);
3690 }
3691
3692 if (s->interrupts & 0x04)
3693 switch (s->interrupts & 3) {
3694 case 0:
3695 s->status |= 0x04;
3696 qemu_irq_pulse(s->irq);
3697 break;
3698 case 1:
3699 if (s->current_tm.tm_sec)
3700 break;
3701 s->status |= 0x08;
3702 qemu_irq_pulse(s->irq);
3703 break;
3704 case 2:
3705 if (s->current_tm.tm_sec || s->current_tm.tm_min)
3706 break;
3707 s->status |= 0x10;
3708 qemu_irq_pulse(s->irq);
3709 break;
3710 case 3:
3711 if (s->current_tm.tm_sec ||
3712 s->current_tm.tm_min || s->current_tm.tm_hour)
3713 break;
3714 s->status |= 0x20;
3715 qemu_irq_pulse(s->irq);
3716 break;
3717 }
3718
3719 /* Move on */
3720 if (s->running)
3721 s->ti ++;
3722 s->tick += 1000;
3723
3724 /*
3725 * Every full hour add a rough approximation of the compensation
3726 * register to the 32kHz Timer (which drives the RTC) value.
3727 */
3728 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
3729 s->tick += s->comp_reg * 1000 / 32768;
3730
3731 qemu_mod_timer(s->clk, s->tick);
3732 }
3733
3734 static void omap_rtc_reset(struct omap_rtc_s *s)
3735 {
3736 struct tm tm;
3737
3738 s->interrupts = 0;
3739 s->comp_reg = 0;
3740 s->running = 0;
3741 s->pm_am = 0;
3742 s->auto_comp = 0;
3743 s->round = 0;
3744 s->tick = qemu_get_clock(rt_clock);
3745 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
3746 s->alarm_tm.tm_mday = 0x01;
3747 s->status = 1 << 7;
3748 qemu_get_timedate(&tm, 0);
3749 s->ti = mktime(&tm);
3750
3751 omap_rtc_alarm_update(s);
3752 omap_rtc_tick(s);
3753 }
3754
3755 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
3756 qemu_irq *irq, omap_clk clk)
3757 {
3758 int iomemtype;
3759 struct omap_rtc_s *s = (struct omap_rtc_s *)
3760 qemu_mallocz(sizeof(struct omap_rtc_s));
3761
3762 s->base = base;
3763 s->irq = irq[0];
3764 s->alarm = irq[1];
3765 s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s);
3766
3767 omap_rtc_reset(s);
3768
3769 iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
3770 omap_rtc_writefn, s);
3771 cpu_register_physical_memory(s->base, 0x800, iomemtype);
3772
3773 return s;
3774 }
3775
3776 /* Multi-channel Buffered Serial Port interfaces */
3777 struct omap_mcbsp_s {
3778 target_phys_addr_t base;
3779 qemu_irq txirq;
3780 qemu_irq rxirq;
3781 qemu_irq txdrq;
3782 qemu_irq rxdrq;
3783
3784 uint16_t spcr[2];
3785 uint16_t rcr[2];
3786 uint16_t xcr[2];
3787 uint16_t srgr[2];
3788 uint16_t mcr[2];
3789 uint16_t pcr;
3790 uint16_t rcer[8];
3791 uint16_t xcer[8];
3792 int tx_rate;
3793 int rx_rate;
3794 int tx_req;
3795 int rx_req;
3796
3797 struct i2s_codec_s *codec;
3798 QEMUTimer *source_timer;
3799 QEMUTimer *sink_timer;
3800 };
3801
3802 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
3803 {
3804 int irq;
3805
3806 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
3807 case 0:
3808 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
3809 break;
3810 case 3:
3811 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
3812 break;
3813 default:
3814 irq = 0;
3815 break;
3816 }
3817
3818 if (irq)
3819 qemu_irq_pulse(s->rxirq);
3820
3821 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
3822 case 0:
3823 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
3824 break;
3825 case 3:
3826 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
3827 break;
3828 default:
3829 irq = 0;
3830 break;
3831 }
3832
3833 if (irq)
3834 qemu_irq_pulse(s->txirq);
3835 }
3836
3837 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
3838 {
3839 if ((s->spcr[0] >> 1) & 1) /* RRDY */
3840 s->spcr[0] |= 1 << 2; /* RFULL */
3841 s->spcr[0] |= 1 << 1; /* RRDY */
3842 qemu_irq_raise(s->rxdrq);
3843 omap_mcbsp_intr_update(s);
3844 }
3845
3846 static void omap_mcbsp_source_tick(void *opaque)
3847 {
3848 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3849 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3850
3851 if (!s->rx_rate)
3852 return;
3853 if (s->rx_req)
3854 printf("%s: Rx FIFO overrun\n", __FUNCTION__);
3855
3856 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
3857
3858 omap_mcbsp_rx_newdata(s);
3859 qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
3860 }
3861
3862 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
3863 {
3864 if (!s->codec || !s->codec->rts)
3865 omap_mcbsp_source_tick(s);
3866 else if (s->codec->in.len) {
3867 s->rx_req = s->codec->in.len;
3868 omap_mcbsp_rx_newdata(s);
3869 }
3870 }
3871
3872 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
3873 {
3874 qemu_del_timer(s->source_timer);
3875 }
3876
3877 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
3878 {
3879 s->spcr[0] &= ~(1 << 1); /* RRDY */
3880 qemu_irq_lower(s->rxdrq);
3881 omap_mcbsp_intr_update(s);
3882 }
3883
3884 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
3885 {
3886 s->spcr[1] |= 1 << 1; /* XRDY */
3887 qemu_irq_raise(s->txdrq);
3888 omap_mcbsp_intr_update(s);
3889 }
3890
3891 static void omap_mcbsp_sink_tick(void *opaque)
3892 {
3893 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3894 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3895
3896 if (!s->tx_rate)
3897 return;
3898 if (s->tx_req)
3899 printf("%s: Tx FIFO underrun\n", __FUNCTION__);
3900
3901 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
3902
3903 omap_mcbsp_tx_newdata(s);
3904 qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
3905 }
3906
3907 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
3908 {
3909 if (!s->codec || !s->codec->cts)
3910 omap_mcbsp_sink_tick(s);
3911 else if (s->codec->out.size) {
3912 s->tx_req = s->codec->out.size;
3913 omap_mcbsp_tx_newdata(s);
3914 }
3915 }
3916
3917 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
3918 {
3919 s->spcr[1] &= ~(1 << 1); /* XRDY */
3920 qemu_irq_lower(s->txdrq);
3921 omap_mcbsp_intr_update(s);
3922 if (s->codec && s->codec->cts)
3923 s->codec->tx_swallow(s->codec->opaque);
3924 }
3925
3926 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3927 {
3928 s->tx_req = 0;
3929 omap_mcbsp_tx_done(s);
3930 qemu_del_timer(s->sink_timer);
3931 }
3932
3933 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3934 {
3935 int prev_rx_rate, prev_tx_rate;
3936 int rx_rate = 0, tx_rate = 0;
3937 int cpu_rate = 1500000; /* XXX */
3938
3939 /* TODO: check CLKSTP bit */
3940 if (s->spcr[1] & (1 << 6)) { /* GRST */
3941 if (s->spcr[0] & (1 << 0)) { /* RRST */
3942 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3943 (s->pcr & (1 << 8))) { /* CLKRM */
3944 if (~s->pcr & (1 << 7)) /* SCLKME */
3945 rx_rate = cpu_rate /
3946 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3947 } else
3948 if (s->codec)
3949 rx_rate = s->codec->rx_rate;
3950 }
3951
3952 if (s->spcr[1] & (1 << 0)) { /* XRST */
3953 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3954 (s->pcr & (1 << 9))) { /* CLKXM */
3955 if (~s->pcr & (1 << 7)) /* SCLKME */
3956 tx_rate = cpu_rate /
3957 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3958 } else
3959 if (s->codec)
3960 tx_rate = s->codec->tx_rate;
3961 }
3962 }
3963 prev_tx_rate = s->tx_rate;
3964 prev_rx_rate = s->rx_rate;
3965 s->tx_rate = tx_rate;
3966 s->rx_rate = rx_rate;
3967
3968 if (s->codec)
3969 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3970
3971 if (!prev_tx_rate && tx_rate)
3972 omap_mcbsp_tx_start(s);
3973 else if (s->tx_rate && !tx_rate)
3974 omap_mcbsp_tx_stop(s);
3975
3976 if (!prev_rx_rate && rx_rate)
3977 omap_mcbsp_rx_start(s);
3978 else if (prev_tx_rate && !tx_rate)
3979 omap_mcbsp_rx_stop(s);
3980 }
3981
3982 static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
3983 {
3984 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3985 int offset = addr & OMAP_MPUI_REG_MASK;
3986 uint16_t ret;
3987
3988 switch (offset) {
3989 case 0x00: /* DRR2 */
3990 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3991 return 0x0000;
3992 /* Fall through. */
3993 case 0x02: /* DRR1 */
3994 if (s->rx_req < 2) {
3995 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
3996 omap_mcbsp_rx_done(s);
3997 } else {
3998 s->tx_req -= 2;
3999 if (s->codec && s->codec->in.len >= 2) {
4000 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
4001 ret |= s->codec->in.fifo[s->codec->in.start ++];
4002 s->codec->in.len -= 2;
4003 } else
4004 ret = 0x0000;
4005 if (!s->tx_req)
4006 omap_mcbsp_rx_done(s);
4007 return ret;
4008 }
4009 return 0x0000;
4010
4011 case 0x04: /* DXR2 */
4012 case 0x06: /* DXR1 */
4013 return 0x0000;
4014
4015 case 0x08: /* SPCR2 */
4016 return s->spcr[1];
4017 case 0x0a: /* SPCR1 */
4018 return s->spcr[0];
4019 case 0x0c: /* RCR2 */
4020 return s->rcr[1];
4021 case 0x0e: /* RCR1 */
4022 return s->rcr[0];
4023 case 0x10: /* XCR2 */
4024 return s->xcr[1];
4025 case 0x12: /* XCR1 */
4026 return s->xcr[0];
4027 case 0x14: /* SRGR2 */
4028 return s->srgr[1];
4029 case 0x16: /* SRGR1 */
4030 return s->srgr[0];
4031 case 0x18: /* MCR2 */
4032 return s->mcr[1];
4033 case 0x1a: /* MCR1 */
4034 return s->mcr[0];
4035 case 0x1c: /* RCERA */
4036 return s->rcer[0];
4037 case 0x1e: /* RCERB */
4038 return s->rcer[1];
4039 case 0x20: /* XCERA */
4040 return s->xcer[0];
4041 case 0x22: /* XCERB */
4042 return s->xcer[1];
4043 case 0x24: /* PCR0 */
4044 return s->pcr;
4045 case 0x26: /* RCERC */
4046 return s->rcer[2];
4047 case 0x28: /* RCERD */
4048 return s->rcer[3];
4049 case 0x2a: /* XCERC */
4050 return s->xcer[2];
4051 case 0x2c: /* XCERD */
4052 return s->xcer[3];
4053 case 0x2e: /* RCERE */
4054 return s->rcer[4];
4055 case 0x30: /* RCERF */
4056 return s->rcer[5];
4057 case 0x32: /* XCERE */
4058 return s->xcer[4];
4059 case 0x34: /* XCERF */
4060 return s->xcer[5];
4061 case 0x36: /* RCERG */
4062 return s->rcer[6];
4063 case 0x38: /* RCERH */
4064 return s->rcer[7];
4065 case 0x3a: /* XCERG */
4066 return s->xcer[6];
4067 case 0x3c: /* XCERH */
4068 return s->xcer[7];
4069 }
4070
4071 OMAP_BAD_REG(addr);
4072 return 0;
4073 }
4074
4075 static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
4076 uint32_t value)
4077 {
4078 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4079 int offset = addr & OMAP_MPUI_REG_MASK;
4080
4081 switch (offset) {
4082 case 0x00: /* DRR2 */
4083 case 0x02: /* DRR1 */
4084 OMAP_RO_REG(addr);
4085 return;
4086
4087 case 0x04: /* DXR2 */
4088 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4089 return;
4090 /* Fall through. */
4091 case 0x06: /* DXR1 */
4092 if (s->tx_req > 1) {
4093 s->tx_req -= 2;
4094 if (s->codec && s->codec->cts) {
4095 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
4096 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
4097 }
4098 if (s->tx_req < 2)
4099 omap_mcbsp_tx_done(s);
4100 } else
4101 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4102 return;
4103
4104 case 0x08: /* SPCR2 */
4105 s->spcr[1] &= 0x0002;
4106 s->spcr[1] |= 0x03f9 & value;
4107 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
4108 if (~value & 1) /* XRST */
4109 s->spcr[1] &= ~6;
4110 omap_mcbsp_req_update(s);
4111 return;
4112 case 0x0a: /* SPCR1 */
4113 s->spcr[0] &= 0x0006;
4114 s->spcr[0] |= 0xf8f9 & value;
4115 if (value & (1 << 15)) /* DLB */
4116 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
4117 if (~value & 1) { /* RRST */
4118 s->spcr[0] &= ~6;
4119 s->rx_req = 0;
4120 omap_mcbsp_rx_done(s);
4121 }
4122 omap_mcbsp_req_update(s);
4123 return;
4124
4125 case 0x0c: /* RCR2 */
4126 s->rcr[1] = value & 0xffff;
4127 return;
4128 case 0x0e: /* RCR1 */
4129 s->rcr[0] = value & 0x7fe0;
4130 return;
4131 case 0x10: /* XCR2 */
4132 s->xcr[1] = value & 0xffff;
4133 return;
4134 case 0x12: /* XCR1 */
4135 s->xcr[0] = value & 0x7fe0;
4136 return;
4137 case 0x14: /* SRGR2 */
4138 s->srgr[1] = value & 0xffff;
4139 omap_mcbsp_req_update(s);
4140 return;
4141 case 0x16: /* SRGR1 */
4142 s->srgr[0] = value & 0xffff;
4143 omap_mcbsp_req_update(s);
4144 return;
4145 case 0x18: /* MCR2 */
4146 s->mcr[1] = value & 0x03e3;
4147 if (value & 3) /* XMCM */
4148 printf("%s: Tx channel selection mode enable attempt\n",
4149 __FUNCTION__);
4150 return;
4151 case 0x1a: /* MCR1 */
4152 s->mcr[0] = value & 0x03e1;
4153 if (value & 1) /* RMCM */
4154 printf("%s: Rx channel selection mode enable attempt\n",
4155 __FUNCTION__);
4156 return;
4157 case 0x1c: /* RCERA */
4158 s->rcer[0] = value & 0xffff;
4159 return;
4160 case 0x1e: /* RCERB */
4161 s->rcer[1] = value & 0xffff;
4162 return;
4163 case 0x20: /* XCERA */
4164 s->xcer[0] = value & 0xffff;
4165 return;
4166 case 0x22: /* XCERB */
4167 s->xcer[1] = value & 0xffff;
4168 return;
4169 case 0x24: /* PCR0 */
4170 s->pcr = value & 0x7faf;
4171 return;
4172 case 0x26: /* RCERC */
4173 s->rcer[2] = value & 0xffff;
4174 return;
4175 case 0x28: /* RCERD */
4176 s->rcer[3] = value & 0xffff;
4177 return;
4178 case 0x2a: /* XCERC */
4179 s->xcer[2] = value & 0xffff;
4180 return;
4181 case 0x2c: /* XCERD */
4182 s->xcer[3] = value & 0xffff;
4183 return;
4184 case 0x2e: /* RCERE */
4185 s->rcer[4] = value & 0xffff;
4186 return;
4187 case 0x30: /* RCERF */
4188 s->rcer[5] = value & 0xffff;
4189 return;
4190 case 0x32: /* XCERE */
4191 s->xcer[4] = value & 0xffff;
4192 return;
4193 case 0x34: /* XCERF */
4194 s->xcer[5] = value & 0xffff;
4195 return;
4196 case 0x36: /* RCERG */
4197 s->rcer[6] = value & 0xffff;
4198 return;
4199 case 0x38: /* RCERH */
4200 s->rcer[7] = value & 0xffff;
4201 return;
4202 case 0x3a: /* XCERG */
4203 s->xcer[6] = value & 0xffff;
4204 return;
4205 case 0x3c: /* XCERH */
4206 s->xcer[7] = value & 0xffff;
4207 return;
4208 }
4209
4210 OMAP_BAD_REG(addr);
4211 }
4212
4213 static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
4214 uint32_t value)
4215 {
4216 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4217 int offset = addr & OMAP_MPUI_REG_MASK;
4218
4219 if (offset == 0x04) { /* DXR */
4220 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4221 return;
4222 if (s->tx_req > 3) {
4223 s->tx_req -= 4;
4224 if (s->codec && s->codec->cts) {
4225 s->codec->out.fifo[s->codec->out.len ++] =
4226 (value >> 24) & 0xff;
4227 s->codec->out.fifo[s->codec->out.len ++] =
4228 (value >> 16) & 0xff;
4229 s->codec->out.fifo[s->codec->out.len ++] =
4230 (value >> 8) & 0xff;
4231 s->codec->out.fifo[s->codec->out.len ++] =
4232 (value >> 0) & 0xff;
4233 }
4234 if (s->tx_req < 4)
4235 omap_mcbsp_tx_done(s);
4236 } else
4237 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4238 return;
4239 }
4240
4241 omap_badwidth_write16(opaque, addr, value);
4242 }
4243
4244 static CPUReadMemoryFunc *omap_mcbsp_readfn[] = {
4245 omap_badwidth_read16,
4246 omap_mcbsp_read,
4247 omap_badwidth_read16,
4248 };
4249
4250 static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = {
4251 omap_badwidth_write16,
4252 omap_mcbsp_writeh,
4253 omap_mcbsp_writew,
4254 };
4255
4256 static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
4257 {
4258 memset(&s->spcr, 0, sizeof(s->spcr));
4259 memset(&s->rcr, 0, sizeof(s->rcr));
4260 memset(&s->xcr, 0, sizeof(s->xcr));
4261 s->srgr[0] = 0x0001;
4262 s->srgr[1] = 0x2000;
4263 memset(&s->mcr, 0, sizeof(s->mcr));
4264 memset(&s->pcr, 0, sizeof(s->pcr));
4265 memset(&s->rcer, 0, sizeof(s->rcer));
4266 memset(&s->xcer, 0, sizeof(s->xcer));
4267 s->tx_req = 0;
4268 s->rx_req = 0;
4269 s->tx_rate = 0;
4270 s->rx_rate = 0;
4271 qemu_del_timer(s->source_timer);
4272 qemu_del_timer(s->sink_timer);
4273 }
4274
4275 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
4276 qemu_irq *irq, qemu_irq *dma, omap_clk clk)
4277 {
4278 int iomemtype;
4279 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
4280 qemu_mallocz(sizeof(struct omap_mcbsp_s));
4281
4282 s->base = base;
4283 s->txirq = irq[0];
4284 s->rxirq = irq[1];
4285 s->txdrq = dma[0];
4286 s->rxdrq = dma[1];
4287 s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s);
4288 s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s);
4289 omap_mcbsp_reset(s);
4290
4291 iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
4292 omap_mcbsp_writefn, s);
4293 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4294
4295 return s;
4296 }
4297
4298 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
4299 {
4300 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4301
4302 if (s->rx_rate) {
4303 s->rx_req = s->codec->in.len;
4304 omap_mcbsp_rx_newdata(s);
4305 }
4306 }
4307
4308 static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
4309 {
4310 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4311
4312 if (s->tx_rate) {
4313 s->tx_req = s->codec->out.size;
4314 omap_mcbsp_tx_newdata(s);
4315 }
4316 }
4317
4318 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave)
4319 {
4320 s->codec = slave;
4321 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
4322 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
4323 }
4324
4325 /* LED Pulse Generators */
4326 struct omap_lpg_s {
4327 target_phys_addr_t base;
4328 QEMUTimer *tm;
4329
4330 uint8_t control;
4331 uint8_t power;
4332 int64_t on;
4333 int64_t period;
4334 int clk;
4335 int cycle;
4336 };
4337
4338 static void omap_lpg_tick(void *opaque)
4339 {
4340 struct omap_lpg_s *s = opaque;
4341
4342 if (s->cycle)
4343 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on);
4344 else
4345 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on);
4346
4347 s->cycle = !s->cycle;
4348 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
4349 }
4350
4351 static void omap_lpg_update(struct omap_lpg_s *s)
4352 {
4353 int64_t on, period = 1, ticks = 1000;
4354 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
4355
4356 if (~s->control & (1 << 6)) /* LPGRES */
4357 on = 0;
4358 else if (s->control & (1 << 7)) /* PERM_ON */
4359 on = period;
4360 else {
4361 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
4362 256 / 32);
4363 on = (s->clk && s->power) ? muldiv64(ticks,
4364 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
4365 }
4366
4367 qemu_del_timer(s->tm);
4368 if (on == period && s->on < s->period)
4369 printf("%s: LED is on\n", __FUNCTION__);
4370 else if (on == 0 && s->on)
4371 printf("%s: LED is off\n", __FUNCTION__);
4372 else if (on && (on != s->on || period != s->period)) {
4373 s->cycle = 0;
4374 s->on = on;
4375 s->period = period;
4376 omap_lpg_tick(s);
4377 return;
4378 }
4379
4380 s->on = on;
4381 s->period = period;
4382 }
4383
4384 static void omap_lpg_reset(struct omap_lpg_s *s)
4385 {
4386 s->control = 0x00;
4387 s->power = 0x00;
4388 s->clk = 1;
4389 omap_lpg_update(s);
4390 }
4391
4392 static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
4393 {
4394 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4395 int offset = addr & OMAP_MPUI_REG_MASK;
4396
4397 switch (offset) {
4398 case 0x00: /* LCR */
4399 return s->control;
4400
4401 case 0x04: /* PMR */
4402 return s->power;
4403 }
4404
4405 OMAP_BAD_REG(addr);
4406 return 0;
4407 }
4408
4409 static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
4410 uint32_t value)
4411 {
4412 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4413 int offset = addr & OMAP_MPUI_REG_MASK;
4414
4415 switch (offset) {
4416 case 0x00: /* LCR */
4417 if (~value & (1 << 6)) /* LPGRES */
4418 omap_lpg_reset(s);
4419 s->control = value & 0xff;
4420 omap_lpg_update(s);
4421 return;
4422
4423 case 0x04: /* PMR */
4424 s->power = value & 0x01;
4425 omap_lpg_update(s);
4426 return;
4427
4428 default:
4429 OMAP_BAD_REG(addr);
4430 return;
4431 }
4432 }
4433
4434 static CPUReadMemoryFunc *omap_lpg_readfn[] = {
4435 omap_lpg_read,
4436 omap_badwidth_read8,
4437 omap_badwidth_read8,
4438 };
4439
4440 static CPUWriteMemoryFunc *omap_lpg_writefn[] = {
4441 omap_lpg_write,
4442 omap_badwidth_write8,
4443 omap_badwidth_write8,
4444 };
4445
4446 static void omap_lpg_clk_update(void *opaque, int line, int on)
4447 {
4448 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4449
4450 s->clk = on;
4451 omap_lpg_update(s);
4452 }
4453
4454 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
4455 {
4456 int iomemtype;
4457 struct omap_lpg_s *s = (struct omap_lpg_s *)
4458 qemu_mallocz(sizeof(struct omap_lpg_s));
4459
4460 s->base = base;
4461 s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s);
4462
4463 omap_lpg_reset(s);
4464
4465 iomemtype = cpu_register_io_memory(0, omap_lpg_readfn,
4466 omap_lpg_writefn, s);
4467 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4468
4469 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
4470
4471 return s;
4472 }
4473
4474 /* MPUI Peripheral Bridge configuration */
4475 static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
4476 {
4477 if (addr == OMAP_MPUI_BASE) /* CMR */
4478 return 0xfe4d;
4479
4480 OMAP_BAD_REG(addr);
4481 return 0;
4482 }
4483
4484 static CPUReadMemoryFunc *omap_mpui_io_readfn[] = {
4485 omap_badwidth_read16,
4486 omap_mpui_io_read,
4487 omap_badwidth_read16,
4488 };
4489
4490 static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = {
4491 omap_badwidth_write16,
4492 omap_badwidth_write16,
4493 omap_badwidth_write16,
4494 };
4495
4496 static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
4497 {
4498 int iomemtype = cpu_register_io_memory(0, omap_mpui_io_readfn,
4499 omap_mpui_io_writefn, mpu);
4500 cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
4501 }
4502
4503 /* General chip reset */
4504 static void omap1_mpu_reset(void *opaque)
4505 {
4506 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4507
4508 omap_inth_reset(mpu->ih[0]);
4509 omap_inth_reset(mpu->ih[1]);
4510 omap_dma_reset(mpu->dma);
4511 omap_mpu_timer_reset(mpu->timer[0]);
4512 omap_mpu_timer_reset(mpu->timer[1]);
4513 omap_mpu_timer_reset(mpu->timer[2]);
4514 omap_wd_timer_reset(mpu->wdt);
4515 omap_os_timer_reset(mpu->os_timer);
4516 omap_lcdc_reset(mpu->lcd);
4517 omap_ulpd_pm_reset(mpu);
4518 omap_pin_cfg_reset(mpu);
4519 omap_mpui_reset(mpu);
4520 omap_tipb_bridge_reset(mpu->private_tipb);
4521 omap_tipb_bridge_reset(mpu->public_tipb);
4522 omap_dpll_reset(&mpu->dpll[0]);
4523 omap_dpll_reset(&mpu->dpll[1]);
4524 omap_dpll_reset(&mpu->dpll[2]);
4525 omap_uart_reset(mpu->uart[0]);
4526 omap_uart_reset(mpu->uart[1]);
4527 omap_uart_reset(mpu->uart[2]);
4528 omap_mmc_reset(mpu->mmc);
4529 omap_mpuio_reset(mpu->mpuio);
4530 omap_gpio_reset(mpu->gpio);
4531 omap_uwire_reset(mpu->microwire);
4532 omap_pwl_reset(mpu);
4533 omap_pwt_reset(mpu);
4534 omap_i2c_reset(mpu->i2c[0]);
4535 omap_rtc_reset(mpu->rtc);
4536 omap_mcbsp_reset(mpu->mcbsp1);
4537 omap_mcbsp_reset(mpu->mcbsp2);
4538 omap_mcbsp_reset(mpu->mcbsp3);
4539 omap_lpg_reset(mpu->led[0]);
4540 omap_lpg_reset(mpu->led[1]);
4541 omap_clkm_reset(mpu);
4542 cpu_reset(mpu->env);
4543 }
4544
4545 static const struct omap_map_s {
4546 target_phys_addr_t phys_dsp;
4547 target_phys_addr_t phys_mpu;
4548 uint32_t size;
4549 const char *name;
4550 } omap15xx_dsp_mm[] = {
4551 /* Strobe 0 */
4552 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
4553 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
4554 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
4555 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
4556 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
4557 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
4558 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
4559 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
4560 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
4561 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
4562 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
4563 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
4564 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
4565 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
4566 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
4567 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
4568 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
4569 /* Strobe 1 */
4570 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
4571
4572 { 0 }
4573 };
4574
4575 static void omap_setup_dsp_mapping(const struct omap_map_s *map)
4576 {
4577 int io;
4578
4579 for (; map->phys_dsp; map ++) {
4580 io = cpu_get_physical_page_desc(map->phys_mpu);
4581
4582 cpu_register_physical_memory(map->phys_dsp, map->size, io);
4583 }
4584 }
4585
4586 void omap_mpu_wakeup(void *opaque, int irq, int req)
4587 {
4588 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4589
4590 if (mpu->env->halted)
4591 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
4592 }
4593
4594 static const struct dma_irq_map omap1_dma_irq_map[] = {
4595 { 0, OMAP_INT_DMA_CH0_6 },
4596 { 0, OMAP_INT_DMA_CH1_7 },
4597 { 0, OMAP_INT_DMA_CH2_8 },
4598 { 0, OMAP_INT_DMA_CH3 },
4599 { 0, OMAP_INT_DMA_CH4 },
4600 { 0, OMAP_INT_DMA_CH5 },
4601 { 1, OMAP_INT_1610_DMA_CH6 },
4602 { 1, OMAP_INT_1610_DMA_CH7 },
4603 { 1, OMAP_INT_1610_DMA_CH8 },
4604 { 1, OMAP_INT_1610_DMA_CH9 },
4605 { 1, OMAP_INT_1610_DMA_CH10 },
4606 { 1, OMAP_INT_1610_DMA_CH11 },
4607 { 1, OMAP_INT_1610_DMA_CH12 },
4608 { 1, OMAP_INT_1610_DMA_CH13 },
4609 { 1, OMAP_INT_1610_DMA_CH14 },
4610 { 1, OMAP_INT_1610_DMA_CH15 }
4611 };
4612
4613 /* DMA ports for OMAP1 */
4614 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
4615 target_phys_addr_t addr)
4616 {
4617 return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
4618 }
4619
4620 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
4621 target_phys_addr_t addr)
4622 {
4623 return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
4624 }
4625
4626 static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
4627 target_phys_addr_t addr)
4628 {
4629 return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
4630 }
4631
4632 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
4633 target_phys_addr_t addr)
4634 {
4635 return addr >= 0xfffb0000 && addr < 0xffff0000;
4636 }
4637
4638 static int omap_validate_local_addr(struct omap_mpu_state_s *s,
4639 target_phys_addr_t addr)
4640 {
4641 return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
4642 }
4643
4644 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
4645 target_phys_addr_t addr)
4646 {
4647 return addr >= 0xe1010000 && addr < 0xe1020004;
4648 }
4649
4650 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
4651 DisplayState *ds, const char *core)
4652 {
4653 int i;
4654 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4655 qemu_mallocz(sizeof(struct omap_mpu_state_s));
4656 ram_addr_t imif_base, emiff_base;
4657 qemu_irq *cpu_irq;
4658 qemu_irq dma_irqs[6];
4659 int sdindex;
4660
4661 if (!core)
4662 core = "ti925t";
4663
4664 /* Core */
4665 s->mpu_model = omap310;
4666 s->env = cpu_init(core);
4667 if (!s->env) {
4668 fprintf(stderr, "Unable to find CPU definition\n");
4669 exit(1);
4670 }
4671 s->sdram_size = sdram_size;
4672 s->sram_size = OMAP15XX_SRAM_SIZE;
4673
4674 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
4675
4676 /* Clocks */
4677 omap_clk_init(s);
4678
4679 /* Memory-mapped stuff */
4680 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
4681 (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
4682 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
4683 (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
4684
4685 omap_clkm_init(0xfffece00, 0xe1008000, s);
4686
4687 cpu_irq = arm_pic_init_cpu(s->env);
4688 s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
4689 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
4690 omap_findclk(s, "arminth_ck"));
4691 s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1],
4692 s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL,
4693 omap_findclk(s, "arminth_ck"));
4694
4695 for (i = 0; i < 6; i ++)
4696 dma_irqs[i] =
4697 s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr];
4698 s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
4699 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
4700
4701 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
4702 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
4703 s->port[imif ].addr_valid = omap_validate_imif_addr;
4704 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
4705 s->port[local ].addr_valid = omap_validate_local_addr;
4706 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
4707
4708 /* Register SDRAM and SRAM DMA ports for fast transfers. */
4709 soc_dma_port_add_mem_ram(s->dma,
4710 emiff_base, OMAP_EMIFF_BASE, s->sdram_size);
4711 soc_dma_port_add_mem_ram(s->dma,
4712 imif_base, OMAP_IMIF_BASE, s->sram_size);
4713
4714 s->timer[0] = omap_mpu_timer_init(0xfffec500,
4715 s->irq[0][OMAP_INT_TIMER1],
4716 omap_findclk(s, "mputim_ck"));
4717 s->timer[1] = omap_mpu_timer_init(0xfffec600,
4718 s->irq[0][OMAP_INT_TIMER2],
4719 omap_findclk(s, "mputim_ck"));
4720 s->timer[2] = omap_mpu_timer_init(0xfffec700,
4721 s->irq[0][OMAP_INT_TIMER3],
4722 omap_findclk(s, "mputim_ck"));
4723
4724 s->wdt = omap_wd_timer_init(0xfffec800,
4725 s->irq[0][OMAP_INT_WD_TIMER],
4726 omap_findclk(s, "armwdt_ck"));
4727
4728 s->os_timer = omap_os_timer_init(0xfffb9000,
4729 s->irq[1][OMAP_INT_OS_TIMER],
4730 omap_findclk(s, "clk32-kHz"));
4731
4732 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
4733 omap_dma_get_lcdch(s->dma), ds, imif_base, emiff_base,
4734 omap_findclk(s, "lcd_ck"));
4735
4736 omap_ulpd_pm_init(0xfffe0800, s);
4737 omap_pin_cfg_init(0xfffe1000, s);
4738 omap_id_init(s);
4739
4740 omap_mpui_init(0xfffec900, s);
4741
4742 s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
4743 s->irq[0][OMAP_INT_BRIDGE_PRIV],
4744 omap_findclk(s, "tipb_ck"));
4745 s->public_tipb = omap_tipb_bridge_init(0xfffed300,
4746 s->irq[0][OMAP_INT_BRIDGE_PUB],
4747 omap_findclk(s, "tipb_ck"));
4748
4749 omap_tcmi_init(0xfffecc00, s);
4750
4751 s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
4752 omap_findclk(s, "uart1_ck"),
4753 omap_findclk(s, "uart1_ck"),
4754 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
4755 serial_hds[0]);
4756 s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
4757 omap_findclk(s, "uart2_ck"),
4758 omap_findclk(s, "uart2_ck"),
4759 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
4760 serial_hds[0] ? serial_hds[1] : 0);
4761 s->uart[2] = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3],
4762 omap_findclk(s, "uart3_ck"),
4763 omap_findclk(s, "uart3_ck"),
4764 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
4765 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
4766
4767 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
4768 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
4769 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
4770
4771 sdindex = drive_get_index(IF_SD, 0, 0);
4772 if (sdindex == -1) {
4773 fprintf(stderr, "qemu: missing SecureDigital device\n");
4774 exit(1);
4775 }
4776 s->mmc = omap_mmc_init(0xfffb7800, drives_table[sdindex].bdrv,
4777 s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
4778 omap_findclk(s, "mmc_ck"));
4779
4780 s->mpuio = omap_mpuio_init(0xfffb5000,
4781 s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
4782 s->wakeup, omap_findclk(s, "clk32-kHz"));
4783
4784 s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1],
4785 omap_findclk(s, "arm_gpio_ck"));
4786
4787 s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
4788 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
4789
4790 omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
4791 omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
4792
4793 s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
4794 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
4795
4796 s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
4797 omap_findclk(s, "clk32-kHz"));
4798
4799 s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
4800 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
4801 s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
4802 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
4803 s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
4804 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
4805
4806 s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
4807 s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
4808
4809 /* Register mappings not currenlty implemented:
4810 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4811 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4812 * USB W2FC fffb4000 - fffb47ff
4813 * Camera Interface fffb6800 - fffb6fff
4814 * USB Host fffba000 - fffba7ff
4815 * FAC fffba800 - fffbafff
4816 * HDQ/1-Wire fffbc000 - fffbc7ff
4817 * TIPB switches fffbc800 - fffbcfff
4818 * Mailbox fffcf000 - fffcf7ff
4819 * Local bus IF fffec100 - fffec1ff
4820 * Local bus MMU fffec200 - fffec2ff
4821 * DSP MMU fffed200 - fffed2ff
4822 */
4823
4824 omap_setup_dsp_mapping(omap15xx_dsp_mm);
4825 omap_setup_mpui_io(s);
4826
4827 qemu_register_reset(omap1_mpu_reset, s);
4828
4829 return s;
4830 }
Samsung s3c2440 and arm920t support for the mini2440 dev board