hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34 #include "fw_cfg.h"
  35
  36 //#define DEBUG_IRQ
  37
  38 #ifdef DEBUG_IRQ
  39 #define DPRINTF(fmt, args...)                           \
  40     do { printf("CPUIRQ: " fmt , ##args); } while (0)
  41 #else
  42 #define DPRINTF(fmt, args...)
  43 #endif
  44
  45 #define KERNEL_LOAD_ADDR     0x00404000
  46 #define CMDLINE_ADDR         0x003ff000
  47 #define INITRD_LOAD_ADDR     0x00300000
  48 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  49 #define PROM_VADDR           0x000ffd00000ULL
  50 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  51 #define APB_MEM_BASE         0x1ff00000000ULL
  52 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  53 #define PROM_FILENAME        "openbios-sparc64"
  54 #define NVRAM_SIZE           0x2000
  55 #define MAX_IDE_BUS          2
  56 #define BIOS_CFG_IOPORT      0x510
  57
  58 #define MAX_PILS 16
  59
  60 struct hwdef {
  61     const char * const default_cpu_model;
  62     uint16_t machine_id;
  63     uint64_t prom_addr;
  64     uint64_t console_serial_base;
  65 };
  66
  67 int DMA_get_channel_mode (int nchan)
  68 {
  69     return 0;
  70 }
  71 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  72 {
  73     return 0;
  74 }
  75 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  76 {
  77     return 0;
  78 }
  79 void DMA_hold_DREQ (int nchan) {}
  80 void DMA_release_DREQ (int nchan) {}
  81 void DMA_schedule(int nchan) {}
  82 void DMA_run (void) {}
  83 void DMA_init (int high_page_enable) {}
  84 void DMA_register_channel (int nchan,
  85                            DMA_transfer_handler transfer_handler,
  86                            void *opaque)
  87 {
  88 }
  89
  90 static int nvram_boot_set(void *opaque, const char *boot_device)
  91 {
  92     unsigned int i;
  93     uint8_t image[sizeof(ohwcfg_v3_t)];
  94     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
  95     m48t59_t *nvram = (m48t59_t *)opaque;
  96
  97     for (i = 0; i < sizeof(image); i++)
  98         image[i] = m48t59_read(nvram, i) & 0xff;
  99
 100     pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
 101             boot_device);
 102     header->nboot_devices = strlen(boot_device) & 0xff;
 103     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
 104
 105     for (i = 0; i < sizeof(image); i++)
 106         m48t59_write(nvram, i, image[i]);
 107
 108     return 0;
 109 }
 110
 111 extern int nographic;
 112
 113 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 114                                    const char *arch,
 115                                    ram_addr_t RAM_size,
 116                                    const char *boot_devices,
 117                                    uint32_t kernel_image, uint32_t kernel_size,
 118                                    const char *cmdline,
 119                                    uint32_t initrd_image, uint32_t initrd_size,
 120                                    uint32_t NVRAM_image,
 121                                    int width, int height, int depth,
 122                                    const uint8_t *macaddr)
 123 {
 124     unsigned int i;
 125     uint32_t start, end;
 126     uint8_t image[0x1ff0];
 127     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
 128     struct sparc_arch_cfg *sparc_header;
 129     struct OpenBIOS_nvpart_v1 *part_header;
 130
 131     memset(image, '\0', sizeof(image));
 132
 133     // Try to match PPC NVRAM
 134     pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
 135             "QEMU_BIOS");
 136     header->struct_version = cpu_to_be32(3); /* structure v3 */
 137
 138     header->nvram_size = cpu_to_be16(NVRAM_size);
 139     header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
 140     header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
 141     pstrcpy((char *)header->arch, sizeof(header->arch), arch);
 142     header->nb_cpus = smp_cpus & 0xff;
 143     header->RAM0_base = 0;
 144     header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
 145     pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
 146             boot_devices);
 147     header->nboot_devices = strlen(boot_devices) & 0xff;
 148     header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
 149     header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
 150     if (cmdline) {
 151         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
 152         header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
 153         header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
 154     }
 155     header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
 156     header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
 157     header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
 158
 159     header->width = cpu_to_be16(width);
 160     header->height = cpu_to_be16(height);
 161     header->depth = cpu_to_be16(depth);
 162     if (nographic)
 163         header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
 164
 165     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
 166
 167     // Architecture specific header
 168     start = sizeof(ohwcfg_v3_t);
 169     sparc_header = (struct sparc_arch_cfg *)&image[start];
 170     sparc_header->valid = 0;
 171     start += sizeof(struct sparc_arch_cfg);
 172
 173     // OpenBIOS nvram variables
 174     // Variable partition
 175     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 176     part_header->signature = OPENBIOS_PART_SYSTEM;
 177     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 178
 179     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 180     for (i = 0; i < nb_prom_envs; i++)
 181         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 182
 183     // End marker
 184     image[end++] = '\0';
 185
 186     end = start + ((end - start + 15) & ~15);
 187     OpenBIOS_finish_partition(part_header, end - start);
 188
 189     // free partition
 190     start = end;
 191     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 192     part_header->signature = OPENBIOS_PART_FREE;
 193     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 194
 195     end = 0x1fd0;
 196     OpenBIOS_finish_partition(part_header, end - start);
 197
 198     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 199
 200     for (i = 0; i < sizeof(image); i++)
 201         m48t59_write(nvram, i, image[i]);
 202
 203     qemu_register_boot_set(nvram_boot_set, nvram);
 204
 205     return 0;
 206 }
 207
 208 void pic_info(void)
 209 {
 210 }
 211
 212 void irq_info(void)
 213 {
 214 }
 215
 216 void cpu_check_irqs(CPUState *env)
 217 {
 218     uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
 219         ((env->softint & SOFTINT_TIMER) << 14);
 220
 221     if (pil && (env->interrupt_index == 0 ||
 222                 (env->interrupt_index & ~15) == TT_EXTINT)) {
 223         unsigned int i;
 224
 225         for (i = 15; i > 0; i--) {
 226             if (pil & (1 << i)) {
 227                 int old_interrupt = env->interrupt_index;
 228
 229                 env->interrupt_index = TT_EXTINT | i;
 230                 if (old_interrupt != env->interrupt_index) {
 231                     DPRINTF("Set CPU IRQ %d\n", i);
 232                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 233                 }
 234                 break;
 235             }
 236         }
 237     } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
 238         DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
 239         env->interrupt_index = 0;
 240         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 241     }
 242 }
 243
 244 static void cpu_set_irq(void *opaque, int irq, int level)
 245 {
 246     CPUState *env = opaque;
 247
 248     if (level) {
 249         DPRINTF("Raise CPU IRQ %d\n", irq);
 250         env->halted = 0;
 251         env->pil_in |= 1 << irq;
 252         cpu_check_irqs(env);
 253     } else {
 254         DPRINTF("Lower CPU IRQ %d\n", irq);
 255         env->pil_in &= ~(1 << irq);
 256         cpu_check_irqs(env);
 257     }
 258 }
 259
 260 void qemu_system_powerdown(void)
 261 {
 262 }
 263
 264 typedef struct ResetData {
 265     CPUState *env;
 266     uint64_t reset_addr;
 267 } ResetData;
 268
 269 static void main_cpu_reset(void *opaque)
 270 {
 271     ResetData *s = (ResetData *)opaque;
 272     CPUState *env = s->env;
 273
 274     cpu_reset(env);
 275     ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
 276     ptimer_run(env->tick, 0);
 277     ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
 278     ptimer_run(env->stick, 0);
 279     ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
 280     ptimer_run(env->hstick, 0);
 281     env->gregs[1] = 0; // Memory start
 282     env->gregs[2] = ram_size; // Memory size
 283     env->gregs[3] = 0; // Machine description XXX
 284     env->pc = s->reset_addr;
 285     env->npc = env->pc + 4;
 286 }
 287
 288 static void tick_irq(void *opaque)
 289 {
 290     CPUState *env = opaque;
 291
 292     env->softint |= SOFTINT_TIMER;
 293     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 294 }
 295
 296 static void stick_irq(void *opaque)
 297 {
 298     CPUState *env = opaque;
 299
 300     env->softint |= SOFTINT_TIMER;
 301     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 302 }
 303
 304 static void hstick_irq(void *opaque)
 305 {
 306     CPUState *env = opaque;
 307
 308     env->softint |= SOFTINT_TIMER;
 309     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 310 }
 311
 312 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 313 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 314 static const int ide_irq[2] = { 14, 15 };
 315
 316 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 317 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 318
 319 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 320 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 321
 322 static fdctrl_t *floppy_controller;
 323
 324 static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
 325                         const char *boot_devices, DisplayState *ds,
 326                         const char *kernel_filename, const char *kernel_cmdline,
 327                         const char *initrd_filename, const char *cpu_model,
 328                         const struct hwdef *hwdef)
 329 {
 330     CPUState *env;
 331     char buf[1024];
 332     m48t59_t *nvram;
 333     int ret, linux_boot;
 334     unsigned int i;
 335     long prom_offset, initrd_size, kernel_size;
 336     PCIBus *pci_bus;
 337     QEMUBH *bh;
 338     qemu_irq *irq;
 339     int drive_index;
 340     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 341     BlockDriverState *fd[MAX_FD];
 342     void *fw_cfg;
 343     ResetData *reset_info;
 344
 345     linux_boot = (kernel_filename != NULL);
 346
 347     /* init CPUs */
 348     if (!cpu_model)
 349         cpu_model = hwdef->default_cpu_model;
 350
 351     env = cpu_init(cpu_model);
 352     if (!env) {
 353         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 354         exit(1);
 355     }
 356     bh = qemu_bh_new(tick_irq, env);
 357     env->tick = ptimer_init(bh);
 358     ptimer_set_period(env->tick, 1ULL);
 359
 360     bh = qemu_bh_new(stick_irq, env);
 361     env->stick = ptimer_init(bh);
 362     ptimer_set_period(env->stick, 1ULL);
 363
 364     bh = qemu_bh_new(hstick_irq, env);
 365     env->hstick = ptimer_init(bh);
 366     ptimer_set_period(env->hstick, 1ULL);
 367
 368     reset_info = qemu_mallocz(sizeof(ResetData));
 369     reset_info->env = env;
 370     reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
 371     qemu_register_reset(main_cpu_reset, reset_info);
 372     main_cpu_reset(reset_info);
 373     // Override warm reset address with cold start address
 374     env->pc = hwdef->prom_addr + 0x20ULL;
 375     env->npc = env->pc + 4;
 376
 377     /* allocate RAM */
 378     cpu_register_physical_memory(0, RAM_size, 0);
 379
 380     prom_offset = RAM_size + vga_ram_size;
 381     cpu_register_physical_memory(hwdef->prom_addr,
 382                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
 383                                  TARGET_PAGE_MASK,
 384                                  prom_offset | IO_MEM_ROM);
 385
 386     if (bios_name == NULL)
 387         bios_name = PROM_FILENAME;
 388     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 389     ret = load_elf(buf, hwdef->prom_addr - PROM_VADDR, NULL, NULL, NULL);
 390     if (ret < 0) {
 391         ret = load_image_targphys(buf, hwdef->prom_addr,
 392                                   (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
 393                                   TARGET_PAGE_MASK);
 394         if (ret < 0) {
 395             fprintf(stderr, "qemu: could not load prom '%s'\n",
 396                     buf);
 397             exit(1);
 398         }
 399     }
 400
 401     kernel_size = 0;
 402     initrd_size = 0;
 403     if (linux_boot) {
 404         /* XXX: put correct offset */
 405         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 406         if (kernel_size < 0)
 407             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 408                                     ram_size - KERNEL_LOAD_ADDR);
 409         if (kernel_size < 0)
 410             kernel_size = load_image_targphys(kernel_filename,
 411                                               KERNEL_LOAD_ADDR,
 412                                               ram_size - KERNEL_LOAD_ADDR);
 413         if (kernel_size < 0) {
 414             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 415                     kernel_filename);
 416             exit(1);
 417         }
 418
 419         /* load initrd */
 420         if (initrd_filename) {
 421             initrd_size = load_image_targphys(initrd_filename,
 422                                               INITRD_LOAD_ADDR,
 423                                               ram_size - INITRD_LOAD_ADDR);
 424             if (initrd_size < 0) {
 425                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 426                         initrd_filename);
 427                 exit(1);
 428             }
 429         }
 430         if (initrd_size > 0) {
 431             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 432                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 433                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 434                     stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
 435                     break;
 436                 }
 437             }
 438         }
 439     }
 440     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
 441     isa_mem_base = VGA_BASE;
 442     pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
 443                         vga_ram_size);
 444
 445     i = 0;
 446     if (hwdef->console_serial_base) {
 447         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 448                        serial_hds[i], 1);
 449         i++;
 450     }
 451     for(; i < MAX_SERIAL_PORTS; i++) {
 452         if (serial_hds[i]) {
 453             serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
 454                         serial_hds[i]);
 455         }
 456     }
 457
 458     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 459         if (parallel_hds[i]) {
 460             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
 461                           parallel_hds[i]);
 462         }
 463     }
 464
 465     for(i = 0; i < nb_nics; i++) {
 466         if (!nd_table[i].model)
 467             nd_table[i].model = "ne2k_pci";
 468         pci_nic_init(pci_bus, &nd_table[i], -1);
 469     }
 470
 471     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 472     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 473         fprintf(stderr, "qemu: too many IDE bus\n");
 474         exit(1);
 475     }
 476     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 477         drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
 478                                       i % MAX_IDE_DEVS);
 479        if (drive_index != -1)
 480            hd[i] = drives_table[drive_index].bdrv;
 481        else
 482            hd[i] = NULL;
 483     }
 484
 485     // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
 486     pci_piix3_ide_init(pci_bus, hd, -1, irq);
 487     /* FIXME: wire up interrupts.  */
 488     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 489     for(i = 0; i < MAX_FD; i++) {
 490         drive_index = drive_get_index(IF_FLOPPY, 0, i);
 491        if (drive_index != -1)
 492            fd[i] = drives_table[drive_index].bdrv;
 493        else
 494            fd[i] = NULL;
 495     }
 496     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
 497     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 498     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 499                            KERNEL_LOAD_ADDR, kernel_size,
 500                            kernel_cmdline,
 501                            INITRD_LOAD_ADDR, initrd_size,
 502                            /* XXX: need an option to load a NVRAM image */
 503                            0,
 504                            graphic_width, graphic_height, graphic_depth,
 505                            (uint8_t *)&nd_table[0].macaddr);
 506
 507     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 508     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 509     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 510     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 511 }
 512
 513 enum {
 514     sun4u_id = 0,
 515     sun4v_id = 64,
 516     niagara_id,
 517 };
 518
 519 static const struct hwdef hwdefs[] = {
 520     /* Sun4u generic PC-like machine */
 521     {
 522         .default_cpu_model = "TI UltraSparc II",
 523         .machine_id = sun4u_id,
 524         .prom_addr = 0x1fff0000000ULL,
 525         .console_serial_base = 0,
 526     },
 527     /* Sun4v generic PC-like machine */
 528     {
 529         .default_cpu_model = "Sun UltraSparc T1",
 530         .machine_id = sun4v_id,
 531         .prom_addr = 0x1fff0000000ULL,
 532         .console_serial_base = 0,
 533     },
 534     /* Sun4v generic Niagara machine */
 535     {
 536         .default_cpu_model = "Sun UltraSparc T1",
 537         .machine_id = niagara_id,
 538         .prom_addr = 0xfff0000000ULL,
 539         .console_serial_base = 0xfff0c2c000ULL,
 540     },
 541 };
 542
 543 /* Sun4u hardware initialisation */
 544 static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
 545                        const char *boot_devices, DisplayState *ds,
 546                        const char *kernel_filename, const char *kernel_cmdline,
 547                        const char *initrd_filename, const char *cpu_model)
 548 {
 549     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 550                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 551 }
 552
 553 /* Sun4v hardware initialisation */
 554 static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
 555                        const char *boot_devices, DisplayState *ds,
 556                        const char *kernel_filename, const char *kernel_cmdline,
 557                        const char *initrd_filename, const char *cpu_model)
 558 {
 559     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 560                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 561 }
 562
 563 /* Niagara hardware initialisation */
 564 static void niagara_init(ram_addr_t RAM_size, int vga_ram_size,
 565                          const char *boot_devices, DisplayState *ds,
 566                          const char *kernel_filename, const char *kernel_cmdline,
 567                          const char *initrd_filename, const char *cpu_model)
 568 {
 569     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 570                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 571 }
 572
 573 QEMUMachine sun4u_machine = {
 574     .name = "sun4u",
 575     .desc = "Sun4u platform",
 576     .init = sun4u_init,
 577     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 578     .nodisk_ok = 1,
 579 };
 580
 581 QEMUMachine sun4v_machine = {
 582     .name = "sun4v",
 583     .desc = "Sun4v platform",
 584     .init = sun4v_init,
 585     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 586     .nodisk_ok = 1,
 587 };
 588
 589 QEMUMachine niagara_machine = {
 590     .name = "Niagara",
 591     .desc = "Sun4v platform, Niagara",
 592     .init = niagara_init,
 593     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 594     .nodisk_ok = 1,
 595 };