?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Add missing static qualifier
[qemu/mini2440.git] / target-sh4 / translate.c
bloba41ec2512badff0bebcc84841a9a1ea8bdf6555d
1 /*
2 * SH4 translation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <assert.h>
26
27 #define DEBUG_DISAS
28 #define SH4_DEBUG_DISAS
29 //#define SH4_SINGLE_STEP
30
31 #include "cpu.h"
32 #include "exec-all.h"
33 #include "disas.h"
34 #include "tcg-op.h"
35 #include "qemu-common.h"
36
37 #include "helper.h"
38 #define GEN_HELPER 1
39 #include "helper.h"
40
41 typedef struct DisasContext {
42 struct TranslationBlock *tb;
43 target_ulong pc;
44 uint32_t sr;
45 uint32_t fpscr;
46 uint16_t opcode;
47 uint32_t flags;
48 int bstate;
49 int memidx;
50 uint32_t delayed_pc;
51 int singlestep_enabled;
52 } DisasContext;
53
54 #if defined(CONFIG_USER_ONLY)
55 #define IS_USER(ctx) 1
56 #else
57 #define IS_USER(ctx) (!(ctx->sr & SR_MD))
58 #endif
59
60 enum {
61 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
62 * exception condition
63 */
64 BS_STOP = 1, /* We want to stop translation for any reason */
65 BS_BRANCH = 2, /* We reached a branch condition */
66 BS_EXCP = 3, /* We reached an exception condition */
67 };
68
69 /* global register indexes */
70 static TCGv_ptr cpu_env;
71 static TCGv cpu_gregs[24];
72 static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
73 static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
74 static TCGv cpu_pr, cpu_fpscr, cpu_fpul;
75 static TCGv cpu_fregs[32];
76
77 /* internal register indexes */
78 static TCGv cpu_flags, cpu_delayed_pc;
79
80 #include "gen-icount.h"
81
82 static void sh4_translate_init(void)
83 {
84 int i;
85 static int done_init = 0;
86 static const char * const gregnames[24] = {
87 "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
88 "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
89 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
90 "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
91 "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
92 };
93 static const char * const fregnames[32] = {
94 "FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0",
95 "FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0",
96 "FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0",
97 "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0",
98 "FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1",
99 "FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1",
100 "FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1",
101 "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
102 };
103
104 if (done_init)
105 return;
106
107 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
108
109 for (i = 0; i < 24; i++)
110 cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, gregs[i]),
112 gregnames[i]);
113
114 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, pc), "PC");
116 cpu_sr = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, sr), "SR");
118 cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, ssr), "SSR");
120 cpu_spc = tcg_global_mem_new_i32(TCG_AREG0,
121 offsetof(CPUState, spc), "SPC");
122 cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0,
123 offsetof(CPUState, gbr), "GBR");
124 cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0,
125 offsetof(CPUState, vbr), "VBR");
126 cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0,
127 offsetof(CPUState, sgr), "SGR");
128 cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0,
129 offsetof(CPUState, dbr), "DBR");
130 cpu_mach = tcg_global_mem_new_i32(TCG_AREG0,
131 offsetof(CPUState, mach), "MACH");
132 cpu_macl = tcg_global_mem_new_i32(TCG_AREG0,
133 offsetof(CPUState, macl), "MACL");
134 cpu_pr = tcg_global_mem_new_i32(TCG_AREG0,
135 offsetof(CPUState, pr), "PR");
136 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
137 offsetof(CPUState, fpscr), "FPSCR");
138 cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0,
139 offsetof(CPUState, fpul), "FPUL");
140
141 cpu_flags = tcg_global_mem_new_i32(TCG_AREG0,
142 offsetof(CPUState, flags), "_flags_");
143 cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
144 offsetof(CPUState, delayed_pc),
145 "_delayed_pc_");
146
147 for (i = 0; i < 32; i++)
148 cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
149 offsetof(CPUState, fregs[i]),
150 fregnames[i]);
151
152 /* register helpers */
153 #define GEN_HELPER 2
154 #include "helper.h"
155
156 done_init = 1;
157 }
158
159 void cpu_dump_state(CPUState * env, FILE * f,
160 int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
161 int flags)
162 {
163 int i;
164 cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
165 env->pc, env->sr, env->pr, env->fpscr);
166 cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
167 env->spc, env->ssr, env->gbr, env->vbr);
168 cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
169 env->sgr, env->dbr, env->delayed_pc, env->fpul);
170 for (i = 0; i < 24; i += 4) {
171 cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
172 i, env->gregs[i], i + 1, env->gregs[i + 1],
173 i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);
174 }
175 if (env->flags & DELAY_SLOT) {
176 cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
177 env->delayed_pc);
178 } else if (env->flags & DELAY_SLOT_CONDITIONAL) {
179 cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
180 env->delayed_pc);
181 }
182 }
183
184 static void cpu_sh4_reset(CPUSH4State * env)
185 {
186 #if defined(CONFIG_USER_ONLY)
187 env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */
188 #else
189 env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */
190 #endif
191 env->vbr = 0;
192 env->pc = 0xA0000000;
193 #if defined(CONFIG_USER_ONLY)
194 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
195 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
196 #else
197 env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
198 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
199 #endif
200 env->mmucr = 0;
201 }
202
203 typedef struct {
204 const char *name;
205 int id;
206 uint32_t pvr;
207 uint32_t prr;
208 uint32_t cvr;
209 } sh4_def_t;
210
211 static sh4_def_t sh4_defs[] = {
212 {
213 .name = "SH7750R",
214 .id = SH_CPU_SH7750R,
215 .pvr = 0x00050000,
216 .prr = 0x00000100,
217 .cvr = 0x00110000,
218 }, {
219 .name = "SH7751R",
220 .id = SH_CPU_SH7751R,
221 .pvr = 0x04050005,
222 .prr = 0x00000113,
223 .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
224 },
225 };
226
227 static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
228 {
229 int i;
230
231 if (strcasecmp(name, "any") == 0)
232 return &sh4_defs[0];
233
234 for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++)
235 if (strcasecmp(name, sh4_defs[i].name) == 0)
236 return &sh4_defs[i];
237
238 return NULL;
239 }
240
241 void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
242 {
243 int i;
244
245 for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++)
246 (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
247 }
248
249 static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def)
250 {
251 env->pvr = def->pvr;
252 env->prr = def->prr;
253 env->cvr = def->cvr;
254 env->id = def->id;
255 }
256
257 CPUSH4State *cpu_sh4_init(const char *cpu_model)
258 {
259 CPUSH4State *env;
260 const sh4_def_t *def;
261
262 def = cpu_sh4_find_by_name(cpu_model);
263 if (!def)
264 return NULL;
265 env = qemu_mallocz(sizeof(CPUSH4State));
266 if (!env)
267 return NULL;
268 cpu_exec_init(env);
269 sh4_translate_init();
270 env->cpu_model_str = cpu_model;
271 cpu_sh4_reset(env);
272 cpu_sh4_register(env, def);
273 tlb_flush(env, 1);
274 return env;
275 }
276
277 static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
278 {
279 TranslationBlock *tb;
280 tb = ctx->tb;
281
282 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
283 !ctx->singlestep_enabled) {
284 /* Use a direct jump if in same page and singlestep not enabled */
285 tcg_gen_goto_tb(n);
286 tcg_gen_movi_i32(cpu_pc, dest);
287 tcg_gen_exit_tb((long) tb + n);
288 } else {
289 tcg_gen_movi_i32(cpu_pc, dest);
290 if (ctx->singlestep_enabled)
291 gen_helper_debug();
292 tcg_gen_exit_tb(0);
293 }
294 }
295
296 static void gen_jump(DisasContext * ctx)
297 {
298 if (ctx->delayed_pc == (uint32_t) - 1) {
299 /* Target is not statically known, it comes necessarily from a
300 delayed jump as immediate jump are conditinal jumps */
301 tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
302 if (ctx->singlestep_enabled)
303 gen_helper_debug();
304 tcg_gen_exit_tb(0);
305 } else {
306 gen_goto_tb(ctx, 0, ctx->delayed_pc);
307 }
308 }
309
310 static inline void gen_branch_slot(uint32_t delayed_pc, int t)
311 {
312 TCGv sr;
313 int label = gen_new_label();
314 tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);
315 sr = tcg_temp_new();
316 tcg_gen_andi_i32(sr, cpu_sr, SR_T);
317 tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label);
318 tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
319 gen_set_label(label);
320 }
321
322 /* Immediate conditional jump (bt or bf) */
323 static void gen_conditional_jump(DisasContext * ctx,
324 target_ulong ift, target_ulong ifnott)
325 {
326 int l1;
327 TCGv sr;
328
329 l1 = gen_new_label();
330 sr = tcg_temp_new();
331 tcg_gen_andi_i32(sr, cpu_sr, SR_T);
332 tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1);
333 gen_goto_tb(ctx, 0, ifnott);
334 gen_set_label(l1);
335 gen_goto_tb(ctx, 1, ift);
336 }
337
338 /* Delayed conditional jump (bt or bf) */
339 static void gen_delayed_conditional_jump(DisasContext * ctx)
340 {
341 int l1;
342 TCGv ds;
343
344 l1 = gen_new_label();
345 ds = tcg_temp_new();
346 tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE);
347 tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1);
348 gen_goto_tb(ctx, 1, ctx->pc + 2);
349 gen_set_label(l1);
350 tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE);
351 gen_jump(ctx);
352 }
353
354 static inline void gen_set_t(void)
355 {
356 tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
357 }
358
359 static inline void gen_clr_t(void)
360 {
361 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
362 }
363
364 static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
365 {
366 int label1 = gen_new_label();
367 int label2 = gen_new_label();
368 tcg_gen_brcond_i32(cond, t1, t0, label1);
369 gen_clr_t();
370 tcg_gen_br(label2);
371 gen_set_label(label1);
372 gen_set_t();
373 gen_set_label(label2);
374 }
375
376 static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)
377 {
378 int label1 = gen_new_label();
379 int label2 = gen_new_label();
380 tcg_gen_brcondi_i32(cond, t0, imm, label1);
381 gen_clr_t();
382 tcg_gen_br(label2);
383 gen_set_label(label1);
384 gen_set_t();
385 gen_set_label(label2);
386 }
387
388 static inline void gen_store_flags(uint32_t flags)
389 {
390 tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
391 tcg_gen_ori_i32(cpu_flags, cpu_flags, flags);
392 }
393
394 static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)
395 {
396 TCGv tmp = tcg_temp_new();
397
398 p0 &= 0x1f;
399 p1 &= 0x1f;
400
401 tcg_gen_andi_i32(tmp, t1, (1 << p1));
402 tcg_gen_andi_i32(t0, t0, ~(1 << p0));
403 if (p0 < p1)
404 tcg_gen_shri_i32(tmp, tmp, p1 - p0);
405 else if (p0 > p1)
406 tcg_gen_shli_i32(tmp, tmp, p0 - p1);
407 tcg_gen_or_i32(t0, t0, tmp);
408
409 tcg_temp_free(tmp);
410 }
411
412 static inline void gen_load_fpr64(TCGv_i64 t, int reg)
413 {
414 tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
415 }
416
417 static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
418 {
419 TCGv_i32 tmp = tcg_temp_new_i32();
420 tcg_gen_trunc_i64_i32(tmp, t);
421 tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
422 tcg_gen_shri_i64(t, t, 32);
423 tcg_gen_trunc_i64_i32(tmp, t);
424 tcg_gen_mov_i32(cpu_fregs[reg], tmp);
425 tcg_temp_free_i32(tmp);
426 }
427
428 #define B3_0 (ctx->opcode & 0xf)
429 #define B6_4 ((ctx->opcode >> 4) & 0x7)
430 #define B7_4 ((ctx->opcode >> 4) & 0xf)
431 #define B7_0 (ctx->opcode & 0xff)
432 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
433 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
434 (ctx->opcode & 0xfff))
435 #define B11_8 ((ctx->opcode >> 8) & 0xf)
436 #define B15_12 ((ctx->opcode >> 12) & 0xf)
437
438 #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
439 (cpu_gregs[x + 16]) : (cpu_gregs[x]))
440
441 #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
442 ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
443
444 #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
445 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
446 #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
447 #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
448
449 #define CHECK_NOT_DELAY_SLOT \
450 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
451 { \
452 tcg_gen_movi_i32(cpu_pc, ctx->pc-2); \
453 gen_helper_raise_slot_illegal_instruction(); \
454 ctx->bstate = BS_EXCP; \
455 return; \
456 }
457
458 #define CHECK_PRIVILEGED \
459 if (IS_USER(ctx)) { \
460 tcg_gen_movi_i32(cpu_pc, ctx->pc); \
461 gen_helper_raise_illegal_instruction(); \
462 ctx->bstate = BS_EXCP; \
463 return; \
464 }
465
466 #define CHECK_FPU_ENABLED \
467 if (ctx->flags & SR_FD) { \
468 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
469 tcg_gen_movi_i32(cpu_pc, ctx->pc-2); \
470 gen_helper_raise_slot_fpu_disable(); \
471 } else { \
472 tcg_gen_movi_i32(cpu_pc, ctx->pc); \
473 gen_helper_raise_fpu_disable(); \
474 } \
475 ctx->bstate = BS_EXCP; \
476 return; \
477 }
478
479 static void _decode_opc(DisasContext * ctx)
480 {
481 #if 0
482 fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
483 #endif
484
485 switch (ctx->opcode) {
486 case 0x0019: /* div0u */
487 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
488 return;
489 case 0x000b: /* rts */
490 CHECK_NOT_DELAY_SLOT
491 tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
492 ctx->flags |= DELAY_SLOT;
493 ctx->delayed_pc = (uint32_t) - 1;
494 return;
495 case 0x0028: /* clrmac */
496 tcg_gen_movi_i32(cpu_mach, 0);
497 tcg_gen_movi_i32(cpu_macl, 0);
498 return;
499 case 0x0048: /* clrs */
500 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
501 return;
502 case 0x0008: /* clrt */
503 gen_clr_t();
504 return;
505 case 0x0038: /* ldtlb */
506 CHECK_PRIVILEGED
507 gen_helper_ldtlb();
508 return;
509 case 0x002b: /* rte */
510 CHECK_PRIVILEGED
511 CHECK_NOT_DELAY_SLOT
512 tcg_gen_mov_i32(cpu_sr, cpu_ssr);
513 tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
514 ctx->flags |= DELAY_SLOT;
515 ctx->delayed_pc = (uint32_t) - 1;
516 return;
517 case 0x0058: /* sets */
518 tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
519 return;
520 case 0x0018: /* sett */
521 gen_set_t();
522 return;
523 case 0xfbfd: /* frchg */
524 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);
525 ctx->bstate = BS_STOP;
526 return;
527 case 0xf3fd: /* fschg */
528 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
529 ctx->bstate = BS_STOP;
530 return;
531 case 0x0009: /* nop */
532 return;
533 case 0x001b: /* sleep */
534 CHECK_PRIVILEGED
535 gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
536 return;
537 }
538
539 switch (ctx->opcode & 0xf000) {
540 case 0x1000: /* mov.l Rm,@(disp,Rn) */
541 {
542 TCGv addr = tcg_temp_new();
543 tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
544 tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
545 tcg_temp_free(addr);
546 }
547 return;
548 case 0x5000: /* mov.l @(disp,Rm),Rn */
549 {
550 TCGv addr = tcg_temp_new();
551 tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
552 tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
553 tcg_temp_free(addr);
554 }
555 return;
556 case 0xe000: /* mov #imm,Rn */
557 tcg_gen_movi_i32(REG(B11_8), B7_0s);
558 return;
559 case 0x9000: /* mov.w @(disp,PC),Rn */
560 {
561 TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2);
562 tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
563 tcg_temp_free(addr);
564 }
565 return;
566 case 0xd000: /* mov.l @(disp,PC),Rn */
567 {
568 TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3);
569 tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
570 tcg_temp_free(addr);
571 }
572 return;
573 case 0x7000: /* add #imm,Rn */
574 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s);
575 return;
576 case 0xa000: /* bra disp */
577 CHECK_NOT_DELAY_SLOT
578 ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
579 tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
580 ctx->flags |= DELAY_SLOT;
581 return;
582 case 0xb000: /* bsr disp */
583 CHECK_NOT_DELAY_SLOT
584 tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
585 ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
586 tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
587 ctx->flags |= DELAY_SLOT;
588 return;
589 }
590
591 switch (ctx->opcode & 0xf00f) {
592 case 0x6003: /* mov Rm,Rn */
593 tcg_gen_mov_i32(REG(B11_8), REG(B7_4));
594 return;
595 case 0x2000: /* mov.b Rm,@Rn */
596 tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx);
597 return;
598 case 0x2001: /* mov.w Rm,@Rn */
599 tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx);
600 return;
601 case 0x2002: /* mov.l Rm,@Rn */
602 tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx);
603 return;
604 case 0x6000: /* mov.b @Rm,Rn */
605 tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
606 return;
607 case 0x6001: /* mov.w @Rm,Rn */
608 tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
609 return;
610 case 0x6002: /* mov.l @Rm,Rn */
611 tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
612 return;
613 case 0x2004: /* mov.b Rm,@-Rn */
614 {
615 TCGv addr = tcg_temp_new();
616 tcg_gen_subi_i32(addr, REG(B11_8), 1);
617 tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */
618 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */
619 tcg_temp_free(addr);
620 }
621 return;
622 case 0x2005: /* mov.w Rm,@-Rn */
623 {
624 TCGv addr = tcg_temp_new();
625 tcg_gen_subi_i32(addr, REG(B11_8), 2);
626 tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
627 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
628 tcg_temp_free(addr);
629 }
630 return;
631 case 0x2006: /* mov.l Rm,@-Rn */
632 {
633 TCGv addr = tcg_temp_new();
634 tcg_gen_subi_i32(addr, REG(B11_8), 4);
635 tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
636 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
637 }
638 return;
639 case 0x6004: /* mov.b @Rm+,Rn */
640 tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
641 if ( B11_8 != B7_4 )
642 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
643 return;
644 case 0x6005: /* mov.w @Rm+,Rn */
645 tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
646 if ( B11_8 != B7_4 )
647 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
648 return;
649 case 0x6006: /* mov.l @Rm+,Rn */
650 tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
651 if ( B11_8 != B7_4 )
652 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
653 return;
654 case 0x0004: /* mov.b Rm,@(R0,Rn) */
655 {
656 TCGv addr = tcg_temp_new();
657 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
658 tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);
659 tcg_temp_free(addr);
660 }
661 return;
662 case 0x0005: /* mov.w Rm,@(R0,Rn) */
663 {
664 TCGv addr = tcg_temp_new();
665 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
666 tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
667 tcg_temp_free(addr);
668 }
669 return;
670 case 0x0006: /* mov.l Rm,@(R0,Rn) */
671 {
672 TCGv addr = tcg_temp_new();
673 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
674 tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
675 tcg_temp_free(addr);
676 }
677 return;
678 case 0x000c: /* mov.b @(R0,Rm),Rn */
679 {
680 TCGv addr = tcg_temp_new();
681 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
682 tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx);
683 tcg_temp_free(addr);
684 }
685 return;
686 case 0x000d: /* mov.w @(R0,Rm),Rn */
687 {
688 TCGv addr = tcg_temp_new();
689 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
690 tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
691 tcg_temp_free(addr);
692 }
693 return;
694 case 0x000e: /* mov.l @(R0,Rm),Rn */
695 {
696 TCGv addr = tcg_temp_new();
697 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
698 tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
699 tcg_temp_free(addr);
700 }
701 return;
702 case 0x6008: /* swap.b Rm,Rn */
703 {
704 TCGv highw, high, low;
705 highw = tcg_temp_new();
706 tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000);
707 high = tcg_temp_new();
708 tcg_gen_ext8u_i32(high, REG(B7_4));
709 tcg_gen_shli_i32(high, high, 8);
710 low = tcg_temp_new();
711 tcg_gen_shri_i32(low, REG(B7_4), 8);
712 tcg_gen_ext8u_i32(low, low);
713 tcg_gen_or_i32(REG(B11_8), high, low);
714 tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw);
715 tcg_temp_free(low);
716 tcg_temp_free(high);
717 }
718 return;
719 case 0x6009: /* swap.w Rm,Rn */
720 {
721 TCGv high, low;
722 high = tcg_temp_new();
723 tcg_gen_ext16u_i32(high, REG(B7_4));
724 tcg_gen_shli_i32(high, high, 16);
725 low = tcg_temp_new();
726 tcg_gen_shri_i32(low, REG(B7_4), 16);
727 tcg_gen_ext16u_i32(low, low);
728 tcg_gen_or_i32(REG(B11_8), high, low);
729 tcg_temp_free(low);
730 tcg_temp_free(high);
731 }
732 return;
733 case 0x200d: /* xtrct Rm,Rn */
734 {
735 TCGv high, low;
736 high = tcg_temp_new();
737 tcg_gen_ext16u_i32(high, REG(B7_4));
738 tcg_gen_shli_i32(high, high, 16);
739 low = tcg_temp_new();
740 tcg_gen_shri_i32(low, REG(B11_8), 16);
741 tcg_gen_ext16u_i32(low, low);
742 tcg_gen_or_i32(REG(B11_8), high, low);
743 tcg_temp_free(low);
744 tcg_temp_free(high);
745 }
746 return;
747 case 0x300c: /* add Rm,Rn */
748 tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
749 return;
750 case 0x300e: /* addc Rm,Rn */
751 gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8));
752 return;
753 case 0x300f: /* addv Rm,Rn */
754 gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8));
755 return;
756 case 0x2009: /* and Rm,Rn */
757 tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
758 return;
759 case 0x3000: /* cmp/eq Rm,Rn */
760 gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8));
761 return;
762 case 0x3003: /* cmp/ge Rm,Rn */
763 gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8));
764 return;
765 case 0x3007: /* cmp/gt Rm,Rn */
766 gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8));
767 return;
768 case 0x3006: /* cmp/hi Rm,Rn */
769 gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8));
770 return;
771 case 0x3002: /* cmp/hs Rm,Rn */
772 gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8));
773 return;
774 case 0x200c: /* cmp/str Rm,Rn */
775 {
776 int label1 = gen_new_label();
777 int label2 = gen_new_label();
778 TCGv cmp1 = tcg_temp_local_new(TCG_TYPE_I32);
779 TCGv cmp2 = tcg_temp_local_new(TCG_TYPE_I32);
780 tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));
781 tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
782 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
783 tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
784 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
785 tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
786 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
787 tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
788 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
789 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
790 tcg_gen_br(label2);
791 gen_set_label(label1);
792 tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
793 gen_set_label(label2);
794 tcg_temp_free(cmp2);
795 tcg_temp_free(cmp1);
796 }
797 return;
798 case 0x2007: /* div0s Rm,Rn */
799 {
800 gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */
801 gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */
802 TCGv val = tcg_temp_new();
803 tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8));
804 gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */
805 tcg_temp_free(val);
806 }
807 return;
808 case 0x3004: /* div1 Rm,Rn */
809 gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8));
810 return;
811 case 0x300d: /* dmuls.l Rm,Rn */
812 {
813 TCGv_i64 tmp1 = tcg_temp_new_i64();
814 TCGv_i64 tmp2 = tcg_temp_new_i64();
815
816 tcg_gen_ext_i32_i64(tmp1, REG(B7_4));
817 tcg_gen_ext_i32_i64(tmp2, REG(B11_8));
818 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
819 tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
820 tcg_gen_shri_i64(tmp1, tmp1, 32);
821 tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
822
823 tcg_temp_free_i64(tmp2);
824 tcg_temp_free_i64(tmp1);
825 }
826 return;
827 case 0x3005: /* dmulu.l Rm,Rn */
828 {
829 TCGv_i64 tmp1 = tcg_temp_new_i64();
830 TCGv_i64 tmp2 = tcg_temp_new_i64();
831
832 tcg_gen_extu_i32_i64(tmp1, REG(B7_4));
833 tcg_gen_extu_i32_i64(tmp2, REG(B11_8));
834 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
835 tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
836 tcg_gen_shri_i64(tmp1, tmp1, 32);
837 tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
838
839 tcg_temp_free_i64(tmp2);
840 tcg_temp_free_i64(tmp1);
841 }
842 return;
843 case 0x600e: /* exts.b Rm,Rn */
844 tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4));
845 return;
846 case 0x600f: /* exts.w Rm,Rn */
847 tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4));
848 return;
849 case 0x600c: /* extu.b Rm,Rn */
850 tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4));
851 return;
852 case 0x600d: /* extu.w Rm,Rn */
853 tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4));
854 return;
855 case 0x000f: /* mac.l @Rm+,@Rn+ */
856 {
857 TCGv arg0, arg1;
858 arg0 = tcg_temp_new();
859 tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
860 arg1 = tcg_temp_new();
861 tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
862 gen_helper_macl(arg0, arg1);
863 tcg_temp_free(arg1);
864 tcg_temp_free(arg0);
865 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
866 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
867 }
868 return;
869 case 0x400f: /* mac.w @Rm+,@Rn+ */
870 {
871 TCGv arg0, arg1;
872 arg0 = tcg_temp_new();
873 tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
874 arg1 = tcg_temp_new();
875 tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
876 gen_helper_macw(arg0, arg1);
877 tcg_temp_free(arg1);
878 tcg_temp_free(arg0);
879 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
880 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
881 }
882 return;
883 case 0x0007: /* mul.l Rm,Rn */
884 tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8));
885 return;
886 case 0x200f: /* muls.w Rm,Rn */
887 {
888 TCGv arg0, arg1;
889 arg0 = tcg_temp_new();
890 tcg_gen_ext16s_i32(arg0, REG(B7_4));
891 arg1 = tcg_temp_new();
892 tcg_gen_ext16s_i32(arg1, REG(B11_8));
893 tcg_gen_mul_i32(cpu_macl, arg0, arg1);
894 tcg_temp_free(arg1);
895 tcg_temp_free(arg0);
896 }
897 return;
898 case 0x200e: /* mulu.w Rm,Rn */
899 {
900 TCGv arg0, arg1;
901 arg0 = tcg_temp_new();
902 tcg_gen_ext16u_i32(arg0, REG(B7_4));
903 arg1 = tcg_temp_new();
904 tcg_gen_ext16u_i32(arg1, REG(B11_8));
905 tcg_gen_mul_i32(cpu_macl, arg0, arg1);
906 tcg_temp_free(arg1);
907 tcg_temp_free(arg0);
908 }
909 return;
910 case 0x600b: /* neg Rm,Rn */
911 tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
912 return;
913 case 0x600a: /* negc Rm,Rn */
914 gen_helper_negc(REG(B11_8), REG(B7_4));
915 return;
916 case 0x6007: /* not Rm,Rn */
917 tcg_gen_not_i32(REG(B11_8), REG(B7_4));
918 return;
919 case 0x200b: /* or Rm,Rn */
920 tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4));
921 return;
922 case 0x400c: /* shad Rm,Rn */
923 {
924 int label1 = gen_new_label();
925 int label2 = gen_new_label();
926 int label3 = gen_new_label();
927 int label4 = gen_new_label();
928 TCGv shift = tcg_temp_local_new(TCG_TYPE_I32);
929 tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
930 /* Rm positive, shift to the left */
931 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
932 tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
933 tcg_gen_br(label4);
934 /* Rm negative, shift to the right */
935 gen_set_label(label1);
936 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
937 tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
938 tcg_gen_not_i32(shift, REG(B7_4));
939 tcg_gen_andi_i32(shift, shift, 0x1f);
940 tcg_gen_addi_i32(shift, shift, 1);
941 tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift);
942 tcg_gen_br(label4);
943 /* Rm = -32 */
944 gen_set_label(label2);
945 tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);
946 tcg_gen_movi_i32(REG(B11_8), 0);
947 tcg_gen_br(label4);
948 gen_set_label(label3);
949 tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
950 gen_set_label(label4);
951 tcg_temp_free(shift);
952 }
953 return;
954 case 0x400d: /* shld Rm,Rn */
955 {
956 int label1 = gen_new_label();
957 int label2 = gen_new_label();
958 int label3 = gen_new_label();
959 TCGv shift = tcg_temp_local_new(TCG_TYPE_I32);
960 tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
961 /* Rm positive, shift to the left */
962 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
963 tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
964 tcg_gen_br(label3);
965 /* Rm negative, shift to the right */
966 gen_set_label(label1);
967 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
968 tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
969 tcg_gen_not_i32(shift, REG(B7_4));
970 tcg_gen_andi_i32(shift, shift, 0x1f);
971 tcg_gen_addi_i32(shift, shift, 1);
972 tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift);
973 tcg_gen_br(label3);
974 /* Rm = -32 */
975 gen_set_label(label2);
976 tcg_gen_movi_i32(REG(B11_8), 0);
977 gen_set_label(label3);
978 tcg_temp_free(shift);
979 }
980 return;
981 case 0x3008: /* sub Rm,Rn */
982 tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
983 return;
984 case 0x300a: /* subc Rm,Rn */
985 gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8));
986 return;
987 case 0x300b: /* subv Rm,Rn */
988 gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8));
989 return;
990 case 0x2008: /* tst Rm,Rn */
991 {
992 TCGv val = tcg_temp_new();
993 tcg_gen_and_i32(val, REG(B7_4), REG(B11_8));
994 gen_cmp_imm(TCG_COND_EQ, val, 0);
995 tcg_temp_free(val);
996 }
997 return;
998 case 0x200a: /* xor Rm,Rn */
999 tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
1000 return;
1001 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
1002 CHECK_FPU_ENABLED
1003 if (ctx->fpscr & FPSCR_SZ) {
1004 TCGv_i64 fp = tcg_temp_new_i64();
1005 gen_load_fpr64(fp, XREG(B7_4));
1006 gen_store_fpr64(fp, XREG(B11_8));
1007 tcg_temp_free_i64(fp);
1008 } else {
1009 tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1010 }
1011 return;
1012 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
1013 CHECK_FPU_ENABLED
1014 if (ctx->fpscr & FPSCR_SZ) {
1015 TCGv addr_hi = tcg_temp_new();
1016 int fr = XREG(B7_4);
1017 tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
1018 tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
1019 tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
1020 tcg_temp_free(addr_hi);
1021 } else {
1022 tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
1023 }
1024 return;
1025 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
1026 CHECK_FPU_ENABLED
1027 if (ctx->fpscr & FPSCR_SZ) {
1028 TCGv addr_hi = tcg_temp_new();
1029 int fr = XREG(B11_8);
1030 tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
1031 tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
1032 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
1033 tcg_temp_free(addr_hi);
1034 } else {
1035 tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
1036 }
1037 return;
1038 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
1039 CHECK_FPU_ENABLED
1040 if (ctx->fpscr & FPSCR_SZ) {
1041 TCGv addr_hi = tcg_temp_new();
1042 int fr = XREG(B11_8);
1043 tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
1044 tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
1045 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
1046 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
1047 tcg_temp_free(addr_hi);
1048 } else {
1049 tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
1050 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
1051 }
1052 return;
1053 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
1054 CHECK_FPU_ENABLED
1055 if (ctx->fpscr & FPSCR_SZ) {
1056 TCGv addr = tcg_temp_new_i32();
1057 int fr = XREG(B7_4);
1058 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1059 tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
1060 tcg_gen_subi_i32(addr, REG(B11_8), 8);
1061 tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx);
1062 tcg_gen_mov_i32(REG(B11_8), addr);
1063 tcg_temp_free(addr);
1064 } else {
1065 TCGv addr;
1066 addr = tcg_temp_new_i32();
1067 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1068 tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
1069 tcg_temp_free(addr);
1070 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1071 }
1072 return;
1073 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
1074 CHECK_FPU_ENABLED
1075 {
1076 TCGv addr = tcg_temp_new_i32();
1077 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
1078 if (ctx->fpscr & FPSCR_SZ) {
1079 int fr = XREG(B11_8);
1080 tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
1081 tcg_gen_addi_i32(addr, addr, 4);
1082 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
1083 } else {
1084 tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
1085 }
1086 tcg_temp_free(addr);
1087 }
1088 return;
1089 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
1090 CHECK_FPU_ENABLED
1091 {
1092 TCGv addr = tcg_temp_new();
1093 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
1094 if (ctx->fpscr & FPSCR_SZ) {
1095 int fr = XREG(B7_4);
1096 tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
1097 tcg_gen_addi_i32(addr, addr, 4);
1098 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
1099 } else {
1100 tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
1101 }
1102 tcg_temp_free(addr);
1103 }
1104 return;
1105 case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1106 case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1107 case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1108 case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1109 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1110 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1111 {
1112 CHECK_FPU_ENABLED
1113 if (ctx->fpscr & FPSCR_PR) {
1114 TCGv_i64 fp0, fp1;
1115
1116 if (ctx->opcode & 0x0110)
1117 break; /* illegal instruction */
1118 fp0 = tcg_temp_new_i64();
1119 fp1 = tcg_temp_new_i64();
1120 gen_load_fpr64(fp0, DREG(B11_8));
1121 gen_load_fpr64(fp1, DREG(B7_4));
1122 switch (ctx->opcode & 0xf00f) {
1123 case 0xf000: /* fadd Rm,Rn */
1124 gen_helper_fadd_DT(fp0, fp0, fp1);
1125 break;
1126 case 0xf001: /* fsub Rm,Rn */
1127 gen_helper_fsub_DT(fp0, fp0, fp1);
1128 break;
1129 case 0xf002: /* fmul Rm,Rn */
1130 gen_helper_fmul_DT(fp0, fp0, fp1);
1131 break;
1132 case 0xf003: /* fdiv Rm,Rn */
1133 gen_helper_fdiv_DT(fp0, fp0, fp1);
1134 break;
1135 case 0xf004: /* fcmp/eq Rm,Rn */
1136 gen_helper_fcmp_eq_DT(fp0, fp1);
1137 return;
1138 case 0xf005: /* fcmp/gt Rm,Rn */
1139 gen_helper_fcmp_gt_DT(fp0, fp1);
1140 return;
1141 }
1142 gen_store_fpr64(fp0, DREG(B11_8));
1143 tcg_temp_free_i64(fp0);
1144 tcg_temp_free_i64(fp1);
1145 } else {
1146 switch (ctx->opcode & 0xf00f) {
1147 case 0xf000: /* fadd Rm,Rn */
1148 gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1149 break;
1150 case 0xf001: /* fsub Rm,Rn */
1151 gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1152 break;
1153 case 0xf002: /* fmul Rm,Rn */
1154 gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1155 break;
1156 case 0xf003: /* fdiv Rm,Rn */
1157 gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1158 break;
1159 case 0xf004: /* fcmp/eq Rm,Rn */
1160 gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1161 return;
1162 case 0xf005: /* fcmp/gt Rm,Rn */
1163 gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1164 return;
1165 }
1166 }
1167 }
1168 return;
1169 }
1170
1171 switch (ctx->opcode & 0xff00) {
1172 case 0xc900: /* and #imm,R0 */
1173 tcg_gen_andi_i32(REG(0), REG(0), B7_0);
1174 return;
1175 case 0xcd00: /* and.b #imm,@(R0,GBR) */
1176 {
1177 TCGv addr, val;
1178 addr = tcg_temp_new();
1179 tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1180 val = tcg_temp_new();
1181 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1182 tcg_gen_andi_i32(val, val, B7_0);
1183 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1184 tcg_temp_free(val);
1185 tcg_temp_free(addr);
1186 }
1187 return;
1188 case 0x8b00: /* bf label */
1189 CHECK_NOT_DELAY_SLOT
1190 gen_conditional_jump(ctx, ctx->pc + 2,
1191 ctx->pc + 4 + B7_0s * 2);
1192 ctx->bstate = BS_BRANCH;
1193 return;
1194 case 0x8f00: /* bf/s label */
1195 CHECK_NOT_DELAY_SLOT
1196 gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0);
1197 ctx->flags |= DELAY_SLOT_CONDITIONAL;
1198 return;
1199 case 0x8900: /* bt label */
1200 CHECK_NOT_DELAY_SLOT
1201 gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,
1202 ctx->pc + 2);
1203 ctx->bstate = BS_BRANCH;
1204 return;
1205 case 0x8d00: /* bt/s label */
1206 CHECK_NOT_DELAY_SLOT
1207 gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1);
1208 ctx->flags |= DELAY_SLOT_CONDITIONAL;
1209 return;
1210 case 0x8800: /* cmp/eq #imm,R0 */
1211 gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);
1212 return;
1213 case 0xc400: /* mov.b @(disp,GBR),R0 */
1214 {
1215 TCGv addr = tcg_temp_new();
1216 tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1217 tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1218 tcg_temp_free(addr);
1219 }
1220 return;
1221 case 0xc500: /* mov.w @(disp,GBR),R0 */
1222 {
1223 TCGv addr = tcg_temp_new();
1224 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1225 tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1226 tcg_temp_free(addr);
1227 }
1228 return;
1229 case 0xc600: /* mov.l @(disp,GBR),R0 */
1230 {
1231 TCGv addr = tcg_temp_new();
1232 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1233 tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
1234 tcg_temp_free(addr);
1235 }
1236 return;
1237 case 0xc000: /* mov.b R0,@(disp,GBR) */
1238 {
1239 TCGv addr = tcg_temp_new();
1240 tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1241 tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1242 tcg_temp_free(addr);
1243 }
1244 return;
1245 case 0xc100: /* mov.w R0,@(disp,GBR) */
1246 {
1247 TCGv addr = tcg_temp_new();
1248 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1249 tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1250 tcg_temp_free(addr);
1251 }
1252 return;
1253 case 0xc200: /* mov.l R0,@(disp,GBR) */
1254 {
1255 TCGv addr = tcg_temp_new();
1256 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1257 tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
1258 tcg_temp_free(addr);
1259 }
1260 return;
1261 case 0x8000: /* mov.b R0,@(disp,Rn) */
1262 {
1263 TCGv addr = tcg_temp_new();
1264 tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1265 tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1266 tcg_temp_free(addr);
1267 }
1268 return;
1269 case 0x8100: /* mov.w R0,@(disp,Rn) */
1270 {
1271 TCGv addr = tcg_temp_new();
1272 tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1273 tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1274 tcg_temp_free(addr);
1275 }
1276 return;
1277 case 0x8400: /* mov.b @(disp,Rn),R0 */
1278 {
1279 TCGv addr = tcg_temp_new();
1280 tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1281 tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1282 tcg_temp_free(addr);
1283 }
1284 return;
1285 case 0x8500: /* mov.w @(disp,Rn),R0 */
1286 {
1287 TCGv addr = tcg_temp_new();
1288 tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1289 tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1290 tcg_temp_free(addr);
1291 }
1292 return;
1293 case 0xc700: /* mova @(disp,PC),R0 */
1294 tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3);
1295 return;
1296 case 0xcb00: /* or #imm,R0 */
1297 tcg_gen_ori_i32(REG(0), REG(0), B7_0);
1298 return;
1299 case 0xcf00: /* or.b #imm,@(R0,GBR) */
1300 {
1301 TCGv addr, val;
1302 addr = tcg_temp_new();
1303 tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1304 val = tcg_temp_new();
1305 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1306 tcg_gen_ori_i32(val, val, B7_0);
1307 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1308 tcg_temp_free(val);
1309 tcg_temp_free(addr);
1310 }
1311 return;
1312 case 0xc300: /* trapa #imm */
1313 {
1314 TCGv imm;
1315 CHECK_NOT_DELAY_SLOT
1316 tcg_gen_movi_i32(cpu_pc, ctx->pc);
1317 imm = tcg_const_i32(B7_0);
1318 gen_helper_trapa(imm);
1319 tcg_temp_free(imm);
1320 ctx->bstate = BS_BRANCH;
1321 }
1322 return;
1323 case 0xc800: /* tst #imm,R0 */
1324 {
1325 TCGv val = tcg_temp_new();
1326 tcg_gen_andi_i32(val, REG(0), B7_0);
1327 gen_cmp_imm(TCG_COND_EQ, val, 0);
1328 tcg_temp_free(val);
1329 }
1330 return;
1331 case 0xcc00: /* tst.b #imm,@(R0,GBR) */
1332 {
1333 TCGv val = tcg_temp_new();
1334 tcg_gen_add_i32(val, REG(0), cpu_gbr);
1335 tcg_gen_qemu_ld8u(val, val, ctx->memidx);
1336 tcg_gen_andi_i32(val, val, B7_0);
1337 gen_cmp_imm(TCG_COND_EQ, val, 0);
1338 tcg_temp_free(val);
1339 }
1340 return;
1341 case 0xca00: /* xor #imm,R0 */
1342 tcg_gen_xori_i32(REG(0), REG(0), B7_0);
1343 return;
1344 case 0xce00: /* xor.b #imm,@(R0,GBR) */
1345 {
1346 TCGv addr, val;
1347 addr = tcg_temp_new();
1348 tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1349 val = tcg_temp_new();
1350 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1351 tcg_gen_xori_i32(val, val, B7_0);
1352 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1353 tcg_temp_free(val);
1354 tcg_temp_free(addr);
1355 }
1356 return;
1357 }
1358
1359 switch (ctx->opcode & 0xf08f) {
1360 case 0x408e: /* ldc Rm,Rn_BANK */
1361 CHECK_PRIVILEGED
1362 tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8));
1363 return;
1364 case 0x4087: /* ldc.l @Rm+,Rn_BANK */
1365 CHECK_PRIVILEGED
1366 tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx);
1367 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1368 return;
1369 case 0x0082: /* stc Rm_BANK,Rn */
1370 CHECK_PRIVILEGED
1371 tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4));
1372 return;
1373 case 0x4083: /* stc.l Rm_BANK,@-Rn */
1374 CHECK_PRIVILEGED
1375 {
1376 TCGv addr = tcg_temp_new();
1377 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1378 tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
1379 tcg_temp_free(addr);
1380 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1381 }
1382 return;
1383 }
1384
1385 switch (ctx->opcode & 0xf0ff) {
1386 case 0x0023: /* braf Rn */
1387 CHECK_NOT_DELAY_SLOT
1388 tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
1389 ctx->flags |= DELAY_SLOT;
1390 ctx->delayed_pc = (uint32_t) - 1;
1391 return;
1392 case 0x0003: /* bsrf Rn */
1393 CHECK_NOT_DELAY_SLOT
1394 tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1395 tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
1396 ctx->flags |= DELAY_SLOT;
1397 ctx->delayed_pc = (uint32_t) - 1;
1398 return;
1399 case 0x4015: /* cmp/pl Rn */
1400 gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);
1401 return;
1402 case 0x4011: /* cmp/pz Rn */
1403 gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);
1404 return;
1405 case 0x4010: /* dt Rn */
1406 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
1407 gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
1408 return;
1409 case 0x402b: /* jmp @Rn */
1410 CHECK_NOT_DELAY_SLOT
1411 tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1412 ctx->flags |= DELAY_SLOT;
1413 ctx->delayed_pc = (uint32_t) - 1;
1414 return;
1415 case 0x400b: /* jsr @Rn */
1416 CHECK_NOT_DELAY_SLOT
1417 tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1418 tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1419 ctx->flags |= DELAY_SLOT;
1420 ctx->delayed_pc = (uint32_t) - 1;
1421 return;
1422 case 0x400e: /* ldc Rm,SR */
1423 CHECK_PRIVILEGED
1424 tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
1425 ctx->bstate = BS_STOP;
1426 return;
1427 case 0x4007: /* ldc.l @Rm+,SR */
1428 CHECK_PRIVILEGED
1429 {
1430 TCGv val = tcg_temp_new();
1431 tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx);
1432 tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
1433 tcg_temp_free(val);
1434 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1435 ctx->bstate = BS_STOP;
1436 }
1437 return;
1438 case 0x0002: /* stc SR,Rn */
1439 CHECK_PRIVILEGED
1440 tcg_gen_mov_i32(REG(B11_8), cpu_sr);
1441 return;
1442 case 0x4003: /* stc SR,@-Rn */
1443 CHECK_PRIVILEGED
1444 {
1445 TCGv addr = tcg_temp_new();
1446 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1447 tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
1448 tcg_temp_free(addr);
1449 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1450 }
1451 return;
1452 #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
1453 case ldnum: \
1454 prechk \
1455 tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \
1456 return; \
1457 case ldpnum: \
1458 prechk \
1459 tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \
1460 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \
1461 return; \
1462 case stnum: \
1463 prechk \
1464 tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \
1465 return; \
1466 case stpnum: \
1467 prechk \
1468 { \
1469 TCGv addr = tcg_temp_new(); \
1470 tcg_gen_subi_i32(addr, REG(B11_8), 4); \
1471 tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \
1472 tcg_temp_free(addr); \
1473 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \
1474 } \
1475 return;
1476 LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {})
1477 LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED)
1478 LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
1479 LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)
1480 LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)
1481 LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})
1482 LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})
1483 LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {})
1484 LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED})
1485 case 0x406a: /* lds Rm,FPSCR */
1486 CHECK_FPU_ENABLED
1487 gen_helper_ld_fpscr(REG(B11_8));
1488 ctx->bstate = BS_STOP;
1489 return;
1490 case 0x4066: /* lds.l @Rm+,FPSCR */
1491 CHECK_FPU_ENABLED
1492 {
1493 TCGv addr = tcg_temp_new();
1494 tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
1495 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1496 gen_helper_ld_fpscr(addr);
1497 tcg_temp_free(addr);
1498 ctx->bstate = BS_STOP;
1499 }
1500 return;
1501 case 0x006a: /* sts FPSCR,Rn */
1502 CHECK_FPU_ENABLED
1503 tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);
1504 return;
1505 case 0x4062: /* sts FPSCR,@-Rn */
1506 CHECK_FPU_ENABLED
1507 {
1508 TCGv addr, val;
1509 val = tcg_temp_new();
1510 tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);
1511 addr = tcg_temp_new();
1512 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1513 tcg_gen_qemu_st32(val, addr, ctx->memidx);
1514 tcg_temp_free(addr);
1515 tcg_temp_free(val);
1516 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1517 }
1518 return;
1519 case 0x00c3: /* movca.l R0,@Rm */
1520 tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
1521 return;
1522 case 0x40a9:
1523 /* MOVUA.L @Rm,R0 (Rm) -> R0
1524 Load non-boundary-aligned data */
1525 tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
1526 return;
1527 case 0x40e9:
1528 /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm
1529 Load non-boundary-aligned data */
1530 tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
1531 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1532 return;
1533 case 0x0029: /* movt Rn */
1534 tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
1535 return;
1536 case 0x0093: /* ocbi @Rn */
1537 {
1538 TCGv dummy = tcg_temp_new();
1539 tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1540 tcg_temp_free(dummy);
1541 }
1542 return;
1543 case 0x00a3: /* ocbp @Rn */
1544 {
1545 TCGv dummy = tcg_temp_new();
1546 tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1547 tcg_temp_free(dummy);
1548 }
1549 return;
1550 case 0x00b3: /* ocbwb @Rn */
1551 {
1552 TCGv dummy = tcg_temp_new();
1553 tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1554 tcg_temp_free(dummy);
1555 }
1556 return;
1557 case 0x0083: /* pref @Rn */
1558 return;
1559 case 0x4024: /* rotcl Rn */
1560 {
1561 TCGv tmp = tcg_temp_new();
1562 tcg_gen_mov_i32(tmp, cpu_sr);
1563 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1564 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1565 gen_copy_bit_i32(REG(B11_8), 0, tmp, 0);
1566 tcg_temp_free(tmp);
1567 }
1568 return;
1569 case 0x4025: /* rotcr Rn */
1570 {
1571 TCGv tmp = tcg_temp_new();
1572 tcg_gen_mov_i32(tmp, cpu_sr);
1573 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1574 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1575 gen_copy_bit_i32(REG(B11_8), 31, tmp, 0);
1576 tcg_temp_free(tmp);
1577 }
1578 return;
1579 case 0x4004: /* rotl Rn */
1580 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1581 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1582 gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);
1583 return;
1584 case 0x4005: /* rotr Rn */
1585 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1586 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1587 gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);
1588 return;
1589 case 0x4000: /* shll Rn */
1590 case 0x4020: /* shal Rn */
1591 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1592 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1593 return;
1594 case 0x4021: /* shar Rn */
1595 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1596 tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
1597 return;
1598 case 0x4001: /* shlr Rn */
1599 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1600 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1601 return;
1602 case 0x4008: /* shll2 Rn */
1603 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);
1604 return;
1605 case 0x4018: /* shll8 Rn */
1606 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);
1607 return;
1608 case 0x4028: /* shll16 Rn */
1609 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);
1610 return;
1611 case 0x4009: /* shlr2 Rn */
1612 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);
1613 return;
1614 case 0x4019: /* shlr8 Rn */
1615 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);
1616 return;
1617 case 0x4029: /* shlr16 Rn */
1618 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
1619 return;
1620 case 0x401b: /* tas.b @Rn */
1621 {
1622 TCGv addr, val;
1623 addr = tcg_temp_local_new(TCG_TYPE_I32);
1624 tcg_gen_mov_i32(addr, REG(B11_8));
1625 val = tcg_temp_local_new(TCG_TYPE_I32);
1626 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1627 gen_cmp_imm(TCG_COND_EQ, val, 0);
1628 tcg_gen_ori_i32(val, val, 0x80);
1629 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1630 tcg_temp_free(val);
1631 tcg_temp_free(addr);
1632 }
1633 return;
1634 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1635 CHECK_FPU_ENABLED
1636 tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul);
1637 return;
1638 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1639 CHECK_FPU_ENABLED
1640 tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]);
1641 return;
1642 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1643 CHECK_FPU_ENABLED
1644 if (ctx->fpscr & FPSCR_PR) {
1645 TCGv_i64 fp;
1646 if (ctx->opcode & 0x0100)
1647 break; /* illegal instruction */
1648 fp = tcg_temp_new_i64();
1649 gen_helper_float_DT(fp, cpu_fpul);
1650 gen_store_fpr64(fp, DREG(B11_8));
1651 tcg_temp_free_i64(fp);
1652 }
1653 else {
1654 gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul);
1655 }
1656 return;
1657 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1658 CHECK_FPU_ENABLED
1659 if (ctx->fpscr & FPSCR_PR) {
1660 TCGv_i64 fp;
1661 if (ctx->opcode & 0x0100)
1662 break; /* illegal instruction */
1663 fp = tcg_temp_new_i64();
1664 gen_load_fpr64(fp, DREG(B11_8));
1665 gen_helper_ftrc_DT(cpu_fpul, fp);
1666 tcg_temp_free_i64(fp);
1667 }
1668 else {
1669 gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]);
1670 }
1671 return;
1672 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
1673 CHECK_FPU_ENABLED
1674 {
1675 gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1676 }
1677 return;
1678 case 0xf05d: /* fabs FRn/DRn */
1679 CHECK_FPU_ENABLED
1680 if (ctx->fpscr & FPSCR_PR) {
1681 if (ctx->opcode & 0x0100)
1682 break; /* illegal instruction */
1683 TCGv_i64 fp = tcg_temp_new_i64();
1684 gen_load_fpr64(fp, DREG(B11_8));
1685 gen_helper_fabs_DT(fp, fp);
1686 gen_store_fpr64(fp, DREG(B11_8));
1687 tcg_temp_free_i64(fp);
1688 } else {
1689 gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1690 }
1691 return;
1692 case 0xf06d: /* fsqrt FRn */
1693 CHECK_FPU_ENABLED
1694 if (ctx->fpscr & FPSCR_PR) {
1695 if (ctx->opcode & 0x0100)
1696 break; /* illegal instruction */
1697 TCGv_i64 fp = tcg_temp_new_i64();
1698 gen_load_fpr64(fp, DREG(B11_8));
1699 gen_helper_fsqrt_DT(fp, fp);
1700 gen_store_fpr64(fp, DREG(B11_8));
1701 tcg_temp_free_i64(fp);
1702 } else {
1703 gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1704 }
1705 return;
1706 case 0xf07d: /* fsrra FRn */
1707 CHECK_FPU_ENABLED
1708 break;
1709 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1710 CHECK_FPU_ENABLED
1711 if (!(ctx->fpscr & FPSCR_PR)) {
1712 tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
1713 }
1714 return;
1715 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1716 CHECK_FPU_ENABLED
1717 if (!(ctx->fpscr & FPSCR_PR)) {
1718 tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
1719 }
1720 return;
1721 case 0xf0ad: /* fcnvsd FPUL,DRn */
1722 CHECK_FPU_ENABLED
1723 {
1724 TCGv_i64 fp = tcg_temp_new_i64();
1725 gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);
1726 gen_store_fpr64(fp, DREG(B11_8));
1727 tcg_temp_free_i64(fp);
1728 }
1729 return;
1730 case 0xf0bd: /* fcnvds DRn,FPUL */
1731 CHECK_FPU_ENABLED
1732 {
1733 TCGv_i64 fp = tcg_temp_new_i64();
1734 gen_load_fpr64(fp, DREG(B11_8));
1735 gen_helper_fcnvds_DT_FT(cpu_fpul, fp);
1736 tcg_temp_free_i64(fp);
1737 }
1738 return;
1739 }
1740
1741 fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
1742 ctx->opcode, ctx->pc);
1743 gen_helper_raise_illegal_instruction();
1744 ctx->bstate = BS_EXCP;
1745 }
1746
1747 static void decode_opc(DisasContext * ctx)
1748 {
1749 uint32_t old_flags = ctx->flags;
1750
1751 _decode_opc(ctx);
1752
1753 if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
1754 if (ctx->flags & DELAY_SLOT_CLEARME) {
1755 gen_store_flags(0);
1756 } else {
1757 /* go out of the delay slot */
1758 uint32_t new_flags = ctx->flags;
1759 new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
1760 gen_store_flags(new_flags);
1761 }
1762 ctx->flags = 0;
1763 ctx->bstate = BS_BRANCH;
1764 if (old_flags & DELAY_SLOT_CONDITIONAL) {
1765 gen_delayed_conditional_jump(ctx);
1766 } else if (old_flags & DELAY_SLOT) {
1767 gen_jump(ctx);
1768 }
1769
1770 }
1771
1772 /* go into a delay slot */
1773 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
1774 gen_store_flags(ctx->flags);
1775 }
1776
1777 static inline void
1778 gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
1779 int search_pc)
1780 {
1781 DisasContext ctx;
1782 target_ulong pc_start;
1783 static uint16_t *gen_opc_end;
1784 CPUBreakpoint *bp;
1785 int i, ii;
1786 int num_insns;
1787 int max_insns;
1788
1789 pc_start = tb->pc;
1790 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1791 ctx.pc = pc_start;
1792 ctx.flags = (uint32_t)tb->flags;
1793 ctx.bstate = BS_NONE;
1794 ctx.sr = env->sr;
1795 ctx.fpscr = env->fpscr;
1796 ctx.memidx = (env->sr & SR_MD) ? 1 : 0;
1797 /* We don't know if the delayed pc came from a dynamic or static branch,
1798 so assume it is a dynamic branch. */
1799 ctx.delayed_pc = -1; /* use delayed pc from env pointer */
1800 ctx.tb = tb;
1801 ctx.singlestep_enabled = env->singlestep_enabled;
1802
1803 #ifdef DEBUG_DISAS
1804 if (loglevel & CPU_LOG_TB_CPU) {
1805 fprintf(logfile,
1806 "------------------------------------------------\n");
1807 cpu_dump_state(env, logfile, fprintf, 0);
1808 }
1809 #endif
1810
1811 ii = -1;
1812 num_insns = 0;
1813 max_insns = tb->cflags & CF_COUNT_MASK;
1814 if (max_insns == 0)
1815 max_insns = CF_COUNT_MASK;
1816 gen_icount_start();
1817 while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
1818 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
1819 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
1820 if (ctx.pc == bp->pc) {
1821 /* We have hit a breakpoint - make sure PC is up-to-date */
1822 tcg_gen_movi_i32(cpu_pc, ctx.pc);
1823 gen_helper_debug();
1824 ctx.bstate = BS_EXCP;
1825 break;
1826 }
1827 }
1828 }
1829 if (search_pc) {
1830 i = gen_opc_ptr - gen_opc_buf;
1831 if (ii < i) {
1832 ii++;
1833 while (ii < i)
1834 gen_opc_instr_start[ii++] = 0;
1835 }
1836 gen_opc_pc[ii] = ctx.pc;
1837 gen_opc_hflags[ii] = ctx.flags;
1838 gen_opc_instr_start[ii] = 1;
1839 gen_opc_icount[ii] = num_insns;
1840 }
1841 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1842 gen_io_start();
1843 #if 0
1844 fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
1845 fflush(stderr);
1846 #endif
1847 ctx.opcode = lduw_code(ctx.pc);
1848 decode_opc(&ctx);
1849 num_insns++;
1850 ctx.pc += 2;
1851 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
1852 break;
1853 if (env->singlestep_enabled)
1854 break;
1855 if (num_insns >= max_insns)
1856 break;
1857 #ifdef SH4_SINGLE_STEP
1858 break;
1859 #endif
1860 }
1861 if (tb->cflags & CF_LAST_IO)
1862 gen_io_end();
1863 if (env->singlestep_enabled) {
1864 tcg_gen_movi_i32(cpu_pc, ctx.pc);
1865 gen_helper_debug();
1866 } else {
1867 switch (ctx.bstate) {
1868 case BS_STOP:
1869 /* gen_op_interrupt_restart(); */
1870 /* fall through */
1871 case BS_NONE:
1872 if (ctx.flags) {
1873 gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME);
1874 }
1875 gen_goto_tb(&ctx, 0, ctx.pc);
1876 break;
1877 case BS_EXCP:
1878 /* gen_op_interrupt_restart(); */
1879 tcg_gen_exit_tb(0);
1880 break;
1881 case BS_BRANCH:
1882 default:
1883 break;
1884 }
1885 }
1886
1887 gen_icount_end(tb, num_insns);
1888 *gen_opc_ptr = INDEX_op_end;
1889 if (search_pc) {
1890 i = gen_opc_ptr - gen_opc_buf;
1891 ii++;
1892 while (ii <= i)
1893 gen_opc_instr_start[ii++] = 0;
1894 } else {
1895 tb->size = ctx.pc - pc_start;
1896 tb->icount = num_insns;
1897 }
1898
1899 #ifdef DEBUG_DISAS
1900 #ifdef SH4_DEBUG_DISAS
1901 if (loglevel & CPU_LOG_TB_IN_ASM)
1902 fprintf(logfile, "\n");
1903 #endif
1904 if (loglevel & CPU_LOG_TB_IN_ASM) {
1905 fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */
1906 target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
1907 fprintf(logfile, "\n");
1908 }
1909 #endif
1910 }
1911
1912 void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb)
1913 {
1914 gen_intermediate_code_internal(env, tb, 0);
1915 }
1916
1917 void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb)
1918 {
1919 gen_intermediate_code_internal(env, tb, 1);
1920 }
1921
1922 void gen_pc_load(CPUState *env, TranslationBlock *tb,
1923 unsigned long searched_pc, int pc_pos, void *puc)
1924 {
1925 env->pc = gen_opc_pc[pc_pos];
1926 env->flags = gen_opc_hflags[pc_pos];
1927 }
Samsung s3c2440 and arm920t support for the mini2440 dev board