hw/s3c.h

   1 /*
   2  * Samsung S3C2410A RISC Microprocessor support (ARM920T based SoC).
   3  *
   4  * Copyright (c) 2007 OpenMoko, Inc.
   5  * Author: Andrzej Zaborowski <andrew@openedhand.com>
   6  *
   7  * This code is licenced under the GNU GPL v2.
   8  */
   9 #ifndef S3C_H
  10 # define S3C_H  "s3c.h"
  11
  12 # include "qemu-common.h"
  13 # include "flash.h"
  14 # include "sd.h"
  15
  16 #define S3C_CPU_2410    0x32410002
  17 #define S3C_CPU_2440    0x32440001
  18
  19 /* Interrupt numbers */
  20 # define S3C_PIC_EINT0  0
  21 # define S3C_PIC_EINT1  1
  22 # define S3C_PIC_EINT2  2
  23 # define S3C_PIC_EINT3  3
  24 # define S3C_PIC_EINT4  4
  25 # define S3C_PIC_EINT8  5
  26 # define S3C_PIC_WDT    9
  27 # define S3C_PIC_TIMER0 10
  28 # define S3C_PIC_TIMER1 11
  29 # define S3C_PIC_TIMER2 12
  30 # define S3C_PIC_TIMER3 13
  31 # define S3C_PIC_TIMER4 14
  32 # define S3C_PIC_UART2  15
  33 # define S3C_PIC_LCD    16
  34 # define S3C_PIC_DMA0   17
  35 # define S3C_PIC_DMA1   18
  36 # define S3C_PIC_DMA2   19
  37 # define S3C_PIC_DMA3   20
  38 # define S3C_PIC_SDI    21
  39 # define S3C_PIC_SPI0   22
  40 # define S3C_PIC_UART1  23
  41 # define S3C_PIC_USBD   25
  42 # define S3C_PIC_USBH   26
  43 # define S3C_PIC_IIC    27
  44 # define S3C_PIC_UART0  28
  45 # define S3C_PIC_SPI1   29
  46 # define S3C_PIC_RTC    30
  47 # define S3C_PIC_ADC    31
  48 /* "Sub source" interrupt numbers */
  49 # define S3C_PICS_RXD0  32
  50 # define S3C_PICS_TXD0  33
  51 # define S3C_PICS_ERR0  34
  52 # define S3C_PICS_RXD1  35
  53 # define S3C_PICS_TXD1  36
  54 # define S3C_PICS_ERR1  37
  55 # define S3C_PICS_RXD2  38
  56 # define S3C_PICS_TXD2  39
  57 # define S3C_PICS_ERR2  40
  58 # define S3C_PICS_TC    41
  59 # define S3C_PICS_ADC   42
  60
  61 # define S3C_PIC_MAX    43
  62 /* External interrupt numbers */
  63 # define S3C_EINT(n)    ((n >= 8) ? (6 << 5) | (n - 8) : (5 << 5) | n)
  64
  65 /* DMA requests */
  66 # define S3C_RQ_nXDREQ0 0x00
  67 # define S3C_RQ_nXDREQ1 0x10
  68 # define S3C_RQ_I2SSDO  0x20
  69 # define S3C_RQ_UART2   0x30
  70 # define S3C_RQ_UART0   0x01
  71 # define S3C_RQ_UART1   0x11
  72 # define S3C_RQ_I2SSDI0 0x21
  73 # define S3C_RQ_SDI0    0x31
  74 # define S3C_RQ_SDI1    0x02
  75 # define S3C_RQ_I2SSDI1 0x12
  76 # define S3C_RQ_SDI2    0x22
  77 # define S3C_RQ_SPI1    0x32
  78 # define S3C_RQ_TIMER0  0x03
  79 # define S3C_RQ_SPI0    0x13
  80 # define S3C_RQ_TIMER1  0x23
  81 # define S3C_RQ_TIMER2  0x33
  82 # define S3C_RQ_USB_EP1 0x04
  83 # define S3C_RQ_USB_EP2 0x14
  84 # define S3C_RQ_USB_EP3 0x24
  85 # define S3C_RQ_USB_EP4 0x34
  86
  87 # define S3C_RQ_MAX     0x35
  88
  89 /* I/O port numbers */
  90 # define S3C_GP(b, n)   (((b) << 5) | n)
  91 # define S3C_GPA(n)     S3C_GP(0, n)
  92 # define S3C_GPB(n)     S3C_GP(1, n)
  93 # define S3C_GPC(n)     S3C_GP(2, n)
  94 # define S3C_GPD(n)     S3C_GP(3, n)
  95 # define S3C_GPE(n)     S3C_GP(4, n)
  96 # define S3C_GPF(n)     S3C_GP(5, n)
  97 # define S3C_GPG(n)     S3C_GP(6, n)
  98 # define S3C_GPH(n)     S3C_GP(7, n)
  99 # define S3C_GP_MAX     S3C_GP(8, 0)
 100
 101 # define S3C_RAM_BASE   0x30000000
 102 # define S3C_SRAM_BASE_NORBOOT  0x40000000
 103 # define S3C_SRAM_BASE_NANDBOOT 0x00000000
 104 # define S3C_SRAM_SIZE  0x00001000
 105
 106 # define S3C_XTAL_FREQ  32768           /* Hz */
 107
 108 /* s3c2410.c */
 109 struct s3c_pic_state_s;
 110 struct s3c_pic_state_s *s3c_pic_init(target_phys_addr_t base,
 111                 qemu_irq *arm_pic);
 112 qemu_irq *s3c_pic_get(struct s3c_pic_state_s *s);
 113
 114 struct s3c_dma_state_s;
 115 struct s3c_dma_state_s *s3c_dma_init(target_phys_addr_t base, qemu_irq *pic);
 116 qemu_irq *s3c_dma_get(struct s3c_dma_state_s *s);
 117
 118 /* GPIO TODO: remove this out, replace with qemu_irq or sumpthin */
 119 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
 120
 121 struct s3c_freq_s;
 122 struct s3c_timers_state_s;
 123 struct s3c_timers_state_s *s3c_timers_init(struct s3c_freq_s * freq,
 124                                 target_phys_addr_t base, qemu_irq *pic, qemu_irq *dma);
 125 void s3c_timers_cmp_handler_set(void *opaque, int line,
 126                 gpio_handler_t handler, void *cmp_opaque);
 127
 128 struct s3c_freq_s;
 129 struct s3c_uart_state_s;
 130 struct s3c_uart_state_s *s3c_uart_init(struct s3c_freq_s * freq, target_phys_addr_t base,
 131                 qemu_irq *irqs, qemu_irq *dma);
 132 void s3c_uart_attach(struct s3c_uart_state_s *s, CharDriverState *chr);
 133
 134 struct s3c_adc_state_s;
 135 struct s3c_adc_state_s *s3c_adc_init(target_phys_addr_t base, qemu_irq irq,
 136                 qemu_irq tcirq);
 137 void s3c_adc_setscale(struct s3c_adc_state_s *adc, const int m[]);
 138
 139 struct s3c_i2c_state_s;
 140 struct s3c_i2c_state_s *s3c_i2c_init(target_phys_addr_t base, qemu_irq irq);
 141 i2c_bus *s3c_i2c_bus(struct s3c_i2c_state_s *s);
 142
 143 struct s3c_i2s_state_s;
 144 struct s3c_i2s_state_s *s3c_i2s_init(target_phys_addr_t base, qemu_irq *dma);
 145
 146 struct s3c_freq_s;
 147 struct s3c_wdt_state_s;
 148 struct s3c_wdt_state_s *s3c_wdt_init(struct s3c_freq_s * freq, target_phys_addr_t base, qemu_irq irq);
 149
 150 /* s3c24xx_gpio.c */
 151 struct s3c_gpio_state_s;
 152 struct s3c_gpio_state_s *s3c_gpio_init(target_phys_addr_t base, qemu_irq *pic, uint32_t cpu_id);
 153 qemu_irq *s3c_gpio_in_get(struct s3c_gpio_state_s *s);
 154 void s3c_gpio_out_set(struct s3c_gpio_state_s *s, int line, qemu_irq handler);
 155 void s3c_gpio_setpwrstat(struct s3c_gpio_state_s *s, int stat);
 156 void s3c_gpio_reset(struct s3c_gpio_state_s *s);
 157 void s3c_gpio_set_dat(struct s3c_gpio_state_s *s, int gpio, int level);
 158
 159 /* s3c24xx_lcd.c */
 160 struct s3c_lcd_state_s;
 161 struct s3c_lcd_state_s *s3c_lcd_init(target_phys_addr_t base,
 162                 qemu_irq irq);
 163 void s3c_lcd_reset(struct s3c_lcd_state_s *s);
 164
 165 /* s3c24xx_mmci.c */
 166 struct s3c_mmci_state_s;
 167 struct s3c_mmci_state_s *s3c_mmci_init(target_phys_addr_t base, uint32_t cpu_id,
 168                 SDState *mmc, qemu_irq irq, qemu_irq *dma);
 169 void s3c_mmci_reset(struct s3c_mmci_state_s *s);
 170
 171 /* s3c24xx_rtc.c */
 172 struct s3c_rtc_state_s;
 173 struct s3c_rtc_state_s *s3c_rtc_init(target_phys_addr_t base, qemu_irq irq);
 174 void s3c_rtc_reset(struct s3c_rtc_state_s *s);
 175
 176 /* s3c24xx_udc.c */
 177 struct s3c_udc_state_s;
 178 struct s3c_udc_state_s *s3c_udc_init(target_phys_addr_t base, qemu_irq irq,
 179                 qemu_irq *dma);
 180 void s3c_udc_reset(struct s3c_udc_state_s *s);
 181
 182 struct s3c_nand_driver_s {
 183         void (*reset)(void * opaque);
 184         void (*setwp)(void * opaque, int wp);
 185         void (*reg)(void * opaque, struct nand_flash_s *chip);
 186 };
 187
 188 /* s3c2410_nand.c */
 189 struct s3c_nand_driver_s * s3c2410_nand_init(void);
 190 /* s3c2440_nand.c */
 191 struct s3c_nand_driver_s * s3c2440_nand_init(void);
 192
 193 /* s3c2410.c */
 194 struct s3c_spi_state_s;
 195 struct s3c_spi_state_s *s3c_spi_init(target_phys_addr_t base,
 196                 qemu_irq irq0, qemu_irq drq0, qemu_irq irq1, qemu_irq drq1,
 197                 struct s3c_gpio_state_s *gpio);
 198 void s3c_spi_attach(struct s3c_spi_state_s *s, int ch,
 199                 uint8_t (*txrx)(void *opaque, uint8_t value),
 200                 uint8_t (*btxrx)(void *opaque, uint8_t value), void *opaque);
 201
 202 struct s3c_freq_s {
 203         uint32_t        xtal;   /* 16 or 12Mhz : Set in init()*/
 204         /* These are recalculated when the guest code changes the clock registers */
 205         uint32_t        clk;    /* CPU clock */
 206         uint32_t        hclk;   /* SDRAM clock */
 207         uint32_t        pclk;   /* peripheral clock */
 208         uint32_t        uclk;
 209 };
 210
 211 struct s3c_state_s {
 212     CPUState *env;
 213     struct s3c_freq_s   clock;
 214     uint32_t cpu_id;
 215     qemu_irq *irq;
 216     qemu_irq *drq;
 217     struct s3c_pic_state_s *pic;
 218     struct s3c_dma_state_s *dma;
 219     struct s3c_gpio_state_s *io;
 220     struct s3c_lcd_state_s *lcd;
 221     struct s3c_timers_state_s *timers;
 222     struct s3c_uart_state_s *uart[3];
 223     struct s3c_mmci_state_s *mmci;
 224     struct s3c_adc_state_s *adc;
 225     struct s3c_i2c_state_s *i2c;
 226     struct s3c_i2s_state_s *i2s;
 227     struct s3c_rtc_state_s *rtc;
 228     struct s3c_spi_state_s *spi;
 229     struct s3c_udc_state_s *udc;
 230     struct s3c_wdt_state_s *wdt;
 231     struct s3c_nand_driver_s *nand;
 232
 233     /* Memory controller */
 234     target_phys_addr_t mc_base;
 235     uint32_t mc_regs[13];
 236
 237     /* Clock & power management */
 238     target_phys_addr_t clkpwr_base;
 239     uint32_t clkpwr_regs[6 + 1];        // 6 2410. 1 2440
 240 };
 241
 242 /* s3c2410.c */
 243 struct s3c_state_s *s3c24xx_init(uint32_t cpu_id, uint32_t xtal, unsigned int sdram_size, uint32_t sram_address,
 244                 SDState *mmc);
 245
 246
 247 struct s3c_i2s_state_s { /* XXX move to .c */
 248     target_phys_addr_t base;
 249     qemu_irq *dma;
 250     void (*data_req)(void *, int, int);
 251
 252     uint16_t control;
 253     uint16_t mode;
 254     uint16_t prescaler;
 255     uint16_t fcontrol;
 256
 257     int tx_en;
 258     int rx_en;
 259     int tx_len;
 260     int rx_len;
 261     void (*codec_out)(void *, uint32_t);
 262     uint32_t (*codec_in)(void *);
 263     void *opaque;
 264
 265     uint16_t buffer;
 266     int cycle;
 267 };
 268
 269 #endif  /* S3C_H */