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[S3C2440] Added a i2c register
[qemu/mini2440.git] / hw / s3c2410.c
blob637f47fc2bbc0c452f3e4fa6a83b7abfd60b7b61
1 /*
2 * Samsung S3C2410A RISC Microprocessor support (ARM920T based SoC).
3 *
4 * Copyright (c) 2007 OpenMoko, Inc.
5 * Author: Andrzej Zaborowski <andrew@openedhand.com>
6 * With: Michel Pollet <buserror@gmail.com>
7 *
8 * This code is licenced under the GNU GPL v2.
9 */
10
11 #include "s3c.h"
12 #include "qemu-timer.h"
13 #include "qemu-char.h"
14 #include "hw.h"
15 #include "console.h"
16 #include "devices.h"
17 #include "arm-misc.h"
18 #include "i2c.h"
19 #include "pxa.h"
20 #include "sysemu.h"
21
22 /* Interrupt controller */
23 struct s3c_pic_state_s {
24 target_phys_addr_t base;
25 qemu_irq *parent_pic;
26 qemu_irq *irqs;
27
28 uint32_t srcpnd;
29 uint32_t intpnd;
30 uint32_t intmsk;
31 uint32_t intmod;
32 uint32_t priority;
33 int intoffset;
34 uint32_t subsrcpnd;
35 uint32_t intsubmsk;
36 };
37
38 static void s3c_pic_update(struct s3c_pic_state_s *s)
39 {
40 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ],
41 s->srcpnd & s->intmod);
42 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ],
43 s->intpnd & ~s->intmsk & ~s->intmod);
44 }
45
46 /*
47 * Performs interrupt arbitration and notifies the CPU.
48 *
49 * Since it's a complex logic which cannot be relied on by the OS
50 * anyway - first because real hardware doesn't do it accurately,
51 * second because it only matters when interrupts occur at the
52 * same time which normally can't be predicted - we use a simpler
53 * version for non-debug runs.
54 */
55 #ifdef DEBUG
56 static const uint32_t s3c_arbmsk[6] = {
57 0x0000000f,
58 0x000003f0,
59 0x0000fc00,
60 0x003f0000,
61 0x0fc00000,
62 0xf0000000,
63 };
64
65 # define S3C_ARB_SEL(i) ((s->priority >> (7 + (i << 1))) & 3)
66 # define S3C_ARB_MODE(i) ((s->priority >> i) & 1)
67 # define S3C_ARB_SEL_SET(i, v) \
68 s->priority &= ~(3 << (7 + (i << 1))); \
69 s->priority |= v << (7 + (i << 1));
70
71 static void s3c_pic_arbitrate(struct s3c_pic_state_s *s)
72 {
73 uint32_t pnd = s->srcpnd & ~s->intmsk & ~s->intmod;
74 int offset, i, arb;
75 if (s->intpnd || !pnd) {
76 s3c_pic_update(s);
77 return;
78 }
79
80 if (pnd & s3c_arbmsk[0]) {
81 offset = 0;
82 arb = 0;
83 } else if (pnd & 0x0ffffff0) {
84 i = S3C_ARB_SEL(6);
85 i ^= i << 1;
86 if (!(pnd & s3c_arbmsk[1 + (i & 3)]))
87 if (!(pnd & s3c_arbmsk[1 + (++ i & 3)]))
88 if (!(pnd & s3c_arbmsk[1 + (++ i & 3)]))
89 i ++;
90
91 if (S3C_ARB_MODE(6))
92 S3C_ARB_SEL_SET(6, ((i + 1) & 3));
93 offset = (i & 3) * 6 + 4;
94 if (pnd & (1 << offset))
95 goto known_offset;
96 else if (!(pnd & (0x1f << offset))) {
97 offset += 5;
98 goto known_offset;
99 }
100 offset ++;
101 arb = (i & 3) + 1;
102 } else {
103 arb = 5;
104 offset = 28;
105 }
106
107 pnd >>= offset;
108 i = S3C_ARB_SEL(arb);
109 i ^= i << 1;
110 if (!(pnd & (1 << (i & 3))))
111 if (!(pnd & (1 << (++ i & 3))))
112 if (!(pnd & (1 << (++ i & 3))))
113 i ++;
114
115 if (S3C_ARB_MODE(arb))
116 S3C_ARB_SEL_SET(arb, ((i + 1) & 3));
117 offset += i & 3;
118 known_offset:
119 s->intoffset = offset;
120 s->intpnd = 1 << offset;
121 s3c_pic_update(s);
122 }
123 #else
124 inline static void s3c_pic_arbitrate(struct s3c_pic_state_s *s)
125 {
126 uint32_t pnd = s->srcpnd & ~s->intmsk & ~s->intmod;
127 if (pnd && !s->intpnd)
128 s->intpnd = 1 << (s->intoffset = ffs(pnd) - 1);
129 s3c_pic_update(s);
130 }
131 #endif
132
133 static const int s3c_sub_src_map[] = {
134 [S3C_PICS_RXD0 & 31] = S3C_PIC_UART0,
135 [S3C_PICS_TXD0 & 31] = S3C_PIC_UART0,
136 [S3C_PICS_ERR0 & 31] = S3C_PIC_UART0,
137 [S3C_PICS_RXD1 & 31] = S3C_PIC_UART1,
138 [S3C_PICS_TXD1 & 31] = S3C_PIC_UART1,
139 [S3C_PICS_ERR1 & 31] = S3C_PIC_UART1,
140 [S3C_PICS_RXD2 & 31] = S3C_PIC_UART2,
141 [S3C_PICS_TXD2 & 31] = S3C_PIC_UART2,
142 [S3C_PICS_ERR2 & 31] = S3C_PIC_UART2,
143 [S3C_PICS_TC & 31] = S3C_PIC_ADC,
144 [S3C_PICS_ADC & 31] = S3C_PIC_ADC,
145 };
146
147 static void s3c_pic_subupdate(struct s3c_pic_state_s *s)
148 {
149 int next;
150 const int *sub = &s3c_sub_src_map[-1];
151 uint32_t pnd = s->subsrcpnd & ~s->intsubmsk;
152 while ((next = ffs(pnd))) {
153 sub += next;
154 pnd >>= next;
155 s->srcpnd |= 1 << *sub;
156 }
157 s3c_pic_arbitrate(s);
158 }
159
160 static void s3c_pic_set_irq(void *opaque, int irq, int req)
161 {
162 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
163 uint32_t mask;
164 /* This interrupt controller doesn't clear any request signals
165 * or register bits automatically. */
166 if (!req)
167 return;
168
169 if (irq & 32) {
170 irq &= 31;
171 s->subsrcpnd |= 1 << irq;
172 if (s->intsubmsk & (1 << irq))
173 return;
174 else
175 irq = s3c_sub_src_map[irq];
176 }
177 s->srcpnd |= (mask = 1 << irq);
178
179 /* A FIQ */
180 if (s->intmod & mask)
181 qemu_irq_raise(s->parent_pic[ARM_PIC_CPU_FIQ]);
182 else if (!s->intpnd && !(s->intmsk & mask)) {
183 #ifdef DEBUG
184 s3c_pic_arbitrate(s);
185 #else
186 s->intpnd = mask;
187 s->intoffset = irq;
188 qemu_irq_raise(s->parent_pic[ARM_PIC_CPU_IRQ]);
189 #endif
190 }
191 }
192
193 static void s3c_pic_reset(struct s3c_pic_state_s *s)
194 {
195 s->srcpnd = 0;
196 s->intpnd = 0;
197 s->intmsk = 0xffffffff;
198 s->intmod = 0;
199 s->priority = 0x7f;
200 s->intoffset = 0;
201 s->subsrcpnd = 0;
202 s->intsubmsk = 0x7ff;
203 s3c_pic_update(s);
204 }
205
206 #define S3C_SRCPND 0x00 /* Source Pending register */
207 #define S3C_INTMOD 0x04 /* Source Mode register */
208 #define S3C_INTMSK 0x08 /* Interrupt Mask register */
209 #define S3C_PRIORITY 0x0c /* Priority register */
210 #define S3C_INTPND 0x10 /* Interrupt Pending register */
211 #define S3C_INTOFFSET 0x14 /* Interrupt Offset register */
212 #define S3C_SUBSRCPND 0x18 /* Sub Source Pending register */
213 #define S3C_INTSUBMSK 0x1c /* Interrupt Sub Mask register */
214
215 static uint32_t s3c_pic_read(void *opaque, target_phys_addr_t addr)
216 {
217 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
218
219 switch (addr) {
220 case S3C_SRCPND:
221 return s->srcpnd;
222 case S3C_INTPND:
223 return s->intpnd;
224 case S3C_INTMSK:
225 return s->intmsk;
226 case S3C_INTMOD:
227 return s->intmod;
228 case S3C_PRIORITY:
229 return s->priority;
230 case S3C_INTOFFSET:
231 return s->intoffset;
232 case S3C_SUBSRCPND:
233 return s->subsrcpnd;
234 case S3C_INTSUBMSK:
235 return s->intsubmsk;
236 default:
237 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
238 break;
239 }
240 return 0;
241 }
242
243 static void s3c_pic_write(void *opaque, target_phys_addr_t addr,
244 uint32_t value)
245 {
246 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
247
248 switch (addr) {
249 case S3C_SRCPND:
250 s->srcpnd &= ~value;
251 if (value & s->intmod)
252 s3c_pic_update(s);
253 break;
254 case S3C_INTPND:
255 if (s->intpnd & value) {
256 s->intpnd = 0;
257 s->intoffset = 0;
258 s3c_pic_arbitrate(s);
259 }
260 break;
261 case S3C_INTMSK:
262 s->intmsk = value;
263 if (s->intpnd & value) {
264 s->intpnd = 0;
265 s->intoffset = 0;
266 }
267 s3c_pic_arbitrate(s);
268 break;
269 case S3C_INTMOD:
270 s->intmod = value;
271 break;
272 case S3C_PRIORITY:
273 s->priority = value;
274 break;
275 case S3C_SUBSRCPND:
276 s->subsrcpnd &= ~value;
277 break;
278 case S3C_INTSUBMSK:
279 s->intsubmsk = value;
280 s3c_pic_subupdate(s);
281 break;
282 default:
283 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
284 }
285 }
286
287 static CPUReadMemoryFunc *s3c_pic_readfn[] = {
288 s3c_pic_read,
289 s3c_pic_read,
290 s3c_pic_read,
291 };
292
293 static CPUWriteMemoryFunc *s3c_pic_writefn[] = {
294 s3c_pic_write,
295 s3c_pic_write,
296 s3c_pic_write,
297 };
298
299 static void s3c_pic_save(QEMUFile *f, void *opaque)
300 {
301 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
302 qemu_put_be32s(f, &s->srcpnd);
303 qemu_put_be32s(f, &s->intpnd);
304 qemu_put_be32s(f, &s->intmsk);
305 qemu_put_be32s(f, &s->intmod);
306 qemu_put_be32s(f, &s->priority);
307 qemu_put_be32s(f, &s->subsrcpnd);
308 qemu_put_be32s(f, &s->intsubmsk);
309 qemu_put_be32(f, s->intoffset);
310 }
311
312 static int s3c_pic_load(QEMUFile *f, void *opaque, int version_id)
313 {
314 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
315 qemu_get_be32s(f, &s->srcpnd);
316 qemu_get_be32s(f, &s->intpnd);
317 qemu_get_be32s(f, &s->intmsk);
318 qemu_get_be32s(f, &s->intmod);
319 qemu_get_be32s(f, &s->priority);
320 qemu_get_be32s(f, &s->subsrcpnd);
321 qemu_get_be32s(f, &s->intsubmsk);
322 s->intoffset = qemu_get_be32(f);
323 s3c_pic_update(s);
324 return 0;
325 }
326
327 struct s3c_pic_state_s *s3c_pic_init(target_phys_addr_t base,
328 qemu_irq *arm_pic)
329 {
330 int iomemtype;
331 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *)
332 qemu_mallocz(sizeof(struct s3c_pic_state_s));
333
334 s->base = base;
335 s->parent_pic = arm_pic;
336 s->irqs = qemu_allocate_irqs(s3c_pic_set_irq, s, S3C_PIC_MAX);
337
338 s3c_pic_reset(s);
339
340 iomemtype = cpu_register_io_memory(0, s3c_pic_readfn,
341 s3c_pic_writefn, s);
342 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
343
344 register_savevm("s3c24xx_pic", 0, 0, s3c_pic_save, s3c_pic_load, s);
345
346 return s;
347 }
348
349 qemu_irq *s3c_pic_get(struct s3c_pic_state_s *s)
350 {
351 return s->irqs;
352 }
353
354 /* Memory controller */
355 #define S3C_BWSCON 0x00 /* Bus Width & Wait Control register */
356 #define S3C_BANKCON0 0x04 /* Bank 0 Control register */
357 #define S3C_BANKCON1 0x08 /* Bank 1 Control register */
358 #define S3C_BANKCON2 0x0c /* Bank 2 Control register */
359 #define S3C_BANKCON3 0x10 /* Bank 3 Control register */
360 #define S3C_BANKCON4 0x14 /* Bank 4 Control register */
361 #define S3C_BANKCON5 0x18 /* Bank 5 Control register */
362 #define S3C_BANKCON6 0x1c /* Bank 6 Control register */
363 #define S3C_BANKCON7 0x20 /* Bank 7 Control register */
364 #define S3C_REFRESH 0x24 /* SDRAM Refresh Control register */
365 #define S3C_BANKSIZE 0x28 /* Flexible Bank Size register */
366 #define S3C_MRSRB6 0x2c /* Bank 6 Mode Set register */
367 #define S3C_MRSRB7 0x30 /* Bank 6 Mode Set register */
368
369 static void s3c_mc_reset(struct s3c_state_s *s)
370 {
371 s->mc_regs[S3C_BWSCON >> 2] = 0x0000000;
372 s->mc_regs[S3C_BANKCON0 >> 2] = 0x0700;
373 s->mc_regs[S3C_BANKCON1 >> 2] = 0x0700;
374 s->mc_regs[S3C_BANKCON2 >> 2] = 0x0700;
375 s->mc_regs[S3C_BANKCON3 >> 2] = 0x0700;
376 s->mc_regs[S3C_BANKCON4 >> 2] = 0x0700;
377 s->mc_regs[S3C_BANKCON5 >> 2] = 0x0700;
378 s->mc_regs[S3C_BANKCON6 >> 2] = 0x18008;
379 s->mc_regs[S3C_BANKCON7 >> 2] = 0x18008;
380 s->mc_regs[S3C_REFRESH >> 2] = 0xac0000;
381 s->mc_regs[S3C_BANKSIZE >> 2] = 0x2;
382 s->mc_regs[S3C_MRSRB6 >> 2] = 0x00;
383 s->mc_regs[S3C_MRSRB7 >> 2] = 0x00;
384 }
385
386 static uint32_t s3c_mc_read(void *opaque, target_phys_addr_t addr)
387 {
388 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
389
390 switch (addr >> 2) {
391 case S3C_BWSCON ... S3C_MRSRB7:
392 return s->mc_regs[addr >> 2];
393 default:
394 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
395 break;
396 }
397 return 0;
398 }
399
400 static void s3c_mc_write(void *opaque, target_phys_addr_t addr,
401 uint32_t value)
402 {
403 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
404
405 switch (addr >> 2) {
406 case S3C_BWSCON ... S3C_MRSRB7:
407 s->mc_regs[addr >> 2] = value;
408 break;
409 default:
410 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
411 }
412 }
413
414 static CPUReadMemoryFunc *s3c_mc_readfn[] = {
415 s3c_mc_read,
416 s3c_mc_read,
417 s3c_mc_read,
418 };
419
420 static CPUWriteMemoryFunc *s3c_mc_writefn[] = {
421 s3c_mc_write,
422 s3c_mc_write,
423 s3c_mc_write,
424 };
425
426 static void s3c_mc_save(QEMUFile *f, void *opaque)
427 {
428 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
429 int i;
430 for (i = 0; i < 13; i ++)
431 qemu_put_be32s(f, &s->mc_regs[i]);
432 }
433
434 static int s3c_mc_load(QEMUFile *f, void *opaque, int version_id)
435 {
436 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
437 int i;
438 for (i = 0; i < 13; i ++)
439 qemu_get_be32s(f, &s->mc_regs[i]);
440 return 0;
441 }
442
443 /* Clock & power management */
444 #define S3C_LOCKTIME 0x00 /* PLL Lock Time Count register */
445 #define S3C_MPLLCON 0x04 /* MPLL Configuration register */
446 #define S3C_UPLLCON 0x08 /* UPLL Configuration register */
447 #define S3C_CLKCON 0x0c /* Clock Generator Control register */
448 #define S3C_CLKSLOW 0x10 /* Slow Clock Control register */
449 #define S3C_CLKDIVN 0x14 /* Clock Divider Control register */
450
451 #define S3C2440_CAMDIVN 0x18 /* Camera Clock Divider register */
452
453 static void s3c_clkpwr_reset(struct s3c_state_s *s)
454 {
455 s->clkpwr_regs[S3C_LOCKTIME >> 2] = 0x00ffffff;
456 s->clkpwr_regs[S3C_MPLLCON >> 2] = 0x0005c080;
457 s->clkpwr_regs[S3C_UPLLCON >> 2] = 0x00028080;
458 s->clkpwr_regs[S3C_CLKCON >> 2] = 0x0007fff0;
459 s->clkpwr_regs[S3C_CLKSLOW >> 2] = 0x00000004;
460 s->clkpwr_regs[S3C_CLKDIVN >> 2] = 0x00000000;
461 s->clkpwr_regs[S3C2440_CAMDIVN >> 2] = 0x00000000;
462 }
463
464 static uint32_t s3c_clkpwr_read(void *opaque, target_phys_addr_t addr)
465 {
466 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
467
468 switch (addr) {
469 case S3C_LOCKTIME ... S3C_CLKDIVN:
470 return s->clkpwr_regs[addr >> 2];
471 case S3C2440_CAMDIVN:
472 if (s->cpu_id == S3C_CPU_2440)
473 return s->clkpwr_regs[addr >> 2];
474 default:
475 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
476 break;
477 }
478 return 0;
479 }
480
481 static void s3c_clkpwr_write(void *opaque, target_phys_addr_t addr,
482 uint32_t value)
483 {
484 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
485
486 switch (addr) {
487 case S3C_LOCKTIME:
488 case S3C_MPLLCON:
489 case S3C_UPLLCON:
490 case S3C_CLKDIVN:
491 s->clkpwr_regs[addr >> 2] = value;
492 break;
493 case S3C_CLKCON:
494 if (value & (1 << 3)) {
495 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
496 printf("%s: processor powered off\n", __FUNCTION__);
497 s3c_gpio_setpwrstat(s->io, 2);
498 #if 0
499 cpu_reset(s->env);
500 s->env->regs[15] = 0; /* XXX */
501 #endif
502 } else
503 if (value & (1 << 2)) /* Normal IDLE mode */
504 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
505 if ((s->clkpwr_regs[addr >> 2] ^ value) & 1)
506 printf("%s: SPECIAL mode %s\n", __FUNCTION__,
507 (value & 1) ? "on" : "off");
508 s->clkpwr_regs[addr >> 2] = value;
509 break;
510 case S3C_CLKSLOW:
511 if ((s->clkpwr_regs[addr >> 2] ^ value) & (1 << 4))
512 printf("%s: SLOW mode %s\n", __FUNCTION__,
513 (value & (1 << 4)) ? "on" : "off");
514 s->clkpwr_regs[addr >> 2] = value;
515 break;
516 case S3C2440_CAMDIVN:
517 if (s->cpu_id == S3C_CPU_2440) {
518 s->clkpwr_regs[addr >> 2] = value;
519 break;
520 }
521 default:
522 printf("%s: Bad register 0x%x (cpu %08x)\n", __FUNCTION__, /*(unsigned long)*/addr, s->cpu_id);
523 }
524 }
525
526 static CPUReadMemoryFunc *s3c_clkpwr_readfn[] = {
527 s3c_clkpwr_read,
528 s3c_clkpwr_read,
529 s3c_clkpwr_read,
530 };
531
532 static CPUWriteMemoryFunc *s3c_clkpwr_writefn[] = {
533 s3c_clkpwr_write,
534 s3c_clkpwr_write,
535 s3c_clkpwr_write,
536 };
537
538 static void s3c_clkpwr_save(QEMUFile *f, void *opaque)
539 {
540 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
541 int i;
542 for (i = 0; i < 7; i ++)
543 qemu_put_be32s(f, &s->clkpwr_regs[i]);
544 }
545
546 static int s3c_clkpwr_load(QEMUFile *f, void *opaque, int version_id)
547 {
548 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
549 int i;
550 for (i = 0; i < 7; i ++)
551 qemu_get_be32s(f, &s->clkpwr_regs[i]);
552 return 0;
553 }
554
555 /* DMA controller */
556 #define S3C_DMA_CH_N 4
557
558 struct s3c_dma_ch_state_s;
559 struct s3c_dma_state_s { /* Modelled as an interrupt controller */
560 target_phys_addr_t base;
561 qemu_irq *drqs;
562 struct s3c_dma_ch_state_s {
563 qemu_irq intr;
564 int curr_tc;
565 int req;
566 int running;
567 uint32_t con;
568 uint32_t isrc;
569 uint32_t isrcc;
570 uint32_t idst;
571 uint32_t idstc;
572 uint32_t csrc;
573 uint32_t cdst;
574 uint32_t mask;
575 } ch[S3C_DMA_CH_N];
576 };
577
578 static inline void s3c_dma_ch_run(struct s3c_dma_state_s *s,
579 struct s3c_dma_ch_state_s *ch)
580 {
581 int width, burst, t;
582 uint8_t buffer[4];
583 width = 1 << ((ch->con >> 20) & 3); /* DSZ */
584 burst = (ch->con & (1 << 28)) ? 4 : 1; /* TSZ */
585
586 while (!ch->running && ch->curr_tc > 0 && ch->req &&
587 (ch->mask & (1 << 1))) { /* ON_OFF */
588 if (width > sizeof(buffer)) {
589 printf("%s: wrong access width\n", __FUNCTION__);
590 return;
591 }
592 ch->running = 1;
593 while (ch->curr_tc --) {
594 for (t = 0; t < burst; t ++) {
595 cpu_physical_memory_read(ch->csrc, buffer, width);
596 cpu_physical_memory_write(ch->cdst, buffer, width);
597
598 if (!(ch->isrcc & 1)) /* INT */
599 ch->csrc += width;
600 if (!(ch->idstc & 1)) /* INT */
601 ch->cdst += width;
602 }
603
604 if (!(ch->con & (1 << 27)) && !ch->req) /* SERVMODE */
605 break;
606 }
607 ch->running = 0;
608
609 if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
610 ch->req = 0;
611 }
612
613 if (ch->curr_tc <= 0) {
614 if (ch->con & (1 << 22)) /* RELOAD */
615 ch->mask &= ~(1 << 1); /* ON_OFF */
616 else {
617 if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
618 printf("%s: auto-reload software controlled transfer\n",
619 __FUNCTION__);
620 break;
621 }
622 ch->csrc = ch->isrc; /* S_ADDR */
623 ch->cdst = ch->idst; /* D_ADDR */
624 ch->curr_tc = ch->con & 0xfffff; /* TC */
625 ch->con |= 1 << 22; /* ON_OFF */
626 }
627
628 if (ch->con & (1 << 31)) /* DMD_HS */
629 ch->req = 0;
630
631 if (ch->con & (1 << 29)) { /* INT */
632 qemu_irq_raise(ch->intr);
633 /* Give the system a chance to respond. */
634 break;
635 }
636 }
637 }
638 }
639
640 static void s3c_dma_reset(struct s3c_dma_state_s *s)
641 {
642 int i;
643 for (i = 0; i < S3C_DMA_CH_N; i ++) {
644 s->ch[i].curr_tc = 0;
645 s->ch[i].csrc = 0;
646 s->ch[i].isrc = 0;
647 s->ch[i].isrcc = 0;
648 s->ch[i].cdst = 0;
649 s->ch[i].idst = 0;
650 s->ch[i].idstc = 0;
651 s->ch[i].con = 0;
652 s->ch[i].csrc = 0;
653 s->ch[i].cdst = 0;
654 s->ch[i].mask = 0;
655 }
656 }
657
658 static void s3c_dma_dreq(void *opaque, int line, int req)
659 {
660 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
661 struct s3c_dma_ch_state_s *ch = &s->ch[line >> 4];
662
663 if (ch->con & (1 << 23)) /* SWHW_SEL */
664 if (((ch->con >> 24) & 7) == (line & 7)) { /* HWSRCSEL */
665 ch->req = req;
666 s3c_dma_ch_run(s, ch);
667 }
668 }
669
670 #define S3C_DISRC 0x00 /* DMA Initial Source register */
671 #define S3C_DISRCC 0x04 /* DMA Initial Source Control register */
672 #define S3C_DIDST 0x08 /* DMA Initial Destination register */
673 #define S3C_DIDSTC 0x0c /* DMA Initial Destination Control register */
674 #define S3C_DCON 0x10 /* DMA Control register */
675 #define S3C_DSTAT 0x14 /* DMA Count register */
676 #define S3C_DCSRC 0x18 /* DMA Current Source register */
677 #define S3C_DCDST 0x1c /* DMA Current Destination register */
678 #define S3C_DMASKTRIG 0x20 /* DMA Mask Trigger register */
679
680 static uint32_t s3c_dma_read(void *opaque, target_phys_addr_t addr)
681 {
682 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
683 struct s3c_dma_ch_state_s *ch = 0;
684
685 if (addr >= 0 && addr <= (S3C_DMA_CH_N << 6)) {
686 ch = &s->ch[addr >> 6];
687 addr &= 0x3f;
688 }
689
690 switch (addr) {
691 case S3C_DISRC:
692 return ch->isrc;
693 case S3C_DISRCC:
694 return ch->isrcc;
695 case S3C_DIDST:
696 return ch->idst;
697 case S3C_DIDSTC:
698 return ch->idstc;
699 case S3C_DCON:
700 return ch->con;
701 case S3C_DSTAT:
702 return ch->curr_tc;
703 case S3C_DCSRC:
704 return ch->csrc;
705 case S3C_DCDST:
706 return ch->cdst;
707 case S3C_DMASKTRIG:
708 return ch->mask;
709 default:
710 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
711 break;
712 }
713 return 0;
714 }
715
716 static void s3c_dma_write(void *opaque, target_phys_addr_t addr,
717 uint32_t value)
718 {
719 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
720 struct s3c_dma_ch_state_s *ch = 0;
721
722 if (addr >= 0 && addr <= (S3C_DMA_CH_N << 6)) {
723 ch = &s->ch[addr >> 6];
724 addr &= 0x3f;
725 }
726
727 switch (addr) {
728 case S3C_DCON:
729 ch->con = value;
730 break;
731 case S3C_DISRC:
732 ch->isrc = value;
733 break;
734 case S3C_DISRCC:
735 ch->isrcc = value;
736 break;
737 case S3C_DIDST:
738 ch->idst = value;
739 break;
740 case S3C_DIDSTC:
741 ch->idstc = value;
742 break;
743 case S3C_DMASKTRIG:
744 if (~ch->mask & value & (1 << 1)) { /* ON_OFF */
745 ch->curr_tc = ch->con & 0xfffff; /* TC */
746 ch->csrc = ch->isrc; /* S_ADDR */
747 ch->cdst = ch->idst; /* D_ADDR */
748 }
749
750 ch->mask = value;
751 if (value & (1 << 2)) { /* STOP */
752 ch->mask &= ~(3 << 1); /* ON_OFF */
753 } else if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
754 ch->req = value & 1; /* SW_TRIG */
755 s3c_dma_ch_run(s, ch);
756 }
757 break;
758 default:
759 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
760 }
761 }
762
763 static CPUReadMemoryFunc *s3c_dma_readfn[] = {
764 s3c_dma_read,
765 s3c_dma_read,
766 s3c_dma_read,
767 };
768
769 static CPUWriteMemoryFunc *s3c_dma_writefn[] = {
770 s3c_dma_write,
771 s3c_dma_write,
772 s3c_dma_write,
773 };
774
775 static void s3c_dma_save(QEMUFile *f, void *opaque)
776 {
777 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
778 int i;
779 for (i = 0; i < S3C_DMA_CH_N; i ++) {
780 qemu_put_be32(f, s->ch[i].curr_tc);
781 qemu_put_be32(f, s->ch[i].req);
782 qemu_put_be32s(f, &s->ch[i].con);
783 qemu_put_be32s(f, &s->ch[i].isrc);
784 qemu_put_be32s(f, &s->ch[i].isrcc);
785 qemu_put_be32s(f, &s->ch[i].idst);
786 qemu_put_be32s(f, &s->ch[i].idstc);
787 qemu_put_be32s(f, &s->ch[i].csrc);
788 qemu_put_be32s(f, &s->ch[i].cdst);
789 qemu_put_be32s(f, &s->ch[i].mask);
790 }
791 }
792
793 static int s3c_dma_load(QEMUFile *f, void *opaque, int version_id)
794 {
795 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
796 int i;
797 for (i = 0; i < S3C_DMA_CH_N; i ++) {
798 s->ch[i].curr_tc = qemu_get_be32(f);
799 s->ch[i].req = qemu_get_be32(f);
800 qemu_get_be32s(f, &s->ch[i].con);
801 qemu_get_be32s(f, &s->ch[i].isrc);
802 qemu_get_be32s(f, &s->ch[i].isrcc);
803 qemu_get_be32s(f, &s->ch[i].idst);
804 qemu_get_be32s(f, &s->ch[i].idstc);
805 qemu_get_be32s(f, &s->ch[i].csrc);
806 qemu_get_be32s(f, &s->ch[i].cdst);
807 qemu_get_be32s(f, &s->ch[i].mask);
808 }
809 return 0;
810 }
811
812 struct s3c_dma_state_s *s3c_dma_init(target_phys_addr_t base, qemu_irq *pic)
813 {
814 int iomemtype;
815 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *)
816 qemu_mallocz(sizeof(struct s3c_dma_state_s));
817
818 s->base = base;
819 s->ch[0].intr = pic[0];
820 s->ch[1].intr = pic[1];
821 s->ch[2].intr = pic[2];
822 s->ch[3].intr = pic[3];
823 s->drqs = qemu_allocate_irqs(s3c_dma_dreq, s, S3C_RQ_MAX);
824
825 s3c_dma_reset(s);
826
827 iomemtype = cpu_register_io_memory(0, s3c_dma_readfn,
828 s3c_dma_writefn, s);
829 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
830
831 register_savevm("s3c24xx_dma", 0, 0, s3c_dma_save, s3c_dma_load, s);
832
833 return s;
834 }
835
836 qemu_irq *s3c_dma_get(struct s3c_dma_state_s *s)
837 {
838 return s->drqs;
839 }
840
841 /* PWM timers controller */
842 struct s3c_timer_state_s;
843 struct s3c_timers_state_s {
844 target_phys_addr_t base;
845 qemu_irq *dma;
846 DisplayState *ds;
847 struct s3c_timer_state_s {
848 QEMUTimer *t;
849 struct s3c_timers_state_s *s;
850 int n;
851 int running;
852 uint32_t divider;
853 uint16_t count;
854 int64_t reload;
855 qemu_irq irq;
856 gpio_handler_t cmp_cb;
857 void *cmp_opaque;
858 } timer[5];
859
860 uint16_t compareb[4];
861 uint16_t countb[5];
862 uint32_t config[2];
863 uint32_t control;
864 };
865
866 static const int s3c_tm_bits[] = { 0, 8, 12, 16, 20 };
867
868 static uint16_t s3c_timers_get(struct s3c_timers_state_s *s, int tm)
869 {
870 uint16_t elapsed;
871 if (!s->timer[tm].running)
872 return s->timer[tm].count;
873
874 elapsed = muldiv64(qemu_get_clock(vm_clock) - s->timer[tm].reload,
875 s->timer[tm].divider, ticks_per_sec);
876 if (unlikely(elapsed > s->timer[tm].count))
877 return s->timer[tm].count;
878
879 return s->timer[tm].count - elapsed;
880 }
881
882 static void s3c_timers_stop(struct s3c_timers_state_s *s, int tm)
883 {
884 s->timer[tm].count = s3c_timers_get(s, tm);
885 s->timer[tm].running = 0;
886 }
887
888 static void s3c_timers_start(struct s3c_timers_state_s *s, int tm)
889 {
890 if (s->timer[tm].running)
891 return;
892
893 s->timer[tm].divider = S3C_PCLK_FREQ >>
894 (((s->config[1] >> (tm * 4)) & 3) + 1);
895 if (tm < 2)
896 s->timer[tm].divider /= ((s->config[0] >> 0) & 0xff) + 1;
897 else
898 s->timer[tm].divider /= ((s->config[0] >> 8) & 0xff) + 1;
899 s->timer[tm].running = 1;
900 s->timer[tm].reload = qemu_get_clock(vm_clock);
901 qemu_mod_timer(s->timer[tm].t,
902 s->timer[tm].reload + muldiv64(s->timer[tm].count,
903 ticks_per_sec, s->timer[tm].divider));
904 }
905
906 static void s3c_timers_reset(struct s3c_timers_state_s *s)
907 {
908 int i;
909 s->config[0] = 0x00000000;
910 s->config[1] = 0x00000000;
911 s->control = 0x00000000;
912
913 for (i = 0; i < 5; i ++) {
914 if (s->timer[i].running)
915 s3c_timers_stop(s, i);
916 s->countb[i] = 0x0000;
917 s->timer[i].count = 0;
918 }
919 for (i = 0; i < 4; i ++)
920 s->compareb[i] = 0x0000;
921 }
922
923 static void s3c_timers_tick(void *opaque)
924 {
925 struct s3c_timer_state_s *t = (struct s3c_timer_state_s *) opaque;
926 struct s3c_timers_state_s *s = t->s;
927 if (!t->running)
928 return;
929
930 if (((s->config[1] >> 20) & 0xf) == t->n + 1) {
931 qemu_irq_raise(s->dma[S3C_RQ_TIMER0]); /* TODO */
932 qemu_irq_raise(s->dma[S3C_RQ_TIMER1]);
933 qemu_irq_raise(s->dma[S3C_RQ_TIMER2]);
934 } else
935 qemu_irq_raise(t->irq);
936
937 t->running = 0;
938 t->count = 0;
939
940 if (s->control & (1 << ((t->n == 4) ? 22 : (s3c_tm_bits[t->n] + 3)))) {
941 /* Auto-reload */
942 t->count = s->countb[t->n];
943 s3c_timers_start(s, t->n);
944 } else
945 s->control &= ~(1 << s3c_tm_bits[t->n]);
946 }
947
948 #define S3C_TCFG0 0x00 /* Timer Configuration register 0 */
949 #define S3C_TCFG1 0x04 /* Timer Configuration register 1 */
950 #define S3C_TCON 0x08 /* Timer Control register */
951 #define S3C_TCNTB0 0x0c /* Timer 0 Count Buffer register */
952 #define S3C_TCMPB0 0x10 /* Timer 0 Compare Buffer register */
953 #define S3C_TCNTO0 0x14 /* Timer 0 Count Observation register */
954 #define S3C_TCNTB1 0x18 /* Timer 1 Count Buffer register */
955 #define S3C_TCMPB1 0x1c /* Timer 1 Compare Buffer register */
956 #define S3C_TCNTO1 0x20 /* Timer 1 Count Observation register */
957 #define S3C_TCNTB2 0x24 /* Timer 2 Count Buffer register */
958 #define S3C_TCMPB2 0x28 /* Timer 2 Compare Buffer register */
959 #define S3C_TCNTO2 0x2c /* Timer 2 Count Observation register */
960 #define S3C_TCNTB3 0x30 /* Timer 3 Count Buffer register */
961 #define S3C_TCMPB3 0x34 /* Timer 3 Compare Buffer register */
962 #define S3C_TCNTO3 0x38 /* Timer 3 Count Observation register */
963 #define S3C_TCNTB4 0x3c /* Timer 4 Count Buffer register */
964 #define S3C_TCNTO4 0x40 /* Timer 4 Count Observation register */
965
966 static uint32_t s3c_timers_read(void *opaque, target_phys_addr_t addr)
967 {
968 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
969 int tm = 0;
970
971 switch (addr) {
972 case S3C_TCFG0:
973 return s->config[0];
974 case S3C_TCFG1:
975 return s->config[1];
976 case S3C_TCON:
977 return s->control;
978 case S3C_TCMPB3: tm ++;
979 case S3C_TCMPB2: tm ++;
980 case S3C_TCMPB1: tm ++;
981 case S3C_TCMPB0:
982 return s->compareb[tm];
983 case S3C_TCNTB4: tm ++;
984 case S3C_TCNTB3: tm ++;
985 case S3C_TCNTB2: tm ++;
986 case S3C_TCNTB1: tm ++;
987 case S3C_TCNTB0:
988 return s->countb[tm];
989 case S3C_TCNTO4: tm ++;
990 case S3C_TCNTO3: tm ++;
991 case S3C_TCNTO2: tm ++;
992 case S3C_TCNTO1: tm ++;
993 case S3C_TCNTO0:
994 return s3c_timers_get(s, tm);
995 default:
996 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
997 break;
998 }
999 return 0;
1000 }
1001
1002 static void s3c_timers_write(void *opaque, target_phys_addr_t addr,
1003 uint32_t value)
1004 {
1005 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1006 int tm = 0;
1007
1008 switch (addr) {
1009 case S3C_TCFG0:
1010 s->config[0] = value & 0x00ffffff;
1011 break;
1012 case S3C_TCFG1:
1013 s->config[1] = value & 0x00ffffff;
1014 break;
1015 case S3C_TCON:
1016 for (tm = 0; tm < 5; tm ++) {
1017 if (value & (2 << (s3c_tm_bits[tm]))) {
1018 if (s->timer[tm].running) {
1019 s3c_timers_stop(s, tm);
1020 s->timer[tm].count = s->countb[tm];
1021 s3c_timers_start(s, tm);
1022 } else
1023 s->timer[tm].count = s->countb[tm];
1024 }
1025 if (((value >> s3c_tm_bits[tm]) & 1) ^ s->timer[tm].running) {
1026 if (s->timer[tm].running)
1027 s3c_timers_stop(s, tm);
1028 else
1029 s3c_timers_start(s, tm);
1030 }
1031 }
1032
1033 s->control = value & 0x007fff1f;
1034 break;
1035 case S3C_TCMPB3: tm ++;
1036 case S3C_TCMPB2: tm ++;
1037 case S3C_TCMPB1: tm ++;
1038 case S3C_TCMPB0:
1039 s->compareb[tm] = value & 0xffff;
1040 if (s->timer[tm].cmp_cb)
1041 s->timer[tm].cmp_cb(tm, s->compareb[tm], s->timer[tm].cmp_opaque);
1042 break;
1043 case S3C_TCNTB4: tm ++;
1044 case S3C_TCNTB3: tm ++;
1045 case S3C_TCNTB2: tm ++;
1046 case S3C_TCNTB1: tm ++;
1047 case S3C_TCNTB0:
1048 s->countb[tm] = value & 0xffff;
1049 break;
1050 default:
1051 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1052 }
1053 }
1054
1055 static CPUReadMemoryFunc *s3c_timers_readfn[] = {
1056 s3c_timers_read,
1057 s3c_timers_read,
1058 s3c_timers_read,
1059 };
1060
1061 static CPUWriteMemoryFunc *s3c_timers_writefn[] = {
1062 s3c_timers_write,
1063 s3c_timers_write,
1064 s3c_timers_write,
1065 };
1066
1067 static void s3c_timers_save(QEMUFile *f, void *opaque)
1068 {
1069 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1070 int i;
1071 for (i = 0; i < 5; i ++) {
1072 qemu_put_be32(f, s->timer[i].running);
1073 qemu_put_be32s(f, &s->timer[i].divider);
1074 qemu_put_be16(f, s3c_timers_get(s, i));
1075 qemu_put_be64s(f, &s->timer[i].reload);
1076 }
1077
1078 for (i = 0; i < 4; i ++)
1079 qemu_put_be16s(f, &s->compareb[i]);
1080 for (i = 0; i < 5; i ++)
1081 qemu_put_be16s(f, &s->countb[i]);
1082 for (i = 0; i < 2; i ++)
1083 qemu_put_be32s(f, &s->config[i]);
1084 qemu_put_be32s(f, &s->control);
1085 }
1086
1087 static int s3c_timers_load(QEMUFile *f, void *opaque, int version_id)
1088 {
1089 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1090 int i, running[5];
1091 for (i = 0; i < 5; i ++) {
1092 s->timer[i].running = 0;
1093 running[i] = qemu_get_be32(f);
1094 qemu_get_be32s(f, &s->timer[i].divider);
1095 qemu_get_be16s(f, &s->timer[i].count);
1096 qemu_get_be64s(f, &s->timer[i].reload);
1097 }
1098
1099 for (i = 0; i < 4; i ++)
1100 qemu_get_be16s(f, &s->compareb[i]);
1101 for (i = 0; i < 5; i ++)
1102 qemu_get_be16s(f, &s->countb[i]);
1103 for (i = 0; i < 2; i ++)
1104 qemu_get_be32s(f, &s->config[i]);
1105 qemu_get_be32s(f, &s->control);
1106
1107 for (i = 0; i < 5; i ++)
1108 if (running[i])
1109 s3c_timers_start(s, i);
1110
1111 return 0;
1112 }
1113
1114 struct s3c_timers_state_s *s3c_timers_init(target_phys_addr_t base,
1115 qemu_irq *pic, qemu_irq *dma)
1116 {
1117 int i, iomemtype;
1118 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *)
1119 qemu_mallocz(sizeof(struct s3c_timers_state_s));
1120
1121 s->base = base;
1122 s->dma = dma;
1123
1124 s3c_timers_reset(s);
1125
1126 for (i = 0; i < 5; i ++) {
1127 s->timer[i].t = qemu_new_timer(vm_clock,
1128 s3c_timers_tick, &s->timer[i]);
1129 s->timer[i].s = s;
1130 s->timer[i].n = i;
1131 s->timer[i].cmp_cb = 0;
1132 s->timer[i].irq = pic[i];
1133 }
1134
1135 iomemtype = cpu_register_io_memory(0, s3c_timers_readfn,
1136 s3c_timers_writefn, s);
1137 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1138
1139 register_savevm("s3c24xx_timers", 0, 0,
1140 s3c_timers_save, s3c_timers_load, s);
1141
1142 return s;
1143 }
1144
1145 void s3c_timers_cmp_handler_set(void *opaque, int line,
1146 gpio_handler_t handler, void *cmp_opaque)
1147 {
1148 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1149 if (line > 4 || line < 0) {
1150 printf("%s: Bad timer number %i.\n", __FUNCTION__, line);
1151 exit(-1);
1152 }
1153 s->timer[line].cmp_cb = handler;
1154 s->timer[line].cmp_opaque = cmp_opaque;
1155 }
1156
1157 /* UART */
1158 struct s3c_uart_state_s {
1159 target_phys_addr_t base;
1160 qemu_irq *irq;
1161 qemu_irq *dma;
1162 uint8_t data;
1163 uint8_t rxfifo[16];
1164 int rxstart;
1165 int rxlen;
1166 #define UART_MAX_CHR 4
1167 int chr_num;
1168 CharDriverState *chr[UART_MAX_CHR];
1169
1170 uint8_t lcontrol;
1171 uint8_t fcontrol;
1172 uint8_t mcontrol;
1173 uint16_t control;
1174 uint16_t brdiv;
1175 uint8_t errstat;
1176 };
1177
1178 static void s3c_uart_reset(struct s3c_uart_state_s *s)
1179 {
1180 s->lcontrol = 0x00;
1181 s->fcontrol = 0x00;
1182 s->mcontrol = 0x00;
1183 s->control = 0x0000;
1184 s->errstat = 0;
1185
1186 s->rxstart = 0;
1187 s->rxlen = 0;
1188 }
1189
1190 static void s3c_uart_err(struct s3c_uart_state_s *s, int err)
1191 {
1192 s->errstat |= err;
1193 if (s->control & (1 << 6))
1194 qemu_irq_raise(s->irq[2]);
1195 }
1196
1197 inline static void s3c_uart_full(struct s3c_uart_state_s *s, int pulse)
1198 {
1199 if (s->fcontrol & 1) /* FIFOEnable */
1200 if (s->rxlen < (((s->fcontrol >> 4) & 3) + 1) * 4) {
1201 if (((s->control >> 0) & 3) != 1 || /* ReceiveMode */
1202 !s->rxlen)
1203 return;
1204 if (!(s->control & (1 << 7))) /* RxTimeOutEnable */
1205 return;
1206 /* When the Rx FIFO trigger level is not reached, the interrupt
1207 * is generated anyway, just after a small timeout instead of
1208 * immediately. */
1209 }
1210
1211 switch ((s->control >> 0) & 3) { /* ReceiveMode */
1212 case 1:
1213 if ((s->control & (1 << 8)) || pulse) /* RxInterruptType */
1214 qemu_irq_raise(s->irq[0]);
1215 break;
1216 case 2:
1217 case 3:
1218 qemu_irq_raise(s->dma[0]);
1219 break;
1220 }
1221 }
1222
1223 inline static void s3c_uart_empty(struct s3c_uart_state_s *s, int pulse)
1224 {
1225 switch ((s->control >> 2) & 3) { /* TransmitMode */
1226 case 1:
1227 if ((s->control & (1 << 9)) || pulse) /* TxInterruptType */
1228 qemu_irq_raise(s->irq[1]);
1229 break;
1230 case 2:
1231 case 3:
1232 qemu_irq_raise(s->dma[0]);
1233 break;
1234 }
1235 }
1236
1237 inline static void s3c_uart_update(struct s3c_uart_state_s *s)
1238 {
1239 s3c_uart_empty(s, 0);
1240 s3c_uart_full(s, 0);
1241 }
1242
1243 static void s3c_uart_params_update(struct s3c_uart_state_s *s)
1244 {
1245 QEMUSerialSetParams ssp;
1246 int i;
1247 if (!s->chr)
1248 return;
1249
1250 /* XXX Calculate PCLK frequency from clock manager registers */
1251 ssp.speed = (S3C_PCLK_FREQ >> 4) / (s->brdiv + 1);
1252
1253 switch ((s->lcontrol >> 3) & 7) {
1254 case 4:
1255 case 6:
1256 ssp.parity = 'O';
1257 break;
1258 case 5:
1259 case 7:
1260 ssp.parity = 'E';
1261 break;
1262 default:
1263 ssp.parity = 'N';
1264 }
1265
1266 ssp.data_bits = 5 + (s->lcontrol & 3);
1267
1268 ssp.stop_bits = (s->lcontrol & (1 << 2)) ? 2 : 1;
1269
1270 for (i = 0; i < s->chr_num; i ++)
1271 qemu_chr_ioctl(s->chr[i], CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1272 }
1273
1274 static int s3c_uart_is_empty(void *opaque)
1275 {
1276 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1277 if (s->fcontrol & 1) /* FIFOEnable */
1278 return 16 - s->rxlen;
1279 else
1280 return 1 - s->rxlen;
1281 }
1282
1283 static void s3c_uart_rx(void *opaque, const uint8_t *buf, int size)
1284 {
1285 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1286 int left;
1287 if (s->fcontrol & 1) { /* FIFOEnable */
1288 if (s->rxlen + size > 16) {
1289 size = 16 - s->rxlen;
1290 s3c_uart_err(s, 1);
1291 }
1292
1293 left = 16 - ((s->rxstart + s->rxlen) & 15);
1294 if (size > left) {
1295 memcpy(s->rxfifo + ((s->rxstart + s->rxlen) & 15), buf, left);
1296 memcpy(s->rxfifo, buf + left, size - left);
1297 } else
1298 memcpy(s->rxfifo + ((s->rxstart + s->rxlen) & 15), buf, size);
1299 s->rxlen += size;
1300 } else {
1301 if (s->rxlen + size > 1)
1302 s3c_uart_err(s, 1);
1303 s->rxlen = 1;
1304 s->data = buf[0];
1305 }
1306 s3c_uart_full(s, 1);
1307 }
1308
1309 /* S3C2410 UART doesn't seem to understand break conditions. */
1310 static void s3c_uart_event(void *opaque, int event)
1311 {
1312 }
1313
1314 #define S3C_ULCON 0x00 /* UART Line Control register */
1315 #define S3C_UCON 0x04 /* UART Control register */
1316 #define S3C_UFCON 0x08 /* UART FIFO Control register */
1317 #define S3C_UMCON 0x0c /* UART Modem Control register */
1318 #define S3C_UTRSTAT 0x10 /* UART Tx/Rx Status register */
1319 #define S3C_UERSTAT 0x14 /* UART Error Status register */
1320 #define S3C_UFSTAT 0x18 /* UART FIFO Status register */
1321 #define S3C_UMSTAT 0x1c /* UART Modem Status register */
1322 #define S3C_UTXH 0x20 /* UART Transmit Buffer register */
1323 #define S3C_URXH 0x24 /* UART Receive Buffer register */
1324 #define S3C_UBRDIV 0x28 /* UART Baud Rate Divisor register */
1325
1326 static uint32_t s3c_uart_read(void *opaque, target_phys_addr_t addr)
1327 {
1328 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1329 uint8_t ret;
1330
1331 switch (addr) {
1332 case S3C_ULCON:
1333 return s->lcontrol;
1334 case S3C_UCON:
1335 return s->control;
1336 case S3C_UFCON:
1337 return s->fcontrol;
1338 case S3C_UMCON:
1339 return s->mcontrol;
1340 case S3C_UTRSTAT:
1341 return 6 | !!s->rxlen;
1342 case S3C_UERSTAT:
1343 /* XXX: UERSTAT[3] is Reserved but Linux thinks it is BREAK */
1344 ret = s->errstat;
1345 s->errstat = 0;
1346 s3c_uart_update(s);
1347 return ret;
1348 case S3C_UFSTAT:
1349 s3c_uart_update(s);
1350 return s->rxlen ? s->rxlen | (1 << 8) : 0;
1351 case S3C_UMSTAT:
1352 s3c_uart_update(s);
1353 return 0x11;
1354 case S3C_UTXH: /* why this is called by u-boot is not clear */
1355 return 0;
1356 case S3C_URXH:
1357 s3c_uart_update(s);
1358 if (s->rxlen) {
1359 s->rxlen --;
1360 if (s->fcontrol & 1) { /* FIFOEnable */
1361 ret = s->rxfifo[s->rxstart ++];
1362 s->rxstart &= 15;
1363 } else
1364 ret = s->data;
1365 return ret;
1366 }
1367 return 0;
1368 case S3C_UBRDIV:
1369 return s->brdiv;
1370 default:
1371 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1372 break;
1373 }
1374 return 0;
1375 }
1376
1377 static void s3c_uart_write(void *opaque, target_phys_addr_t addr,
1378 uint32_t value)
1379 {
1380 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1381 uint8_t ch;
1382 int i, afc;
1383
1384 switch (addr) {
1385 case S3C_ULCON:
1386 if ((s->lcontrol ^ value) & (1 << 6))
1387 printf("%s: UART Infra-red mode %s\n", __FUNCTION__,
1388 (value & (1 << 6)) ? "on" : "off");
1389 s->lcontrol = value;
1390 s3c_uart_params_update(s);
1391 s3c_uart_update(s);
1392 break;
1393 case S3C_UCON:
1394 /* XXX: UCON[4] is Reserved but Linux thinks it is BREAK */
1395 if ((s->control ^ value) & (1 << 5))
1396 printf("%s: UART loopback test mode %s\n", __FUNCTION__,
1397 (value & (1 << 5)) ? "on" : "off");
1398 s->control = value & 0x7ef;
1399 s3c_uart_update(s);
1400 break;
1401 case S3C_UFCON:
1402 if (value & (1 << 1)) /* RxReset */
1403 s->rxlen = 0;
1404 s->fcontrol = value & 0xf1;
1405 s3c_uart_update(s);
1406 break;
1407 case S3C_UMCON:
1408 #ifdef CONFIG_S3C_MODEM /* not handled, openmoko modem.c not imported */
1409 if ((s->mcontrol ^ value) & (1 << 4)) {
1410 afc = (value >> 4) & 1;
1411 for (i = 0; i < s->chr_num; i ++)
1412 qemu_chr_ioctl(s->chr[i], CHR_IOCTL_MODEM_HANDSHAKE, &afc);
1413 }
1414 #endif
1415 s->mcontrol = value & 0x11;
1416 s3c_uart_update(s);
1417 break;
1418 case S3C_UTXH:
1419 ch = value & 0xff;
1420 for (i = 0; i < s->chr_num; i ++)
1421 qemu_chr_write(s->chr[i], &ch, 1);
1422 s3c_uart_empty(s, 1);
1423 s3c_uart_update(s);
1424 break;
1425 case S3C_UBRDIV:
1426 s->brdiv = value & 0xffff;
1427 s3c_uart_params_update(s);
1428 s3c_uart_update(s);
1429 break;
1430 default:
1431 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1432 }
1433 }
1434
1435 static CPUReadMemoryFunc *s3c_uart_readfn[] = {
1436 s3c_uart_read,
1437 s3c_uart_read,
1438 s3c_uart_read,
1439 };
1440
1441 static CPUWriteMemoryFunc *s3c_uart_writefn[] = {
1442 s3c_uart_write,
1443 s3c_uart_write,
1444 s3c_uart_write,
1445 };
1446
1447 static void s3c_uart_save(QEMUFile *f, void *opaque)
1448 {
1449 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1450 qemu_put_8s(f, &s->data);
1451 qemu_put_buffer(f, s->rxfifo, sizeof(s->rxfifo));
1452 qemu_put_be32(f, s->rxstart);
1453 qemu_put_be32(f, s->rxlen);
1454 qemu_put_8s(f, &s->lcontrol);
1455 qemu_put_8s(f, &s->fcontrol);
1456 qemu_put_8s(f, &s->mcontrol);
1457 qemu_put_be16s(f, &s->control);
1458 qemu_put_be16s(f, &s->brdiv);
1459 qemu_put_8s(f, &s->errstat);
1460 }
1461
1462 static int s3c_uart_load(QEMUFile *f, void *opaque, int version_id)
1463 {
1464 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1465 qemu_get_8s(f, &s->data);
1466 qemu_get_buffer(f, s->rxfifo, sizeof(s->rxfifo));
1467 s->rxstart = qemu_get_be32(f);
1468 s->rxlen = qemu_get_be32(f);
1469 qemu_get_8s(f, &s->lcontrol);
1470 qemu_get_8s(f, &s->fcontrol);
1471 qemu_get_8s(f, &s->mcontrol);
1472 qemu_get_be16s(f, &s->control);
1473 qemu_get_be16s(f, &s->brdiv);
1474 qemu_get_8s(f, &s->errstat);
1475
1476 return 0;
1477 }
1478
1479 struct s3c_uart_state_s *s3c_uart_init(target_phys_addr_t base,
1480 qemu_irq *irqs, qemu_irq *dma)
1481 {
1482 int iomemtype;
1483 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *)
1484 qemu_mallocz(sizeof(struct s3c_uart_state_s));
1485
1486 s->base = base;
1487 s->irq = irqs;
1488 s->dma = dma;
1489
1490 s3c_uart_reset(s);
1491
1492 iomemtype = cpu_register_io_memory(0, s3c_uart_readfn,
1493 s3c_uart_writefn, s);
1494 cpu_register_physical_memory(s->base, 0xfff, iomemtype);
1495
1496 register_savevm("s3c24xx_uart", base, 0, s3c_uart_save, s3c_uart_load, s);
1497
1498 return s;
1499 }
1500
1501 void s3c_uart_attach(struct s3c_uart_state_s *s, CharDriverState *chr)
1502 {
1503 if (s->chr_num >= UART_MAX_CHR)
1504 cpu_abort(cpu_single_env, "%s: Too many devices\n", __FUNCTION__);
1505 s->chr[s->chr_num ++] = chr;
1506
1507 qemu_chr_add_handlers(chr, s3c_uart_is_empty,
1508 s3c_uart_rx, s3c_uart_event, s);
1509 }
1510
1511 /* ADC & Touchscreen interface */
1512 struct s3c_adc_state_s {
1513 target_phys_addr_t base;
1514 qemu_irq irq;
1515 qemu_irq tcirq;
1516 QEMUTimer *convt;
1517 QEMUTimer *tst;
1518 int x;
1519 int y;
1520 int down;
1521 int enable;
1522 int input[8];
1523 int in_idx;
1524 int noise;
1525 int scale[6];
1526
1527 uint16_t control;
1528 uint16_t ts;
1529 uint16_t delay;
1530 int16_t xdata;
1531 int16_t ydata;
1532 };
1533
1534 static void s3c_adc_reset(struct s3c_adc_state_s *s)
1535 {
1536 s->down = 0;
1537 s->control = 0x3fc4;
1538 s->ts = 0x58;
1539 s->delay = 0xff;
1540 s->enable = 1;
1541 }
1542
1543 static void s3c_adc_start(struct s3c_adc_state_s *s)
1544 {
1545 if (!s->enable || (s->ts & 7) == 0)
1546 return;
1547 s->control &= ~(1 << 15);
1548 s->in_idx = (s->control >> 3) & 7;
1549 qemu_mod_timer(s->convt, qemu_get_clock(vm_clock) + (ticks_per_sec >> 5));
1550 }
1551
1552 static void s3c_adc_done(void *opaque)
1553 {
1554 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1555 s->xdata = s->input[s->in_idx] & 0x3ff;
1556 s->control |= 1 << 15;
1557 qemu_irq_raise(s->irq);
1558 }
1559
1560 static void s3c_adc_tick(void *opaque)
1561 {
1562 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1563 int sx, sy;
1564
1565 if (s->down) {
1566 if ((s->ts & 3) == 3 && s->enable)
1567 qemu_irq_raise(s->tcirq);
1568 else if (s->enable && ((s->ts & (1 << 2)) || (s->ts & 3))) {
1569 sx = s->x * s->scale[0] + s->y * s->scale[1] + s->scale[2];
1570 sy = s->x * s->scale[3] + s->y * s->scale[4] + s->scale[5];
1571 s->xdata = ((sx >> 13) & 0xfff) | (1 << 14) | ((s->ts & 3) << 12);
1572 s->ydata = ((sy >> 13) & 0xfff) | (1 << 14) | ((s->ts & 3) << 12);
1573 s->xdata ^= s->noise >> 1;
1574 s->ydata ^= s->noise >> 2;
1575 qemu_irq_raise(s->irq);
1576 s->noise ++;
1577 s->noise &= 7;
1578 }
1579 qemu_mod_timer(s->tst, qemu_get_clock(vm_clock) +
1580 (ticks_per_sec >> 5));
1581 }
1582 }
1583
1584 static void s3c_adc_event(void *opaque,
1585 int x, int y, int z, int buttons_state)
1586 {
1587 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1588 s->down = !!buttons_state;
1589 s->x = x;
1590 s->y = y;
1591 s3c_adc_tick(s);
1592 }
1593
1594 #define S3C_ADCCON 0x00 /* ADC Control register */
1595 #define S3C_ADCTSC 0x04 /* ADC Touchscreen Control register */
1596 #define S3C_ADCDLY 0x08 /* ADC Start or Interval Delay register */
1597 #define S3C_ADCDAT0 0x0c /* ADC Conversion Data register 0 */
1598 #define S3C_ADCDAT1 0x10 /* ADC Conversion Data register 1 */
1599
1600 static uint32_t s3c_adc_read(void *opaque, target_phys_addr_t addr)
1601 {
1602 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1603
1604 switch (addr) {
1605 case S3C_ADCCON:
1606 return s->control;
1607 case S3C_ADCTSC:
1608 return s->ts;
1609 case S3C_ADCDLY:
1610 return s->delay;
1611 case S3C_ADCDAT0:
1612 if (s->control & 2)
1613 s3c_adc_start(s);
1614 return ((!s->down) << 15) | s->xdata;
1615 case S3C_ADCDAT1:
1616 return ((!s->down) << 15) | s->ydata;
1617 default:
1618 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1619 break;
1620 }
1621 return 0;
1622 }
1623
1624 static void s3c_adc_write(void *opaque, target_phys_addr_t addr,
1625 uint32_t value)
1626 {
1627 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1628
1629 switch (addr) {
1630 case S3C_ADCCON:
1631 s->control = (s->control & 0x8000) | (value & 0x7ffe);
1632 s->enable = !(value & 4);
1633 if ((value & 1) && !(value & 2))
1634 s3c_adc_start(s);
1635 if (!s->enable)
1636 qemu_del_timer(s->convt);
1637 s3c_adc_tick(s);
1638 break;
1639
1640 case S3C_ADCTSC:
1641 s->ts = value & 0xff;
1642 break;
1643
1644 case S3C_ADCDLY:
1645 s->delay = value & 0xffff;
1646 break;
1647
1648 default:
1649 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1650 }
1651 }
1652
1653 static CPUReadMemoryFunc *s3c_adc_readfn[] = {
1654 s3c_adc_read,
1655 s3c_adc_read,
1656 s3c_adc_read,
1657 };
1658
1659 static CPUWriteMemoryFunc *s3c_adc_writefn[] = {
1660 s3c_adc_write,
1661 s3c_adc_write,
1662 s3c_adc_write,
1663 };
1664
1665 static void s3c_adc_save(QEMUFile *f, void *opaque)
1666 {
1667 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1668 int i;
1669 qemu_put_be32(f, s->enable);
1670 for (i = 0; i < 8; i ++)
1671 qemu_put_be32(f, s->input[i]);
1672 qemu_put_be32(f, s->in_idx);
1673 qemu_put_be32(f, s->noise);
1674
1675 qemu_put_be16s(f, &s->control);
1676 qemu_put_be16s(f, &s->ts);
1677 qemu_put_be16s(f, &s->delay);
1678 qemu_put_be16s(f, &s->xdata);
1679 qemu_put_be16s(f, &s->ydata);
1680 }
1681
1682 static int s3c_adc_load(QEMUFile *f, void *opaque, int version_id)
1683 {
1684 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1685 int i;
1686 s->enable = qemu_get_be32(f);
1687 for (i = 0; i < 8; i ++)
1688 s->input[i] = qemu_get_be32(f);
1689 s->in_idx = qemu_get_be32(f);
1690 s->noise = qemu_get_be32(f);
1691
1692 qemu_get_be16s(f, &s->control);
1693 qemu_get_be16s(f, &s->ts);
1694 qemu_get_be16s(f, &s->delay);
1695 qemu_get_be16s(f, &s->xdata);
1696 qemu_get_be16s(f, &s->ydata);
1697
1698 if (s->enable && (s->ts & 7) && !(s->control & (1 << 15)))
1699 s3c_adc_start(s);
1700
1701 return 0;
1702 }
1703
1704 struct s3c_adc_state_s *s3c_adc_init(target_phys_addr_t base, qemu_irq irq,
1705 qemu_irq tcirq)
1706 {
1707 int iomemtype;
1708 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *)
1709 qemu_mallocz(sizeof(struct s3c_adc_state_s));
1710
1711 s->base = base;
1712 s->irq = irq;
1713 s->tcirq = tcirq;
1714 s->convt = qemu_new_timer(vm_clock, s3c_adc_done, s);
1715 s->tst = qemu_new_timer(vm_clock, s3c_adc_tick, s);
1716
1717 s3c_adc_reset(s);
1718
1719 iomemtype = cpu_register_io_memory(0, s3c_adc_readfn,
1720 s3c_adc_writefn, s);
1721 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1722
1723 /* We want absolute coordinates */
1724 qemu_add_mouse_event_handler(s3c_adc_event, s, 1,
1725 "QEMU S3C2410-driven Touchscreen");
1726
1727 register_savevm("s3c24xx_adc", 0, 0, s3c_adc_save, s3c_adc_load, s);
1728
1729 return s;
1730 }
1731
1732 void s3c_adc_setscale(struct s3c_adc_state_s *adc, const int m[])
1733 {
1734 memcpy(adc->scale, m, 6 * sizeof(int));
1735 }
1736
1737 /* IIC-bus serial interface */
1738 struct s3c_i2c_state_s {
1739 i2c_slave slave;
1740 i2c_bus *bus;
1741 target_phys_addr_t base;
1742 qemu_irq irq;
1743
1744 uint8_t control;
1745 uint8_t status;
1746 uint8_t data;
1747 uint8_t addy;
1748 uint8_t mmaster;
1749 int busy;
1750 int newstart;
1751 };
1752
1753 static void s3c_i2c_irq(struct s3c_i2c_state_s *s)
1754 {
1755 s->control |= 1 << 4;
1756 if (s->control & (1 << 5))
1757 qemu_irq_raise(s->irq);
1758 }
1759
1760 static void s3c_i2c_reset(struct s3c_i2c_state_s *s)
1761 {
1762 s->control = 0x00;
1763 s->status = 0x00;
1764 s->busy = 0;
1765 s->newstart = 0;
1766 s->mmaster = 0;
1767 }
1768
1769 static void s3c_i2c_event(i2c_slave *i2c, enum i2c_event event)
1770 {
1771 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1772 if (!(s->status & (1 << 4)))
1773 return;
1774
1775 switch (event) {
1776 case I2C_START_RECV:
1777 case I2C_START_SEND:
1778 s->status |= 1 << 2;
1779 s3c_i2c_irq(s);
1780 break;
1781 case I2C_FINISH:
1782 s->status &= ~6;
1783 break;
1784 case I2C_NACK:
1785 s->status |= 1 << 0;
1786 break;
1787 default:
1788 break;
1789 }
1790 }
1791
1792 static int s3c_i2c_tx(i2c_slave *i2c, uint8_t data)
1793 {
1794 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1795 if (!(s->status & (1 << 4)))
1796 return 1;
1797
1798 if ((s->status >> 6) == 0)
1799 s->data = data; /* TODO */
1800 s->status &= ~(1 << 0);
1801 s3c_i2c_irq(s);
1802
1803 return !(s->control & (1 << 7));
1804 }
1805
1806 static int s3c_i2c_rx(i2c_slave *i2c)
1807 {
1808 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1809 if (!(s->status & (1 << 4)))
1810 return 1;
1811
1812 if ((s->status >> 6) == 1) {
1813 s->status &= ~(1 << 0);
1814 s3c_i2c_irq(s);
1815 return s->data;
1816 }
1817
1818 return 0x00;
1819 }
1820
1821 static void s3c_master_work(void *opaque)
1822 {
1823 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1824 int start = 0, stop = 0, ack = 1;
1825 if (s->control & (1 << 4)) /* Interrupt pending */
1826 return;
1827 if ((s->status & 0x90) != 0x90) /* Master */
1828 return;
1829 stop = ~s->status & (1 << 5);
1830 if (s->newstart && s->status & (1 << 5)) { /* START */
1831 s->busy = 1;
1832 start = 1;
1833 }
1834 s->newstart = 0;
1835 if (!s->busy)
1836 return;
1837
1838 if (start)
1839 ack = !i2c_start_transfer(s->bus, s->data >> 1, (~s->status >> 6) & 1);
1840 else if (stop)
1841 i2c_end_transfer(s->bus);
1842 else if (s->status & (1 << 6))
1843 ack = !i2c_send(s->bus, s->data);
1844 else {
1845 s->data = i2c_recv(s->bus);
1846
1847 if (!(s->control & (1 << 7))) /* ACK */
1848 i2c_nack(s->bus);
1849 }
1850
1851 if (!(s->status & (1 << 5))) {
1852 s->busy = 0;
1853 return;
1854 }
1855 s->status &= ~1;
1856 s->status |= !ack;
1857 if (!ack)
1858 s->busy = 0;
1859 s3c_i2c_irq(s);
1860 }
1861
1862 #define S3C_IICCON 0x00 /* IIC-Bus Control register */
1863 #define S3C_IICSTAT 0x04 /* IIC-Bus Control / Status register */
1864 #define S3C_IICADD 0x08 /* IIC-Bus Address register */
1865 #define S3C_IICDS 0x0c /* IIC-Bus Tx / Rx Data Shift register */
1866
1867 #define S3C2440_IICLC 0x10 /* IIC-Bus multi-master line control register */
1868
1869 static uint32_t s3c_i2c_read(void *opaque, target_phys_addr_t addr)
1870 {
1871 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1872
1873 switch (addr) {
1874 case S3C_IICCON:
1875 return s->control;
1876 case S3C_IICSTAT:
1877 return s->status & ~(1 << 5); /* Busy signal */
1878 case S3C_IICADD:
1879 return s->addy;
1880 case S3C_IICDS:
1881 return s->data;
1882 case S3C2440_IICLC: /* s3c2440 only ! */
1883 return s->mmaster;
1884 default:
1885 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1886 break;
1887 }
1888 return 0;
1889 }
1890
1891 static void s3c_i2c_write(void *opaque, target_phys_addr_t addr,
1892 uint32_t value)
1893 {
1894 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1895
1896 switch (addr) {
1897 case S3C_IICCON:
1898 s->control = (s->control | 0xef) & value;
1899 if (s->busy)
1900 s3c_master_work(s);
1901 break;
1902
1903 case S3C_IICSTAT:
1904 s->status &= 0x0f;
1905 s->status |= value & 0xf0;
1906 if (s->status & (1 << 5))
1907 s->newstart = 1;
1908 s3c_master_work(s);
1909 break;
1910
1911 case S3C_IICADD:
1912 s->addy = value & 0x7f;
1913 i2c_set_slave_address(&s->slave, s->addy);
1914 break;
1915
1916 case S3C_IICDS:
1917 s->data = value & 0xff;
1918 break;
1919
1920 case S3C2440_IICLC: /* s3c2440 only ! */
1921 s->mmaster = value & 0xff;
1922 break;
1923
1924 default:
1925 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1926 }
1927 }
1928
1929 static CPUReadMemoryFunc *s3c_i2c_readfn[] = {
1930 s3c_i2c_read,
1931 s3c_i2c_read,
1932 s3c_i2c_read,
1933 };
1934
1935 static CPUWriteMemoryFunc *s3c_i2c_writefn[] = {
1936 s3c_i2c_write,
1937 s3c_i2c_write,
1938 s3c_i2c_write,
1939 };
1940
1941 static void s3c_i2c_save(QEMUFile *f, void *opaque)
1942 {
1943 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1944 qemu_put_8s(f, &s->control);
1945 qemu_put_8s(f, &s->status);
1946 qemu_put_8s(f, &s->data);
1947 qemu_put_8s(f, &s->addy);
1948 qemu_put_8s(f, &s->mmaster);
1949
1950 qemu_put_be32(f, s->busy);
1951 qemu_put_be32(f, s->newstart);
1952
1953 i2c_slave_save(f, &s->slave);
1954 }
1955
1956 static int s3c_i2c_load(QEMUFile *f, void *opaque, int version_id)
1957 {
1958 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1959 qemu_get_8s(f, &s->control);
1960 qemu_get_8s(f, &s->status);
1961 qemu_get_8s(f, &s->data);
1962 qemu_get_8s(f, &s->addy);
1963 qemu_get_8s(f, &s->mmaster);
1964
1965 s->busy = qemu_get_be32(f);
1966 s->newstart = qemu_get_be32(f);
1967
1968 i2c_slave_load(f, &s->slave);
1969 return 0;
1970 }
1971
1972 struct s3c_i2c_state_s *s3c_i2c_init(target_phys_addr_t base, qemu_irq irq)
1973 {
1974 int iomemtype;
1975 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *)
1976 qemu_mallocz(sizeof(struct s3c_i2c_state_s));
1977
1978 s->base = base;
1979 s->irq = irq;
1980 s->slave.event = s3c_i2c_event;
1981 s->slave.send = s3c_i2c_tx;
1982 s->slave.recv = s3c_i2c_rx;
1983 s->bus = i2c_init_bus();
1984
1985 s3c_i2c_reset(s);
1986
1987 iomemtype = cpu_register_io_memory(0, s3c_i2c_readfn,
1988 s3c_i2c_writefn, s);
1989 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1990
1991 register_savevm("s3c24xx_i2c", 0, 0, s3c_i2c_save, s3c_i2c_load, s);
1992
1993 return s;
1994 }
1995
1996 i2c_bus *s3c_i2c_bus(struct s3c_i2c_state_s *s)
1997 {
1998 return s->bus;
1999 }
2000
2001 /* Serial Peripheral Interface */
2002 struct s3c_spi_state_s {
2003 target_phys_addr_t base;
2004
2005 struct {
2006 qemu_irq irq;
2007 qemu_irq drq;
2008 qemu_irq miso;
2009
2010 uint8_t control;
2011 uint8_t pin;
2012 uint8_t pre;
2013
2014 int cs_pin;
2015 int clk_pin;
2016 int mosi_pin;
2017 uint8_t txbuf;
2018 uint8_t rxbuf;
2019 int bit;
2020 } chan[2];
2021
2022 uint8_t (*txrx[2])(void *opaque, uint8_t value);
2023 uint8_t (*btxrx[2])(void *opaque, uint8_t value);
2024 void *opaque[2];
2025 };
2026
2027 static void s3c_spi_update(struct s3c_spi_state_s *s)
2028 {
2029 int i;
2030 for (i = 0; i < 2; i ++) {
2031 switch ((s->chan[i].control >> 5) & 3) { /* SMOD */
2032 case 1:
2033 qemu_irq_raise(s->chan[i].irq);
2034 break;
2035 case 2:
2036 qemu_irq_raise(s->chan[i].drq);
2037 break;
2038 }
2039 }
2040 }
2041
2042 static void s3c_spi_reset(struct s3c_spi_state_s *s)
2043 {
2044 memset(s->chan, 0, sizeof(s->chan));
2045 s->chan[0].pin = 0x02;
2046 s->chan[1].pin = 0x02;
2047 s3c_spi_update(s);
2048 }
2049
2050 #define S3C_SPCON0 0x00 /* SPI channel 0 control register */
2051 #define S3C_SPSTA0 0x04 /* SPI channel 0 status register */
2052 #define S3C_SPPIN0 0x08 /* SPI channel 0 pin control register */
2053 #define S3C_SPPRE0 0x0c /* SPI channel 0 baudrate prescaler register */
2054 #define S3C_SPTDAT0 0x10 /* SPI channel 0 Tx data register */
2055 #define S3C_SPRDAT0 0x14 /* SPI channel 0 Rx data register */
2056 #define S3C_SPCON1 0x20 /* SPI channel 1 control register */
2057 #define S3C_SPSTA1 0x24 /* SPI channel 1 status register */
2058 #define S3C_SPPIN1 0x28 /* SPI channel 1 pin control register */
2059 #define S3C_SPPRE1 0x2c /* SPI channel 1 baudrate prescaler register */
2060 #define S3C_SPTDAT1 0x30 /* SPI channel 1 Tx data register */
2061 #define S3C_SPRDAT1 0x34 /* SPI channel 1 Rx data register */
2062
2063 static uint32_t s3c_spi_read(void *opaque, target_phys_addr_t addr)
2064 {
2065 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2066 int ch;
2067
2068 ch = addr >> 5;
2069
2070 switch (addr) {
2071 case S3C_SPCON0:
2072 case S3C_SPCON1:
2073 return s->chan[ch].control;
2074
2075 case S3C_SPSTA0:
2076 case S3C_SPSTA1:
2077 return 0x01;
2078
2079 case S3C_SPPIN0:
2080 case S3C_SPPIN1:
2081 return s->chan[ch].pin;
2082
2083 case S3C_SPPRE0:
2084 case S3C_SPPRE1:
2085 return s->chan[ch].pre;
2086
2087 case S3C_SPTDAT0:
2088 case S3C_SPTDAT1:
2089 return s->chan[ch + 2].txbuf;
2090
2091 case S3C_SPRDAT0:
2092 case S3C_SPRDAT1:
2093 if (s->txrx[ch] && (s->chan[ch].control & 0x19) == 0x19)
2094 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], 'Q');
2095 s3c_spi_update(s);
2096 return s->chan[ch].rxbuf;
2097
2098 default:
2099 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2100 break;
2101 }
2102 return 0;
2103 }
2104
2105 static void s3c_spi_write(void *opaque, target_phys_addr_t addr,
2106 uint32_t value)
2107 {
2108 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2109 int ch;
2110
2111 ch = addr >> 5;
2112
2113 switch (addr) {
2114 case S3C_SPCON0:
2115 case S3C_SPCON1:
2116 s->chan[ch].control = value & 0x7f;
2117 s3c_spi_update(s);
2118 break;
2119
2120 case S3C_SPPIN0:
2121 case S3C_SPPIN1:
2122 s->chan[ch].pin = value & 0x07;
2123 break;
2124
2125 case S3C_SPPRE0:
2126 case S3C_SPPRE1:
2127 s->chan[ch].pre = value & 0xff;
2128 break;
2129
2130 case S3C_SPTDAT0:
2131 case S3C_SPTDAT1:
2132 s->chan[ch].txbuf = value & 0xff;
2133 if (s->txrx[ch] && (s->chan[ch].control & 0x19) == 0x18)
2134 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], value & 0xff);
2135 s3c_spi_update(s);
2136 break;
2137
2138 default:
2139 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2140 }
2141 }
2142
2143 static CPUReadMemoryFunc *s3c_spi_readfn[] = {
2144 s3c_spi_read,
2145 s3c_spi_read,
2146 s3c_spi_read,
2147 };
2148
2149 static CPUWriteMemoryFunc *s3c_spi_writefn[] = {
2150 s3c_spi_write,
2151 s3c_spi_write,
2152 s3c_spi_write,
2153 };
2154
2155 static void s3c_spi_save(QEMUFile *f, void *opaque)
2156 {
2157 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2158 int i;
2159 for (i = 0; i < 2; i ++) {
2160 qemu_put_8s(f, &s->chan[i].control);
2161 qemu_put_8s(f, &s->chan[i].pin);
2162 qemu_put_8s(f, &s->chan[i].pre);
2163
2164 qemu_put_8s(f, &s->chan[i].txbuf);
2165 qemu_put_8s(f, &s->chan[i].rxbuf);
2166 qemu_put_be32(f, s->chan[i].cs_pin);
2167 qemu_put_be32(f, s->chan[i].clk_pin);
2168 qemu_put_be32(f, s->chan[i].mosi_pin);
2169 qemu_put_be32(f, s->chan[i].bit);
2170 }
2171 }
2172
2173 static int s3c_spi_load(QEMUFile *f, void *opaque, int version_id)
2174 {
2175 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2176 int i;
2177 for (i = 0; i < 2; i ++) {
2178 qemu_get_8s(f, &s->chan[i].control);
2179 qemu_get_8s(f, &s->chan[i].pin);
2180 qemu_get_8s(f, &s->chan[i].pre);
2181
2182 qemu_get_8s(f, &s->chan[i].txbuf);
2183 qemu_get_8s(f, &s->chan[i].rxbuf);
2184 s->chan[i].cs_pin = qemu_get_be32(f);
2185 s->chan[i].clk_pin = qemu_get_be32(f);
2186 s->chan[i].mosi_pin = qemu_get_be32(f);
2187 s->chan[i].bit = qemu_get_be32(f);
2188 }
2189
2190 return 0;
2191 }
2192
2193 static void s3c_spi_bitbang_cs(void *opaque, int line, int level)
2194 {
2195 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2196 int ch = line;
2197 if (s->chan[ch].cs_pin || level) {
2198 if (s->chan[ch].bit && s->txrx[ch] && !s->btxrx[ch]) {
2199 s->chan[ch].txbuf <<= 8 - s->chan[ch].bit;
2200 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], s->chan[ch].txbuf);
2201 }
2202 } else if (!s->chan[ch].cs_pin || !level)
2203 s->chan[ch].bit = 0;
2204
2205 /* SSn is active low. */
2206 s->chan[ch].cs_pin = !level;
2207 }
2208
2209 static void s3c_spi_bitbang_clk(void *opaque, int line, int level)
2210 {
2211 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2212 int ch = line;
2213 if (!s->chan[ch].cs_pin)
2214 goto done;
2215
2216 /* Detect CLK rising edge */
2217 if (s->chan[ch].clk_pin || !level)
2218 goto done;
2219
2220 if (s->btxrx[ch]) {
2221 qemu_set_irq(s->chan[ch].miso,
2222 s->btxrx[ch](s->opaque[ch], s->chan[ch].mosi_pin));
2223 goto done;
2224 }
2225
2226 s->chan[ch].txbuf <<= 1;
2227 s->chan[ch].txbuf |= s->chan[ch].mosi_pin;
2228
2229 qemu_set_irq(s->chan[ch].miso, (s->chan[ch].rxbuf >> 7) & 1);
2230 s->chan[ch].rxbuf <<= 1;
2231
2232 if (++ s->chan[ch].bit == 8) {
2233 if (s->txrx[ch])
2234 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], s->chan[ch].txbuf);
2235 s->chan[ch].bit = 0;
2236 }
2237
2238 done:
2239 s->chan[ch].clk_pin = level;
2240 }
2241
2242 static void s3c_spi_bitbang_mosi(void *opaque, int line, int level)
2243 {
2244 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2245 int ch = line;
2246 s->chan[ch].mosi_pin = level;
2247 }
2248
2249 static const struct {
2250 int cs, clk, miso, mosi;
2251 } s3c_spi_pins[2] = {
2252 { S3C_GPG(2), S3C_GPE(13), S3C_GPE(11), S3C_GPE(12) },
2253 { S3C_GPG(3), S3C_GPG(7), S3C_GPG(5), S3C_GPG(6) },
2254 };
2255
2256 static void s3c_spi_bitbang_init(struct s3c_spi_state_s *s,
2257 struct s3c_gpio_state_s *gpio)
2258 {
2259 int i;
2260 qemu_irq *cs = qemu_allocate_irqs(s3c_spi_bitbang_cs, s, 2);
2261 qemu_irq *clk = qemu_allocate_irqs(s3c_spi_bitbang_clk, s, 2);
2262 qemu_irq *mosi = qemu_allocate_irqs(s3c_spi_bitbang_mosi, s, 2);
2263
2264 for (i = 0; i < 2; i ++) {
2265 s3c_gpio_out_set(gpio, s3c_spi_pins[i].cs, cs[i]);
2266 s3c_gpio_out_set(gpio, s3c_spi_pins[i].clk, clk[i]);
2267 s->chan[i].miso = s3c_gpio_in_get(gpio)[s3c_spi_pins[i].miso];
2268 s3c_gpio_out_set(gpio, s3c_spi_pins[i].mosi, mosi[i]);
2269 }
2270 }
2271
2272 struct s3c_spi_state_s *s3c_spi_init(target_phys_addr_t base,
2273 qemu_irq irq0, qemu_irq drq0, qemu_irq irq1, qemu_irq drq1,
2274 struct s3c_gpio_state_s *gpio)
2275 {
2276 int iomemtype;
2277 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *)
2278 qemu_mallocz(sizeof(struct s3c_spi_state_s));
2279
2280 s->base = base;
2281 s->chan[0].irq = irq0;
2282 s->chan[0].drq = drq0;
2283 s->chan[1].irq = irq1;
2284 s->chan[1].drq = drq1;
2285
2286 s3c_spi_reset(s);
2287
2288 iomemtype = cpu_register_io_memory(0, s3c_spi_readfn,
2289 s3c_spi_writefn, s);
2290 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2291
2292 s3c_spi_bitbang_init(s, gpio);
2293
2294 register_savevm("s3c24xx_spi", 0, 0, s3c_spi_save, s3c_spi_load, s);
2295
2296 return s;
2297 }
2298
2299 void s3c_spi_attach(struct s3c_spi_state_s *s, int ch,
2300 uint8_t (*txrx)(void *opaque, uint8_t value),
2301 uint8_t (*btxrx)(void *opaque, uint8_t value), void *opaque)
2302 {
2303 if (ch & ~1)
2304 cpu_abort(cpu_single_env, "%s: No channel %i\n", __FUNCTION__, ch);
2305 s->txrx[ch] = txrx;
2306 s->btxrx[ch] = btxrx;
2307 s->opaque[ch] = opaque;
2308 }
2309
2310 /* IIS-BUS interface */
2311 static inline void s3c_i2s_update(struct s3c_i2s_state_s *s)
2312 {
2313 s->tx_en =
2314 (s->control & (1 << 0)) && !(s->control & (1 << 3)) &&
2315 (s->mode & (1 << 7)) && (s->fcontrol & (1 << 13));
2316 s->rx_en =
2317 (s->control & (1 << 0)) && !(s->control & (1 << 2)) &&
2318 (s->mode & (1 << 6)) && (s->fcontrol & (1 << 12));
2319 s->control &= ~0xc0;
2320 /* The specs are unclear about the FIFO-ready flags logic.
2321 * Implement semantics that make most sense. */
2322 if (s->tx_en && s->tx_len)
2323 s->control |= (1 << 7);
2324 if (s->rx_en && s->rx_len)
2325 s->control |= (1 << 6);
2326
2327 qemu_set_irq(s->dma[S3C_RQ_I2SSDO], (s->control >> 5) &
2328 (s->control >> 7) & (s->fcontrol >> 15) & 1);
2329 qemu_set_irq(s->dma[S3C_RQ_I2SSDI0], (s->control >> 4) &
2330 (s->control >> 6) & (s->fcontrol >> 14) & 1);
2331 qemu_set_irq(s->dma[S3C_RQ_I2SSDI1], (s->control >> 4) &
2332 (s->control >> 6) & (s->fcontrol >> 14) & 1);
2333 }
2334
2335 static void s3c_i2s_reset(struct s3c_i2s_state_s *s)
2336 {
2337 s->control = 0x100;
2338 s->mode = 0x000;
2339 s->prescaler = 0x000;
2340 s->fcontrol = 0x0000;
2341 s->tx_len = 0;
2342 s->rx_len = 0;
2343 s3c_i2s_update(s);
2344 }
2345
2346 #define S3C_IISCON 0x00 /* IIS Control register */
2347 #define S3C_IISMOD 0x04 /* IIS Mode register */
2348 #define S3C_IISPSR 0x08 /* IIS Prescaler register */
2349 #define S3C_IISFCON 0x0c /* IIS FIFO Interface register */
2350 #define S3C_IISFIFO 0x10 /* IIS FIFO register */
2351
2352 static uint32_t s3c_i2s_read(void *opaque, target_phys_addr_t addr)
2353 {
2354 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2355 uint32_t ret;
2356
2357 switch (addr) {
2358 case S3C_IISCON:
2359 return s->control;
2360 case S3C_IISMOD:
2361 return s->mode;
2362 case S3C_IISPSR:
2363 return s->prescaler;
2364 case S3C_IISFCON:
2365 return s->fcontrol |
2366 (MAX(32 - s->tx_len, 0) << 6) |
2367 MIN(s->rx_len, 32);
2368 case S3C_IISFIFO:
2369 if (s->rx_len > 0) {
2370 s->rx_len --;
2371 s3c_i2s_update(s);
2372 s->cycle ^= 1;
2373 if (s->cycle) {
2374 s->buffer = (uint16_t) (ret = s->codec_in(s->opaque));
2375 return ret >> 16;
2376 } else
2377 return s->buffer;
2378 }
2379 default:
2380 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2381 break;
2382 }
2383 return 0;
2384 }
2385
2386 static void s3c_i2s_write(void *opaque, target_phys_addr_t addr,
2387 uint32_t value)
2388 {
2389 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2390
2391 switch (addr) {
2392 case S3C_IISCON:
2393 s->control = (s->control & 0x100) | (value & 0x03f);
2394 s3c_i2s_update(s);
2395 break;
2396 case S3C_IISMOD:
2397 s->mode = value & 0x1ff;
2398 s3c_i2s_update(s);
2399 break;
2400 case S3C_IISPSR:
2401 s->prescaler = value & 0x3ff;
2402 break;
2403 case S3C_IISFCON:
2404 s->fcontrol = value & 0xf000;
2405 s3c_i2s_update(s);
2406 break;
2407 case S3C_IISFIFO:
2408 if (s->tx_len && s->tx_en) {
2409 s->tx_len --;
2410 s3c_i2s_update(s);
2411 if (s->cycle)
2412 s->codec_out(s->opaque, value | ((uint32_t) s->buffer << 16));
2413 else
2414 s->buffer = (uint16_t) value;
2415 s->cycle ^= 1;
2416 }
2417 break;
2418 default:
2419 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2420 }
2421 }
2422
2423 static CPUReadMemoryFunc *s3c_i2s_readfn[] = {
2424 s3c_i2s_read,
2425 s3c_i2s_read,
2426 s3c_i2s_read,
2427 };
2428
2429 static CPUWriteMemoryFunc *s3c_i2s_writefn[] = {
2430 s3c_i2s_write,
2431 s3c_i2s_write,
2432 s3c_i2s_write,
2433 };
2434
2435 static void s3c_i2s_save(QEMUFile *f, void *opaque)
2436 {
2437 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2438 qemu_put_be16s(f, &s->control);
2439 qemu_put_be16s(f, &s->mode);
2440 qemu_put_be16s(f, &s->prescaler);
2441 qemu_put_be16s(f, &s->fcontrol);
2442
2443 qemu_put_be32(f, s->tx_en);
2444 qemu_put_be32(f, s->rx_en);
2445 qemu_put_be32(f, s->tx_len);
2446 qemu_put_be32(f, s->rx_len);
2447 qemu_put_be16(f, s->buffer);
2448 qemu_put_be32(f, s->cycle);
2449 }
2450
2451 static int s3c_i2s_load(QEMUFile *f, void *opaque, int version_id)
2452 {
2453 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2454 qemu_get_be16s(f, &s->control);
2455 qemu_get_be16s(f, &s->mode);
2456 qemu_get_be16s(f, &s->prescaler);
2457 qemu_get_be16s(f, &s->fcontrol);
2458
2459 s->tx_en = qemu_get_be32(f);
2460 s->rx_en = qemu_get_be32(f);
2461 s->tx_len = qemu_get_be32(f);
2462 s->rx_len = qemu_get_be32(f);
2463 s->buffer = qemu_get_be16(f);
2464 s->cycle = qemu_get_be32(f);
2465
2466 return 0;
2467 }
2468
2469 static void s3c_i2s_data_req(void *opaque, int tx, int rx)
2470 {
2471 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2472 s->tx_len = tx;
2473 s->rx_len = rx;
2474 s3c_i2s_update(s);
2475 }
2476
2477 struct s3c_i2s_state_s *s3c_i2s_init(target_phys_addr_t base, qemu_irq *dma)
2478 {
2479 int iomemtype;
2480 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *)
2481 qemu_mallocz(sizeof(struct s3c_i2s_state_s));
2482
2483 s->base = base;
2484 s->dma = dma;
2485 s->data_req = s3c_i2s_data_req;
2486
2487 s3c_i2s_reset(s);
2488
2489 iomemtype = cpu_register_io_memory(0, s3c_i2s_readfn,
2490 s3c_i2s_writefn, s);
2491 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2492
2493 register_savevm("s3c24xx_iis", 0, 0, s3c_i2s_save, s3c_i2s_load, s);
2494
2495 return s;
2496 }
2497
2498 /* Watchdog Timer */
2499 struct s3c_wdt_state_s {
2500 target_phys_addr_t base;
2501 qemu_irq irq;
2502 uint16_t control;
2503 uint16_t data;
2504 uint16_t count;
2505 QEMUTimer *tm;
2506 int64_t timestamp;
2507 };
2508
2509 static void s3c_wdt_start(struct s3c_wdt_state_s *s)
2510 {
2511 int enable = s->control & (1 << 5);
2512 int prescaler = (s->control >> 8) + 1;
2513 int divider = prescaler << (((s->control >> 3) & 3) + 4);
2514 if (enable) {
2515 s->timestamp = qemu_get_clock(vm_clock);
2516 qemu_mod_timer(s->tm, s->timestamp + muldiv64(divider * s->count,
2517 ticks_per_sec, S3C_PCLK_FREQ));
2518 } else
2519 qemu_del_timer(s->tm);
2520 }
2521
2522 static void s3c_wdt_stop(struct s3c_wdt_state_s *s)
2523 {
2524 int prescaler = (s->control >> 8) + 1;
2525 int divider = prescaler << (((s->control >> 3) & 3) + 4);
2526 int diff;
2527
2528 diff = muldiv64(qemu_get_clock(vm_clock) - s->timestamp, S3C_PCLK_FREQ,
2529 ticks_per_sec) / divider;
2530 s->count -= MIN(s->count, diff);
2531 s->timestamp = qemu_get_clock(vm_clock);
2532 }
2533
2534 static void s3c_wdt_reset(struct s3c_wdt_state_s *s)
2535 {
2536 s->control = 0x8021;
2537 s->data = 0x8000;
2538 s->count = 0x8000;
2539 s3c_wdt_start(s);
2540 }
2541
2542 static void s3c_wdt_timeout(void *opaque)
2543 {
2544 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2545 if (s->control & (1 << 0)) {
2546 qemu_system_reset_request();
2547 return;
2548 }
2549 if (s->control & (1 << 2))
2550 qemu_irq_raise(s->irq);
2551 s->count = s->data;
2552 s3c_wdt_start(s);
2553 }
2554
2555 #define S3C_WTCON 0x00 /* Watchdog timer control register */
2556 #define S3C_WTDAT 0x04 /* Watchdog timer data register */
2557 #define S3C_WTCNT 0x08 /* Watchdog timer count register */
2558
2559 static uint32_t s3c_wdt_read(void *opaque, target_phys_addr_t addr)
2560 {
2561 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2562
2563 switch (addr) {
2564 case S3C_WTCON:
2565 return s->control;
2566 case S3C_WTDAT:
2567 return s->data;
2568 case S3C_WTCNT:
2569 s3c_wdt_stop(s);
2570 return s->count;
2571 default:
2572 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2573 break;
2574 }
2575 return 0;
2576 }
2577
2578 static void s3c_wdt_write(void *opaque, target_phys_addr_t addr,
2579 uint32_t value)
2580 {
2581 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2582
2583 switch (addr) {
2584 case S3C_WTCON:
2585 s3c_wdt_stop(s);
2586 s->control = value;
2587 s3c_wdt_start(s);
2588 break;
2589 case S3C_WTDAT:
2590 s->data = value;
2591 break;
2592 case S3C_WTCNT:
2593 s->count = value;
2594 s3c_wdt_start(s);
2595 break;
2596 default:
2597 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2598 }
2599 }
2600
2601 static CPUReadMemoryFunc *s3c_wdt_readfn[] = {
2602 s3c_wdt_read,
2603 s3c_wdt_read,
2604 s3c_wdt_read,
2605 };
2606
2607 static CPUWriteMemoryFunc *s3c_wdt_writefn[] = {
2608 s3c_wdt_write,
2609 s3c_wdt_write,
2610 s3c_wdt_write,
2611 };
2612
2613 static void s3c_wdt_save(QEMUFile *f, void *opaque)
2614 {
2615 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2616
2617 s3c_wdt_stop(s);
2618 qemu_put_be16s(f, &s->control);
2619 qemu_put_be16s(f, &s->data);
2620 qemu_put_be16s(f, &s->count);
2621 qemu_put_be64s(f, &s->timestamp);
2622 }
2623
2624 static int s3c_wdt_load(QEMUFile *f, void *opaque, int version_id)
2625 {
2626 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2627
2628 qemu_get_be16s(f, &s->control);
2629 qemu_get_be16s(f, &s->data);
2630 qemu_get_be16s(f, &s->count);
2631 qemu_get_be64s(f, &s->timestamp);
2632 s3c_wdt_start(s);
2633
2634 return 0;
2635 }
2636
2637 struct s3c_wdt_state_s *s3c_wdt_init(target_phys_addr_t base, qemu_irq irq)
2638 {
2639 int iomemtype;
2640 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *)
2641 qemu_mallocz(sizeof(struct s3c_wdt_state_s));
2642
2643 s->base = base;
2644 s->irq = irq;
2645 s->tm = qemu_new_timer(vm_clock, s3c_wdt_timeout, s);
2646
2647 s3c_wdt_reset(s);
2648
2649 iomemtype = cpu_register_io_memory(0, s3c_wdt_readfn,
2650 s3c_wdt_writefn, s);
2651 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2652
2653 register_savevm("s3c24xx_wdt", 0, 0, s3c_wdt_save, s3c_wdt_load, s);
2654
2655 return s;
2656 }
2657
2658 /* On-chip UARTs */
2659 static struct {
2660 target_phys_addr_t base;
2661 int irq[3];
2662 int dma[1];
2663 } s3c2410_uart[] = {
2664 {
2665 0x50000000,
2666 { S3C_PICS_RXD0, S3C_PICS_TXD0, S3C_PICS_ERR0 },
2667 { S3C_RQ_UART0 },
2668 },
2669 {
2670 0x50004000,
2671 { S3C_PICS_RXD1, S3C_PICS_TXD1, S3C_PICS_ERR1 },
2672 { S3C_RQ_UART1 },
2673 },
2674 {
2675 0x50008000,
2676 { S3C_PICS_RXD2, S3C_PICS_TXD2, S3C_PICS_ERR2 },
2677 { S3C_RQ_UART2 },
2678 },
2679 { 0, { 0, 0, 0 }, { 0 } }
2680 };
2681
2682 /* General CPU reset */
2683 static void s3c2410_reset(void *opaque)
2684 {
2685 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
2686 int i;
2687 s3c_mc_reset(s);
2688 s3c_pic_reset(s->pic);
2689 s3c_dma_reset(s->dma);
2690 s3c_gpio_reset(s->io);
2691 s3c_lcd_reset(s->lcd);
2692 s3c_timers_reset(s->timers);
2693 s3c_mmci_reset(s->mmci);
2694 s3c_adc_reset(s->adc);
2695 s3c_i2c_reset(s->i2c);
2696 s3c_i2s_reset(s->i2s);
2697 s3c_rtc_reset(s->rtc);
2698 s3c_spi_reset(s->spi);
2699 s3c_udc_reset(s->udc);
2700 s3c_wdt_reset(s->wdt);
2701 s3c_clkpwr_reset(s);
2702 s->nand->reset(s->nand);
2703 for (i = 0; s3c2410_uart[i].base; i ++)
2704 s3c_uart_reset(s->uart[i]);
2705 cpu_reset(s->env);
2706 }
2707
2708 struct s3c_state_s * g_s3c;
2709
2710 /* Initialise an S3C24XX microprocessor. */
2711 struct s3c_state_s *s3c24xx_init(
2712 uint32_t cpu_id,
2713 unsigned int sdram_size,
2714 uint32_t sram_address,
2715 SDState *mmc)
2716 {
2717 struct s3c_state_s *s;
2718 int iomemtype, i;
2719 s = (struct s3c_state_s *) qemu_mallocz(sizeof(struct s3c_state_s));
2720
2721 g_s3c = s;
2722
2723 s->cpu_id = cpu_id;
2724
2725 s->env = cpu_init("arm920t");
2726 if (!s->env) {
2727 fprintf(stderr, "Unable to initialize ARM920T\n");
2728 exit(2);
2729 }
2730 register_savevm("s3c24xx", 0, 0,
2731 cpu_save, cpu_load, s->env);
2732
2733 cpu_register_physical_memory(S3C_RAM_BASE, sdram_size,
2734 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2735
2736 /* If OM pins are 00, SRAM is mapped at 0x0 instead. */
2737 cpu_register_physical_memory(sram_address, S3C_SRAM_SIZE,
2738 qemu_ram_alloc(S3C_SRAM_SIZE) | IO_MEM_RAM);
2739
2740 s->mc_base = 0x48000000;
2741 s3c_mc_reset(s);
2742 iomemtype = cpu_register_io_memory(0, s3c_mc_readfn, s3c_mc_writefn, s);
2743 cpu_register_physical_memory(s->mc_base, 0xffffff, iomemtype);
2744 register_savevm("s3c24xx_mc", 0, 0, s3c_mc_save, s3c_mc_load, s);
2745
2746 s->pic = s3c_pic_init(0x4a000000, arm_pic_init_cpu(s->env));
2747 s->irq = s3c_pic_get(s->pic);
2748
2749 s->dma = s3c_dma_init(0x4b000000, &s->irq[S3C_PIC_DMA0]);
2750 s->drq = s3c_dma_get(s->dma);
2751
2752 s->clkpwr_base = 0x4c000000;
2753 s3c_clkpwr_reset(s);
2754 iomemtype = cpu_register_io_memory(0, s3c_clkpwr_readfn,
2755 s3c_clkpwr_writefn, s);
2756 cpu_register_physical_memory(s->clkpwr_base, 0xffffff, iomemtype);
2757 register_savevm("s3c24xx_clkpwr", 0, 0,
2758 s3c_clkpwr_save, s3c_clkpwr_load, s);
2759
2760 s->lcd = s3c_lcd_init(0x4d000000, s->irq[S3C_PIC_LCD]);
2761
2762 if (s->cpu_id == S3C_CPU_2440)
2763 s->nand = s3c2440_nand_init();
2764 else
2765 s->nand = s3c2410_nand_init();
2766
2767 for (i = 0; s3c2410_uart[i].base; i ++) {
2768 s->uart[i] = s3c_uart_init(s3c2410_uart[i].base,
2769 &s->irq[s3c2410_uart[i].irq[0]],
2770 &s->drq[s3c2410_uart[i].dma[0]]);
2771 if (serial_hds[i])
2772 s3c_uart_attach(s->uart[i], serial_hds[i]);
2773 }
2774
2775 s->timers = s3c_timers_init(0x51000000, &s->irq[S3C_PIC_TIMER0], s->drq);
2776
2777 s->udc = s3c_udc_init(0x52000000, s->irq[S3C_PIC_USBD], s->drq);
2778
2779 s->wdt = s3c_wdt_init(0x53000000, s->irq[S3C_PIC_WDT]);
2780
2781 s->i2c = s3c_i2c_init(0x54000000, s->irq[S3C_PIC_IIC]);
2782
2783 s->i2s = s3c_i2s_init(0x55000000, s->drq);
2784
2785 s->io = s3c_gpio_init(0x56000000, s->irq, s->cpu_id);
2786
2787 s->rtc = s3c_rtc_init(0x57000000, s->irq[S3C_PIC_RTC]);
2788
2789 s->adc = s3c_adc_init(0x58000000, s->irq[S3C_PICS_ADC],
2790 s->irq[S3C_PICS_TC]);
2791
2792 s->spi = s3c_spi_init(0x59000000,
2793 s->irq[S3C_PIC_SPI0], s->drq[S3C_RQ_SPI0],
2794 s->irq[S3C_PIC_SPI1], s->drq[S3C_RQ_SPI1], s->io);
2795
2796 s->mmci = s3c_mmci_init(0x5a000000, s->cpu_id, mmc,
2797 s->irq[S3C_PIC_SDI], s->drq);
2798
2799 if (usb_enabled) {
2800 usb_ohci_init_pxa(0x49000000, 3, -1, s->irq[S3C_PIC_USBH]);
2801 }
2802
2803 qemu_register_reset(s3c2410_reset, s);
2804
2805 s->nand->setwp(s->nand, 1);
2806
2807 /* Power on reset */
2808 s3c_gpio_setpwrstat(s->io, 1);
2809 return s;
2810 }
Samsung s3c2440 and arm920t support for the mini2440 dev board