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[qemu/mini2440.git] / hw / sun4m.c
blobec933786ef817d2085fe4cda5bf0f15d84a4dc79
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39
40 //#define DEBUG_IRQ
41
42 /*
43 * Sun4m architecture was used in the following machines:
44 *
45 * SPARCserver 6xxMP/xx
46 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47 * SPARCclassic X (4/10)
48 * SPARCstation LX/ZX (4/30)
49 * SPARCstation Voyager
50 * SPARCstation 10/xx, SPARCserver 10/xx
51 * SPARCstation 5, SPARCserver 5
52 * SPARCstation 20/xx, SPARCserver 20
53 * SPARCstation 4
54 *
55 * Sun4d architecture was used in the following machines:
56 *
57 * SPARCcenter 2000
58 * SPARCserver 1000
59 *
60 * Sun4c architecture was used in the following machines:
61 * SPARCstation 1/1+, SPARCserver 1/1+
62 * SPARCstation SLC
63 * SPARCstation IPC
64 * SPARCstation ELC
65 * SPARCstation IPX
66 *
67 * See for example: http://www.sunhelp.org/faq/sunref1.html
68 */
69
70 #ifdef DEBUG_IRQ
71 #define DPRINTF(fmt, ...) \
72 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
73 #else
74 #define DPRINTF(fmt, ...)
75 #endif
76
77 #define KERNEL_LOAD_ADDR 0x00004000
78 #define CMDLINE_ADDR 0x007ff000
79 #define INITRD_LOAD_ADDR 0x00800000
80 #define PROM_SIZE_MAX (1024 * 1024)
81 #define PROM_VADDR 0xffd00000
82 #define PROM_FILENAME "openbios-sparc32"
83 #define CFG_ADDR 0xd00000510ULL
84 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85
86 #define MAX_CPUS 16
87 #define MAX_PILS 16
88
89 #define ESCC_CLOCK 4915200
90
91 struct sun4m_hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint32_t intbit_to_level[32];
148 uint64_t max_mem;
149 const char * const default_cpu_model;
150 };
151
152 int DMA_get_channel_mode (int nchan)
153 {
154 return 0;
155 }
156 int DMA_read_memory (int nchan, void *buf, int pos, int size)
157 {
158 return 0;
159 }
160 int DMA_write_memory (int nchan, void *buf, int pos, int size)
161 {
162 return 0;
163 }
164 void DMA_hold_DREQ (int nchan) {}
165 void DMA_release_DREQ (int nchan) {}
166 void DMA_schedule(int nchan) {}
167 void DMA_init (int high_page_enable) {}
168 void DMA_register_channel (int nchan,
169 DMA_transfer_handler transfer_handler,
170 void *opaque)
171 {
172 }
173
174 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
175 {
176 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
177 return 0;
178 }
179
180 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
181 const char *boot_devices, ram_addr_t RAM_size,
182 uint32_t kernel_size,
183 int width, int height, int depth,
184 int nvram_machine_id, const char *arch)
185 {
186 unsigned int i;
187 uint32_t start, end;
188 uint8_t image[0x1ff0];
189 struct OpenBIOS_nvpart_v1 *part_header;
190
191 memset(image, '\0', sizeof(image));
192
193 start = 0;
194
195 // OpenBIOS nvram variables
196 // Variable partition
197 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
198 part_header->signature = OPENBIOS_PART_SYSTEM;
199 pstrcpy(part_header->name, sizeof(part_header->name), "system");
200
201 end = start + sizeof(struct OpenBIOS_nvpart_v1);
202 for (i = 0; i < nb_prom_envs; i++)
203 end = OpenBIOS_set_var(image, end, prom_envs[i]);
204
205 // End marker
206 image[end++] = '\0';
207
208 end = start + ((end - start + 15) & ~15);
209 OpenBIOS_finish_partition(part_header, end - start);
210
211 // free partition
212 start = end;
213 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
214 part_header->signature = OPENBIOS_PART_FREE;
215 pstrcpy(part_header->name, sizeof(part_header->name), "free");
216
217 end = 0x1fd0;
218 OpenBIOS_finish_partition(part_header, end - start);
219
220 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
221 nvram_machine_id);
222
223 for (i = 0; i < sizeof(image); i++)
224 m48t59_write(nvram, i, image[i]);
225 }
226
227 static void *slavio_intctl;
228
229 void pic_info(Monitor *mon)
230 {
231 if (slavio_intctl)
232 slavio_pic_info(mon, slavio_intctl);
233 }
234
235 void irq_info(Monitor *mon)
236 {
237 if (slavio_intctl)
238 slavio_irq_info(mon, slavio_intctl);
239 }
240
241 void cpu_check_irqs(CPUState *env)
242 {
243 if (env->pil_in && (env->interrupt_index == 0 ||
244 (env->interrupt_index & ~15) == TT_EXTINT)) {
245 unsigned int i;
246
247 for (i = 15; i > 0; i--) {
248 if (env->pil_in & (1 << i)) {
249 int old_interrupt = env->interrupt_index;
250
251 env->interrupt_index = TT_EXTINT | i;
252 if (old_interrupt != env->interrupt_index) {
253 DPRINTF("Set CPU IRQ %d\n", i);
254 cpu_interrupt(env, CPU_INTERRUPT_HARD);
255 }
256 break;
257 }
258 }
259 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
260 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
261 env->interrupt_index = 0;
262 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
263 }
264 }
265
266 static void cpu_set_irq(void *opaque, int irq, int level)
267 {
268 CPUState *env = opaque;
269
270 if (level) {
271 DPRINTF("Raise CPU IRQ %d\n", irq);
272 env->halted = 0;
273 env->pil_in |= 1 << irq;
274 cpu_check_irqs(env);
275 } else {
276 DPRINTF("Lower CPU IRQ %d\n", irq);
277 env->pil_in &= ~(1 << irq);
278 cpu_check_irqs(env);
279 }
280 }
281
282 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
283 {
284 }
285
286 static void *slavio_misc;
287
288 void qemu_system_powerdown(void)
289 {
290 slavio_set_power_fail(slavio_misc, 1);
291 }
292
293 static void main_cpu_reset(void *opaque)
294 {
295 CPUState *env = opaque;
296
297 cpu_reset(env);
298 env->halted = 0;
299 }
300
301 static void secondary_cpu_reset(void *opaque)
302 {
303 CPUState *env = opaque;
304
305 cpu_reset(env);
306 env->halted = 1;
307 }
308
309 static void cpu_halt_signal(void *opaque, int irq, int level)
310 {
311 if (level && cpu_single_env)
312 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
313 }
314
315 static unsigned long sun4m_load_kernel(const char *kernel_filename,
316 const char *initrd_filename,
317 ram_addr_t RAM_size)
318 {
319 int linux_boot;
320 unsigned int i;
321 long initrd_size, kernel_size;
322
323 linux_boot = (kernel_filename != NULL);
324
325 kernel_size = 0;
326 if (linux_boot) {
327 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
328 NULL);
329 if (kernel_size < 0)
330 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
331 RAM_size - KERNEL_LOAD_ADDR);
332 if (kernel_size < 0)
333 kernel_size = load_image_targphys(kernel_filename,
334 KERNEL_LOAD_ADDR,
335 RAM_size - KERNEL_LOAD_ADDR);
336 if (kernel_size < 0) {
337 fprintf(stderr, "qemu: could not load kernel '%s'\n",
338 kernel_filename);
339 exit(1);
340 }
341
342 /* load initrd */
343 initrd_size = 0;
344 if (initrd_filename) {
345 initrd_size = load_image_targphys(initrd_filename,
346 INITRD_LOAD_ADDR,
347 RAM_size - INITRD_LOAD_ADDR);
348 if (initrd_size < 0) {
349 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
350 initrd_filename);
351 exit(1);
352 }
353 }
354 if (initrd_size > 0) {
355 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
356 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
357 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
358 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
359 break;
360 }
361 }
362 }
363 }
364 return kernel_size;
365 }
366
367 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
368 void *dma_opaque, qemu_irq irq, qemu_irq *reset)
369 {
370 DeviceState *dev;
371 SysBusDevice *s;
372
373 qemu_check_nic_model(&nd_table[0], "lance");
374
375 dev = qdev_create(NULL, "lance");
376 qdev_set_netdev(dev, nd);
377 qdev_set_prop_ptr(dev, "dma", dma_opaque);
378 qdev_init(dev);
379 s = sysbus_from_qdev(dev);
380 sysbus_mmio_map(s, 0, leaddr);
381 sysbus_connect_irq(s, 0, irq);
382 *reset = qdev_get_irq_sink(dev, 0);
383 }
384
385 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
386 const char *boot_device,
387 const char *kernel_filename,
388 const char *kernel_cmdline,
389 const char *initrd_filename, const char *cpu_model)
390
391 {
392 CPUState *env, *envs[MAX_CPUS];
393 unsigned int i;
394 void *iommu, *espdma, *ledma, *nvram;
395 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
396 *espdma_irq, *ledma_irq;
397 qemu_irq *esp_reset, *le_reset;
398 qemu_irq *fdc_tc;
399 qemu_irq *cpu_halt;
400 ram_addr_t ram_offset, prom_offset, idreg_offset;
401 unsigned long kernel_size;
402 int ret;
403 char buf[1024];
404 BlockDriverState *fd[MAX_FD];
405 int drive_index;
406 void *fw_cfg;
407
408 /* init CPUs */
409 if (!cpu_model)
410 cpu_model = hwdef->default_cpu_model;
411
412 for(i = 0; i < smp_cpus; i++) {
413 env = cpu_init(cpu_model);
414 if (!env) {
415 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
416 exit(1);
417 }
418 cpu_sparc_set_id(env, i);
419 envs[i] = env;
420 if (i == 0) {
421 qemu_register_reset(main_cpu_reset, env);
422 } else {
423 qemu_register_reset(secondary_cpu_reset, env);
424 env->halted = 1;
425 }
426 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
427 env->prom_addr = hwdef->slavio_base;
428 }
429
430 for (i = smp_cpus; i < MAX_CPUS; i++)
431 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
432
433
434 /* allocate RAM */
435 if ((uint64_t)RAM_size > hwdef->max_mem) {
436 fprintf(stderr,
437 "qemu: Too much memory for this machine: %d, maximum %d\n",
438 (unsigned int)(RAM_size / (1024 * 1024)),
439 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
440 exit(1);
441 }
442 ram_offset = qemu_ram_alloc(RAM_size);
443 cpu_register_physical_memory(0, RAM_size, ram_offset);
444
445 /* load boot prom */
446 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
447 cpu_register_physical_memory(hwdef->slavio_base,
448 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
449 TARGET_PAGE_MASK,
450 prom_offset | IO_MEM_ROM);
451
452 if (bios_name == NULL)
453 bios_name = PROM_FILENAME;
454 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
455 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
456 if (ret < 0 || ret > PROM_SIZE_MAX)
457 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
458 if (ret < 0 || ret > PROM_SIZE_MAX) {
459 fprintf(stderr, "qemu: could not load prom '%s'\n",
460 buf);
461 exit(1);
462 }
463
464 /* set up devices */
465 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
466 hwdef->intctl_base + 0x10000ULL,
467 &hwdef->intbit_to_level[0],
468 &slavio_irq, &slavio_cpu_irq,
469 cpu_irqs,
470 hwdef->clock_irq);
471
472 if (hwdef->idreg_base) {
473 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
474
475 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
476 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
477 idreg_offset | IO_MEM_ROM);
478 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
479 sizeof(idreg_data));
480 }
481
482 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
483 slavio_irq[hwdef->me_irq]);
484
485 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
486 iommu, &espdma_irq, &esp_reset);
487
488 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
489 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
490 &le_reset);
491
492 if (graphic_depth != 8 && graphic_depth != 24) {
493 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
494 exit (1);
495 }
496 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
497 graphic_depth);
498
499 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
500
501 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
502 hwdef->nvram_size, 8);
503
504 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
505 slavio_cpu_irq, smp_cpus);
506
507 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
508 nographic, ESCC_CLOCK, 1);
509 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
510 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
511 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
512 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
513
514 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
515 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
516 hwdef->aux1_base, hwdef->aux2_base,
517 slavio_irq[hwdef->me_irq], cpu_halt[0],
518 &fdc_tc);
519
520 if (hwdef->fd_base) {
521 /* there is zero or one floppy drive */
522 memset(fd, 0, sizeof(fd));
523 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
524 if (drive_index != -1)
525 fd[0] = drives_table[drive_index].bdrv;
526
527 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
528 fdc_tc);
529 }
530
531 if (drive_get_max_bus(IF_SCSI) > 0) {
532 fprintf(stderr, "qemu: too many SCSI bus\n");
533 exit(1);
534 }
535
536 esp_init(hwdef->esp_base, 2,
537 espdma_memory_read, espdma_memory_write,
538 espdma, *espdma_irq, esp_reset);
539
540 if (hwdef->cs_base)
541 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
542
543 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
544 RAM_size);
545
546 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
547 boot_device, RAM_size, kernel_size, graphic_width,
548 graphic_height, graphic_depth, hwdef->nvram_machine_id,
549 "Sun4m");
550
551 if (hwdef->ecc_base)
552 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
553 hwdef->ecc_version);
554
555 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
556 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
557 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
558 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
559 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
560 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
561 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
562 if (kernel_cmdline) {
563 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
564 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
565 } else {
566 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
567 }
568 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
569 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
570 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
571 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
572 }
573
574 enum {
575 ss2_id = 0,
576 ss5_id = 32,
577 vger_id,
578 lx_id,
579 ss4_id,
580 scls_id,
581 sbook_id,
582 ss10_id = 64,
583 ss20_id,
584 ss600mp_id,
585 ss1000_id = 96,
586 ss2000_id,
587 };
588
589 static const struct sun4m_hwdef sun4m_hwdefs[] = {
590 /* SS-5 */
591 {
592 .iommu_base = 0x10000000,
593 .tcx_base = 0x50000000,
594 .cs_base = 0x6c000000,
595 .slavio_base = 0x70000000,
596 .ms_kb_base = 0x71000000,
597 .serial_base = 0x71100000,
598 .nvram_base = 0x71200000,
599 .fd_base = 0x71400000,
600 .counter_base = 0x71d00000,
601 .intctl_base = 0x71e00000,
602 .idreg_base = 0x78000000,
603 .dma_base = 0x78400000,
604 .esp_base = 0x78800000,
605 .le_base = 0x78c00000,
606 .apc_base = 0x6a000000,
607 .aux1_base = 0x71900000,
608 .aux2_base = 0x71910000,
609 .vram_size = 0x00100000,
610 .nvram_size = 0x2000,
611 .esp_irq = 18,
612 .le_irq = 16,
613 .clock_irq = 7,
614 .clock1_irq = 19,
615 .ms_kb_irq = 14,
616 .ser_irq = 15,
617 .fd_irq = 22,
618 .me_irq = 30,
619 .cs_irq = 5,
620 .nvram_machine_id = 0x80,
621 .machine_id = ss5_id,
622 .iommu_version = 0x05000000,
623 .intbit_to_level = {
624 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
625 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
626 },
627 .max_mem = 0x10000000,
628 .default_cpu_model = "Fujitsu MB86904",
629 },
630 /* SS-10 */
631 {
632 .iommu_base = 0xfe0000000ULL,
633 .tcx_base = 0xe20000000ULL,
634 .slavio_base = 0xff0000000ULL,
635 .ms_kb_base = 0xff1000000ULL,
636 .serial_base = 0xff1100000ULL,
637 .nvram_base = 0xff1200000ULL,
638 .fd_base = 0xff1700000ULL,
639 .counter_base = 0xff1300000ULL,
640 .intctl_base = 0xff1400000ULL,
641 .idreg_base = 0xef0000000ULL,
642 .dma_base = 0xef0400000ULL,
643 .esp_base = 0xef0800000ULL,
644 .le_base = 0xef0c00000ULL,
645 .apc_base = 0xefa000000ULL, // XXX should not exist
646 .aux1_base = 0xff1800000ULL,
647 .aux2_base = 0xff1a01000ULL,
648 .ecc_base = 0xf00000000ULL,
649 .ecc_version = 0x10000000, // version 0, implementation 1
650 .vram_size = 0x00100000,
651 .nvram_size = 0x2000,
652 .esp_irq = 18,
653 .le_irq = 16,
654 .clock_irq = 7,
655 .clock1_irq = 19,
656 .ms_kb_irq = 14,
657 .ser_irq = 15,
658 .fd_irq = 22,
659 .me_irq = 30,
660 .ecc_irq = 28,
661 .nvram_machine_id = 0x72,
662 .machine_id = ss10_id,
663 .iommu_version = 0x03000000,
664 .intbit_to_level = {
665 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
666 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
667 },
668 .max_mem = 0xf00000000ULL,
669 .default_cpu_model = "TI SuperSparc II",
670 },
671 /* SS-600MP */
672 {
673 .iommu_base = 0xfe0000000ULL,
674 .tcx_base = 0xe20000000ULL,
675 .slavio_base = 0xff0000000ULL,
676 .ms_kb_base = 0xff1000000ULL,
677 .serial_base = 0xff1100000ULL,
678 .nvram_base = 0xff1200000ULL,
679 .counter_base = 0xff1300000ULL,
680 .intctl_base = 0xff1400000ULL,
681 .dma_base = 0xef0081000ULL,
682 .esp_base = 0xef0080000ULL,
683 .le_base = 0xef0060000ULL,
684 .apc_base = 0xefa000000ULL, // XXX should not exist
685 .aux1_base = 0xff1800000ULL,
686 .aux2_base = 0xff1a01000ULL, // XXX should not exist
687 .ecc_base = 0xf00000000ULL,
688 .ecc_version = 0x00000000, // version 0, implementation 0
689 .vram_size = 0x00100000,
690 .nvram_size = 0x2000,
691 .esp_irq = 18,
692 .le_irq = 16,
693 .clock_irq = 7,
694 .clock1_irq = 19,
695 .ms_kb_irq = 14,
696 .ser_irq = 15,
697 .fd_irq = 22,
698 .me_irq = 30,
699 .ecc_irq = 28,
700 .nvram_machine_id = 0x71,
701 .machine_id = ss600mp_id,
702 .iommu_version = 0x01000000,
703 .intbit_to_level = {
704 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
705 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
706 },
707 .max_mem = 0xf00000000ULL,
708 .default_cpu_model = "TI SuperSparc II",
709 },
710 /* SS-20 */
711 {
712 .iommu_base = 0xfe0000000ULL,
713 .tcx_base = 0xe20000000ULL,
714 .slavio_base = 0xff0000000ULL,
715 .ms_kb_base = 0xff1000000ULL,
716 .serial_base = 0xff1100000ULL,
717 .nvram_base = 0xff1200000ULL,
718 .fd_base = 0xff1700000ULL,
719 .counter_base = 0xff1300000ULL,
720 .intctl_base = 0xff1400000ULL,
721 .idreg_base = 0xef0000000ULL,
722 .dma_base = 0xef0400000ULL,
723 .esp_base = 0xef0800000ULL,
724 .le_base = 0xef0c00000ULL,
725 .apc_base = 0xefa000000ULL, // XXX should not exist
726 .aux1_base = 0xff1800000ULL,
727 .aux2_base = 0xff1a01000ULL,
728 .ecc_base = 0xf00000000ULL,
729 .ecc_version = 0x20000000, // version 0, implementation 2
730 .vram_size = 0x00100000,
731 .nvram_size = 0x2000,
732 .esp_irq = 18,
733 .le_irq = 16,
734 .clock_irq = 7,
735 .clock1_irq = 19,
736 .ms_kb_irq = 14,
737 .ser_irq = 15,
738 .fd_irq = 22,
739 .me_irq = 30,
740 .ecc_irq = 28,
741 .nvram_machine_id = 0x72,
742 .machine_id = ss20_id,
743 .iommu_version = 0x13000000,
744 .intbit_to_level = {
745 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
746 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
747 },
748 .max_mem = 0xf00000000ULL,
749 .default_cpu_model = "TI SuperSparc II",
750 },
751 /* Voyager */
752 {
753 .iommu_base = 0x10000000,
754 .tcx_base = 0x50000000,
755 .slavio_base = 0x70000000,
756 .ms_kb_base = 0x71000000,
757 .serial_base = 0x71100000,
758 .nvram_base = 0x71200000,
759 .fd_base = 0x71400000,
760 .counter_base = 0x71d00000,
761 .intctl_base = 0x71e00000,
762 .idreg_base = 0x78000000,
763 .dma_base = 0x78400000,
764 .esp_base = 0x78800000,
765 .le_base = 0x78c00000,
766 .apc_base = 0x71300000, // pmc
767 .aux1_base = 0x71900000,
768 .aux2_base = 0x71910000,
769 .vram_size = 0x00100000,
770 .nvram_size = 0x2000,
771 .esp_irq = 18,
772 .le_irq = 16,
773 .clock_irq = 7,
774 .clock1_irq = 19,
775 .ms_kb_irq = 14,
776 .ser_irq = 15,
777 .fd_irq = 22,
778 .me_irq = 30,
779 .nvram_machine_id = 0x80,
780 .machine_id = vger_id,
781 .iommu_version = 0x05000000,
782 .intbit_to_level = {
783 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
784 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
785 },
786 .max_mem = 0x10000000,
787 .default_cpu_model = "Fujitsu MB86904",
788 },
789 /* LX */
790 {
791 .iommu_base = 0x10000000,
792 .tcx_base = 0x50000000,
793 .slavio_base = 0x70000000,
794 .ms_kb_base = 0x71000000,
795 .serial_base = 0x71100000,
796 .nvram_base = 0x71200000,
797 .fd_base = 0x71400000,
798 .counter_base = 0x71d00000,
799 .intctl_base = 0x71e00000,
800 .idreg_base = 0x78000000,
801 .dma_base = 0x78400000,
802 .esp_base = 0x78800000,
803 .le_base = 0x78c00000,
804 .aux1_base = 0x71900000,
805 .aux2_base = 0x71910000,
806 .vram_size = 0x00100000,
807 .nvram_size = 0x2000,
808 .esp_irq = 18,
809 .le_irq = 16,
810 .clock_irq = 7,
811 .clock1_irq = 19,
812 .ms_kb_irq = 14,
813 .ser_irq = 15,
814 .fd_irq = 22,
815 .me_irq = 30,
816 .nvram_machine_id = 0x80,
817 .machine_id = lx_id,
818 .iommu_version = 0x04000000,
819 .intbit_to_level = {
820 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
821 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
822 },
823 .max_mem = 0x10000000,
824 .default_cpu_model = "TI MicroSparc I",
825 },
826 /* SS-4 */
827 {
828 .iommu_base = 0x10000000,
829 .tcx_base = 0x50000000,
830 .cs_base = 0x6c000000,
831 .slavio_base = 0x70000000,
832 .ms_kb_base = 0x71000000,
833 .serial_base = 0x71100000,
834 .nvram_base = 0x71200000,
835 .fd_base = 0x71400000,
836 .counter_base = 0x71d00000,
837 .intctl_base = 0x71e00000,
838 .idreg_base = 0x78000000,
839 .dma_base = 0x78400000,
840 .esp_base = 0x78800000,
841 .le_base = 0x78c00000,
842 .apc_base = 0x6a000000,
843 .aux1_base = 0x71900000,
844 .aux2_base = 0x71910000,
845 .vram_size = 0x00100000,
846 .nvram_size = 0x2000,
847 .esp_irq = 18,
848 .le_irq = 16,
849 .clock_irq = 7,
850 .clock1_irq = 19,
851 .ms_kb_irq = 14,
852 .ser_irq = 15,
853 .fd_irq = 22,
854 .me_irq = 30,
855 .cs_irq = 5,
856 .nvram_machine_id = 0x80,
857 .machine_id = ss4_id,
858 .iommu_version = 0x05000000,
859 .intbit_to_level = {
860 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
861 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
862 },
863 .max_mem = 0x10000000,
864 .default_cpu_model = "Fujitsu MB86904",
865 },
866 /* SPARCClassic */
867 {
868 .iommu_base = 0x10000000,
869 .tcx_base = 0x50000000,
870 .slavio_base = 0x70000000,
871 .ms_kb_base = 0x71000000,
872 .serial_base = 0x71100000,
873 .nvram_base = 0x71200000,
874 .fd_base = 0x71400000,
875 .counter_base = 0x71d00000,
876 .intctl_base = 0x71e00000,
877 .idreg_base = 0x78000000,
878 .dma_base = 0x78400000,
879 .esp_base = 0x78800000,
880 .le_base = 0x78c00000,
881 .apc_base = 0x6a000000,
882 .aux1_base = 0x71900000,
883 .aux2_base = 0x71910000,
884 .vram_size = 0x00100000,
885 .nvram_size = 0x2000,
886 .esp_irq = 18,
887 .le_irq = 16,
888 .clock_irq = 7,
889 .clock1_irq = 19,
890 .ms_kb_irq = 14,
891 .ser_irq = 15,
892 .fd_irq = 22,
893 .me_irq = 30,
894 .nvram_machine_id = 0x80,
895 .machine_id = scls_id,
896 .iommu_version = 0x05000000,
897 .intbit_to_level = {
898 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
899 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
900 },
901 .max_mem = 0x10000000,
902 .default_cpu_model = "TI MicroSparc I",
903 },
904 /* SPARCbook */
905 {
906 .iommu_base = 0x10000000,
907 .tcx_base = 0x50000000, // XXX
908 .slavio_base = 0x70000000,
909 .ms_kb_base = 0x71000000,
910 .serial_base = 0x71100000,
911 .nvram_base = 0x71200000,
912 .fd_base = 0x71400000,
913 .counter_base = 0x71d00000,
914 .intctl_base = 0x71e00000,
915 .idreg_base = 0x78000000,
916 .dma_base = 0x78400000,
917 .esp_base = 0x78800000,
918 .le_base = 0x78c00000,
919 .apc_base = 0x6a000000,
920 .aux1_base = 0x71900000,
921 .aux2_base = 0x71910000,
922 .vram_size = 0x00100000,
923 .nvram_size = 0x2000,
924 .esp_irq = 18,
925 .le_irq = 16,
926 .clock_irq = 7,
927 .clock1_irq = 19,
928 .ms_kb_irq = 14,
929 .ser_irq = 15,
930 .fd_irq = 22,
931 .me_irq = 30,
932 .nvram_machine_id = 0x80,
933 .machine_id = sbook_id,
934 .iommu_version = 0x05000000,
935 .intbit_to_level = {
936 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
937 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
938 },
939 .max_mem = 0x10000000,
940 .default_cpu_model = "TI MicroSparc I",
941 },
942 };
943
944 /* SPARCstation 5 hardware initialisation */
945 static void ss5_init(ram_addr_t RAM_size,
946 const char *boot_device,
947 const char *kernel_filename, const char *kernel_cmdline,
948 const char *initrd_filename, const char *cpu_model)
949 {
950 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
951 kernel_cmdline, initrd_filename, cpu_model);
952 }
953
954 /* SPARCstation 10 hardware initialisation */
955 static void ss10_init(ram_addr_t RAM_size,
956 const char *boot_device,
957 const char *kernel_filename, const char *kernel_cmdline,
958 const char *initrd_filename, const char *cpu_model)
959 {
960 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
961 kernel_cmdline, initrd_filename, cpu_model);
962 }
963
964 /* SPARCserver 600MP hardware initialisation */
965 static void ss600mp_init(ram_addr_t RAM_size,
966 const char *boot_device,
967 const char *kernel_filename,
968 const char *kernel_cmdline,
969 const char *initrd_filename, const char *cpu_model)
970 {
971 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
972 kernel_cmdline, initrd_filename, cpu_model);
973 }
974
975 /* SPARCstation 20 hardware initialisation */
976 static void ss20_init(ram_addr_t RAM_size,
977 const char *boot_device,
978 const char *kernel_filename, const char *kernel_cmdline,
979 const char *initrd_filename, const char *cpu_model)
980 {
981 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
982 kernel_cmdline, initrd_filename, cpu_model);
983 }
984
985 /* SPARCstation Voyager hardware initialisation */
986 static void vger_init(ram_addr_t RAM_size,
987 const char *boot_device,
988 const char *kernel_filename, const char *kernel_cmdline,
989 const char *initrd_filename, const char *cpu_model)
990 {
991 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
992 kernel_cmdline, initrd_filename, cpu_model);
993 }
994
995 /* SPARCstation LX hardware initialisation */
996 static void ss_lx_init(ram_addr_t RAM_size,
997 const char *boot_device,
998 const char *kernel_filename, const char *kernel_cmdline,
999 const char *initrd_filename, const char *cpu_model)
1000 {
1001 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1002 kernel_cmdline, initrd_filename, cpu_model);
1003 }
1004
1005 /* SPARCstation 4 hardware initialisation */
1006 static void ss4_init(ram_addr_t RAM_size,
1007 const char *boot_device,
1008 const char *kernel_filename, const char *kernel_cmdline,
1009 const char *initrd_filename, const char *cpu_model)
1010 {
1011 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1012 kernel_cmdline, initrd_filename, cpu_model);
1013 }
1014
1015 /* SPARCClassic hardware initialisation */
1016 static void scls_init(ram_addr_t RAM_size,
1017 const char *boot_device,
1018 const char *kernel_filename, const char *kernel_cmdline,
1019 const char *initrd_filename, const char *cpu_model)
1020 {
1021 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1022 kernel_cmdline, initrd_filename, cpu_model);
1023 }
1024
1025 /* SPARCbook hardware initialisation */
1026 static void sbook_init(ram_addr_t RAM_size,
1027 const char *boot_device,
1028 const char *kernel_filename, const char *kernel_cmdline,
1029 const char *initrd_filename, const char *cpu_model)
1030 {
1031 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1032 kernel_cmdline, initrd_filename, cpu_model);
1033 }
1034
1035 QEMUMachine ss5_machine = {
1036 .name = "SS-5",
1037 .desc = "Sun4m platform, SPARCstation 5",
1038 .init = ss5_init,
1039 .use_scsi = 1,
1040 };
1041
1042 QEMUMachine ss10_machine = {
1043 .name = "SS-10",
1044 .desc = "Sun4m platform, SPARCstation 10",
1045 .init = ss10_init,
1046 .use_scsi = 1,
1047 .max_cpus = 4,
1048 };
1049
1050 QEMUMachine ss600mp_machine = {
1051 .name = "SS-600MP",
1052 .desc = "Sun4m platform, SPARCserver 600MP",
1053 .init = ss600mp_init,
1054 .use_scsi = 1,
1055 .max_cpus = 4,
1056 };
1057
1058 QEMUMachine ss20_machine = {
1059 .name = "SS-20",
1060 .desc = "Sun4m platform, SPARCstation 20",
1061 .init = ss20_init,
1062 .use_scsi = 1,
1063 .max_cpus = 4,
1064 };
1065
1066 QEMUMachine voyager_machine = {
1067 .name = "Voyager",
1068 .desc = "Sun4m platform, SPARCstation Voyager",
1069 .init = vger_init,
1070 .use_scsi = 1,
1071 };
1072
1073 QEMUMachine ss_lx_machine = {
1074 .name = "LX",
1075 .desc = "Sun4m platform, SPARCstation LX",
1076 .init = ss_lx_init,
1077 .use_scsi = 1,
1078 };
1079
1080 QEMUMachine ss4_machine = {
1081 .name = "SS-4",
1082 .desc = "Sun4m platform, SPARCstation 4",
1083 .init = ss4_init,
1084 .use_scsi = 1,
1085 };
1086
1087 QEMUMachine scls_machine = {
1088 .name = "SPARCClassic",
1089 .desc = "Sun4m platform, SPARCClassic",
1090 .init = scls_init,
1091 .use_scsi = 1,
1092 };
1093
1094 QEMUMachine sbook_machine = {
1095 .name = "SPARCbook",
1096 .desc = "Sun4m platform, SPARCbook",
1097 .init = sbook_init,
1098 .use_scsi = 1,
1099 };
1100
1101 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1102 /* SS-1000 */
1103 {
1104 .iounit_bases = {
1105 0xfe0200000ULL,
1106 0xfe1200000ULL,
1107 0xfe2200000ULL,
1108 0xfe3200000ULL,
1109 -1,
1110 },
1111 .tcx_base = 0x820000000ULL,
1112 .slavio_base = 0xf00000000ULL,
1113 .ms_kb_base = 0xf00240000ULL,
1114 .serial_base = 0xf00200000ULL,
1115 .nvram_base = 0xf00280000ULL,
1116 .counter_base = 0xf00300000ULL,
1117 .espdma_base = 0x800081000ULL,
1118 .esp_base = 0x800080000ULL,
1119 .ledma_base = 0x800040000ULL,
1120 .le_base = 0x800060000ULL,
1121 .sbi_base = 0xf02800000ULL,
1122 .vram_size = 0x00100000,
1123 .nvram_size = 0x2000,
1124 .esp_irq = 3,
1125 .le_irq = 4,
1126 .clock_irq = 14,
1127 .clock1_irq = 10,
1128 .ms_kb_irq = 12,
1129 .ser_irq = 12,
1130 .nvram_machine_id = 0x80,
1131 .machine_id = ss1000_id,
1132 .iounit_version = 0x03000000,
1133 .max_mem = 0xf00000000ULL,
1134 .default_cpu_model = "TI SuperSparc II",
1135 },
1136 /* SS-2000 */
1137 {
1138 .iounit_bases = {
1139 0xfe0200000ULL,
1140 0xfe1200000ULL,
1141 0xfe2200000ULL,
1142 0xfe3200000ULL,
1143 0xfe4200000ULL,
1144 },
1145 .tcx_base = 0x820000000ULL,
1146 .slavio_base = 0xf00000000ULL,
1147 .ms_kb_base = 0xf00240000ULL,
1148 .serial_base = 0xf00200000ULL,
1149 .nvram_base = 0xf00280000ULL,
1150 .counter_base = 0xf00300000ULL,
1151 .espdma_base = 0x800081000ULL,
1152 .esp_base = 0x800080000ULL,
1153 .ledma_base = 0x800040000ULL,
1154 .le_base = 0x800060000ULL,
1155 .sbi_base = 0xf02800000ULL,
1156 .vram_size = 0x00100000,
1157 .nvram_size = 0x2000,
1158 .esp_irq = 3,
1159 .le_irq = 4,
1160 .clock_irq = 14,
1161 .clock1_irq = 10,
1162 .ms_kb_irq = 12,
1163 .ser_irq = 12,
1164 .nvram_machine_id = 0x80,
1165 .machine_id = ss2000_id,
1166 .iounit_version = 0x03000000,
1167 .max_mem = 0xf00000000ULL,
1168 .default_cpu_model = "TI SuperSparc II",
1169 },
1170 };
1171
1172 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1173 const char *boot_device,
1174 const char *kernel_filename,
1175 const char *kernel_cmdline,
1176 const char *initrd_filename, const char *cpu_model)
1177 {
1178 CPUState *env, *envs[MAX_CPUS];
1179 unsigned int i;
1180 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
1181 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1182 *espdma_irq, *ledma_irq;
1183 qemu_irq *esp_reset, *le_reset;
1184 ram_addr_t ram_offset, prom_offset;
1185 unsigned long kernel_size;
1186 int ret;
1187 char buf[1024];
1188 void *fw_cfg;
1189
1190 /* init CPUs */
1191 if (!cpu_model)
1192 cpu_model = hwdef->default_cpu_model;
1193
1194 for (i = 0; i < smp_cpus; i++) {
1195 env = cpu_init(cpu_model);
1196 if (!env) {
1197 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1198 exit(1);
1199 }
1200 cpu_sparc_set_id(env, i);
1201 envs[i] = env;
1202 if (i == 0) {
1203 qemu_register_reset(main_cpu_reset, env);
1204 } else {
1205 qemu_register_reset(secondary_cpu_reset, env);
1206 env->halted = 1;
1207 }
1208 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1209 env->prom_addr = hwdef->slavio_base;
1210 }
1211
1212 for (i = smp_cpus; i < MAX_CPUS; i++)
1213 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1214
1215 /* allocate RAM */
1216 if ((uint64_t)RAM_size > hwdef->max_mem) {
1217 fprintf(stderr,
1218 "qemu: Too much memory for this machine: %d, maximum %d\n",
1219 (unsigned int)(RAM_size / (1024 * 1024)),
1220 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1221 exit(1);
1222 }
1223 ram_offset = qemu_ram_alloc(RAM_size);
1224 cpu_register_physical_memory(0, RAM_size, ram_offset);
1225
1226 /* load boot prom */
1227 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1228 cpu_register_physical_memory(hwdef->slavio_base,
1229 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1230 TARGET_PAGE_MASK,
1231 prom_offset | IO_MEM_ROM);
1232
1233 if (bios_name == NULL)
1234 bios_name = PROM_FILENAME;
1235 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1236 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1237 if (ret < 0 || ret > PROM_SIZE_MAX)
1238 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1239 if (ret < 0 || ret > PROM_SIZE_MAX) {
1240 fprintf(stderr, "qemu: could not load prom '%s'\n",
1241 buf);
1242 exit(1);
1243 }
1244
1245 /* set up devices */
1246 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1247
1248 for (i = 0; i < MAX_IOUNITS; i++)
1249 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1250 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1251 hwdef->iounit_version,
1252 sbi_irq[hwdef->me_irq]);
1253
1254 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1255 iounits[0], &espdma_irq, &esp_reset);
1256
1257 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1258 iounits[0], &ledma_irq, &le_reset);
1259
1260 if (graphic_depth != 8 && graphic_depth != 24) {
1261 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1262 exit (1);
1263 }
1264 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1265 graphic_depth);
1266
1267 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1268
1269 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1270 hwdef->nvram_size, 8);
1271
1272 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1273 sbi_cpu_irq, smp_cpus);
1274
1275 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1276 nographic, ESCC_CLOCK, 1);
1277 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1278 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1279 escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1280 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1281
1282 if (drive_get_max_bus(IF_SCSI) > 0) {
1283 fprintf(stderr, "qemu: too many SCSI bus\n");
1284 exit(1);
1285 }
1286
1287 esp_init(hwdef->esp_base, 2,
1288 espdma_memory_read, espdma_memory_write,
1289 espdma, *espdma_irq, esp_reset);
1290
1291 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1292 RAM_size);
1293
1294 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1295 boot_device, RAM_size, kernel_size, graphic_width,
1296 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1297 "Sun4d");
1298
1299 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1300 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1301 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1302 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1303 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1304 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1305 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1306 if (kernel_cmdline) {
1307 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1308 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1309 } else {
1310 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1311 }
1312 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1313 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1314 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1315 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1316 }
1317
1318 /* SPARCserver 1000 hardware initialisation */
1319 static void ss1000_init(ram_addr_t RAM_size,
1320 const char *boot_device,
1321 const char *kernel_filename, const char *kernel_cmdline,
1322 const char *initrd_filename, const char *cpu_model)
1323 {
1324 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1325 kernel_cmdline, initrd_filename, cpu_model);
1326 }
1327
1328 /* SPARCcenter 2000 hardware initialisation */
1329 static void ss2000_init(ram_addr_t RAM_size,
1330 const char *boot_device,
1331 const char *kernel_filename, const char *kernel_cmdline,
1332 const char *initrd_filename, const char *cpu_model)
1333 {
1334 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1335 kernel_cmdline, initrd_filename, cpu_model);
1336 }
1337
1338 QEMUMachine ss1000_machine = {
1339 .name = "SS-1000",
1340 .desc = "Sun4d platform, SPARCserver 1000",
1341 .init = ss1000_init,
1342 .use_scsi = 1,
1343 .max_cpus = 8,
1344 };
1345
1346 QEMUMachine ss2000_machine = {
1347 .name = "SS-2000",
1348 .desc = "Sun4d platform, SPARCcenter 2000",
1349 .init = ss2000_init,
1350 .use_scsi = 1,
1351 .max_cpus = 20,
1352 };
1353
1354 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1355 /* SS-2 */
1356 {
1357 .iommu_base = 0xf8000000,
1358 .tcx_base = 0xfe000000,
1359 .slavio_base = 0xf6000000,
1360 .intctl_base = 0xf5000000,
1361 .counter_base = 0xf3000000,
1362 .ms_kb_base = 0xf0000000,
1363 .serial_base = 0xf1000000,
1364 .nvram_base = 0xf2000000,
1365 .fd_base = 0xf7200000,
1366 .dma_base = 0xf8400000,
1367 .esp_base = 0xf8800000,
1368 .le_base = 0xf8c00000,
1369 .aux1_base = 0xf7400003,
1370 .vram_size = 0x00100000,
1371 .nvram_size = 0x800,
1372 .esp_irq = 2,
1373 .le_irq = 3,
1374 .clock_irq = 5,
1375 .clock1_irq = 7,
1376 .ms_kb_irq = 1,
1377 .ser_irq = 1,
1378 .fd_irq = 1,
1379 .me_irq = 1,
1380 .nvram_machine_id = 0x55,
1381 .machine_id = ss2_id,
1382 .max_mem = 0x10000000,
1383 .default_cpu_model = "Cypress CY7C601",
1384 },
1385 };
1386
1387 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1388 const char *boot_device,
1389 const char *kernel_filename,
1390 const char *kernel_cmdline,
1391 const char *initrd_filename, const char *cpu_model)
1392 {
1393 CPUState *env;
1394 void *iommu, *espdma, *ledma, *nvram;
1395 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1396 qemu_irq *esp_reset, *le_reset;
1397 qemu_irq *fdc_tc;
1398 ram_addr_t ram_offset, prom_offset;
1399 unsigned long kernel_size;
1400 int ret;
1401 char buf[1024];
1402 BlockDriverState *fd[MAX_FD];
1403 int drive_index;
1404 void *fw_cfg;
1405
1406 /* init CPU */
1407 if (!cpu_model)
1408 cpu_model = hwdef->default_cpu_model;
1409
1410 env = cpu_init(cpu_model);
1411 if (!env) {
1412 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1413 exit(1);
1414 }
1415
1416 cpu_sparc_set_id(env, 0);
1417
1418 qemu_register_reset(main_cpu_reset, env);
1419 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1420 env->prom_addr = hwdef->slavio_base;
1421
1422 /* allocate RAM */
1423 if ((uint64_t)RAM_size > hwdef->max_mem) {
1424 fprintf(stderr,
1425 "qemu: Too much memory for this machine: %d, maximum %d\n",
1426 (unsigned int)(RAM_size / (1024 * 1024)),
1427 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1428 exit(1);
1429 }
1430 ram_offset = qemu_ram_alloc(RAM_size);
1431 cpu_register_physical_memory(0, RAM_size, ram_offset);
1432
1433 /* load boot prom */
1434 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1435 cpu_register_physical_memory(hwdef->slavio_base,
1436 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1437 TARGET_PAGE_MASK,
1438 prom_offset | IO_MEM_ROM);
1439
1440 if (bios_name == NULL)
1441 bios_name = PROM_FILENAME;
1442 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1443 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1444 if (ret < 0 || ret > PROM_SIZE_MAX)
1445 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1446 if (ret < 0 || ret > PROM_SIZE_MAX) {
1447 fprintf(stderr, "qemu: could not load prom '%s'\n",
1448 buf);
1449 exit(1);
1450 }
1451
1452 /* set up devices */
1453 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1454 &slavio_irq, cpu_irqs);
1455
1456 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1457 slavio_irq[hwdef->me_irq]);
1458
1459 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1460 iommu, &espdma_irq, &esp_reset);
1461
1462 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1463 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1464 &le_reset);
1465
1466 if (graphic_depth != 8 && graphic_depth != 24) {
1467 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1468 exit (1);
1469 }
1470 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1471 graphic_depth);
1472
1473 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1474
1475 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1476 hwdef->nvram_size, 2);
1477
1478 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1479 nographic, ESCC_CLOCK, 1);
1480 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1481 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1482 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1483 slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1484 ESCC_CLOCK, 1);
1485
1486 slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0,
1487 slavio_irq[hwdef->me_irq], NULL, &fdc_tc);
1488
1489 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1490 /* there is zero or one floppy drive */
1491 memset(fd, 0, sizeof(fd));
1492 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1493 if (drive_index != -1)
1494 fd[0] = drives_table[drive_index].bdrv;
1495
1496 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1497 fdc_tc);
1498 }
1499
1500 if (drive_get_max_bus(IF_SCSI) > 0) {
1501 fprintf(stderr, "qemu: too many SCSI bus\n");
1502 exit(1);
1503 }
1504
1505 esp_init(hwdef->esp_base, 2,
1506 espdma_memory_read, espdma_memory_write,
1507 espdma, *espdma_irq, esp_reset);
1508
1509 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1510 RAM_size);
1511
1512 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1513 boot_device, RAM_size, kernel_size, graphic_width,
1514 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1515 "Sun4c");
1516
1517 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1518 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1519 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1520 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1521 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1522 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1523 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1524 if (kernel_cmdline) {
1525 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1526 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1527 } else {
1528 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1529 }
1530 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1531 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1532 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1533 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1534 }
1535
1536 /* SPARCstation 2 hardware initialisation */
1537 static void ss2_init(ram_addr_t RAM_size,
1538 const char *boot_device,
1539 const char *kernel_filename, const char *kernel_cmdline,
1540 const char *initrd_filename, const char *cpu_model)
1541 {
1542 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1543 kernel_cmdline, initrd_filename, cpu_model);
1544 }
1545
1546 QEMUMachine ss2_machine = {
1547 .name = "SS-2",
1548 .desc = "Sun4c platform, SPARCstation 2",
1549 .init = ss2_init,
1550 .use_scsi = 1,
1551 };
Samsung s3c2440 and arm920t support for the mini2440 dev board