hw/pl190.c

   1 /*
   2  * Arm PrimeCell PL190 Vector Interrupt Controller
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11
  12 /* The number of virtual priority levels.  16 user vectors plus the
  13    unvectored IRQ.  Chained interrupts would require an additional level
  14    if implemented.  */
  15
  16 #define PL190_NUM_PRIO 17
  17
  18 typedef struct {
  19     SysBusDevice busdev;
  20     uint32_t level;
  21     uint32_t soft_level;
  22     uint32_t irq_enable;
  23     uint32_t fiq_select;
  24     uint32_t default_addr;
  25     uint8_t vect_control[16];
  26     uint32_t vect_addr[PL190_NUM_PRIO];
  27     /* Mask containing interrupts with higher priority than this one.  */
  28     uint32_t prio_mask[PL190_NUM_PRIO + 1];
  29     int protected;
  30     /* Current priority level.  */
  31     int priority;
  32     int prev_prio[PL190_NUM_PRIO];
  33     qemu_irq irq;
  34     qemu_irq fiq;
  35 } pl190_state;
  36
  37 static const unsigned char pl190_id[] =
  38 { 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 };
  39
  40 static inline uint32_t pl190_irq_level(pl190_state *s)
  41 {
  42     return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select;
  43 }
  44
  45 /* Update interrupts.  */
  46 static void pl190_update(pl190_state *s)
  47 {
  48     uint32_t level = pl190_irq_level(s);
  49     int set;
  50
  51     set = (level & s->prio_mask[s->priority]) != 0;
  52     qemu_set_irq(s->irq, set);
  53     set = ((s->level | s->soft_level) & s->fiq_select) != 0;
  54     qemu_set_irq(s->fiq, set);
  55 }
  56
  57 static void pl190_set_irq(void *opaque, int irq, int level)
  58 {
  59     pl190_state *s = (pl190_state *)opaque;
  60
  61     if (level)
  62         s->level |= 1u << irq;
  63     else
  64         s->level &= ~(1u << irq);
  65     pl190_update(s);
  66 }
  67
  68 static void pl190_update_vectors(pl190_state *s)
  69 {
  70     uint32_t mask;
  71     int i;
  72     int n;
  73
  74     mask = 0;
  75     for (i = 0; i < 16; i++)
  76       {
  77         s->prio_mask[i] = mask;
  78         if (s->vect_control[i] & 0x20)
  79           {
  80             n = s->vect_control[i] & 0x1f;
  81             mask |= 1 << n;
  82           }
  83       }
  84     s->prio_mask[16] = mask;
  85     pl190_update(s);
  86 }
  87
  88 static uint32_t pl190_read(void *opaque, target_phys_addr_t offset)
  89 {
  90     pl190_state *s = (pl190_state *)opaque;
  91     int i;
  92
  93     if (offset >= 0xfe0 && offset < 0x1000) {
  94         return pl190_id[(offset - 0xfe0) >> 2];
  95     }
  96     if (offset >= 0x100 && offset < 0x140) {
  97         return s->vect_addr[(offset - 0x100) >> 2];
  98     }
  99     if (offset >= 0x200 && offset < 0x240) {
 100         return s->vect_control[(offset - 0x200) >> 2];
 101     }
 102     switch (offset >> 2) {
 103     case 0: /* IRQSTATUS */
 104         return pl190_irq_level(s);
 105     case 1: /* FIQSATUS */
 106         return (s->level | s->soft_level) & s->fiq_select;
 107     case 2: /* RAWINTR */
 108         return s->level | s->soft_level;
 109     case 3: /* INTSELECT */
 110         return s->fiq_select;
 111     case 4: /* INTENABLE */
 112         return s->irq_enable;
 113     case 6: /* SOFTINT */
 114         return s->soft_level;
 115     case 8: /* PROTECTION */
 116         return s->protected;
 117     case 12: /* VECTADDR */
 118         /* Read vector address at the start of an ISR.  Increases the
 119            current priority level to that of the current interrupt.  */
 120         for (i = 0; i < s->priority; i++)
 121           {
 122             if ((s->level | s->soft_level) & s->prio_mask[i])
 123               break;
 124           }
 125         /* Reading this value with no pending interrupts is undefined.
 126            We return the default address.  */
 127         if (i == PL190_NUM_PRIO)
 128           return s->vect_addr[16];
 129         if (i < s->priority)
 130           {
 131             s->prev_prio[i] = s->priority;
 132             s->priority = i;
 133             pl190_update(s);
 134           }
 135         return s->vect_addr[s->priority];
 136     case 13: /* DEFVECTADDR */
 137         return s->vect_addr[16];
 138     default:
 139         hw_error("pl190_read: Bad offset %x\n", (int)offset);
 140         return 0;
 141     }
 142 }
 143
 144 static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val)
 145 {
 146     pl190_state *s = (pl190_state *)opaque;
 147
 148     if (offset >= 0x100 && offset < 0x140) {
 149         s->vect_addr[(offset - 0x100) >> 2] = val;
 150         pl190_update_vectors(s);
 151         return;
 152     }
 153     if (offset >= 0x200 && offset < 0x240) {
 154         s->vect_control[(offset - 0x200) >> 2] = val;
 155         pl190_update_vectors(s);
 156         return;
 157     }
 158     switch (offset >> 2) {
 159     case 0: /* SELECT */
 160         /* This is a readonly register, but linux tries to write to it
 161            anyway.  Ignore the write.  */
 162         break;
 163     case 3: /* INTSELECT */
 164         s->fiq_select = val;
 165         break;
 166     case 4: /* INTENABLE */
 167         s->irq_enable |= val;
 168         break;
 169     case 5: /* INTENCLEAR */
 170         s->irq_enable &= ~val;
 171         break;
 172     case 6: /* SOFTINT */
 173         s->soft_level |= val;
 174         break;
 175     case 7: /* SOFTINTCLEAR */
 176         s->soft_level &= ~val;
 177         break;
 178     case 8: /* PROTECTION */
 179         /* TODO: Protection (supervisor only access) is not implemented.  */
 180         s->protected = val & 1;
 181         break;
 182     case 12: /* VECTADDR */
 183         /* Restore the previous priority level.  The value written is
 184            ignored.  */
 185         if (s->priority < PL190_NUM_PRIO)
 186             s->priority = s->prev_prio[s->priority];
 187         break;
 188     case 13: /* DEFVECTADDR */
 189         s->default_addr = val;
 190         break;
 191     case 0xc0: /* ITCR */
 192         if (val) {
 193             hw_error("pl190: Test mode not implemented\n");
 194         }
 195         break;
 196     default:
 197         hw_error("pl190_write: Bad offset %x\n", (int)offset);
 198         return;
 199     }
 200     pl190_update(s);
 201 }
 202
 203 static CPUReadMemoryFunc *pl190_readfn[] = {
 204    pl190_read,
 205    pl190_read,
 206    pl190_read
 207 };
 208
 209 static CPUWriteMemoryFunc *pl190_writefn[] = {
 210    pl190_write,
 211    pl190_write,
 212    pl190_write
 213 };
 214
 215 static void pl190_reset(pl190_state *s)
 216 {
 217   int i;
 218
 219   for (i = 0; i < 16; i++)
 220     {
 221       s->vect_addr[i] = 0;
 222       s->vect_control[i] = 0;
 223     }
 224   s->vect_addr[16] = 0;
 225   s->prio_mask[17] = 0xffffffff;
 226   s->priority = PL190_NUM_PRIO;
 227   pl190_update_vectors(s);
 228 }
 229
 230 static void pl190_init(SysBusDevice *dev)
 231 {
 232     pl190_state *s = FROM_SYSBUS(pl190_state, dev);
 233     int iomemtype;
 234
 235     iomemtype = cpu_register_io_memory(0, pl190_readfn,
 236                                        pl190_writefn, s);
 237     sysbus_init_mmio(dev, 0x1000, iomemtype);
 238     qdev_init_irq_sink(&dev->qdev, pl190_set_irq, 32);
 239     sysbus_init_irq(dev, &s->irq);
 240     sysbus_init_irq(dev, &s->fiq);
 241     pl190_reset(s);
 242     /* ??? Save/restore.  */
 243 }
 244
 245 static void pl190_register_devices(void)
 246 {
 247     sysbus_register_dev("pl190", sizeof(pl190_state), pl190_init);
 248 }
 249
 250 device_init(pl190_register_devices)