hw/etraxfs_timer.c

   1 /*
   2  * QEMU ETRAX Timers
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "sysbus.h"
  25 #include "sysemu.h"
  26 #include "qemu-timer.h"
  27
  28 #define D(x)
  29
  30 #define RW_TMR0_DIV   0x00
  31 #define R_TMR0_DATA   0x04
  32 #define RW_TMR0_CTRL  0x08
  33 #define RW_TMR1_DIV   0x10
  34 #define R_TMR1_DATA   0x14
  35 #define RW_TMR1_CTRL  0x18
  36 #define R_TIME        0x38
  37 #define RW_WD_CTRL    0x40
  38 #define R_WD_STAT     0x44
  39 #define RW_INTR_MASK  0x48
  40 #define RW_ACK_INTR   0x4c
  41 #define R_INTR        0x50
  42 #define R_MASKED_INTR 0x54
  43
  44 struct etrax_timer {
  45     SysBusDevice busdev;
  46     qemu_irq irq;
  47     qemu_irq nmi;
  48
  49     QEMUBH *bh_t0;
  50     QEMUBH *bh_t1;
  51     QEMUBH *bh_wd;
  52     ptimer_state *ptimer_t0;
  53     ptimer_state *ptimer_t1;
  54     ptimer_state *ptimer_wd;
  55     struct timeval last;
  56
  57     int wd_hits;
  58
  59     /* Control registers.  */
  60     uint32_t rw_tmr0_div;
  61     uint32_t r_tmr0_data;
  62     uint32_t rw_tmr0_ctrl;
  63
  64     uint32_t rw_tmr1_div;
  65     uint32_t r_tmr1_data;
  66     uint32_t rw_tmr1_ctrl;
  67
  68     uint32_t rw_wd_ctrl;
  69
  70     uint32_t rw_intr_mask;
  71     uint32_t rw_ack_intr;
  72     uint32_t r_intr;
  73     uint32_t r_masked_intr;
  74 };
  75
  76 static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
  77 {
  78     struct etrax_timer *t = opaque;
  79     uint32_t r = 0;
  80
  81     switch (addr) {
  82     case R_TMR0_DATA:
  83         r = ptimer_get_count(t->ptimer_t0);
  84         break;
  85     case R_TMR1_DATA:
  86         r = ptimer_get_count(t->ptimer_t1);
  87         break;
  88     case R_TIME:
  89         r = qemu_get_clock(vm_clock) / 10;
  90         break;
  91     case RW_INTR_MASK:
  92         r = t->rw_intr_mask;
  93         break;
  94     case R_MASKED_INTR:
  95         r = t->r_intr & t->rw_intr_mask;
  96         break;
  97     default:
  98         D(printf ("%s %x\n", __func__, addr));
  99         break;
 100     }
 101     return r;
 102 }
 103
 104 #define TIMER_SLOWDOWN 1
 105 static void update_ctrl(struct etrax_timer *t, int tnum)
 106 {
 107     unsigned int op;
 108     unsigned int freq;
 109     unsigned int freq_hz;
 110     unsigned int div;
 111     uint32_t ctrl;
 112
 113     ptimer_state *timer;
 114
 115     if (tnum == 0) {
 116         ctrl = t->rw_tmr0_ctrl;
 117         div = t->rw_tmr0_div;
 118         timer = t->ptimer_t0;
 119     } else {
 120         ctrl = t->rw_tmr1_ctrl;
 121         div = t->rw_tmr1_div;
 122         timer = t->ptimer_t1;
 123     }
 124
 125
 126     op = ctrl & 3;
 127     freq = ctrl >> 2;
 128     freq_hz = 32000000;
 129
 130     switch (freq)
 131     {
 132     case 0:
 133     case 1:
 134         D(printf ("extern or disabled timer clock?\n"));
 135         break;
 136     case 4: freq_hz =  29493000; break;
 137     case 5: freq_hz =  32000000; break;
 138     case 6: freq_hz =  32768000; break;
 139     case 7: freq_hz = 100000000; break;
 140     default:
 141         abort();
 142         break;
 143     }
 144
 145     D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
 146     div = div * TIMER_SLOWDOWN;
 147     div /= 1000;
 148     freq_hz /= 1000;
 149     ptimer_set_freq(timer, freq_hz);
 150     ptimer_set_limit(timer, div, 0);
 151
 152     switch (op)
 153     {
 154         case 0:
 155             /* Load.  */
 156             ptimer_set_limit(timer, div, 1);
 157             break;
 158         case 1:
 159             /* Hold.  */
 160             ptimer_stop(timer);
 161             break;
 162         case 2:
 163             /* Run.  */
 164             ptimer_run(timer, 0);
 165             break;
 166         default:
 167             abort();
 168             break;
 169     }
 170 }
 171
 172 static void timer_update_irq(struct etrax_timer *t)
 173 {
 174     t->r_intr &= ~(t->rw_ack_intr);
 175     t->r_masked_intr = t->r_intr & t->rw_intr_mask;
 176
 177     D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
 178     qemu_set_irq(t->irq, !!t->r_masked_intr);
 179 }
 180
 181 static void timer0_hit(void *opaque)
 182 {
 183     struct etrax_timer *t = opaque;
 184     t->r_intr |= 1;
 185     timer_update_irq(t);
 186 }
 187
 188 static void timer1_hit(void *opaque)
 189 {
 190     struct etrax_timer *t = opaque;
 191     t->r_intr |= 2;
 192     timer_update_irq(t);
 193 }
 194
 195 static void watchdog_hit(void *opaque)
 196 {
 197     struct etrax_timer *t = opaque;
 198     if (t->wd_hits == 0) {
 199         /* real hw gives a single tick before reseting but we are
 200            a bit friendlier to compensate for our slower execution.  */
 201         ptimer_set_count(t->ptimer_wd, 10);
 202         ptimer_run(t->ptimer_wd, 1);
 203         qemu_irq_raise(t->nmi);
 204     }
 205     else
 206         qemu_system_reset_request();
 207
 208     t->wd_hits++;
 209 }
 210
 211 static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
 212 {
 213     unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
 214     unsigned int wd_key = t->rw_wd_ctrl >> 9;
 215     unsigned int wd_cnt = t->rw_wd_ctrl & 511;
 216     unsigned int new_key = value >> 9 & ((1 << 7) - 1);
 217     unsigned int new_cmd = (value >> 8) & 1;
 218
 219     /* If the watchdog is enabled, they written key must match the
 220        complement of the previous.  */
 221     wd_key = ~wd_key & ((1 << 7) - 1);
 222
 223     if (wd_en && wd_key != new_key)
 224         return;
 225
 226     D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
 227          wd_en, new_key, wd_key, new_cmd, wd_cnt));
 228
 229     if (t->wd_hits)
 230         qemu_irq_lower(t->nmi);
 231
 232     t->wd_hits = 0;
 233
 234     ptimer_set_freq(t->ptimer_wd, 760);
 235     if (wd_cnt == 0)
 236         wd_cnt = 256;
 237     ptimer_set_count(t->ptimer_wd, wd_cnt);
 238     if (new_cmd)
 239         ptimer_run(t->ptimer_wd, 1);
 240     else
 241         ptimer_stop(t->ptimer_wd);
 242
 243     t->rw_wd_ctrl = value;
 244 }
 245
 246 static void
 247 timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 248 {
 249     struct etrax_timer *t = opaque;
 250
 251     switch (addr)
 252     {
 253         case RW_TMR0_DIV:
 254             t->rw_tmr0_div = value;
 255             break;
 256         case RW_TMR0_CTRL:
 257             D(printf ("RW_TMR0_CTRL=%x\n", value));
 258             t->rw_tmr0_ctrl = value;
 259             update_ctrl(t, 0);
 260             break;
 261         case RW_TMR1_DIV:
 262             t->rw_tmr1_div = value;
 263             break;
 264         case RW_TMR1_CTRL:
 265             D(printf ("RW_TMR1_CTRL=%x\n", value));
 266             t->rw_tmr1_ctrl = value;
 267             update_ctrl(t, 1);
 268             break;
 269         case RW_INTR_MASK:
 270             D(printf ("RW_INTR_MASK=%x\n", value));
 271             t->rw_intr_mask = value;
 272             timer_update_irq(t);
 273             break;
 274         case RW_WD_CTRL:
 275             timer_watchdog_update(t, value);
 276             break;
 277         case RW_ACK_INTR:
 278             t->rw_ack_intr = value;
 279             timer_update_irq(t);
 280             t->rw_ack_intr = 0;
 281             break;
 282         default:
 283             printf ("%s " TARGET_FMT_plx " %x\n",
 284                 __func__, addr, value);
 285             break;
 286     }
 287 }
 288
 289 static CPUReadMemoryFunc *timer_read[] = {
 290     NULL, NULL,
 291     &timer_readl,
 292 };
 293
 294 static CPUWriteMemoryFunc *timer_write[] = {
 295     NULL, NULL,
 296     &timer_writel,
 297 };
 298
 299 static void etraxfs_timer_reset(void *opaque)
 300 {
 301     struct etrax_timer *t = opaque;
 302
 303     ptimer_stop(t->ptimer_t0);
 304     ptimer_stop(t->ptimer_t1);
 305     ptimer_stop(t->ptimer_wd);
 306     t->rw_wd_ctrl = 0;
 307     t->r_intr = 0;
 308     t->rw_intr_mask = 0;
 309     qemu_irq_lower(t->irq);
 310 }
 311
 312 static void etraxfs_timer_init(SysBusDevice *dev)
 313 {
 314     struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);
 315     int timer_regs;
 316
 317     t->bh_t0 = qemu_bh_new(timer0_hit, t);
 318     t->bh_t1 = qemu_bh_new(timer1_hit, t);
 319     t->bh_wd = qemu_bh_new(watchdog_hit, t);
 320     t->ptimer_t0 = ptimer_init(t->bh_t0);
 321     t->ptimer_t1 = ptimer_init(t->bh_t1);
 322     t->ptimer_wd = ptimer_init(t->bh_wd);
 323
 324     sysbus_init_irq(dev, &t->irq);
 325     sysbus_init_irq(dev, &t->nmi);
 326
 327     timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
 328     sysbus_init_mmio(dev, 0x5c, timer_regs);
 329
 330     qemu_register_reset(etraxfs_timer_reset, t);
 331 }
 332
 333 static void etraxfs_timer_register(void)
 334 {
 335     sysbus_register_dev("etraxfs,timer", sizeof (struct etrax_timer),
 336                         etraxfs_timer_init);
 337 }
 338
 339 device_init(etraxfs_timer_register)