hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "hw.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "audio/audio.h"
  21 #include "i2c.h"
  22
  23 #define MP_ETH_BASE             0x80008000
  24 #define MP_ETH_SIZE             0x00001000
  25
  26 #define MP_UART1_BASE           0x8000C840
  27 #define MP_UART2_BASE           0x8000C940
  28
  29 #define MP_FLASHCFG_BASE        0x90006000
  30 #define MP_FLASHCFG_SIZE        0x00001000
  31
  32 #define MP_AUDIO_BASE           0x90007000
  33 #define MP_AUDIO_SIZE           0x00001000
  34
  35 #define MP_PIC_BASE             0x90008000
  36 #define MP_PIC_SIZE             0x00001000
  37
  38 #define MP_PIT_BASE             0x90009000
  39 #define MP_PIT_SIZE             0x00001000
  40
  41 #define MP_LCD_BASE             0x9000c000
  42 #define MP_LCD_SIZE             0x00001000
  43
  44 #define MP_SRAM_BASE            0xC0000000
  45 #define MP_SRAM_SIZE            0x00020000
  46
  47 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  48 #define MP_FLASH_SIZE_MAX       32*1024*1024
  49
  50 #define MP_TIMER1_IRQ           4
  51 /* ... */
  52 #define MP_TIMER4_IRQ           7
  53 #define MP_EHCI_IRQ             8
  54 #define MP_ETH_IRQ              9
  55 #define MP_UART1_IRQ            11
  56 #define MP_UART2_IRQ            11
  57 #define MP_GPIO_IRQ             12
  58 #define MP_RTC_IRQ              28
  59 #define MP_AUDIO_IRQ            30
  60
  61 static uint32_t gpio_in_state = 0xffffffff;
  62 static uint32_t gpio_isr;
  63 static uint32_t gpio_out_state;
  64 static ram_addr_t sram_off;
  65
  66 /* Address conversion helpers */
  67 static void *target2host_addr(uint32_t addr)
  68 {
  69     if (addr < MP_SRAM_BASE) {
  70         if (addr >= MP_RAM_DEFAULT_SIZE)
  71             return NULL;
  72         return (void *)(phys_ram_base + addr);
  73     } else {
  74         if (addr >= MP_SRAM_BASE + MP_SRAM_SIZE)
  75             return NULL;
  76         return (void *)(phys_ram_base + sram_off + addr - MP_SRAM_BASE);
  77     }
  78 }
  79
  80 static uint32_t host2target_addr(void *addr)
  81 {
  82     if (addr < ((void *)phys_ram_base) + sram_off)
  83         return (unsigned long)addr - (unsigned long)phys_ram_base;
  84     else
  85         return (unsigned long)addr - (unsigned long)phys_ram_base -
  86             sram_off + MP_SRAM_BASE;
  87 }
  88
  89
  90 typedef enum i2c_state {
  91     STOPPED = 0,
  92     INITIALIZING,
  93     SENDING_BIT7,
  94     SENDING_BIT6,
  95     SENDING_BIT5,
  96     SENDING_BIT4,
  97     SENDING_BIT3,
  98     SENDING_BIT2,
  99     SENDING_BIT1,
 100     SENDING_BIT0,
 101     WAITING_FOR_ACK,
 102     RECEIVING_BIT7,
 103     RECEIVING_BIT6,
 104     RECEIVING_BIT5,
 105     RECEIVING_BIT4,
 106     RECEIVING_BIT3,
 107     RECEIVING_BIT2,
 108     RECEIVING_BIT1,
 109     RECEIVING_BIT0,
 110     SENDING_ACK
 111 } i2c_state;
 112
 113 typedef struct i2c_interface {
 114     i2c_bus *bus;
 115     i2c_state state;
 116     int last_data;
 117     int last_clock;
 118     uint8_t buffer;
 119     int current_addr;
 120 } i2c_interface;
 121
 122 static void i2c_enter_stop(i2c_interface *i2c)
 123 {
 124     if (i2c->current_addr >= 0)
 125         i2c_end_transfer(i2c->bus);
 126     i2c->current_addr = -1;
 127     i2c->state = STOPPED;
 128 }
 129
 130 static void i2c_state_update(i2c_interface *i2c, int data, int clock)
 131 {
 132     if (!i2c)
 133         return;
 134
 135     switch (i2c->state) {
 136     case STOPPED:
 137         if (data == 0 && i2c->last_data == 1 && clock == 1)
 138             i2c->state = INITIALIZING;
 139         break;
 140
 141     case INITIALIZING:
 142         if (clock == 0 && i2c->last_clock == 1 && data == 0)
 143             i2c->state = SENDING_BIT7;
 144         else
 145             i2c_enter_stop(i2c);
 146         break;
 147
 148     case SENDING_BIT7 ... SENDING_BIT0:
 149         if (clock == 0 && i2c->last_clock == 1) {
 150             i2c->buffer = (i2c->buffer << 1) | data;
 151             i2c->state++; /* will end up in WAITING_FOR_ACK */
 152         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 153             i2c_enter_stop(i2c);
 154         break;
 155
 156     case WAITING_FOR_ACK:
 157         if (clock == 0 && i2c->last_clock == 1) {
 158             if (i2c->current_addr < 0) {
 159                 i2c->current_addr = i2c->buffer;
 160                 i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
 161                                    i2c->buffer & 1);
 162             } else
 163                 i2c_send(i2c->bus, i2c->buffer);
 164             if (i2c->current_addr & 1) {
 165                 i2c->state = RECEIVING_BIT7;
 166                 i2c->buffer = i2c_recv(i2c->bus);
 167             } else
 168                 i2c->state = SENDING_BIT7;
 169         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 170             i2c_enter_stop(i2c);
 171         break;
 172
 173     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 174         if (clock == 0 && i2c->last_clock == 1) {
 175             i2c->state++; /* will end up in SENDING_ACK */
 176             i2c->buffer <<= 1;
 177         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 178             i2c_enter_stop(i2c);
 179         break;
 180
 181     case SENDING_ACK:
 182         if (clock == 0 && i2c->last_clock == 1) {
 183             i2c->state = RECEIVING_BIT7;
 184             if (data == 0)
 185                 i2c->buffer = i2c_recv(i2c->bus);
 186             else
 187                 i2c_nack(i2c->bus);
 188         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 189             i2c_enter_stop(i2c);
 190         break;
 191     }
 192
 193     i2c->last_data = data;
 194     i2c->last_clock = clock;
 195 }
 196
 197 static int i2c_get_data(i2c_interface *i2c)
 198 {
 199     if (!i2c)
 200         return 0;
 201
 202     switch (i2c->state) {
 203     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 204         return (i2c->buffer >> 7);
 205
 206     case WAITING_FOR_ACK:
 207     default:
 208         return 0;
 209     }
 210 }
 211
 212 static i2c_interface *mixer_i2c;
 213
 214 #ifdef HAS_AUDIO
 215
 216 /* Audio register offsets */
 217 #define MP_AUDIO_PLAYBACK_MODE  0x00
 218 #define MP_AUDIO_CLOCK_DIV      0x18
 219 #define MP_AUDIO_IRQ_STATUS     0x20
 220 #define MP_AUDIO_IRQ_ENABLE     0x24
 221 #define MP_AUDIO_TX_START_LO    0x28
 222 #define MP_AUDIO_TX_THRESHOLD   0x2C
 223 #define MP_AUDIO_TX_STATUS      0x38
 224 #define MP_AUDIO_TX_START_HI    0x40
 225
 226 /* Status register and IRQ enable bits */
 227 #define MP_AUDIO_TX_HALF        (1 << 6)
 228 #define MP_AUDIO_TX_FULL        (1 << 7)
 229
 230 /* Playback mode bits */
 231 #define MP_AUDIO_16BIT_SAMPLE   (1 << 0)
 232 #define MP_AUDIO_PLAYBACK_EN    (1 << 7)
 233 #define MP_AUDIO_CLOCK_24MHZ    (1 << 9)
 234 #define MP_AUDIO_MONO           (1 << 14)
 235
 236 /* Wolfson 8750 I2C address */
 237 #define MP_WM_ADDR              0x34
 238
 239 static const char audio_name[] = "mv88w8618";
 240
 241 typedef struct musicpal_audio_state {
 242     uint32_t base;
 243     qemu_irq irq;
 244     uint32_t playback_mode;
 245     uint32_t status;
 246     uint32_t irq_enable;
 247     unsigned long phys_buf;
 248     int8_t *target_buffer;
 249     unsigned int threshold;
 250     unsigned int play_pos;
 251     unsigned int last_free;
 252     uint32_t clock_div;
 253     i2c_slave *wm;
 254 } musicpal_audio_state;
 255
 256 static void audio_callback(void *opaque, int free_out, int free_in)
 257 {
 258     musicpal_audio_state *s = opaque;
 259     int16_t *codec_buffer;
 260     int8_t *mem_buffer;
 261     int pos, block_size;
 262
 263     if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
 264         return;
 265
 266     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
 267         free_out <<= 1;
 268
 269     if (!(s->playback_mode & MP_AUDIO_MONO))
 270         free_out <<= 1;
 271
 272     block_size = s->threshold/2;
 273     if (free_out - s->last_free < block_size)
 274         return;
 275
 276     mem_buffer = s->target_buffer + s->play_pos;
 277     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
 278         if (s->playback_mode & MP_AUDIO_MONO) {
 279             codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
 280             for (pos = 0; pos < block_size; pos += 2) {
 281                 *codec_buffer++ = *(int16_t *)mem_buffer;
 282                 *codec_buffer++ = *(int16_t *)mem_buffer;
 283                 mem_buffer += 2;
 284             }
 285         } else
 286             memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
 287                    (uint32_t *)mem_buffer, block_size);
 288     } else {
 289         if (s->playback_mode & MP_AUDIO_MONO) {
 290             codec_buffer = wm8750_dac_buffer(s->wm, block_size);
 291             for (pos = 0; pos < block_size; pos++) {
 292                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
 293                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 294             }
 295         } else {
 296             codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
 297             for (pos = 0; pos < block_size; pos += 2) {
 298                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 299                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 300             }
 301         }
 302     }
 303     wm8750_dac_commit(s->wm);
 304
 305     s->last_free = free_out - block_size;
 306
 307     if (s->play_pos == 0) {
 308         s->status |= MP_AUDIO_TX_HALF;
 309         s->play_pos = block_size;
 310     } else {
 311         s->status |= MP_AUDIO_TX_FULL;
 312         s->play_pos = 0;
 313     }
 314
 315     if (s->status & s->irq_enable)
 316         qemu_irq_raise(s->irq);
 317 }
 318
 319 static void musicpal_audio_clock_update(musicpal_audio_state *s)
 320 {
 321     int rate;
 322
 323     if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
 324         rate = 24576000 / 64; /* 24.576MHz */
 325     else
 326         rate = 11289600 / 64; /* 11.2896MHz */
 327
 328     rate /= ((s->clock_div >> 8) & 0xff) + 1;
 329
 330     wm8750_set_bclk_in(s->wm, rate);
 331 }
 332
 333 static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
 334 {
 335     musicpal_audio_state *s = opaque;
 336
 337     offset -= s->base;
 338     switch (offset) {
 339     case MP_AUDIO_PLAYBACK_MODE:
 340         return s->playback_mode;
 341
 342     case MP_AUDIO_CLOCK_DIV:
 343         return s->clock_div;
 344
 345     case MP_AUDIO_IRQ_STATUS:
 346         return s->status;
 347
 348     case MP_AUDIO_IRQ_ENABLE:
 349         return s->irq_enable;
 350
 351     case MP_AUDIO_TX_STATUS:
 352         return s->play_pos >> 2;
 353
 354     default:
 355         return 0;
 356     }
 357 }
 358
 359 static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
 360                                  uint32_t value)
 361 {
 362     musicpal_audio_state *s = opaque;
 363
 364     offset -= s->base;
 365     switch (offset) {
 366     case MP_AUDIO_PLAYBACK_MODE:
 367         if (value & MP_AUDIO_PLAYBACK_EN &&
 368             !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
 369             s->status = 0;
 370             s->last_free = 0;
 371             s->play_pos = 0;
 372         }
 373         s->playback_mode = value;
 374         musicpal_audio_clock_update(s);
 375         break;
 376
 377     case MP_AUDIO_CLOCK_DIV:
 378         s->clock_div = value;
 379         s->last_free = 0;
 380         s->play_pos = 0;
 381         musicpal_audio_clock_update(s);
 382         break;
 383
 384     case MP_AUDIO_IRQ_STATUS:
 385         s->status &= ~value;
 386         break;
 387
 388     case MP_AUDIO_IRQ_ENABLE:
 389         s->irq_enable = value;
 390         if (s->status & s->irq_enable)
 391             qemu_irq_raise(s->irq);
 392         break;
 393
 394     case MP_AUDIO_TX_START_LO:
 395         s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
 396         s->target_buffer = target2host_addr(s->phys_buf);
 397         s->play_pos = 0;
 398         s->last_free = 0;
 399         break;
 400
 401     case MP_AUDIO_TX_THRESHOLD:
 402         s->threshold = (value + 1) * 4;
 403         break;
 404
 405     case MP_AUDIO_TX_START_HI:
 406         s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
 407         s->target_buffer = target2host_addr(s->phys_buf);
 408         s->play_pos = 0;
 409         s->last_free = 0;
 410         break;
 411     }
 412 }
 413
 414 static void musicpal_audio_reset(void *opaque)
 415 {
 416     musicpal_audio_state *s = opaque;
 417
 418     s->playback_mode = 0;
 419     s->status = 0;
 420     s->irq_enable = 0;
 421 }
 422
 423 static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
 424     musicpal_audio_read,
 425     musicpal_audio_read,
 426     musicpal_audio_read
 427 };
 428
 429 static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
 430     musicpal_audio_write,
 431     musicpal_audio_write,
 432     musicpal_audio_write
 433 };
 434
 435 static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
 436 {
 437     AudioState *audio;
 438     musicpal_audio_state *s;
 439     i2c_interface *i2c;
 440     int iomemtype;
 441
 442     audio = AUD_init();
 443     if (!audio) {
 444         AUD_log(audio_name, "No audio state\n");
 445         return NULL;
 446     }
 447
 448     s = qemu_mallocz(sizeof(musicpal_audio_state));
 449     if (!s)
 450         return NULL;
 451     s->base = base;
 452     s->irq = irq;
 453
 454     i2c = qemu_mallocz(sizeof(i2c_interface));
 455     if (!i2c)
 456         return NULL;
 457     i2c->bus = i2c_init_bus();
 458     i2c->current_addr = -1;
 459
 460     s->wm = wm8750_init(i2c->bus, audio);
 461     if (!s->wm)
 462         return NULL;
 463     i2c_set_slave_address(s->wm, MP_WM_ADDR);
 464     wm8750_data_req_set(s->wm, audio_callback, s);
 465
 466     iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
 467                        musicpal_audio_writefn, s);
 468     cpu_register_physical_memory(base, MP_AUDIO_SIZE, iomemtype);
 469
 470     qemu_register_reset(musicpal_audio_reset, s);
 471
 472     return i2c;
 473 }
 474 #else  /* !HAS_AUDIO */
 475 static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
 476 {
 477     return NULL;
 478 }
 479 #endif /* !HAS_AUDIO */
 480
 481 /* Ethernet register offsets */
 482 #define MP_ETH_SMIR             0x010
 483 #define MP_ETH_PCXR             0x408
 484 #define MP_ETH_SDCMR            0x448
 485 #define MP_ETH_ICR              0x450
 486 #define MP_ETH_IMR              0x458
 487 #define MP_ETH_FRDP0            0x480
 488 #define MP_ETH_FRDP1            0x484
 489 #define MP_ETH_FRDP2            0x488
 490 #define MP_ETH_FRDP3            0x48C
 491 #define MP_ETH_CRDP0            0x4A0
 492 #define MP_ETH_CRDP1            0x4A4
 493 #define MP_ETH_CRDP2            0x4A8
 494 #define MP_ETH_CRDP3            0x4AC
 495 #define MP_ETH_CTDP0            0x4E0
 496 #define MP_ETH_CTDP1            0x4E4
 497 #define MP_ETH_CTDP2            0x4E8
 498 #define MP_ETH_CTDP3            0x4EC
 499
 500 /* MII PHY access */
 501 #define MP_ETH_SMIR_DATA        0x0000FFFF
 502 #define MP_ETH_SMIR_ADDR        0x03FF0000
 503 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
 504 #define MP_ETH_SMIR_RDVALID     (1 << 27)
 505
 506 /* PHY registers */
 507 #define MP_ETH_PHY1_BMSR        0x00210000
 508 #define MP_ETH_PHY1_PHYSID1     0x00410000
 509 #define MP_ETH_PHY1_PHYSID2     0x00610000
 510
 511 #define MP_PHY_BMSR_LINK        0x0004
 512 #define MP_PHY_BMSR_AUTONEG     0x0008
 513
 514 #define MP_PHY_88E3015          0x01410E20
 515
 516 /* TX descriptor status */
 517 #define MP_ETH_TX_OWN           (1 << 31)
 518
 519 /* RX descriptor status */
 520 #define MP_ETH_RX_OWN           (1 << 31)
 521
 522 /* Interrupt cause/mask bits */
 523 #define MP_ETH_IRQ_RX_BIT       0
 524 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 525 #define MP_ETH_IRQ_TXHI_BIT     2
 526 #define MP_ETH_IRQ_TXLO_BIT     3
 527
 528 /* Port config bits */
 529 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 530
 531 /* SDMA command bits */
 532 #define MP_ETH_CMD_TXHI         (1 << 23)
 533 #define MP_ETH_CMD_TXLO         (1 << 22)
 534
 535 typedef struct mv88w8618_tx_desc {
 536     uint32_t cmdstat;
 537     uint16_t res;
 538     uint16_t bytes;
 539     uint32_t buffer;
 540     uint32_t next;
 541 } mv88w8618_tx_desc;
 542
 543 typedef struct mv88w8618_rx_desc {
 544     uint32_t cmdstat;
 545     uint16_t bytes;
 546     uint16_t buffer_size;
 547     uint32_t buffer;
 548     uint32_t next;
 549 } mv88w8618_rx_desc;
 550
 551 typedef struct mv88w8618_eth_state {
 552     uint32_t base;
 553     qemu_irq irq;
 554     uint32_t smir;
 555     uint32_t icr;
 556     uint32_t imr;
 557     int vlan_header;
 558     mv88w8618_tx_desc *tx_queue[2];
 559     mv88w8618_rx_desc *rx_queue[4];
 560     mv88w8618_rx_desc *frx_queue[4];
 561     mv88w8618_rx_desc *cur_rx[4];
 562     VLANClientState *vc;
 563 } mv88w8618_eth_state;
 564
 565 static int eth_can_receive(void *opaque)
 566 {
 567     return 1;
 568 }
 569
 570 static void eth_receive(void *opaque, const uint8_t *buf, int size)
 571 {
 572     mv88w8618_eth_state *s = opaque;
 573     mv88w8618_rx_desc *desc;
 574     int i;
 575
 576     for (i = 0; i < 4; i++) {
 577         desc = s->cur_rx[i];
 578         if (!desc)
 579             continue;
 580         do {
 581             if (le32_to_cpu(desc->cmdstat) & MP_ETH_RX_OWN &&
 582                 le16_to_cpu(desc->buffer_size) >= size) {
 583                 memcpy(target2host_addr(le32_to_cpu(desc->buffer) +
 584                                         s->vlan_header),
 585                        buf, size);
 586                 desc->bytes = cpu_to_le16(size + s->vlan_header);
 587                 desc->cmdstat &= cpu_to_le32(~MP_ETH_RX_OWN);
 588                 s->cur_rx[i] = target2host_addr(le32_to_cpu(desc->next));
 589
 590                 s->icr |= MP_ETH_IRQ_RX;
 591                 if (s->icr & s->imr)
 592                     qemu_irq_raise(s->irq);
 593                 return;
 594             }
 595             desc = target2host_addr(le32_to_cpu(desc->next));
 596         } while (desc != s->rx_queue[i]);
 597     }
 598 }
 599
 600 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 601 {
 602     mv88w8618_tx_desc *desc = s->tx_queue[queue_index];
 603
 604     do {
 605         if (le32_to_cpu(desc->cmdstat) & MP_ETH_TX_OWN) {
 606             qemu_send_packet(s->vc,
 607                              target2host_addr(le32_to_cpu(desc->buffer)),
 608                              le16_to_cpu(desc->bytes));
 609             desc->cmdstat &= cpu_to_le32(~MP_ETH_TX_OWN);
 610             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 611         }
 612         desc = target2host_addr(le32_to_cpu(desc->next));
 613     } while (desc != s->tx_queue[queue_index]);
 614 }
 615
 616 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 617 {
 618     mv88w8618_eth_state *s = opaque;
 619
 620     offset -= s->base;
 621     switch (offset) {
 622     case MP_ETH_SMIR:
 623         if (s->smir & MP_ETH_SMIR_OPCODE) {
 624             switch (s->smir & MP_ETH_SMIR_ADDR) {
 625             case MP_ETH_PHY1_BMSR:
 626                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 627                        MP_ETH_SMIR_RDVALID;
 628             case MP_ETH_PHY1_PHYSID1:
 629                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 630             case MP_ETH_PHY1_PHYSID2:
 631                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 632             default:
 633                 return MP_ETH_SMIR_RDVALID;
 634             }
 635         }
 636         return 0;
 637
 638     case MP_ETH_ICR:
 639         return s->icr;
 640
 641     case MP_ETH_IMR:
 642         return s->imr;
 643
 644     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 645         return host2target_addr(s->frx_queue[(offset - MP_ETH_FRDP0)/4]);
 646
 647     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 648         return host2target_addr(s->rx_queue[(offset - MP_ETH_CRDP0)/4]);
 649
 650     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 651         return host2target_addr(s->tx_queue[(offset - MP_ETH_CTDP0)/4]);
 652
 653     default:
 654         return 0;
 655     }
 656 }
 657
 658 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 659                                 uint32_t value)
 660 {
 661     mv88w8618_eth_state *s = opaque;
 662
 663     offset -= s->base;
 664     switch (offset) {
 665     case MP_ETH_SMIR:
 666         s->smir = value;
 667         break;
 668
 669     case MP_ETH_PCXR:
 670         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 671         break;
 672
 673     case MP_ETH_SDCMR:
 674         if (value & MP_ETH_CMD_TXHI)
 675             eth_send(s, 1);
 676         if (value & MP_ETH_CMD_TXLO)
 677             eth_send(s, 0);
 678         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
 679             qemu_irq_raise(s->irq);
 680         break;
 681
 682     case MP_ETH_ICR:
 683         s->icr &= value;
 684         break;
 685
 686     case MP_ETH_IMR:
 687         s->imr = value;
 688         if (s->icr & s->imr)
 689             qemu_irq_raise(s->irq);
 690         break;
 691
 692     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 693         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = target2host_addr(value);
 694         break;
 695
 696     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 697         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 698             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = target2host_addr(value);
 699         break;
 700
 701     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 702         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = target2host_addr(value);
 703         break;
 704     }
 705 }
 706
 707 static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
 708     mv88w8618_eth_read,
 709     mv88w8618_eth_read,
 710     mv88w8618_eth_read
 711 };
 712
 713 static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
 714     mv88w8618_eth_write,
 715     mv88w8618_eth_write,
 716     mv88w8618_eth_write
 717 };
 718
 719 static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq)
 720 {
 721     mv88w8618_eth_state *s;
 722     int iomemtype;
 723
 724     s = qemu_mallocz(sizeof(mv88w8618_eth_state));
 725     if (!s)
 726         return;
 727     s->base = base;
 728     s->irq = irq;
 729     s->vc = qemu_new_vlan_client(nd->vlan, eth_receive, eth_can_receive, s);
 730     iomemtype = cpu_register_io_memory(0, mv88w8618_eth_readfn,
 731                                        mv88w8618_eth_writefn, s);
 732     cpu_register_physical_memory(base, MP_ETH_SIZE, iomemtype);
 733 }
 734
 735 /* LCD register offsets */
 736 #define MP_LCD_IRQCTRL          0x180
 737 #define MP_LCD_IRQSTAT          0x184
 738 #define MP_LCD_SPICTRL          0x1ac
 739 #define MP_LCD_INST             0x1bc
 740 #define MP_LCD_DATA             0x1c0
 741
 742 /* Mode magics */
 743 #define MP_LCD_SPI_DATA         0x00100011
 744 #define MP_LCD_SPI_CMD          0x00104011
 745 #define MP_LCD_SPI_INVALID      0x00000000
 746
 747 /* Commmands */
 748 #define MP_LCD_INST_SETPAGE0    0xB0
 749 /* ... */
 750 #define MP_LCD_INST_SETPAGE7    0xB7
 751
 752 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 753
 754 typedef struct musicpal_lcd_state {
 755     uint32_t base;
 756     uint32_t mode;
 757     uint32_t irqctrl;
 758     int page;
 759     int page_off;
 760     DisplayState *ds;
 761     QEMUConsole *console;
 762     uint8_t video_ram[128*64/8];
 763 } musicpal_lcd_state;
 764
 765 static uint32_t lcd_brightness;
 766
 767 static uint8_t scale_lcd_color(uint8_t col)
 768 {
 769     int tmp = col;
 770
 771     switch (lcd_brightness) {
 772     case 0x00000007: /* 0 */
 773         return 0;
 774
 775     case 0x00020000: /* 1 */
 776         return (tmp * 1) / 7;
 777
 778     case 0x00020001: /* 2 */
 779         return (tmp * 2) / 7;
 780
 781     case 0x00040000: /* 3 */
 782         return (tmp * 3) / 7;
 783
 784     case 0x00010006: /* 4 */
 785         return (tmp * 4) / 7;
 786
 787     case 0x00020005: /* 5 */
 788         return (tmp * 5) / 7;
 789
 790     case 0x00040003: /* 6 */
 791         return (tmp * 6) / 7;
 792
 793     case 0x00030004: /* 7 */
 794     default:
 795         return col;
 796     }
 797 }
 798
 799 #define SET_LCD_PIXEL(depth, type) \
 800 static inline void glue(set_lcd_pixel, depth) \
 801         (musicpal_lcd_state *s, int x, int y, type col) \
 802 { \
 803     int dx, dy; \
 804     type *pixel = &((type *) s->ds->data)[(y * 128 * 3 + x) * 3]; \
 805 \
 806     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 807         for (dx = 0; dx < 3; dx++, pixel++) \
 808             *pixel = col; \
 809 }
 810 SET_LCD_PIXEL(8, uint8_t)
 811 SET_LCD_PIXEL(16, uint16_t)
 812 SET_LCD_PIXEL(32, uint32_t)
 813
 814 #include "pixel_ops.h"
 815
 816 static void lcd_refresh(void *opaque)
 817 {
 818     musicpal_lcd_state *s = opaque;
 819     int x, y, col;
 820
 821     switch (s->ds->depth) {
 822     case 0:
 823         return;
 824 #define LCD_REFRESH(depth, func) \
 825     case depth: \
 826         col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 827                    scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 828                    scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
 829         for (x = 0; x < 128; x++) \
 830             for (y = 0; y < 64; y++) \
 831                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
 832                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 833                 else \
 834                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 835         break;
 836     LCD_REFRESH(8, rgb_to_pixel8)
 837     LCD_REFRESH(16, rgb_to_pixel16)
 838     LCD_REFRESH(32, (s->ds->bgr ? rgb_to_pixel32bgr : rgb_to_pixel32))
 839     default:
 840         cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
 841                   s->ds->depth);
 842     }
 843
 844     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 845 }
 846
 847 static void lcd_invalidate(void *opaque)
 848 {
 849 }
 850
 851 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 852 {
 853     musicpal_lcd_state *s = opaque;
 854
 855     offset -= s->base;
 856     switch (offset) {
 857     case MP_LCD_IRQCTRL:
 858         return s->irqctrl;
 859
 860     default:
 861         return 0;
 862     }
 863 }
 864
 865 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 866                                uint32_t value)
 867 {
 868     musicpal_lcd_state *s = opaque;
 869
 870     offset -= s->base;
 871     switch (offset) {
 872     case MP_LCD_IRQCTRL:
 873         s->irqctrl = value;
 874         break;
 875
 876     case MP_LCD_SPICTRL:
 877         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
 878             s->mode = value;
 879         else
 880             s->mode = MP_LCD_SPI_INVALID;
 881         break;
 882
 883     case MP_LCD_INST:
 884         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 885             s->page = value - MP_LCD_INST_SETPAGE0;
 886             s->page_off = 0;
 887         }
 888         break;
 889
 890     case MP_LCD_DATA:
 891         if (s->mode == MP_LCD_SPI_CMD) {
 892             if (value >= MP_LCD_INST_SETPAGE0 &&
 893                 value <= MP_LCD_INST_SETPAGE7) {
 894                 s->page = value - MP_LCD_INST_SETPAGE0;
 895                 s->page_off = 0;
 896             }
 897         } else if (s->mode == MP_LCD_SPI_DATA) {
 898             s->video_ram[s->page*128 + s->page_off] = value;
 899             s->page_off = (s->page_off + 1) & 127;
 900         }
 901         break;
 902     }
 903 }
 904
 905 static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
 906     musicpal_lcd_read,
 907     musicpal_lcd_read,
 908     musicpal_lcd_read
 909 };
 910
 911 static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
 912     musicpal_lcd_write,
 913     musicpal_lcd_write,
 914     musicpal_lcd_write
 915 };
 916
 917 static void musicpal_lcd_init(DisplayState *ds, uint32_t base)
 918 {
 919     musicpal_lcd_state *s;
 920     int iomemtype;
 921
 922     s = qemu_mallocz(sizeof(musicpal_lcd_state));
 923     if (!s)
 924         return;
 925     s->base = base;
 926     s->ds = ds;
 927     iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
 928                                        musicpal_lcd_writefn, s);
 929     cpu_register_physical_memory(base, MP_LCD_SIZE, iomemtype);
 930
 931     s->console = graphic_console_init(ds, lcd_refresh, lcd_invalidate,
 932                                       NULL, NULL, s);
 933     qemu_console_resize(s->console, 128*3, 64*3);
 934 }
 935
 936 /* PIC register offsets */
 937 #define MP_PIC_STATUS           0x00
 938 #define MP_PIC_ENABLE_SET       0x08
 939 #define MP_PIC_ENABLE_CLR       0x0C
 940
 941 typedef struct mv88w8618_pic_state
 942 {
 943     uint32_t base;
 944     uint32_t level;
 945     uint32_t enabled;
 946     qemu_irq parent_irq;
 947 } mv88w8618_pic_state;
 948
 949 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 950 {
 951     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 952 }
 953
 954 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 955 {
 956     mv88w8618_pic_state *s = opaque;
 957
 958     if (level)
 959         s->level |= 1 << irq;
 960     else
 961         s->level &= ~(1 << irq);
 962     mv88w8618_pic_update(s);
 963 }
 964
 965 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 966 {
 967     mv88w8618_pic_state *s = opaque;
 968
 969     offset -= s->base;
 970     switch (offset) {
 971     case MP_PIC_STATUS:
 972         return s->level & s->enabled;
 973
 974     default:
 975         return 0;
 976     }
 977 }
 978
 979 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 980                                 uint32_t value)
 981 {
 982     mv88w8618_pic_state *s = opaque;
 983
 984     offset -= s->base;
 985     switch (offset) {
 986     case MP_PIC_ENABLE_SET:
 987         s->enabled |= value;
 988         break;
 989
 990     case MP_PIC_ENABLE_CLR:
 991         s->enabled &= ~value;
 992         s->level &= ~value;
 993         break;
 994     }
 995     mv88w8618_pic_update(s);
 996 }
 997
 998 static void mv88w8618_pic_reset(void *opaque)
 999 {
1000     mv88w8618_pic_state *s = opaque;
1001
1002     s->level = 0;
1003     s->enabled = 0;
1004 }
1005
1006 static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
1007     mv88w8618_pic_read,
1008     mv88w8618_pic_read,
1009     mv88w8618_pic_read
1010 };
1011
1012 static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
1013     mv88w8618_pic_write,
1014     mv88w8618_pic_write,
1015     mv88w8618_pic_write
1016 };
1017
1018 static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
1019 {
1020     mv88w8618_pic_state *s;
1021     int iomemtype;
1022     qemu_irq *qi;
1023
1024     s = qemu_mallocz(sizeof(mv88w8618_pic_state));
1025     if (!s)
1026         return NULL;
1027     qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
1028     s->base = base;
1029     s->parent_irq = parent_irq;
1030     iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
1031                                        mv88w8618_pic_writefn, s);
1032     cpu_register_physical_memory(base, MP_PIC_SIZE, iomemtype);
1033
1034     qemu_register_reset(mv88w8618_pic_reset, s);
1035
1036     return qi;
1037 }
1038
1039 /* PIT register offsets */
1040 #define MP_PIT_TIMER1_LENGTH    0x00
1041 /* ... */
1042 #define MP_PIT_TIMER4_LENGTH    0x0C
1043 #define MP_PIT_CONTROL          0x10
1044 #define MP_PIT_TIMER1_VALUE     0x14
1045 /* ... */
1046 #define MP_PIT_TIMER4_VALUE     0x20
1047 #define MP_BOARD_RESET          0x34
1048
1049 /* Magic board reset value (probably some watchdog behind it) */
1050 #define MP_BOARD_RESET_MAGIC    0x10000
1051
1052 typedef struct mv88w8618_timer_state {
1053     ptimer_state *timer;
1054     uint32_t limit;
1055     int freq;
1056     qemu_irq irq;
1057 } mv88w8618_timer_state;
1058
1059 typedef struct mv88w8618_pit_state {
1060     void *timer[4];
1061     uint32_t control;
1062     uint32_t base;
1063 } mv88w8618_pit_state;
1064
1065 static void mv88w8618_timer_tick(void *opaque)
1066 {
1067     mv88w8618_timer_state *s = opaque;
1068
1069     qemu_irq_raise(s->irq);
1070 }
1071
1072 static void *mv88w8618_timer_init(uint32_t freq, qemu_irq irq)
1073 {
1074     mv88w8618_timer_state *s;
1075     QEMUBH *bh;
1076
1077     s = qemu_mallocz(sizeof(mv88w8618_timer_state));
1078     s->irq = irq;
1079     s->freq = freq;
1080
1081     bh = qemu_bh_new(mv88w8618_timer_tick, s);
1082     s->timer = ptimer_init(bh);
1083
1084     return s;
1085 }
1086
1087 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
1088 {
1089     mv88w8618_pit_state *s = opaque;
1090     mv88w8618_timer_state *t;
1091
1092     offset -= s->base;
1093     switch (offset) {
1094     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
1095         t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
1096         return ptimer_get_count(t->timer);
1097
1098     default:
1099         return 0;
1100     }
1101 }
1102
1103 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
1104                                 uint32_t value)
1105 {
1106     mv88w8618_pit_state *s = opaque;
1107     mv88w8618_timer_state *t;
1108     int i;
1109
1110     offset -= s->base;
1111     switch (offset) {
1112     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
1113         t = s->timer[offset >> 2];
1114         t->limit = value;
1115         ptimer_set_limit(t->timer, t->limit, 1);
1116         break;
1117
1118     case MP_PIT_CONTROL:
1119         for (i = 0; i < 4; i++) {
1120             if (value & 0xf) {
1121                 t = s->timer[i];
1122                 ptimer_set_limit(t->timer, t->limit, 0);
1123                 ptimer_set_freq(t->timer, t->freq);
1124                 ptimer_run(t->timer, 0);
1125             }
1126             value >>= 4;
1127         }
1128         break;
1129
1130     case MP_BOARD_RESET:
1131         if (value == MP_BOARD_RESET_MAGIC)
1132             qemu_system_reset_request();
1133         break;
1134     }
1135 }
1136
1137 static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
1138     mv88w8618_pit_read,
1139     mv88w8618_pit_read,
1140     mv88w8618_pit_read
1141 };
1142
1143 static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
1144     mv88w8618_pit_write,
1145     mv88w8618_pit_write,
1146     mv88w8618_pit_write
1147 };
1148
1149 static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq)
1150 {
1151     int iomemtype;
1152     mv88w8618_pit_state *s;
1153
1154     s = qemu_mallocz(sizeof(mv88w8618_pit_state));
1155     if (!s)
1156         return;
1157
1158     s->base = base;
1159     /* Letting them all run at 1 MHz is likely just a pragmatic
1160      * simplification. */
1161     s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]);
1162     s->timer[1] = mv88w8618_timer_init(1000000, pic[irq + 1]);
1163     s->timer[2] = mv88w8618_timer_init(1000000, pic[irq + 2]);
1164     s->timer[3] = mv88w8618_timer_init(1000000, pic[irq + 3]);
1165
1166     iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
1167                                        mv88w8618_pit_writefn, s);
1168     cpu_register_physical_memory(base, MP_PIT_SIZE, iomemtype);
1169 }
1170
1171 /* Flash config register offsets */
1172 #define MP_FLASHCFG_CFGR0    0x04
1173
1174 typedef struct mv88w8618_flashcfg_state {
1175     uint32_t base;
1176     uint32_t cfgr0;
1177 } mv88w8618_flashcfg_state;
1178
1179 static uint32_t mv88w8618_flashcfg_read(void *opaque,
1180                                         target_phys_addr_t offset)
1181 {
1182     mv88w8618_flashcfg_state *s = opaque;
1183
1184     offset -= s->base;
1185     switch (offset) {
1186     case MP_FLASHCFG_CFGR0:
1187         return s->cfgr0;
1188
1189     default:
1190         return 0;
1191     }
1192 }
1193
1194 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
1195                                      uint32_t value)
1196 {
1197     mv88w8618_flashcfg_state *s = opaque;
1198
1199     offset -= s->base;
1200     switch (offset) {
1201     case MP_FLASHCFG_CFGR0:
1202         s->cfgr0 = value;
1203         break;
1204     }
1205 }
1206
1207 static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
1208     mv88w8618_flashcfg_read,
1209     mv88w8618_flashcfg_read,
1210     mv88w8618_flashcfg_read
1211 };
1212
1213 static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
1214     mv88w8618_flashcfg_write,
1215     mv88w8618_flashcfg_write,
1216     mv88w8618_flashcfg_write
1217 };
1218
1219 static void mv88w8618_flashcfg_init(uint32_t base)
1220 {
1221     int iomemtype;
1222     mv88w8618_flashcfg_state *s;
1223
1224     s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
1225     if (!s)
1226         return;
1227
1228     s->base = base;
1229     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1230     iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
1231                        mv88w8618_flashcfg_writefn, s);
1232     cpu_register_physical_memory(base, MP_FLASHCFG_SIZE, iomemtype);
1233 }
1234
1235 /* Various registers in the 0x80000000 domain */
1236 #define MP_BOARD_REVISION       0x2018
1237
1238 #define MP_WLAN_MAGIC1          0xc11c
1239 #define MP_WLAN_MAGIC2          0xc124
1240
1241 #define MP_GPIO_OE_LO           0xd008
1242 #define MP_GPIO_OUT_LO          0xd00c
1243 #define MP_GPIO_IN_LO           0xd010
1244 #define MP_GPIO_ISR_LO          0xd020
1245 #define MP_GPIO_OE_HI           0xd508
1246 #define MP_GPIO_OUT_HI          0xd50c
1247 #define MP_GPIO_IN_HI           0xd510
1248 #define MP_GPIO_ISR_HI          0xd520
1249
1250 /* GPIO bits & masks */
1251 #define MP_GPIO_WHEEL_VOL       (1 << 8)
1252 #define MP_GPIO_WHEEL_VOL_INV   (1 << 9)
1253 #define MP_GPIO_WHEEL_NAV       (1 << 10)
1254 #define MP_GPIO_WHEEL_NAV_INV   (1 << 11)
1255 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1256 #define MP_GPIO_BTN_FAVORITS    (1 << 19)
1257 #define MP_GPIO_BTN_MENU        (1 << 20)
1258 #define MP_GPIO_BTN_VOLUME      (1 << 21)
1259 #define MP_GPIO_BTN_NAVIGATION  (1 << 22)
1260 #define MP_GPIO_I2C_DATA_BIT    29
1261 #define MP_GPIO_I2C_DATA        (1 << MP_GPIO_I2C_DATA_BIT)
1262 #define MP_GPIO_I2C_CLOCK_BIT   30
1263
1264 /* LCD brightness bits in GPIO_OE_HI */
1265 #define MP_OE_LCD_BRIGHTNESS    0x0007
1266
1267 static uint32_t musicpal_read(void *opaque, target_phys_addr_t offset)
1268 {
1269     offset -= 0x80000000;
1270     switch (offset) {
1271     case MP_BOARD_REVISION:
1272         return 0x0031;
1273
1274     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1275         return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1276
1277     case MP_GPIO_OUT_LO:
1278         return gpio_out_state & 0xFFFF;
1279     case MP_GPIO_OUT_HI:
1280         return gpio_out_state >> 16;
1281
1282     case MP_GPIO_IN_LO:
1283         return gpio_in_state & 0xFFFF;
1284     case MP_GPIO_IN_HI:
1285         /* Update received I2C data */
1286         gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
1287                         (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
1288         return gpio_in_state >> 16;
1289
1290     case MP_GPIO_ISR_LO:
1291         return gpio_isr & 0xFFFF;
1292     case MP_GPIO_ISR_HI:
1293         return gpio_isr >> 16;
1294
1295     /* Workaround to allow loading the binary-only wlandrv.ko crap
1296      * from the original Freecom firmware. */
1297     case MP_WLAN_MAGIC1:
1298         return ~3;
1299     case MP_WLAN_MAGIC2:
1300         return -1;
1301
1302     default:
1303         return 0;
1304     }
1305 }
1306
1307 static void musicpal_write(void *opaque, target_phys_addr_t offset,
1308                            uint32_t value)
1309 {
1310     offset -= 0x80000000;
1311     switch (offset) {
1312     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1313         lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1314                          (value & MP_OE_LCD_BRIGHTNESS);
1315         break;
1316
1317     case MP_GPIO_OUT_LO:
1318         gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
1319         break;
1320     case MP_GPIO_OUT_HI:
1321         gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
1322         lcd_brightness = (lcd_brightness & 0xFFFF) |
1323                          (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
1324         i2c_state_update(mixer_i2c,
1325                          (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
1326                          (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1327         break;
1328
1329     }
1330 }
1331
1332 /* Keyboard codes & masks */
1333 #define KEY_RELEASED            0x80
1334 #define KEY_CODE                0x7f
1335
1336 #define KEYCODE_TAB             0x0f
1337 #define KEYCODE_ENTER           0x1c
1338 #define KEYCODE_F               0x21
1339 #define KEYCODE_M               0x32
1340
1341 #define KEYCODE_EXTENDED        0xe0
1342 #define KEYCODE_UP              0x48
1343 #define KEYCODE_DOWN            0x50
1344 #define KEYCODE_LEFT            0x4b
1345 #define KEYCODE_RIGHT           0x4d
1346
1347 static void musicpal_key_event(void *opaque, int keycode)
1348 {
1349     qemu_irq irq = opaque;
1350     uint32_t event = 0;
1351     static int kbd_extended;
1352
1353     if (keycode == KEYCODE_EXTENDED) {
1354         kbd_extended = 1;
1355         return;
1356     }
1357
1358     if (kbd_extended)
1359         switch (keycode & KEY_CODE) {
1360         case KEYCODE_UP:
1361             event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
1362             break;
1363
1364         case KEYCODE_DOWN:
1365             event = MP_GPIO_WHEEL_NAV;
1366             break;
1367
1368         case KEYCODE_LEFT:
1369             event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
1370             break;
1371
1372         case KEYCODE_RIGHT:
1373             event = MP_GPIO_WHEEL_VOL;
1374             break;
1375         }
1376     else {
1377         switch (keycode & KEY_CODE) {
1378         case KEYCODE_F:
1379             event = MP_GPIO_BTN_FAVORITS;
1380             break;
1381
1382         case KEYCODE_TAB:
1383             event = MP_GPIO_BTN_VOLUME;
1384             break;
1385
1386         case KEYCODE_ENTER:
1387             event = MP_GPIO_BTN_NAVIGATION;
1388             break;
1389
1390         case KEYCODE_M:
1391             event = MP_GPIO_BTN_MENU;
1392             break;
1393         }
1394         /* Do not repeat already pressed buttons */
1395         if (!(keycode & KEY_RELEASED) && !(gpio_in_state & event))
1396             event = 0;
1397     }
1398
1399     if (event) {
1400         if (keycode & KEY_RELEASED) {
1401             gpio_in_state |= event;
1402         } else {
1403             gpio_in_state &= ~event;
1404             gpio_isr = event;
1405             qemu_irq_raise(irq);
1406         }
1407     }
1408
1409     kbd_extended = 0;
1410 }
1411
1412 static CPUReadMemoryFunc *musicpal_readfn[] = {
1413     musicpal_read,
1414     musicpal_read,
1415     musicpal_read,
1416 };
1417
1418 static CPUWriteMemoryFunc *musicpal_writefn[] = {
1419     musicpal_write,
1420     musicpal_write,
1421     musicpal_write,
1422 };
1423
1424 static struct arm_boot_info musicpal_binfo = {
1425     .loader_start = 0x0,
1426     .board_id = 0x20e,
1427 };
1428
1429 static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
1430                const char *boot_device, DisplayState *ds,
1431                const char *kernel_filename, const char *kernel_cmdline,
1432                const char *initrd_filename, const char *cpu_model)
1433 {
1434     CPUState *env;
1435     qemu_irq *pic;
1436     int index;
1437     int iomemtype;
1438     unsigned long flash_size;
1439
1440     if (!cpu_model)
1441         cpu_model = "arm926";
1442
1443     env = cpu_init(cpu_model);
1444     if (!env) {
1445         fprintf(stderr, "Unable to find CPU definition\n");
1446         exit(1);
1447     }
1448     pic = arm_pic_init_cpu(env);
1449
1450     /* For now we use a fixed - the original - RAM size */
1451     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1452                                  qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1453
1454     sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1455     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1456
1457     /* Catch various stuff not handled by separate subsystems */
1458     iomemtype = cpu_register_io_memory(0, musicpal_readfn,
1459                                        musicpal_writefn, env);
1460     cpu_register_physical_memory(0x80000000, 0x10000, iomemtype);
1461
1462     pic = mv88w8618_pic_init(MP_PIC_BASE, pic[ARM_PIC_CPU_IRQ]);
1463     mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
1464
1465     if (serial_hds[0])
1466         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1467                    serial_hds[0], 1);
1468     if (serial_hds[1])
1469         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1470                    serial_hds[1], 1);
1471
1472     /* Register flash */
1473     index = drive_get_index(IF_PFLASH, 0, 0);
1474     if (index != -1) {
1475         flash_size = bdrv_getlength(drives_table[index].bdrv);
1476         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1477             flash_size != 32*1024*1024) {
1478             fprintf(stderr, "Invalid flash image size\n");
1479             exit(1);
1480         }
1481
1482         /*
1483          * The original U-Boot accesses the flash at 0xFE000000 instead of
1484          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1485          * image is smaller than 32 MB.
1486          */
1487         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1488                               drives_table[index].bdrv, 0x10000,
1489                               (flash_size + 0xffff) >> 16,
1490                               MP_FLASH_SIZE_MAX / flash_size,
1491                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1492                               0x5555, 0x2AAA);
1493     }
1494     mv88w8618_flashcfg_init(MP_FLASHCFG_BASE);
1495
1496     musicpal_lcd_init(ds, MP_LCD_BASE);
1497
1498     qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
1499
1500     mv88w8618_eth_init(&nd_table[0], MP_ETH_BASE, pic[MP_ETH_IRQ]);
1501
1502     mixer_i2c = musicpal_audio_init(MP_AUDIO_BASE, pic[MP_AUDIO_IRQ]);
1503
1504     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1505     musicpal_binfo.kernel_filename = kernel_filename;
1506     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1507     musicpal_binfo.initrd_filename = initrd_filename;
1508     arm_load_kernel(env, &musicpal_binfo);
1509 }
1510
1511 QEMUMachine musicpal_machine = {
1512     .name = "musicpal",
1513     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1514     .init = musicpal_init,
1515     .ram_require = MP_RAM_DEFAULT_SIZE + MP_SRAM_SIZE +
1516             MP_FLASH_SIZE_MAX + RAMSIZE_FIXED,
1517 };