hw/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL
   8  */
   9
  10 #include "hw.h"
  11 #include "primecell.h"
  12 #include "devices.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "arm-misc.h"
  16 #include "net.h"
  17
  18 typedef struct {
  19     uint32_t flash_offset;
  20     uint32_t cm_osc;
  21     uint32_t cm_ctrl;
  22     uint32_t cm_lock;
  23     uint32_t cm_auxosc;
  24     uint32_t cm_sdram;
  25     uint32_t cm_init;
  26     uint32_t cm_flags;
  27     uint32_t cm_nvflags;
  28     uint32_t int_level;
  29     uint32_t irq_enabled;
  30     uint32_t fiq_enabled;
  31 } integratorcm_state;
  32
  33 static uint8_t integrator_spd[128] = {
  34    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  35    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  36 };
  37
  38 static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
  39 {
  40     integratorcm_state *s = (integratorcm_state *)opaque;
  41     offset -= 0x10000000;
  42     if (offset >= 0x100 && offset < 0x200) {
  43         /* CM_SPD */
  44         if (offset >= 0x180)
  45             return 0;
  46         return integrator_spd[offset >> 2];
  47     }
  48     switch (offset >> 2) {
  49     case 0: /* CM_ID */
  50         return 0x411a3001;
  51     case 1: /* CM_PROC */
  52         return 0;
  53     case 2: /* CM_OSC */
  54         return s->cm_osc;
  55     case 3: /* CM_CTRL */
  56         return s->cm_ctrl;
  57     case 4: /* CM_STAT */
  58         return 0x00100000;
  59     case 5: /* CM_LOCK */
  60         if (s->cm_lock == 0xa05f) {
  61             return 0x1a05f;
  62         } else {
  63             return s->cm_lock;
  64         }
  65     case 6: /* CM_LMBUSCNT */
  66         /* ??? High frequency timer.  */
  67         cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
  68     case 7: /* CM_AUXOSC */
  69         return s->cm_auxosc;
  70     case 8: /* CM_SDRAM */
  71         return s->cm_sdram;
  72     case 9: /* CM_INIT */
  73         return s->cm_init;
  74     case 10: /* CM_REFCT */
  75         /* ??? High frequency timer.  */
  76         cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
  77     case 12: /* CM_FLAGS */
  78         return s->cm_flags;
  79     case 14: /* CM_NVFLAGS */
  80         return s->cm_nvflags;
  81     case 16: /* CM_IRQ_STAT */
  82         return s->int_level & s->irq_enabled;
  83     case 17: /* CM_IRQ_RSTAT */
  84         return s->int_level;
  85     case 18: /* CM_IRQ_ENSET */
  86         return s->irq_enabled;
  87     case 20: /* CM_SOFT_INTSET */
  88         return s->int_level & 1;
  89     case 24: /* CM_FIQ_STAT */
  90         return s->int_level & s->fiq_enabled;
  91     case 25: /* CM_FIQ_RSTAT */
  92         return s->int_level;
  93     case 26: /* CM_FIQ_ENSET */
  94         return s->fiq_enabled;
  95     case 32: /* CM_VOLTAGE_CTL0 */
  96     case 33: /* CM_VOLTAGE_CTL1 */
  97     case 34: /* CM_VOLTAGE_CTL2 */
  98     case 35: /* CM_VOLTAGE_CTL3 */
  99         /* ??? Voltage control unimplemented.  */
 100         return 0;
 101     default:
 102         cpu_abort (cpu_single_env,
 103             "integratorcm_read: Unimplemented offset 0x%x\n", (int)offset);
 104         return 0;
 105     }
 106 }
 107
 108 static void integratorcm_do_remap(integratorcm_state *s, int flash)
 109 {
 110     if (flash) {
 111         cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM);
 112     } else {
 113         cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM);
 114     }
 115     //??? tlb_flush (cpu_single_env, 1);
 116 }
 117
 118 static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
 119 {
 120     if (value & 8) {
 121         cpu_abort(cpu_single_env, "Board reset\n");
 122     }
 123     if ((s->cm_init ^ value) & 4) {
 124         integratorcm_do_remap(s, (value & 4) == 0);
 125     }
 126     if ((s->cm_init ^ value) & 1) {
 127         printf("Green LED %s\n", (value & 1) ? "on" : "off");
 128     }
 129     s->cm_init = (s->cm_init & ~ 5) | (value ^ 5);
 130 }
 131
 132 static void integratorcm_update(integratorcm_state *s)
 133 {
 134     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 135        are active.  */
 136     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 137         cpu_abort(cpu_single_env, "Core module interrupt\n");
 138 }
 139
 140 static void integratorcm_write(void *opaque, target_phys_addr_t offset,
 141                                uint32_t value)
 142 {
 143     integratorcm_state *s = (integratorcm_state *)opaque;
 144     offset -= 0x10000000;
 145     switch (offset >> 2) {
 146     case 2: /* CM_OSC */
 147         if (s->cm_lock == 0xa05f)
 148             s->cm_osc = value;
 149         break;
 150     case 3: /* CM_CTRL */
 151         integratorcm_set_ctrl(s, value);
 152         break;
 153     case 5: /* CM_LOCK */
 154         s->cm_lock = value & 0xffff;
 155         break;
 156     case 7: /* CM_AUXOSC */
 157         if (s->cm_lock == 0xa05f)
 158             s->cm_auxosc = value;
 159         break;
 160     case 8: /* CM_SDRAM */
 161         s->cm_sdram = value;
 162         break;
 163     case 9: /* CM_INIT */
 164         /* ??? This can change the memory bus frequency.  */
 165         s->cm_init = value;
 166         break;
 167     case 12: /* CM_FLAGSS */
 168         s->cm_flags |= value;
 169         break;
 170     case 13: /* CM_FLAGSC */
 171         s->cm_flags &= ~value;
 172         break;
 173     case 14: /* CM_NVFLAGSS */
 174         s->cm_nvflags |= value;
 175         break;
 176     case 15: /* CM_NVFLAGSS */
 177         s->cm_nvflags &= ~value;
 178         break;
 179     case 18: /* CM_IRQ_ENSET */
 180         s->irq_enabled |= value;
 181         integratorcm_update(s);
 182         break;
 183     case 19: /* CM_IRQ_ENCLR */
 184         s->irq_enabled &= ~value;
 185         integratorcm_update(s);
 186         break;
 187     case 20: /* CM_SOFT_INTSET */
 188         s->int_level |= (value & 1);
 189         integratorcm_update(s);
 190         break;
 191     case 21: /* CM_SOFT_INTCLR */
 192         s->int_level &= ~(value & 1);
 193         integratorcm_update(s);
 194         break;
 195     case 26: /* CM_FIQ_ENSET */
 196         s->fiq_enabled |= value;
 197         integratorcm_update(s);
 198         break;
 199     case 27: /* CM_FIQ_ENCLR */
 200         s->fiq_enabled &= ~value;
 201         integratorcm_update(s);
 202         break;
 203     case 32: /* CM_VOLTAGE_CTL0 */
 204     case 33: /* CM_VOLTAGE_CTL1 */
 205     case 34: /* CM_VOLTAGE_CTL2 */
 206     case 35: /* CM_VOLTAGE_CTL3 */
 207         /* ??? Voltage control unimplemented.  */
 208         break;
 209     default:
 210         cpu_abort (cpu_single_env,
 211             "integratorcm_write: Unimplemented offset 0x%x\n", (int)offset);
 212         break;
 213     }
 214 }
 215
 216 /* Integrator/CM control registers.  */
 217
 218 static CPUReadMemoryFunc *integratorcm_readfn[] = {
 219    integratorcm_read,
 220    integratorcm_read,
 221    integratorcm_read
 222 };
 223
 224 static CPUWriteMemoryFunc *integratorcm_writefn[] = {
 225    integratorcm_write,
 226    integratorcm_write,
 227    integratorcm_write
 228 };
 229
 230 static void integratorcm_init(int memsz)
 231 {
 232     int iomemtype;
 233     integratorcm_state *s;
 234
 235     s = (integratorcm_state *)qemu_mallocz(sizeof(integratorcm_state));
 236     s->cm_osc = 0x01000048;
 237     /* ??? What should the high bits of this value be?  */
 238     s->cm_auxosc = 0x0007feff;
 239     s->cm_sdram = 0x00011122;
 240     if (memsz >= 256) {
 241         integrator_spd[31] = 64;
 242         s->cm_sdram |= 0x10;
 243     } else if (memsz >= 128) {
 244         integrator_spd[31] = 32;
 245         s->cm_sdram |= 0x0c;
 246     } else if (memsz >= 64) {
 247         integrator_spd[31] = 16;
 248         s->cm_sdram |= 0x08;
 249     } else if (memsz >= 32) {
 250         integrator_spd[31] = 4;
 251         s->cm_sdram |= 0x04;
 252     } else {
 253         integrator_spd[31] = 2;
 254     }
 255     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 256     s->cm_init = 0x00000112;
 257     s->flash_offset = qemu_ram_alloc(0x100000);
 258
 259     iomemtype = cpu_register_io_memory(0, integratorcm_readfn,
 260                                        integratorcm_writefn, s);
 261     cpu_register_physical_memory(0x10000000, 0x00800000, iomemtype);
 262     integratorcm_do_remap(s, 1);
 263     /* ??? Save/restore.  */
 264 }
 265
 266 /* Integrator/CP hardware emulation.  */
 267 /* Primary interrupt controller.  */
 268
 269 typedef struct icp_pic_state
 270 {
 271   uint32_t base;
 272   uint32_t level;
 273   uint32_t irq_enabled;
 274   uint32_t fiq_enabled;
 275   qemu_irq parent_irq;
 276   qemu_irq parent_fiq;
 277 } icp_pic_state;
 278
 279 static void icp_pic_update(icp_pic_state *s)
 280 {
 281     uint32_t flags;
 282
 283     flags = (s->level & s->irq_enabled);
 284     qemu_set_irq(s->parent_irq, flags != 0);
 285     flags = (s->level & s->fiq_enabled);
 286     qemu_set_irq(s->parent_fiq, flags != 0);
 287 }
 288
 289 static void icp_pic_set_irq(void *opaque, int irq, int level)
 290 {
 291     icp_pic_state *s = (icp_pic_state *)opaque;
 292     if (level)
 293         s->level |= 1 << irq;
 294     else
 295         s->level &= ~(1 << irq);
 296     icp_pic_update(s);
 297 }
 298
 299 static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
 300 {
 301     icp_pic_state *s = (icp_pic_state *)opaque;
 302
 303     offset -= s->base;
 304     switch (offset >> 2) {
 305     case 0: /* IRQ_STATUS */
 306         return s->level & s->irq_enabled;
 307     case 1: /* IRQ_RAWSTAT */
 308         return s->level;
 309     case 2: /* IRQ_ENABLESET */
 310         return s->irq_enabled;
 311     case 4: /* INT_SOFTSET */
 312         return s->level & 1;
 313     case 8: /* FRQ_STATUS */
 314         return s->level & s->fiq_enabled;
 315     case 9: /* FRQ_RAWSTAT */
 316         return s->level;
 317     case 10: /* FRQ_ENABLESET */
 318         return s->fiq_enabled;
 319     case 3: /* IRQ_ENABLECLR */
 320     case 5: /* INT_SOFTCLR */
 321     case 11: /* FRQ_ENABLECLR */
 322     default:
 323         printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
 324         return 0;
 325     }
 326 }
 327
 328 static void icp_pic_write(void *opaque, target_phys_addr_t offset,
 329                           uint32_t value)
 330 {
 331     icp_pic_state *s = (icp_pic_state *)opaque;
 332     offset -= s->base;
 333
 334     switch (offset >> 2) {
 335     case 2: /* IRQ_ENABLESET */
 336         s->irq_enabled |= value;
 337         break;
 338     case 3: /* IRQ_ENABLECLR */
 339         s->irq_enabled &= ~value;
 340         break;
 341     case 4: /* INT_SOFTSET */
 342         if (value & 1)
 343             icp_pic_set_irq(s, 0, 1);
 344         break;
 345     case 5: /* INT_SOFTCLR */
 346         if (value & 1)
 347             icp_pic_set_irq(s, 0, 0);
 348         break;
 349     case 10: /* FRQ_ENABLESET */
 350         s->fiq_enabled |= value;
 351         break;
 352     case 11: /* FRQ_ENABLECLR */
 353         s->fiq_enabled &= ~value;
 354         break;
 355     case 0: /* IRQ_STATUS */
 356     case 1: /* IRQ_RAWSTAT */
 357     case 8: /* FRQ_STATUS */
 358     case 9: /* FRQ_RAWSTAT */
 359     default:
 360         printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
 361         return;
 362     }
 363     icp_pic_update(s);
 364 }
 365
 366 static CPUReadMemoryFunc *icp_pic_readfn[] = {
 367    icp_pic_read,
 368    icp_pic_read,
 369    icp_pic_read
 370 };
 371
 372 static CPUWriteMemoryFunc *icp_pic_writefn[] = {
 373    icp_pic_write,
 374    icp_pic_write,
 375    icp_pic_write
 376 };
 377
 378 static qemu_irq *icp_pic_init(uint32_t base,
 379                               qemu_irq parent_irq, qemu_irq parent_fiq)
 380 {
 381     icp_pic_state *s;
 382     int iomemtype;
 383     qemu_irq *qi;
 384
 385     s = (icp_pic_state *)qemu_mallocz(sizeof(icp_pic_state));
 386     if (!s)
 387         return NULL;
 388     qi = qemu_allocate_irqs(icp_pic_set_irq, s, 32);
 389     s->base = base;
 390     s->parent_irq = parent_irq;
 391     s->parent_fiq = parent_fiq;
 392     iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
 393                                        icp_pic_writefn, s);
 394     cpu_register_physical_memory(base, 0x00800000, iomemtype);
 395     /* ??? Save/restore.  */
 396     return qi;
 397 }
 398
 399 /* CP control registers.  */
 400 typedef struct {
 401     uint32_t base;
 402 } icp_control_state;
 403
 404 static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
 405 {
 406     icp_control_state *s = (icp_control_state *)opaque;
 407     offset -= s->base;
 408     switch (offset >> 2) {
 409     case 0: /* CP_IDFIELD */
 410         return 0x41034003;
 411     case 1: /* CP_FLASHPROG */
 412         return 0;
 413     case 2: /* CP_INTREG */
 414         return 0;
 415     case 3: /* CP_DECODE */
 416         return 0x11;
 417     default:
 418         cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n",
 419                    (int)offset);
 420         return 0;
 421     }
 422 }
 423
 424 static void icp_control_write(void *opaque, target_phys_addr_t offset,
 425                           uint32_t value)
 426 {
 427     icp_control_state *s = (icp_control_state *)opaque;
 428     offset -= s->base;
 429     switch (offset >> 2) {
 430     case 1: /* CP_FLASHPROG */
 431     case 2: /* CP_INTREG */
 432     case 3: /* CP_DECODE */
 433         /* Nothing interesting implemented yet.  */
 434         break;
 435     default:
 436         cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n",
 437                    (int)offset);
 438     }
 439 }
 440 static CPUReadMemoryFunc *icp_control_readfn[] = {
 441    icp_control_read,
 442    icp_control_read,
 443    icp_control_read
 444 };
 445
 446 static CPUWriteMemoryFunc *icp_control_writefn[] = {
 447    icp_control_write,
 448    icp_control_write,
 449    icp_control_write
 450 };
 451
 452 static void icp_control_init(uint32_t base)
 453 {
 454     int iomemtype;
 455     icp_control_state *s;
 456
 457     s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state));
 458     iomemtype = cpu_register_io_memory(0, icp_control_readfn,
 459                                        icp_control_writefn, s);
 460     cpu_register_physical_memory(base, 0x00800000, iomemtype);
 461     s->base = base;
 462     /* ??? Save/restore.  */
 463 }
 464
 465
 466 /* Board init.  */
 467
 468 static struct arm_boot_info integrator_binfo = {
 469     .loader_start = 0x0,
 470     .board_id = 0x113,
 471 };
 472
 473 static void integratorcp_init(ram_addr_t ram_size, int vga_ram_size,
 474                      const char *boot_device, DisplayState *ds,
 475                      const char *kernel_filename, const char *kernel_cmdline,
 476                      const char *initrd_filename, const char *cpu_model)
 477 {
 478     CPUState *env;
 479     uint32_t ram_offset;
 480     qemu_irq *pic;
 481     qemu_irq *cpu_pic;
 482     int sd;
 483
 484     if (!cpu_model)
 485         cpu_model = "arm926";
 486     env = cpu_init(cpu_model);
 487     if (!env) {
 488         fprintf(stderr, "Unable to find CPU definition\n");
 489         exit(1);
 490     }
 491     ram_offset = qemu_ram_alloc(ram_size);
 492     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 493     /* ??? RAM should repeat to fill physical memory space.  */
 494     /* SDRAM at address zero*/
 495     cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
 496     /* And again at address 0x80000000 */
 497     cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
 498
 499     integratorcm_init(ram_size >> 20);
 500     cpu_pic = arm_pic_init_cpu(env);
 501     pic = icp_pic_init(0x14000000, cpu_pic[ARM_PIC_CPU_IRQ],
 502                        cpu_pic[ARM_PIC_CPU_FIQ]);
 503     icp_pic_init(0xca000000, pic[26], NULL);
 504     icp_pit_init(0x13000000, pic, 5);
 505     pl031_init(0x15000000, pic[8]);
 506     pl011_init(0x16000000, pic[1], serial_hds[0], PL011_ARM);
 507     pl011_init(0x17000000, pic[2], serial_hds[1], PL011_ARM);
 508     icp_control_init(0xcb000000);
 509     pl050_init(0x18000000, pic[3], 0);
 510     pl050_init(0x19000000, pic[4], 1);
 511     sd = drive_get_index(IF_SD, 0, 0);
 512     if (sd == -1) {
 513         fprintf(stderr, "qemu: missing SecureDigital card\n");
 514         exit(1);
 515     }
 516     pl181_init(0x1c000000, drives_table[sd].bdrv, pic[23], pic[24]);
 517     if (nd_table[0].vlan) {
 518         if (nd_table[0].model == NULL
 519             || strcmp(nd_table[0].model, "smc91c111") == 0) {
 520             smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
 521         } else if (strcmp(nd_table[0].model, "?") == 0) {
 522             fprintf(stderr, "qemu: Supported NICs: smc91c111\n");
 523             exit (1);
 524         } else {
 525             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 526             exit (1);
 527         }
 528     }
 529     pl110_init(ds, 0xc0000000, pic[22], 0);
 530
 531     integrator_binfo.ram_size = ram_size;
 532     integrator_binfo.kernel_filename = kernel_filename;
 533     integrator_binfo.kernel_cmdline = kernel_cmdline;
 534     integrator_binfo.initrd_filename = initrd_filename;
 535     arm_load_kernel(env, &integrator_binfo);
 536 }
 537
 538 QEMUMachine integratorcp_machine = {
 539     .name = "integratorcp",
 540     .desc = "ARM Integrator/CP (ARM926EJ-S)",
 541     .init = integratorcp_init,
 542     .ram_require = 0x100000,
 543 };