hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 /* PCI includes legacy ISA access.  */
   7 #include "isa.h"
   8
   9 /* PCI bus */
  10
  11 extern target_phys_addr_t pci_mem_base;
  12
  13 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  14 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  15 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  16
  17 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  18 #include "pci_ids.h"
  19
  20 /* QEMU-specific Vendor and Device ID definitions */
  21
  22 /* IBM (0x1014) */
  23 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  24 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  25
  26 /* Hitachi (0x1054) */
  27 #define PCI_VENDOR_ID_HITACHI            0x1054
  28 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  29
  30 /* Apple (0x106b) */
  31 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  32 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  33 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  34 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  35 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  36
  37 /* Realtek (0x10ec) */
  38 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  39
  40 /* Xilinx (0x10ee) */
  41 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  42
  43 /* Marvell (0x11ab) */
  44 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  45
  46 /* QEMU/Bochs VGA (0x1234) */
  47 #define PCI_VENDOR_ID_QEMU               0x1234
  48 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  49
  50 /* VMWare (0x15ad) */
  51 #define PCI_VENDOR_ID_VMWARE             0x15ad
  52 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  53 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  54 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  55 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  56 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  57
  58 /* Intel (0x8086) */
  59 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  60
  61 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  62 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  63 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  64 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  65
  66 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  67 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  68 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  69 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  70
  71 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  72                                 uint32_t address, uint32_t data, int len);
  73 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  74                                    uint32_t address, int len);
  75 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  76                                 uint32_t addr, uint32_t size, int type);
  77 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  78
  79 #define PCI_ADDRESS_SPACE_MEM           0x00
  80 #define PCI_ADDRESS_SPACE_IO            0x01
  81 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
  82
  83 typedef struct PCIIORegion {
  84     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
  85     uint32_t size;
  86     uint8_t type;
  87     PCIMapIORegionFunc *map_func;
  88 } PCIIORegion;
  89
  90 #define PCI_ROM_SLOT 6
  91 #define PCI_NUM_REGIONS 7
  92
  93 #define PCI_DEVICES_MAX 64
  94
  95 /* Declarations from linux/pci_regs.h */
  96 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  97 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  98 #define PCI_COMMAND             0x04    /* 16 bits */
  99 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 100 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 101 #define PCI_STATUS              0x06    /* 16 bits */
 102 #define PCI_REVISION_ID         0x08    /* 8 bits  */
 103 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 104 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
 105 #define  PCI_HEADER_TYPE_NORMAL         0
 106 #define  PCI_HEADER_TYPE_BRIDGE         1
 107 #define  PCI_HEADER_TYPE_CARDBUS        2
 108 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 109 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
 110 #define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */
 111 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 112 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 113 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 114 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 115
 116 #define PCI_REVISION            0x08    /* obsolete, use PCI_REVISION_ID */
 117 #define PCI_SUBVENDOR_ID        0x2c    /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
 118 #define PCI_SUBDEVICE_ID        0x2e    /* obsolete, use PCI_SUBSYSTEM_ID */
 119
 120 /* Bits in the PCI Status Register (PCI 2.3 spec) */
 121 #define PCI_STATUS_RESERVED1    0x007
 122 #define PCI_STATUS_INT_STATUS   0x008
 123 #define PCI_STATUS_CAPABILITIES 0x010
 124 #define PCI_STATUS_66MHZ        0x020
 125 #define PCI_STATUS_RESERVED2    0x040
 126 #define PCI_STATUS_FAST_BACK    0x080
 127 #define PCI_STATUS_DEVSEL       0x600
 128
 129 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 130                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 131                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 132
 133 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 134
 135 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 136 #define PCI_COMMAND_RESERVED    0xf800
 137
 138 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 139
 140 struct PCIDevice {
 141     /* PCI config space */
 142     uint8_t config[256];
 143
 144     /* the following fields are read only */
 145     PCIBus *bus;
 146     int devfn;
 147     char name[64];
 148     PCIIORegion io_regions[PCI_NUM_REGIONS];
 149
 150     /* do not access the following fields */
 151     PCIConfigReadFunc *config_read;
 152     PCIConfigWriteFunc *config_write;
 153     PCIUnregisterFunc *unregister;
 154     /* ??? This is a PC-specific hack, and should be removed.  */
 155     int irq_index;
 156
 157     /* IRQ objects for the INTA-INTD pins.  */
 158     qemu_irq *irq;
 159
 160     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 161     int irq_state[4];
 162 };
 163
 164 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 165                                int instance_size, int devfn,
 166                                PCIConfigReadFunc *config_read,
 167                                PCIConfigWriteFunc *config_write);
 168 int pci_unregister_device(PCIDevice *pci_dev);
 169
 170 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 171                             uint32_t size, int type,
 172                             PCIMapIORegionFunc *map_func);
 173
 174 uint32_t pci_default_read_config(PCIDevice *d,
 175                                  uint32_t address, int len);
 176 void pci_default_write_config(PCIDevice *d,
 177                               uint32_t address, uint32_t val, int len);
 178 void pci_device_save(PCIDevice *s, QEMUFile *f);
 179 int pci_device_load(PCIDevice *s, QEMUFile *f);
 180
 181 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
 182 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 183 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 184                          qemu_irq *pic, int devfn_min, int nirq);
 185
 186 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 187                   const char *default_model);
 188 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 189 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 190 int pci_bus_num(PCIBus *s);
 191 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 192 PCIBus *pci_find_bus(int bus_num);
 193 PCIDevice *pci_find_device(int bus_num, int slot, int function);
 194
 195 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp);
 196 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp);
 197
 198 void pci_info(Monitor *mon);
 199 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 200                         pci_map_irq_fn map_irq, const char *name);
 201
 202 static inline void
 203 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 204 {
 205     cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
 206 }
 207
 208 static inline void
 209 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 210 {
 211     cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
 212 }
 213
 214 static inline void
 215 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 216 {
 217     cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val);
 218 }
 219
 220 /* lsi53c895a.c */
 221 #define LSI_MAX_DEVS 7
 222 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
 223 void *lsi_scsi_init(PCIBus *bus, int devfn);
 224
 225 /* vmware_vga.c */
 226 void pci_vmsvga_init(PCIBus *bus, int vga_ram_size);
 227
 228 /* usb-uhci.c */
 229 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 230 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 231
 232 /* usb-ohci.c */
 233 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
 234
 235 /* eepro100.c */
 236
 237 PCIDevice *pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
 238 PCIDevice *pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
 239 PCIDevice *pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
 240
 241 /* ne2000.c */
 242
 243 PCIDevice *pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
 244
 245 /* rtl8139.c */
 246
 247 PCIDevice *pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
 248
 249 /* e1000.c */
 250 PCIDevice *pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn);
 251
 252 /* pcnet.c */
 253 PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
 254
 255 /* prep_pci.c */
 256 PCIBus *pci_prep_init(qemu_irq *pic);
 257
 258 /* apb_pci.c */
 259 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 260                      target_phys_addr_t mem_base,
 261                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
 262
 263 /* sh_pci.c */
 264 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 265                             qemu_irq *pic, int devfn_min, int nirq);
 266
 267 #endif