hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "virtio-net.h"
  29 #include "sysemu.h"
  30
  31 //#define DEBUG_PCI
  32
  33 struct PCIBus {
  34     int bus_num;
  35     int devfn_min;
  36     pci_set_irq_fn set_irq;
  37     pci_map_irq_fn map_irq;
  38     uint32_t config_reg; /* XXX: suppress */
  39     /* low level pic */
  40     SetIRQFunc *low_set_irq;
  41     qemu_irq *irq_opaque;
  42     PCIDevice *devices[256];
  43     PCIDevice *parent_dev;
  44     PCIBus *next;
  45     /* The bus IRQ state is the logical OR of the connected devices.
  46        Keep a count of the number of devices with raised IRQs.  */
  47     int nirq;
  48     int irq_count[];
  49 };
  50
  51 static void pci_update_mappings(PCIDevice *d);
  52 static void pci_set_irq(void *opaque, int irq_num, int level);
  53
  54 target_phys_addr_t pci_mem_base;
  55 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  56 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  57 static int pci_irq_index;
  58 static PCIBus *first_bus;
  59
  60 static void pcibus_save(QEMUFile *f, void *opaque)
  61 {
  62     PCIBus *bus = (PCIBus *)opaque;
  63     int i;
  64
  65     qemu_put_be32(f, bus->nirq);
  66     for (i = 0; i < bus->nirq; i++)
  67         qemu_put_be32(f, bus->irq_count[i]);
  68 }
  69
  70 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  71 {
  72     PCIBus *bus = (PCIBus *)opaque;
  73     int i, nirq;
  74
  75     if (version_id != 1)
  76         return -EINVAL;
  77
  78     nirq = qemu_get_be32(f);
  79     if (bus->nirq != nirq) {
  80         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  81                 nirq, bus->nirq);
  82         return -EINVAL;
  83     }
  84
  85     for (i = 0; i < nirq; i++)
  86         bus->irq_count[i] = qemu_get_be32(f);
  87
  88     return 0;
  89 }
  90
  91 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  92                          qemu_irq *pic, int devfn_min, int nirq)
  93 {
  94     PCIBus *bus;
  95     static int nbus = 0;
  96
  97     bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
  98     bus->set_irq = set_irq;
  99     bus->map_irq = map_irq;
 100     bus->irq_opaque = pic;
 101     bus->devfn_min = devfn_min;
 102     bus->nirq = nirq;
 103     bus->next = first_bus;
 104     first_bus = bus;
 105     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 106     return bus;
 107 }
 108
 109 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 110 {
 111     PCIBus *bus;
 112     bus = qemu_mallocz(sizeof(PCIBus));
 113     bus->map_irq = map_irq;
 114     bus->parent_dev = dev;
 115     bus->next = dev->bus->next;
 116     dev->bus->next = bus;
 117     return bus;
 118 }
 119
 120 int pci_bus_num(PCIBus *s)
 121 {
 122     return s->bus_num;
 123 }
 124
 125 void pci_device_save(PCIDevice *s, QEMUFile *f)
 126 {
 127     int i;
 128
 129     qemu_put_be32(f, 2); /* PCI device version */
 130     qemu_put_buffer(f, s->config, 256);
 131     for (i = 0; i < 4; i++)
 132         qemu_put_be32(f, s->irq_state[i]);
 133 }
 134
 135 int pci_device_load(PCIDevice *s, QEMUFile *f)
 136 {
 137     uint32_t version_id;
 138     int i;
 139
 140     version_id = qemu_get_be32(f);
 141     if (version_id > 2)
 142         return -EINVAL;
 143     qemu_get_buffer(f, s->config, 256);
 144     pci_update_mappings(s);
 145
 146     if (version_id >= 2)
 147         for (i = 0; i < 4; i ++)
 148             s->irq_state[i] = qemu_get_be32(f);
 149
 150     return 0;
 151 }
 152
 153 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 154 {
 155     uint16_t *id;
 156
 157     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 158     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 159     id[1] = cpu_to_le16(pci_default_sub_device_id);
 160     return 0;
 161 }
 162
 163 /*
 164  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 165  */
 166 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 167 {
 168     const char *p;
 169     char *e;
 170     unsigned long val;
 171     unsigned long dom = 0, bus = 0;
 172     unsigned slot = 0;
 173
 174     p = addr;
 175     val = strtoul(p, &e, 16);
 176     if (e == p)
 177         return -1;
 178     if (*e == ':') {
 179         bus = val;
 180         p = e + 1;
 181         val = strtoul(p, &e, 16);
 182         if (e == p)
 183             return -1;
 184         if (*e == ':') {
 185             dom = bus;
 186             bus = val;
 187             p = e + 1;
 188             val = strtoul(p, &e, 16);
 189             if (e == p)
 190                 return -1;
 191         }
 192     }
 193
 194     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 195         return -1;
 196
 197     slot = val;
 198
 199     if (*e)
 200         return -1;
 201
 202     /* Note: QEMU doesn't implement domains other than 0 */
 203     if (dom != 0 || pci_find_bus(bus) == NULL)
 204         return -1;
 205
 206     *domp = dom;
 207     *busp = bus;
 208     *slotp = slot;
 209     return 0;
 210 }
 211
 212 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 213 {
 214     char devaddr[32];
 215
 216     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 217         return -1;
 218
 219     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 220 }
 221
 222 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 223 {
 224     char devaddr[32];
 225
 226     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 227         return -1;
 228
 229     if (!strcmp(devaddr, "auto")) {
 230         *domp = *busp = 0;
 231         *slotp = -1;
 232         /* want to support dom/bus auto-assign at some point */
 233         return 0;
 234     }
 235
 236     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 237 }
 238
 239 /* -1 for devfn means auto assign */
 240 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 241                                int instance_size, int devfn,
 242                                PCIConfigReadFunc *config_read,
 243                                PCIConfigWriteFunc *config_write)
 244 {
 245     PCIDevice *pci_dev;
 246
 247     if (pci_irq_index >= PCI_DEVICES_MAX)
 248         return NULL;
 249
 250     if (devfn < 0) {
 251         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 252             if (!bus->devices[devfn])
 253                 goto found;
 254         }
 255         return NULL;
 256     found: ;
 257     }
 258     pci_dev = qemu_mallocz(instance_size);
 259     pci_dev->bus = bus;
 260     pci_dev->devfn = devfn;
 261     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 262     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 263     pci_set_default_subsystem_id(pci_dev);
 264
 265     if (!config_read)
 266         config_read = pci_default_read_config;
 267     if (!config_write)
 268         config_write = pci_default_write_config;
 269     pci_dev->config_read = config_read;
 270     pci_dev->config_write = config_write;
 271     pci_dev->irq_index = pci_irq_index++;
 272     bus->devices[devfn] = pci_dev;
 273     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 274     return pci_dev;
 275 }
 276
 277 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 278 {
 279     return addr + pci_mem_base;
 280 }
 281
 282 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 283 {
 284     PCIIORegion *r;
 285     int i;
 286
 287     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 288         r = &pci_dev->io_regions[i];
 289         if (!r->size || r->addr == -1)
 290             continue;
 291         if (r->type == PCI_ADDRESS_SPACE_IO) {
 292             isa_unassign_ioport(r->addr, r->size);
 293         } else {
 294             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 295                                                      r->size,
 296                                                      IO_MEM_UNASSIGNED);
 297         }
 298     }
 299 }
 300
 301 int pci_unregister_device(PCIDevice *pci_dev)
 302 {
 303     int ret = 0;
 304
 305     if (pci_dev->unregister)
 306         ret = pci_dev->unregister(pci_dev);
 307     if (ret)
 308         return ret;
 309
 310     pci_unregister_io_regions(pci_dev);
 311
 312     qemu_free_irqs(pci_dev->irq);
 313     pci_irq_index--;
 314     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 315     qemu_free(pci_dev);
 316     return 0;
 317 }
 318
 319 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 320                             uint32_t size, int type,
 321                             PCIMapIORegionFunc *map_func)
 322 {
 323     PCIIORegion *r;
 324     uint32_t addr;
 325
 326     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 327         return;
 328
 329     if (size & (size-1)) {
 330         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 331                     "type=0x%x, size=0x%x\n", type, size);
 332         exit(1);
 333     }
 334
 335     r = &pci_dev->io_regions[region_num];
 336     r->addr = -1;
 337     r->size = size;
 338     r->type = type;
 339     r->map_func = map_func;
 340     if (region_num == PCI_ROM_SLOT) {
 341         addr = 0x30;
 342     } else {
 343         addr = 0x10 + region_num * 4;
 344     }
 345     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 346 }
 347
 348 static void pci_update_mappings(PCIDevice *d)
 349 {
 350     PCIIORegion *r;
 351     int cmd, i;
 352     uint32_t last_addr, new_addr, config_ofs;
 353
 354     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 355     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 356         r = &d->io_regions[i];
 357         if (i == PCI_ROM_SLOT) {
 358             config_ofs = 0x30;
 359         } else {
 360             config_ofs = 0x10 + i * 4;
 361         }
 362         if (r->size != 0) {
 363             if (r->type & PCI_ADDRESS_SPACE_IO) {
 364                 if (cmd & PCI_COMMAND_IO) {
 365                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 366                                                          config_ofs));
 367                     new_addr = new_addr & ~(r->size - 1);
 368                     last_addr = new_addr + r->size - 1;
 369                     /* NOTE: we have only 64K ioports on PC */
 370                     if (last_addr <= new_addr || new_addr == 0 ||
 371                         last_addr >= 0x10000) {
 372                         new_addr = -1;
 373                     }
 374                 } else {
 375                     new_addr = -1;
 376                 }
 377             } else {
 378                 if (cmd & PCI_COMMAND_MEMORY) {
 379                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 380                                                          config_ofs));
 381                     /* the ROM slot has a specific enable bit */
 382                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 383                         goto no_mem_map;
 384                     new_addr = new_addr & ~(r->size - 1);
 385                     last_addr = new_addr + r->size - 1;
 386                     /* NOTE: we do not support wrapping */
 387                     /* XXX: as we cannot support really dynamic
 388                        mappings, we handle specific values as invalid
 389                        mappings. */
 390                     if (last_addr <= new_addr || new_addr == 0 ||
 391                         last_addr == -1) {
 392                         new_addr = -1;
 393                     }
 394                 } else {
 395                 no_mem_map:
 396                     new_addr = -1;
 397                 }
 398             }
 399             /* now do the real mapping */
 400             if (new_addr != r->addr) {
 401                 if (r->addr != -1) {
 402                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 403                         int class;
 404                         /* NOTE: specific hack for IDE in PC case:
 405                            only one byte must be mapped. */
 406                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 407                         if (class == 0x0101 && r->size == 4) {
 408                             isa_unassign_ioport(r->addr + 2, 1);
 409                         } else {
 410                             isa_unassign_ioport(r->addr, r->size);
 411                         }
 412                     } else {
 413                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 414                                                      r->size,
 415                                                      IO_MEM_UNASSIGNED);
 416                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 417                     }
 418                 }
 419                 r->addr = new_addr;
 420                 if (r->addr != -1) {
 421                     r->map_func(d, i, r->addr, r->size, r->type);
 422                 }
 423             }
 424         }
 425     }
 426 }
 427
 428 uint32_t pci_default_read_config(PCIDevice *d,
 429                                  uint32_t address, int len)
 430 {
 431     uint32_t val;
 432
 433     switch(len) {
 434     default:
 435     case 4:
 436         if (address <= 0xfc) {
 437             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 438             break;
 439         }
 440         /* fall through */
 441     case 2:
 442         if (address <= 0xfe) {
 443             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 444             break;
 445         }
 446         /* fall through */
 447     case 1:
 448         val = d->config[address];
 449         break;
 450     }
 451     return val;
 452 }
 453
 454 void pci_default_write_config(PCIDevice *d,
 455                               uint32_t address, uint32_t val, int len)
 456 {
 457     int can_write, i;
 458     uint32_t end, addr;
 459
 460     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 461                      (address >= 0x30 && address < 0x34))) {
 462         PCIIORegion *r;
 463         int reg;
 464
 465         if ( address >= 0x30 ) {
 466             reg = PCI_ROM_SLOT;
 467         }else{
 468             reg = (address - 0x10) >> 2;
 469         }
 470         r = &d->io_regions[reg];
 471         if (r->size == 0)
 472             goto default_config;
 473         /* compute the stored value */
 474         if (reg == PCI_ROM_SLOT) {
 475             /* keep ROM enable bit */
 476             val &= (~(r->size - 1)) | 1;
 477         } else {
 478             val &= ~(r->size - 1);
 479             val |= r->type;
 480         }
 481         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 482         pci_update_mappings(d);
 483         return;
 484     }
 485  default_config:
 486     /* not efficient, but simple */
 487     addr = address;
 488     for(i = 0; i < len; i++) {
 489         /* default read/write accesses */
 490         switch(d->config[0x0e]) {
 491         case 0x00:
 492         case 0x80:
 493             switch(addr) {
 494             case 0x00:
 495             case 0x01:
 496             case 0x02:
 497             case 0x03:
 498             case 0x06:
 499             case 0x07:
 500             case 0x08:
 501             case 0x09:
 502             case 0x0a:
 503             case 0x0b:
 504             case 0x0e:
 505             case 0x10 ... 0x27: /* base */
 506             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 507             case 0x30 ... 0x33: /* rom */
 508             case 0x3d:
 509                 can_write = 0;
 510                 break;
 511             default:
 512                 can_write = 1;
 513                 break;
 514             }
 515             break;
 516         default:
 517         case 0x01:
 518             switch(addr) {
 519             case 0x00:
 520             case 0x01:
 521             case 0x02:
 522             case 0x03:
 523             case 0x06:
 524             case 0x07:
 525             case 0x08:
 526             case 0x09:
 527             case 0x0a:
 528             case 0x0b:
 529             case 0x0e:
 530             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 531             case 0x38 ... 0x3b: /* rom */
 532             case 0x3d:
 533                 can_write = 0;
 534                 break;
 535             default:
 536                 can_write = 1;
 537                 break;
 538             }
 539             break;
 540         }
 541         if (can_write) {
 542             /* Mask out writes to reserved bits in registers */
 543             switch (addr) {
 544             case 0x05:
 545                 val &= ~PCI_COMMAND_RESERVED_MASK_HI;
 546                 break;
 547             case 0x06:
 548                 val &= ~PCI_STATUS_RESERVED_MASK_LO;
 549                 break;
 550             case 0x07:
 551                 val &= ~PCI_STATUS_RESERVED_MASK_HI;
 552                 break;
 553             }
 554             d->config[addr] = val;
 555         }
 556         if (++addr > 0xff)
 557                 break;
 558         val >>= 8;
 559     }
 560
 561     end = address + len;
 562     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 563         /* if the command register is modified, we must modify the mappings */
 564         pci_update_mappings(d);
 565     }
 566 }
 567
 568 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 569 {
 570     PCIBus *s = opaque;
 571     PCIDevice *pci_dev;
 572     int config_addr, bus_num;
 573
 574 #if defined(DEBUG_PCI) && 0
 575     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 576            addr, val, len);
 577 #endif
 578     bus_num = (addr >> 16) & 0xff;
 579     while (s && s->bus_num != bus_num)
 580         s = s->next;
 581     if (!s)
 582         return;
 583     pci_dev = s->devices[(addr >> 8) & 0xff];
 584     if (!pci_dev)
 585         return;
 586     config_addr = addr & 0xff;
 587 #if defined(DEBUG_PCI)
 588     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 589            pci_dev->name, config_addr, val, len);
 590 #endif
 591     pci_dev->config_write(pci_dev, config_addr, val, len);
 592 }
 593
 594 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 595 {
 596     PCIBus *s = opaque;
 597     PCIDevice *pci_dev;
 598     int config_addr, bus_num;
 599     uint32_t val;
 600
 601     bus_num = (addr >> 16) & 0xff;
 602     while (s && s->bus_num != bus_num)
 603         s= s->next;
 604     if (!s)
 605         goto fail;
 606     pci_dev = s->devices[(addr >> 8) & 0xff];
 607     if (!pci_dev) {
 608     fail:
 609         switch(len) {
 610         case 1:
 611             val = 0xff;
 612             break;
 613         case 2:
 614             val = 0xffff;
 615             break;
 616         default:
 617         case 4:
 618             val = 0xffffffff;
 619             break;
 620         }
 621         goto the_end;
 622     }
 623     config_addr = addr & 0xff;
 624     val = pci_dev->config_read(pci_dev, config_addr, len);
 625 #if defined(DEBUG_PCI)
 626     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 627            pci_dev->name, config_addr, val, len);
 628 #endif
 629  the_end:
 630 #if defined(DEBUG_PCI) && 0
 631     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 632            addr, val, len);
 633 #endif
 634     return val;
 635 }
 636
 637 /***********************************************************/
 638 /* generic PCI irq support */
 639
 640 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 641 static void pci_set_irq(void *opaque, int irq_num, int level)
 642 {
 643     PCIDevice *pci_dev = (PCIDevice *)opaque;
 644     PCIBus *bus;
 645     int change;
 646
 647     change = level - pci_dev->irq_state[irq_num];
 648     if (!change)
 649         return;
 650
 651     pci_dev->irq_state[irq_num] = level;
 652     for (;;) {
 653         bus = pci_dev->bus;
 654         irq_num = bus->map_irq(pci_dev, irq_num);
 655         if (bus->set_irq)
 656             break;
 657         pci_dev = bus->parent_dev;
 658     }
 659     bus->irq_count[irq_num] += change;
 660     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 661 }
 662
 663 /***********************************************************/
 664 /* monitor info on PCI */
 665
 666 typedef struct {
 667     uint16_t class;
 668     const char *desc;
 669 } pci_class_desc;
 670
 671 static const pci_class_desc pci_class_descriptions[] =
 672 {
 673     { 0x0100, "SCSI controller"},
 674     { 0x0101, "IDE controller"},
 675     { 0x0102, "Floppy controller"},
 676     { 0x0103, "IPI controller"},
 677     { 0x0104, "RAID controller"},
 678     { 0x0106, "SATA controller"},
 679     { 0x0107, "SAS controller"},
 680     { 0x0180, "Storage controller"},
 681     { 0x0200, "Ethernet controller"},
 682     { 0x0201, "Token Ring controller"},
 683     { 0x0202, "FDDI controller"},
 684     { 0x0203, "ATM controller"},
 685     { 0x0280, "Network controller"},
 686     { 0x0300, "VGA controller"},
 687     { 0x0301, "XGA controller"},
 688     { 0x0302, "3D controller"},
 689     { 0x0380, "Display controller"},
 690     { 0x0400, "Video controller"},
 691     { 0x0401, "Audio controller"},
 692     { 0x0402, "Phone"},
 693     { 0x0480, "Multimedia controller"},
 694     { 0x0500, "RAM controller"},
 695     { 0x0501, "Flash controller"},
 696     { 0x0580, "Memory controller"},
 697     { 0x0600, "Host bridge"},
 698     { 0x0601, "ISA bridge"},
 699     { 0x0602, "EISA bridge"},
 700     { 0x0603, "MC bridge"},
 701     { 0x0604, "PCI bridge"},
 702     { 0x0605, "PCMCIA bridge"},
 703     { 0x0606, "NUBUS bridge"},
 704     { 0x0607, "CARDBUS bridge"},
 705     { 0x0608, "RACEWAY bridge"},
 706     { 0x0680, "Bridge"},
 707     { 0x0c03, "USB controller"},
 708     { 0, NULL}
 709 };
 710
 711 static void pci_info_device(PCIDevice *d)
 712 {
 713     Monitor *mon = cur_mon;
 714     int i, class;
 715     PCIIORegion *r;
 716     const pci_class_desc *desc;
 717
 718     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 719                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 720     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 721     monitor_printf(mon, "    ");
 722     desc = pci_class_descriptions;
 723     while (desc->desc && class != desc->class)
 724         desc++;
 725     if (desc->desc) {
 726         monitor_printf(mon, "%s", desc->desc);
 727     } else {
 728         monitor_printf(mon, "Class %04x", class);
 729     }
 730     monitor_printf(mon, ": PCI device %04x:%04x\n",
 731            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 732            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 733
 734     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 735         monitor_printf(mon, "      IRQ %d.\n",
 736                        d->config[PCI_INTERRUPT_LINE]);
 737     }
 738     if (class == 0x0604) {
 739         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 740     }
 741     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 742         r = &d->io_regions[i];
 743         if (r->size != 0) {
 744             monitor_printf(mon, "      BAR%d: ", i);
 745             if (r->type & PCI_ADDRESS_SPACE_IO) {
 746                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 747                                r->addr, r->addr + r->size - 1);
 748             } else {
 749                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 750                                r->addr, r->addr + r->size - 1);
 751             }
 752         }
 753     }
 754     if (class == 0x0604 && d->config[0x19] != 0) {
 755         pci_for_each_device(d->config[0x19], pci_info_device);
 756     }
 757 }
 758
 759 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 760 {
 761     PCIBus *bus = first_bus;
 762     PCIDevice *d;
 763     int devfn;
 764
 765     while (bus && bus->bus_num != bus_num)
 766         bus = bus->next;
 767     if (bus) {
 768         for(devfn = 0; devfn < 256; devfn++) {
 769             d = bus->devices[devfn];
 770             if (d)
 771                 fn(d);
 772         }
 773     }
 774 }
 775
 776 void pci_info(Monitor *mon)
 777 {
 778     pci_for_each_device(0, pci_info_device);
 779 }
 780
 781 static const char * const pci_nic_models[] = {
 782     "ne2k_pci",
 783     "i82551",
 784     "i82557b",
 785     "i82559er",
 786     "rtl8139",
 787     "e1000",
 788     "pcnet",
 789     "virtio",
 790     NULL
 791 };
 792
 793 typedef PCIDevice *(*PCINICInitFn)(PCIBus *, NICInfo *, int);
 794
 795 static PCINICInitFn pci_nic_init_fns[] = {
 796     pci_ne2000_init,
 797     pci_i82551_init,
 798     pci_i82557b_init,
 799     pci_i82559er_init,
 800     pci_rtl8139_init,
 801     pci_e1000_init,
 802     pci_pcnet_init,
 803     virtio_net_init,
 804     NULL
 805 };
 806
 807 /* Initialize a PCI NIC.  */
 808 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 809                   const char *default_model)
 810 {
 811     PCIDevice *pci_dev;
 812     int i;
 813
 814     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 815
 816     for (i = 0; pci_nic_models[i]; i++)
 817         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 818             pci_dev = pci_nic_init_fns[i](bus, nd, devfn);
 819             if (pci_dev)
 820                 nd->private = pci_dev;
 821             return pci_dev;
 822         }
 823
 824     return NULL;
 825 }
 826
 827 typedef struct {
 828     PCIDevice dev;
 829     PCIBus *bus;
 830 } PCIBridge;
 831
 832 static void pci_bridge_write_config(PCIDevice *d,
 833                              uint32_t address, uint32_t val, int len)
 834 {
 835     PCIBridge *s = (PCIBridge *)d;
 836
 837     if (address == 0x19 || (address == 0x18 && len > 1)) {
 838         if (address == 0x19)
 839             s->bus->bus_num = val & 0xff;
 840         else
 841             s->bus->bus_num = (val >> 8) & 0xff;
 842 #if defined(DEBUG_PCI)
 843         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 844 #endif
 845     }
 846     pci_default_write_config(d, address, val, len);
 847 }
 848
 849 PCIBus *pci_find_bus(int bus_num)
 850 {
 851     PCIBus *bus = first_bus;
 852
 853     while (bus && bus->bus_num != bus_num)
 854         bus = bus->next;
 855
 856     return bus;
 857 }
 858
 859 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 860 {
 861     PCIBus *bus = pci_find_bus(bus_num);
 862
 863     if (!bus)
 864         return NULL;
 865
 866     return bus->devices[PCI_DEVFN(slot, function)];
 867 }
 868
 869 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 870                         pci_map_irq_fn map_irq, const char *name)
 871 {
 872     PCIBridge *s;
 873     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 874                                          devfn, NULL, pci_bridge_write_config);
 875
 876     pci_config_set_vendor_id(s->dev.config, vid);
 877     pci_config_set_device_id(s->dev.config, did);
 878
 879     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 880     s->dev.config[0x05] = 0x00;
 881     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 882     s->dev.config[0x07] = 0x00; // status = fast devsel
 883     s->dev.config[0x08] = 0x00; // revision
 884     s->dev.config[0x09] = 0x00; // programming i/f
 885     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 886     s->dev.config[0x0D] = 0x10; // latency_timer
 887     s->dev.config[PCI_HEADER_TYPE] =
 888         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 889     s->dev.config[0x1E] = 0xa0; // secondary status
 890
 891     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 892     return s->bus;
 893 }