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Avoid clobbering input/aliased registers in !SOFTMMU+64bit+bswap case
[qemu/mini2440.git] / tcg / ppc64 / tcg-target.c
blobf79459da273b558b6be1fc749934c2022f2b6905
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #define TCG_CT_CONST_U32 0x100
26
27 static uint8_t *tb_ret_addr;
28
29 #define FAST_PATH
30
31 #if TARGET_PHYS_ADDR_BITS == 32
32 #define LD_ADDEND LWZ
33 #else
34 #define LD_ADDEND LD
35 #endif
36
37 #if TARGET_LONG_BITS == 32
38 #define LD_ADDR LWZU
39 #define CMP_L 0
40 #else
41 #define LD_ADDR LDU
42 #define CMP_L (1<<21)
43 #endif
44
45 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 "r0",
47 "r1",
48 "rp",
49 "r3",
50 "r4",
51 "r5",
52 "r6",
53 "r7",
54 "r8",
55 "r9",
56 "r10",
57 "r11",
58 "r12",
59 "r13",
60 "r14",
61 "r15",
62 "r16",
63 "r17",
64 "r18",
65 "r19",
66 "r20",
67 "r21",
68 "r22",
69 "r23",
70 "r24",
71 "r25",
72 "r26",
73 "r27",
74 "r28",
75 "r29",
76 "r30",
77 "r31"
78 };
79
80 static const int tcg_target_reg_alloc_order[] = {
81 TCG_REG_R14,
82 TCG_REG_R15,
83 TCG_REG_R16,
84 TCG_REG_R17,
85 TCG_REG_R18,
86 TCG_REG_R19,
87 TCG_REG_R20,
88 TCG_REG_R21,
89 TCG_REG_R22,
90 TCG_REG_R23,
91 TCG_REG_R28,
92 TCG_REG_R29,
93 TCG_REG_R30,
94 TCG_REG_R31,
95 TCG_REG_R3,
96 TCG_REG_R4,
97 TCG_REG_R5,
98 TCG_REG_R6,
99 TCG_REG_R7,
100 TCG_REG_R8,
101 TCG_REG_R9,
102 TCG_REG_R10,
103 TCG_REG_R11,
104 TCG_REG_R12,
105 TCG_REG_R13,
106 TCG_REG_R0,
107 TCG_REG_R1,
108 TCG_REG_R2,
109 TCG_REG_R24,
110 TCG_REG_R25,
111 TCG_REG_R26,
112 TCG_REG_R27
113 };
114
115 static const int tcg_target_call_iarg_regs[] = {
116 TCG_REG_R3,
117 TCG_REG_R4,
118 TCG_REG_R5,
119 TCG_REG_R6,
120 TCG_REG_R7,
121 TCG_REG_R8,
122 TCG_REG_R9,
123 TCG_REG_R10
124 };
125
126 static const int tcg_target_call_oarg_regs[2] = {
127 TCG_REG_R3
128 };
129
130 static const int tcg_target_callee_save_regs[] = {
131 TCG_REG_R14,
132 TCG_REG_R15,
133 TCG_REG_R16,
134 TCG_REG_R17,
135 TCG_REG_R18,
136 TCG_REG_R19,
137 TCG_REG_R20,
138 TCG_REG_R21,
139 TCG_REG_R22,
140 TCG_REG_R23,
141 TCG_REG_R28,
142 TCG_REG_R29,
143 TCG_REG_R30,
144 TCG_REG_R31
145 };
146
147 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
148 {
149 tcg_target_long disp;
150
151 disp = target - (tcg_target_long) pc;
152 if ((disp << 38) >> 38 != disp)
153 tcg_abort ();
154
155 return disp & 0x3fffffc;
156 }
157
158 static void reloc_pc24 (void *pc, tcg_target_long target)
159 {
160 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
161 | reloc_pc24_val (pc, target);
162 }
163
164 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
165 {
166 tcg_target_long disp;
167
168 disp = target - (tcg_target_long) pc;
169 if (disp != (int16_t) disp)
170 tcg_abort ();
171
172 return disp & 0xfffc;
173 }
174
175 static void reloc_pc14 (void *pc, tcg_target_long target)
176 {
177 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
178 | reloc_pc14_val (pc, target);
179 }
180
181 static void patch_reloc (uint8_t *code_ptr, int type,
182 tcg_target_long value, tcg_target_long addend)
183 {
184 value += addend;
185 switch (type) {
186 case R_PPC_REL14:
187 reloc_pc14 (code_ptr, value);
188 break;
189 case R_PPC_REL24:
190 reloc_pc24 (code_ptr, value);
191 break;
192 default:
193 tcg_abort ();
194 }
195 }
196
197 /* maximum number of register used for input function arguments */
198 static int tcg_target_get_call_iarg_regs_count (int flags)
199 {
200 return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]);
201 }
202
203 /* parse target specific constraints */
204 static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
205 {
206 const char *ct_str;
207
208 ct_str = *pct_str;
209 switch (ct_str[0]) {
210 case 'A': case 'B': case 'C': case 'D':
211 ct->ct |= TCG_CT_REG;
212 tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A');
213 break;
214 case 'r':
215 ct->ct |= TCG_CT_REG;
216 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
217 break;
218 case 'L': /* qemu_ld constraint */
219 ct->ct |= TCG_CT_REG;
220 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
221 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
222 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
223 break;
224 case 'S': /* qemu_st constraint */
225 ct->ct |= TCG_CT_REG;
226 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
227 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
228 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
229 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
230 break;
231 case 'Z':
232 ct->ct |= TCG_CT_CONST_U32;
233 break;
234 default:
235 return -1;
236 }
237 ct_str++;
238 *pct_str = ct_str;
239 return 0;
240 }
241
242 /* test if a constant matches the constraint */
243 static int tcg_target_const_match (tcg_target_long val,
244 const TCGArgConstraint *arg_ct)
245 {
246 int ct;
247
248 ct = arg_ct->ct;
249 if (ct & TCG_CT_CONST)
250 return 1;
251 else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val))
252 return 1;
253 return 0;
254 }
255
256 #define OPCD(opc) ((opc)<<26)
257 #define XO19(opc) (OPCD(19)|((opc)<<1))
258 #define XO30(opc) (OPCD(30)|((opc)<<2))
259 #define XO31(opc) (OPCD(31)|((opc)<<1))
260 #define XO58(opc) (OPCD(58)|(opc))
261 #define XO62(opc) (OPCD(62)|(opc))
262
263 #define B OPCD( 18)
264 #define BC OPCD( 16)
265 #define LBZ OPCD( 34)
266 #define LHZ OPCD( 40)
267 #define LHA OPCD( 42)
268 #define LWZ OPCD( 32)
269 #define STB OPCD( 38)
270 #define STH OPCD( 44)
271 #define STW OPCD( 36)
272
273 #define STD XO62( 0)
274 #define STDU XO62( 1)
275 #define STDX XO31(149)
276
277 #define LD XO58( 0)
278 #define LDX XO31( 21)
279 #define LDU XO58( 1)
280 #define LWA XO58( 2)
281 #define LWAX XO31(341)
282
283 #define ADDI OPCD( 14)
284 #define ADDIS OPCD( 15)
285 #define ORI OPCD( 24)
286 #define ORIS OPCD( 25)
287 #define XORI OPCD( 26)
288 #define XORIS OPCD( 27)
289 #define ANDI OPCD( 28)
290 #define ANDIS OPCD( 29)
291 #define MULLI OPCD( 7)
292 #define CMPLI OPCD( 10)
293 #define CMPI OPCD( 11)
294
295 #define LWZU OPCD( 33)
296 #define STWU OPCD( 37)
297
298 #define RLWINM OPCD( 21)
299
300 #define RLDICL XO30( 0)
301 #define RLDICR XO30( 1)
302
303 #define BCLR XO19( 16)
304 #define BCCTR XO19(528)
305 #define CRAND XO19(257)
306 #define CRANDC XO19(129)
307 #define CRNAND XO19(225)
308 #define CROR XO19(449)
309
310 #define EXTSB XO31(954)
311 #define EXTSH XO31(922)
312 #define EXTSW XO31(986)
313 #define ADD XO31(266)
314 #define ADDE XO31(138)
315 #define ADDC XO31( 10)
316 #define AND XO31( 28)
317 #define SUBF XO31( 40)
318 #define SUBFC XO31( 8)
319 #define SUBFE XO31(136)
320 #define OR XO31(444)
321 #define XOR XO31(316)
322 #define MULLW XO31(235)
323 #define MULHWU XO31( 11)
324 #define DIVW XO31(491)
325 #define DIVWU XO31(459)
326 #define CMP XO31( 0)
327 #define CMPL XO31( 32)
328 #define LHBRX XO31(790)
329 #define LWBRX XO31(534)
330 #define STHBRX XO31(918)
331 #define STWBRX XO31(662)
332 #define MFSPR XO31(339)
333 #define MTSPR XO31(467)
334 #define SRAWI XO31(824)
335 #define NEG XO31(104)
336
337 #define MULLD XO31(233)
338 #define MULHD XO31( 73)
339 #define MULHDU XO31( 9)
340 #define DIVD XO31(489)
341 #define DIVDU XO31(457)
342
343 #define LBZX XO31( 87)
344 #define LHZX XO31(276)
345 #define LHAX XO31(343)
346 #define LWZX XO31( 23)
347 #define STBX XO31(215)
348 #define STHX XO31(407)
349 #define STWX XO31(151)
350
351 #define SPR(a,b) ((((a)<<5)|(b))<<11)
352 #define LR SPR(8, 0)
353 #define CTR SPR(9, 0)
354
355 #define SLW XO31( 24)
356 #define SRW XO31(536)
357 #define SRAW XO31(792)
358
359 #define SLD XO31( 27)
360 #define SRD XO31(539)
361 #define SRAD XO31(794)
362 #define SRADI XO31(413<<1)
363
364 #define LMW OPCD( 46)
365 #define STMW OPCD( 47)
366
367 #define TW XO31( 4)
368 #define TRAP (TW | TO (31))
369
370 #define RT(r) ((r)<<21)
371 #define RS(r) ((r)<<21)
372 #define RA(r) ((r)<<16)
373 #define RB(r) ((r)<<11)
374 #define TO(t) ((t)<<21)
375 #define SH(s) ((s)<<11)
376 #define MB(b) ((b)<<6)
377 #define ME(e) ((e)<<1)
378 #define BO(o) ((o)<<21)
379 #define MB64(b) ((b)<<5)
380
381 #define LK 1
382
383 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
384 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
385
386 #define BF(n) ((n)<<23)
387 #define BI(n, c) (((c)+((n)*4))<<16)
388 #define BT(n, c) (((c)+((n)*4))<<21)
389 #define BA(n, c) (((c)+((n)*4))<<16)
390 #define BB(n, c) (((c)+((n)*4))<<11)
391
392 #define BO_COND_TRUE BO (12)
393 #define BO_COND_FALSE BO ( 4)
394 #define BO_ALWAYS BO (20)
395
396 enum {
397 CR_LT,
398 CR_GT,
399 CR_EQ,
400 CR_SO
401 };
402
403 static const uint32_t tcg_to_bc[10] = {
404 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
405 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
406 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
407 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
408 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
409 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
410 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
411 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
412 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
413 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
414 };
415
416 static void tcg_out_mov (TCGContext *s, int ret, int arg)
417 {
418 tcg_out32 (s, OR | SAB (arg, ret, arg));
419 }
420
421 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
422 {
423 sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
424 mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f));
425 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
426 }
427
428 static void tcg_out_movi32 (TCGContext *s, int ret, int32_t arg)
429 {
430 if (arg == (int16_t) arg)
431 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
432 else {
433 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
434 if (arg & 0xffff)
435 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
436 }
437 }
438
439 static void tcg_out_movi (TCGContext *s, TCGType type,
440 int ret, tcg_target_long arg)
441 {
442 int32_t arg32 = arg;
443
444 if (type == TCG_TYPE_I32 || arg == arg32) {
445 tcg_out_movi32 (s, ret, arg32);
446 }
447 else {
448 if ((uint64_t) arg >> 32) {
449 uint16_t h16 = arg >> 16;
450 uint16_t l16 = arg;
451
452 tcg_out_movi32 (s, ret, arg >> 32);
453 tcg_out_rld (s, RLDICR, ret, ret, 32, 31);
454 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
455 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
456 }
457 else {
458 tcg_out_movi32 (s, ret, arg32);
459 if (arg32 < 0)
460 tcg_out_rld (s, RLDICL, ret, ret, 0, 32);
461 }
462 }
463 }
464
465 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
466 {
467 int reg;
468
469 if (const_arg) {
470 reg = 2;
471 tcg_out_movi (s, TCG_TYPE_I64, reg, arg);
472 }
473 else reg = arg;
474
475 tcg_out32 (s, LD | RT (0) | RA (reg));
476 tcg_out32 (s, MTSPR | RA (0) | CTR);
477 tcg_out32 (s, LD | RT (11) | RA (reg) | 16);
478 tcg_out32 (s, LD | RT (2) | RA (reg) | 8);
479 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
480 }
481
482 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
483 int offset, int op1, int op2)
484 {
485 if (offset == (int16_t) offset)
486 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
487 else {
488 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
489 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
490 }
491 }
492
493 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
494 {
495 tcg_target_long disp;
496
497 disp = target - (tcg_target_long) s->code_ptr;
498 if ((disp << 38) >> 38 == disp)
499 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
500 else {
501 tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
502 tcg_out32 (s, MTSPR | RS (0) | CTR);
503 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
504 }
505 }
506
507 #if defined (CONFIG_SOFTMMU)
508 extern void __ldb_mmu(void);
509 extern void __ldw_mmu(void);
510 extern void __ldl_mmu(void);
511 extern void __ldq_mmu(void);
512
513 extern void __stb_mmu(void);
514 extern void __stw_mmu(void);
515 extern void __stl_mmu(void);
516 extern void __stq_mmu(void);
517
518 static void *qemu_ld_helpers[4] = {
519 __ldb_mmu,
520 __ldw_mmu,
521 __ldl_mmu,
522 __ldq_mmu,
523 };
524
525 static void *qemu_st_helpers[4] = {
526 __stb_mmu,
527 __stw_mmu,
528 __stl_mmu,
529 __stq_mmu,
530 };
531
532 static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
533 int addr_reg, int s_bits, int offset)
534 {
535 #if TARGET_LONG_BITS == 32
536 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
537
538 tcg_out32 (s, (RLWINM
539 | RA (r0)
540 | RS (addr_reg)
541 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
542 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
543 | ME (31 - CPU_TLB_ENTRY_BITS)
544 )
545 );
546 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
547 tcg_out32 (s, (LWZU | RT (r1) | RA (r0) | offset));
548 tcg_out32 (s, (RLWINM
549 | RA (r2)
550 | RS (addr_reg)
551 | SH (0)
552 | MB ((32 - s_bits) & 31)
553 | ME (31 - TARGET_PAGE_BITS)
554 )
555 );
556 #else
557 tcg_out_rld (s, RLDICL, r0, addr_reg,
558 64 - TARGET_PAGE_BITS,
559 64 - CPU_TLB_BITS);
560 tcg_out_rld (s, RLDICR, r0, r0,
561 CPU_TLB_ENTRY_BITS,
562 63 - CPU_TLB_ENTRY_BITS);
563
564 tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
565 tcg_out32 (s, LD_ADDR | RT (r1) | RA (r0) | offset);
566
567 if (!s_bits) {
568 tcg_out_rld (s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS);
569 }
570 else {
571 tcg_out_rld (s, RLDICL, r2, addr_reg,
572 64 - TARGET_PAGE_BITS,
573 TARGET_PAGE_BITS - s_bits);
574 tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
575 }
576 #endif
577 }
578 #endif
579
580 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
581 {
582 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap;
583 #ifdef CONFIG_SOFTMMU
584 int r2;
585 void *label1_ptr, *label2_ptr;
586 #endif
587
588 data_reg = *args++;
589 addr_reg = *args++;
590 mem_index = *args;
591 s_bits = opc & 3;
592
593 #ifdef CONFIG_SOFTMMU
594 r0 = 3;
595 r1 = 4;
596 r2 = 0;
597
598 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits,
599 offsetof (CPUState, tlb_table[mem_index][0].addr_read));
600
601 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
602
603 label1_ptr = s->code_ptr;
604 #ifdef FAST_PATH
605 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
606 #endif
607
608 /* slow path */
609 tcg_out_mov (s, 3, addr_reg);
610 tcg_out_movi (s, TCG_TYPE_I64, 4, mem_index);
611
612 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
613
614 switch (opc) {
615 case 0|4:
616 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
617 break;
618 case 1|4:
619 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
620 break;
621 case 2|4:
622 tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
623 break;
624 case 0:
625 case 1:
626 case 2:
627 case 3:
628 if (data_reg != 3)
629 tcg_out_mov (s, data_reg, 3);
630 break;
631 }
632 label2_ptr = s->code_ptr;
633 tcg_out32 (s, B);
634
635 /* label1: fast path */
636 #ifdef FAST_PATH
637 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
638 #endif
639
640 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
641 tcg_out32 (s, (LD_ADDEND
642 | RT (r0)
643 | RA (r0)
644 | (offsetof (CPUTLBEntry, addend)
645 - offsetof (CPUTLBEntry, addr_read))
646 ));
647 /* r0 = env->tlb_table[mem_index][index].addend */
648 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
649 /* r0 = env->tlb_table[mem_index][index].addend + addr */
650
651 #else /* !CONFIG_SOFTMMU */
652 #if TARGET_LONG_BITS == 32
653 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
654 #endif
655 r0 = addr_reg;
656 r1 = 4;
657 #endif
658
659 #ifdef TARGET_WORDS_BIGENDIAN
660 bswap = 0;
661 #else
662 bswap = 1;
663 #endif
664 switch (opc) {
665 default:
666 case 0:
667 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
668 break;
669 case 0|4:
670 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
671 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
672 break;
673 case 1:
674 if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
675 else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
676 break;
677 case 1|4:
678 if (bswap) {
679 tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
680 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
681 }
682 else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
683 break;
684 case 2:
685 if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
686 else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
687 break;
688 case 2|4:
689 if (bswap) {
690 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
691 tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg));
692 }
693 else tcg_out32 (s, LWA | RT (data_reg)| RA (r0));
694 break;
695 case 3:
696 if (bswap) {
697 tcg_out32 (s, LWBRX | RT (0) | RB (r0));
698 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
699 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r1));
700 tcg_out_rld (s, RLDICR, data_reg, data_reg, 32, 31);
701 tcg_out32 (s, OR | SAB (0, data_reg, data_reg));
702 }
703 else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
704 break;
705 }
706
707 #ifdef CONFIG_SOFTMMU
708 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
709 #endif
710 }
711
712 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
713 {
714 int addr_reg, r0, r1, data_reg, mem_index, bswap;
715 #ifdef CONFIG_SOFTMMU
716 int r2;
717 void *label1_ptr, *label2_ptr;
718 #endif
719
720 data_reg = *args++;
721 addr_reg = *args++;
722 mem_index = *args;
723
724 #ifdef CONFIG_SOFTMMU
725 r0 = 3;
726 r1 = 4;
727 r2 = 0;
728
729 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc,
730 offsetof (CPUState, tlb_table[mem_index][0].addr_write));
731
732 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
733
734 label1_ptr = s->code_ptr;
735 #ifdef FAST_PATH
736 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
737 #endif
738
739 /* slow path */
740 tcg_out_mov (s, 3, addr_reg);
741 tcg_out_rld (s, RLDICL, 4, data_reg, 0, 64 - (1 << (3 + opc)));
742 tcg_out_movi (s, TCG_TYPE_I64, 5, mem_index);
743
744 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
745
746 label2_ptr = s->code_ptr;
747 tcg_out32 (s, B);
748
749 /* label1: fast path */
750 #ifdef FAST_PATH
751 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
752 #endif
753
754 tcg_out32 (s, (LD_ADDEND
755 | RT (r0)
756 | RA (r0)
757 | (offsetof (CPUTLBEntry, addend)
758 - offsetof (CPUTLBEntry, addr_write))
759 ));
760 /* r0 = env->tlb_table[mem_index][index].addend */
761 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
762 /* r0 = env->tlb_table[mem_index][index].addend + addr */
763
764 #else /* !CONFIG_SOFTMMU */
765 #if TARGET_LONG_BITS == 32
766 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
767 #endif
768 r1 = 4;
769 r0 = addr_reg;
770 #endif
771
772 #ifdef TARGET_WORDS_BIGENDIAN
773 bswap = 0;
774 #else
775 bswap = 1;
776 #endif
777 switch (opc) {
778 case 0:
779 tcg_out32 (s, STB | RS (data_reg) | RA (r0));
780 break;
781 case 1:
782 if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
783 else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
784 break;
785 case 2:
786 if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
787 else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
788 break;
789 case 3:
790 if (bswap) {
791 tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
792 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
793 tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0);
794 tcg_out32 (s, STWBRX | RS (0) | RA (0) | RB (r1));
795 }
796 else tcg_out32 (s, STD | RS (data_reg) | RA (r0));
797 break;
798 }
799
800 #ifdef CONFIG_SOFTMMU
801 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
802 #endif
803 }
804
805 void tcg_target_qemu_prologue (TCGContext *s)
806 {
807 int i, frame_size;
808 uint64_t addr;
809
810 frame_size = 0
811 + 8 /* back chain */
812 + 8 /* CR */
813 + 8 /* LR */
814 + 8 /* compiler doubleword */
815 + 8 /* link editor doubleword */
816 + 8 /* TOC save area */
817 + TCG_STATIC_CALL_ARGS_SIZE
818 + ARRAY_SIZE (tcg_target_callee_save_regs) * 8
819 ;
820 frame_size = (frame_size + 15) & ~15;
821
822 /* First emit adhoc function descriptor */
823 addr = (uint64_t) s->code_ptr + 24;
824 tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */
825 s->code_ptr += 16; /* skip TOC and environment pointer */
826
827 /* Prologue */
828 tcg_out32 (s, MFSPR | RT (0) | LR);
829 tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff));
830 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
831 tcg_out32 (s, (STD
832 | RS (tcg_target_callee_save_regs[i])
833 | RA (1)
834 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
835 )
836 );
837 tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16));
838
839 tcg_out32 (s, MTSPR | RS (3) | CTR);
840 tcg_out32 (s, BCCTR | BO_ALWAYS);
841
842 /* Epilogue */
843 tb_ret_addr = s->code_ptr;
844
845 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
846 tcg_out32 (s, (LD
847 | RT (tcg_target_callee_save_regs[i])
848 | RA (1)
849 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
850 )
851 );
852 tcg_out32 (s, LD | RT (0) | RA (1) | (frame_size + 16));
853 tcg_out32 (s, MTSPR | RS (0) | LR);
854 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
855 tcg_out32 (s, BCLR | BO_ALWAYS);
856 }
857
858 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
859 tcg_target_long arg2)
860 {
861 if (type == TCG_TYPE_I32)
862 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
863 else
864 tcg_out_ldst (s, ret, arg1, arg2, LD, LDX);
865 }
866
867 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
868 tcg_target_long arg2)
869 {
870 if (type == TCG_TYPE_I32)
871 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
872 else
873 tcg_out_ldst (s, arg, arg1, arg2, STD, STDX);
874 }
875
876 static void ppc_addi32 (TCGContext *s, int rt, int ra, tcg_target_long si)
877 {
878 if (!si && rt == ra)
879 return;
880
881 if (si == (int16_t) si)
882 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
883 else {
884 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
885 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
886 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
887 }
888 }
889
890 static void ppc_addi64 (TCGContext *s, int rt, int ra, tcg_target_long si)
891 {
892 /* XXX: suboptimal */
893 if (si == (int16_t) si
894 || (((uint64_t) si >> 31) == 0) && (si & 0x8000) == 0)
895 ppc_addi32 (s, rt, ra, si);
896 else {
897 tcg_out_movi (s, TCG_TYPE_I64, 0, si);
898 tcg_out32 (s, ADD | RT (rt) | RA (ra));
899 }
900 }
901
902 static void tcg_out_addi (TCGContext *s, int reg, tcg_target_long val)
903 {
904 ppc_addi64 (s, reg, reg, val);
905 }
906
907 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
908 int const_arg2, int cr, int arch64)
909 {
910 int imm;
911 uint32_t op;
912
913 switch (cond) {
914 case TCG_COND_EQ:
915 case TCG_COND_NE:
916 if (const_arg2) {
917 if ((int16_t) arg2 == arg2) {
918 op = CMPI;
919 imm = 1;
920 break;
921 }
922 else if ((uint16_t) arg2 == arg2) {
923 op = CMPLI;
924 imm = 1;
925 break;
926 }
927 }
928 op = CMPL;
929 imm = 0;
930 break;
931
932 case TCG_COND_LT:
933 case TCG_COND_GE:
934 case TCG_COND_LE:
935 case TCG_COND_GT:
936 if (const_arg2) {
937 if ((int16_t) arg2 == arg2) {
938 op = CMPI;
939 imm = 1;
940 break;
941 }
942 }
943 op = CMP;
944 imm = 0;
945 break;
946
947 case TCG_COND_LTU:
948 case TCG_COND_GEU:
949 case TCG_COND_LEU:
950 case TCG_COND_GTU:
951 if (const_arg2) {
952 if ((uint16_t) arg2 == arg2) {
953 op = CMPLI;
954 imm = 1;
955 break;
956 }
957 }
958 op = CMPL;
959 imm = 0;
960 break;
961
962 default:
963 tcg_abort ();
964 }
965 op |= BF (cr) | (arch64 << 21);
966
967 if (imm)
968 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
969 else {
970 if (const_arg2) {
971 tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
972 tcg_out32 (s, op | RA (arg1) | RB (0));
973 }
974 else
975 tcg_out32 (s, op | RA (arg1) | RB (arg2));
976 }
977
978 }
979
980 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
981 {
982 TCGLabel *l = &s->labels[label_index];
983
984 if (l->has_value)
985 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
986 else {
987 uint16_t val = *(uint16_t *) &s->code_ptr[2];
988
989 /* Thanks to Andrzej Zaborowski */
990 tcg_out32 (s, bc | (val & 0xfffc));
991 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
992 }
993 }
994
995 static void tcg_out_brcond (TCGContext *s, int cond,
996 TCGArg arg1, TCGArg arg2, int const_arg2,
997 int label_index, int arch64)
998 {
999 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, arch64);
1000 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1001 }
1002
1003 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1004 {
1005 TCGContext s;
1006 unsigned long patch_size;
1007
1008 s.code_ptr = (uint8_t *) jmp_addr;
1009 tcg_out_b (&s, 0, addr);
1010 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
1011 flush_icache_range (jmp_addr, jmp_addr + patch_size);
1012 }
1013
1014 static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
1015 const int *const_args)
1016 {
1017 int c;
1018
1019 switch (opc) {
1020 case INDEX_op_exit_tb:
1021 tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1022 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1023 break;
1024 case INDEX_op_goto_tb:
1025 if (s->tb_jmp_offset) {
1026 /* direct jump method */
1027
1028 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1029 s->code_ptr += 28;
1030 }
1031 else {
1032 tcg_abort ();
1033 }
1034 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1035 break;
1036 case INDEX_op_br:
1037 {
1038 TCGLabel *l = &s->labels[args[0]];
1039
1040 if (l->has_value) {
1041 tcg_out_b (s, 0, l->u.value);
1042 }
1043 else {
1044 uint32_t val = *(uint32_t *) s->code_ptr;
1045
1046 /* Thanks to Andrzej Zaborowski */
1047 tcg_out32 (s, B | (val & 0x3fffffc));
1048 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1049 }
1050 }
1051 break;
1052 case INDEX_op_call:
1053 tcg_out_call (s, args[0], const_args[0]);
1054 break;
1055 case INDEX_op_jmp:
1056 if (const_args[0]) {
1057 tcg_out_b (s, 0, args[0]);
1058 }
1059 else {
1060 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1061 tcg_out32 (s, BCCTR | BO_ALWAYS);
1062 }
1063 break;
1064 case INDEX_op_movi_i32:
1065 tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
1066 break;
1067 case INDEX_op_movi_i64:
1068 tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]);
1069 break;
1070 case INDEX_op_ld8u_i32:
1071 case INDEX_op_ld8u_i64:
1072 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1073 break;
1074 case INDEX_op_ld8s_i32:
1075 case INDEX_op_ld8s_i64:
1076 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1077 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1078 break;
1079 case INDEX_op_ld16u_i32:
1080 case INDEX_op_ld16u_i64:
1081 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1082 break;
1083 case INDEX_op_ld16s_i32:
1084 case INDEX_op_ld16s_i64:
1085 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1086 break;
1087 case INDEX_op_ld_i32:
1088 case INDEX_op_ld32u_i64:
1089 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1090 break;
1091 case INDEX_op_ld32s_i64:
1092 tcg_out_ldst (s, args[0], args[1], args[2], LWA, LWAX);
1093 break;
1094 case INDEX_op_ld_i64:
1095 tcg_out_ldst (s, args[0], args[1], args[2], LD, LDX);
1096 break;
1097 case INDEX_op_st8_i32:
1098 case INDEX_op_st8_i64:
1099 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1100 break;
1101 case INDEX_op_st16_i32:
1102 case INDEX_op_st16_i64:
1103 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1104 break;
1105 case INDEX_op_st_i32:
1106 case INDEX_op_st32_i64:
1107 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1108 break;
1109 case INDEX_op_st_i64:
1110 tcg_out_ldst (s, args[0], args[1], args[2], STD, STDX);
1111 break;
1112
1113 case INDEX_op_add_i32:
1114 if (const_args[2])
1115 ppc_addi32 (s, args[0], args[1], args[2]);
1116 else
1117 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1118 break;
1119 case INDEX_op_sub_i32:
1120 if (const_args[2])
1121 ppc_addi32 (s, args[0], args[1], -args[2]);
1122 else
1123 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1124 break;
1125
1126 case INDEX_op_and_i64:
1127 case INDEX_op_and_i32:
1128 if (const_args[2]) {
1129 if ((args[2] & 0xffff) == args[2])
1130 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1131 else if ((args[2] & 0xffff0000) == args[2])
1132 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1133 | ((args[2] >> 16) & 0xffff));
1134 else {
1135 tcg_out_movi (s, (opc == INDEX_op_and_i32
1136 ? TCG_TYPE_I32
1137 : TCG_TYPE_I64),
1138 0, args[2]);
1139 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1140 }
1141 }
1142 else
1143 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1144 break;
1145 case INDEX_op_or_i64:
1146 case INDEX_op_or_i32:
1147 if (const_args[2]) {
1148 if (args[2] & 0xffff) {
1149 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1150 | (args[2] & 0xffff));
1151 if (args[2] >> 16)
1152 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1153 | ((args[2] >> 16) & 0xffff));
1154 }
1155 else {
1156 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1157 | ((args[2] >> 16) & 0xffff));
1158 }
1159 }
1160 else
1161 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1162 break;
1163 case INDEX_op_xor_i64:
1164 case INDEX_op_xor_i32:
1165 if (const_args[2]) {
1166 if ((args[2] & 0xffff) == args[2])
1167 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1168 | (args[2] & 0xffff));
1169 else if ((args[2] & 0xffff0000) == args[2])
1170 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1171 | ((args[2] >> 16) & 0xffff));
1172 else {
1173 tcg_out_movi (s, (opc == INDEX_op_and_i32
1174 ? TCG_TYPE_I32
1175 : TCG_TYPE_I64),
1176 0, args[2]);
1177 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1178 }
1179 }
1180 else
1181 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1182 break;
1183
1184 case INDEX_op_mul_i32:
1185 if (const_args[2]) {
1186 if (args[2] == (int16_t) args[2])
1187 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1188 | (args[2] & 0xffff));
1189 else {
1190 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1191 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1192 }
1193 }
1194 else
1195 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1196 break;
1197
1198 case INDEX_op_div_i32:
1199 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1200 break;
1201
1202 case INDEX_op_divu_i32:
1203 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1204 break;
1205
1206 case INDEX_op_rem_i32:
1207 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1208 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1209 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1210 break;
1211
1212 case INDEX_op_remu_i32:
1213 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1214 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1215 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1216 break;
1217
1218 case INDEX_op_shl_i32:
1219 if (const_args[2]) {
1220 tcg_out32 (s, (RLWINM
1221 | RA (args[0])
1222 | RS (args[1])
1223 | SH (args[2])
1224 | MB (0)
1225 | ME (31 - args[2])
1226 )
1227 );
1228 }
1229 else
1230 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1231 break;
1232 case INDEX_op_shr_i32:
1233 if (const_args[2]) {
1234 tcg_out32 (s, (RLWINM
1235 | RA (args[0])
1236 | RS (args[1])
1237 | SH (32 - args[2])
1238 | MB (args[2])
1239 | ME (31)
1240 )
1241 );
1242 }
1243 else
1244 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1245 break;
1246 case INDEX_op_sar_i32:
1247 if (const_args[2])
1248 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1249 else
1250 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1251 break;
1252
1253 case INDEX_op_brcond_i32:
1254 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 0);
1255 break;
1256
1257 case INDEX_op_brcond_i64:
1258 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 1);
1259 break;
1260
1261 case INDEX_op_neg_i32:
1262 case INDEX_op_neg_i64:
1263 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1264 break;
1265
1266 case INDEX_op_add_i64:
1267 if (const_args[2])
1268 ppc_addi64 (s, args[0], args[1], args[2]);
1269 else
1270 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1271 break;
1272 case INDEX_op_sub_i64:
1273 if (const_args[2])
1274 ppc_addi64 (s, args[0], args[1], -args[2]);
1275 else
1276 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1277 break;
1278
1279 case INDEX_op_shl_i64:
1280 if (const_args[2])
1281 tcg_out_rld (s, RLDICR, args[0], args[1], args[2], 63 - args[2]);
1282 else
1283 tcg_out32 (s, SLD | SAB (args[1], args[0], args[2]));
1284 break;
1285 case INDEX_op_shr_i64:
1286 if (const_args[2])
1287 tcg_out_rld (s, RLDICL, args[0], args[1], 64 - args[2], args[2]);
1288 else
1289 tcg_out32 (s, SRD | SAB (args[1], args[0], args[2]));
1290 break;
1291 case INDEX_op_sar_i64:
1292 if (const_args[2]) {
1293 int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1294 tcg_out32 (s, SRADI | RA (args[0]) | RS (args[1]) | sh);
1295 }
1296 else
1297 tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2]));
1298 break;
1299
1300 case INDEX_op_mul_i64:
1301 tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2]));
1302 break;
1303 case INDEX_op_div_i64:
1304 tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2]));
1305 break;
1306 case INDEX_op_divu_i64:
1307 tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
1308 break;
1309 case INDEX_op_rem_i64:
1310 tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
1311 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1312 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1313 break;
1314 case INDEX_op_remu_i64:
1315 tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
1316 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1317 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1318 break;
1319
1320 case INDEX_op_qemu_ld8u:
1321 tcg_out_qemu_ld (s, args, 0);
1322 break;
1323 case INDEX_op_qemu_ld8s:
1324 tcg_out_qemu_ld (s, args, 0 | 4);
1325 break;
1326 case INDEX_op_qemu_ld16u:
1327 tcg_out_qemu_ld (s, args, 1);
1328 break;
1329 case INDEX_op_qemu_ld16s:
1330 tcg_out_qemu_ld (s, args, 1 | 4);
1331 break;
1332 case INDEX_op_qemu_ld32u:
1333 tcg_out_qemu_ld (s, args, 2);
1334 break;
1335 case INDEX_op_qemu_ld32s:
1336 tcg_out_qemu_ld (s, args, 2 | 4);
1337 break;
1338 case INDEX_op_qemu_ld64:
1339 tcg_out_qemu_ld (s, args, 3);
1340 break;
1341 case INDEX_op_qemu_st8:
1342 tcg_out_qemu_st (s, args, 0);
1343 break;
1344 case INDEX_op_qemu_st16:
1345 tcg_out_qemu_st (s, args, 1);
1346 break;
1347 case INDEX_op_qemu_st32:
1348 tcg_out_qemu_st (s, args, 2);
1349 break;
1350 case INDEX_op_qemu_st64:
1351 tcg_out_qemu_st (s, args, 3);
1352 break;
1353
1354 case INDEX_op_ext8s_i32:
1355 case INDEX_op_ext8s_i64:
1356 c = EXTSB;
1357 goto gen_ext;
1358 case INDEX_op_ext16s_i32:
1359 case INDEX_op_ext16s_i64:
1360 c = EXTSH;
1361 goto gen_ext;
1362 case INDEX_op_ext32s_i64:
1363 c = EXTSW;
1364 goto gen_ext;
1365 gen_ext:
1366 tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
1367 break;
1368
1369 default:
1370 tcg_dump_ops (s, stderr);
1371 tcg_abort ();
1372 }
1373 }
1374
1375 static const TCGTargetOpDef ppc_op_defs[] = {
1376 { INDEX_op_exit_tb, { } },
1377 { INDEX_op_goto_tb, { } },
1378 { INDEX_op_call, { "ri" } },
1379 { INDEX_op_jmp, { "ri" } },
1380 { INDEX_op_br, { } },
1381
1382 { INDEX_op_mov_i32, { "r", "r" } },
1383 { INDEX_op_mov_i64, { "r", "r" } },
1384 { INDEX_op_movi_i32, { "r" } },
1385 { INDEX_op_movi_i64, { "r" } },
1386
1387 { INDEX_op_ld8u_i32, { "r", "r" } },
1388 { INDEX_op_ld8s_i32, { "r", "r" } },
1389 { INDEX_op_ld16u_i32, { "r", "r" } },
1390 { INDEX_op_ld16s_i32, { "r", "r" } },
1391 { INDEX_op_ld_i32, { "r", "r" } },
1392 { INDEX_op_ld_i64, { "r", "r" } },
1393 { INDEX_op_st8_i32, { "r", "r" } },
1394 { INDEX_op_st8_i64, { "r", "r" } },
1395 { INDEX_op_st16_i32, { "r", "r" } },
1396 { INDEX_op_st16_i64, { "r", "r" } },
1397 { INDEX_op_st_i32, { "r", "r" } },
1398 { INDEX_op_st_i64, { "r", "r" } },
1399 { INDEX_op_st32_i64, { "r", "r" } },
1400
1401 { INDEX_op_ld8u_i64, { "r", "r" } },
1402 { INDEX_op_ld8s_i64, { "r", "r" } },
1403 { INDEX_op_ld16u_i64, { "r", "r" } },
1404 { INDEX_op_ld16s_i64, { "r", "r" } },
1405 { INDEX_op_ld32u_i64, { "r", "r" } },
1406 { INDEX_op_ld32s_i64, { "r", "r" } },
1407 { INDEX_op_ld_i64, { "r", "r" } },
1408
1409 { INDEX_op_add_i32, { "r", "r", "ri" } },
1410 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1411 { INDEX_op_div_i32, { "r", "r", "r" } },
1412 { INDEX_op_divu_i32, { "r", "r", "r" } },
1413 { INDEX_op_rem_i32, { "r", "r", "r" } },
1414 { INDEX_op_remu_i32, { "r", "r", "r" } },
1415 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1416 { INDEX_op_and_i32, { "r", "r", "ri" } },
1417 { INDEX_op_or_i32, { "r", "r", "ri" } },
1418 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1419
1420 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1421 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1422 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1423
1424 { INDEX_op_brcond_i32, { "r", "ri" } },
1425 { INDEX_op_brcond_i64, { "r", "ri" } },
1426
1427 { INDEX_op_neg_i32, { "r", "r" } },
1428
1429 { INDEX_op_add_i64, { "r", "r", "ri" } },
1430 { INDEX_op_sub_i64, { "r", "r", "ri" } },
1431 { INDEX_op_and_i64, { "r", "r", "rZ" } },
1432 { INDEX_op_or_i64, { "r", "r", "rZ" } },
1433 { INDEX_op_xor_i64, { "r", "r", "rZ" } },
1434
1435 { INDEX_op_shl_i64, { "r", "r", "ri" } },
1436 { INDEX_op_shr_i64, { "r", "r", "ri" } },
1437 { INDEX_op_sar_i64, { "r", "r", "ri" } },
1438
1439 { INDEX_op_mul_i64, { "r", "r", "r" } },
1440 { INDEX_op_div_i64, { "r", "r", "r" } },
1441 { INDEX_op_divu_i64, { "r", "r", "r" } },
1442 { INDEX_op_rem_i64, { "r", "r", "r" } },
1443 { INDEX_op_remu_i64, { "r", "r", "r" } },
1444
1445 { INDEX_op_neg_i64, { "r", "r" } },
1446
1447 { INDEX_op_qemu_ld8u, { "r", "L" } },
1448 { INDEX_op_qemu_ld8s, { "r", "L" } },
1449 { INDEX_op_qemu_ld16u, { "r", "L" } },
1450 { INDEX_op_qemu_ld16s, { "r", "L" } },
1451 { INDEX_op_qemu_ld32u, { "r", "L" } },
1452 { INDEX_op_qemu_ld32s, { "r", "L" } },
1453 { INDEX_op_qemu_ld64, { "r", "L" } },
1454
1455 { INDEX_op_qemu_st8, { "S", "S" } },
1456 { INDEX_op_qemu_st16, { "S", "S" } },
1457 { INDEX_op_qemu_st32, { "S", "S" } },
1458 { INDEX_op_qemu_st64, { "S", "S", "S" } },
1459
1460 { INDEX_op_ext8s_i32, { "r", "r" } },
1461 { INDEX_op_ext16s_i32, { "r", "r" } },
1462 { INDEX_op_ext8s_i64, { "r", "r" } },
1463 { INDEX_op_ext16s_i64, { "r", "r" } },
1464 { INDEX_op_ext32s_i64, { "r", "r" } },
1465
1466 { -1 },
1467 };
1468
1469 void tcg_target_init (TCGContext *s)
1470 {
1471 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1472 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1473 tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
1474 (1 << TCG_REG_R0) |
1475 (1 << TCG_REG_R3) |
1476 (1 << TCG_REG_R4) |
1477 (1 << TCG_REG_R5) |
1478 (1 << TCG_REG_R6) |
1479 (1 << TCG_REG_R7) |
1480 (1 << TCG_REG_R8) |
1481 (1 << TCG_REG_R9) |
1482 (1 << TCG_REG_R10) |
1483 (1 << TCG_REG_R11) |
1484 (1 << TCG_REG_R12)
1485 );
1486
1487 tcg_regset_clear (s->reserved_regs);
1488 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0);
1489 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1);
1490 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2);
1491 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13);
1492
1493 tcg_add_target_add_op_defs (ppc_op_defs);
1494 }
Samsung s3c2440 and arm920t support for the mini2440 dev board