hw/pxa.h

   1 /*
   2  * Intel XScale PXA255/270 processor support.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licenced under the GNU GPL v2.
   8  */
   9 #ifndef PXA_H
  10 # define PXA_H                  "pxa.h"
  11
  12 /* Interrupt numbers */
  13 # define PXA2XX_PIC_SSP3        0
  14 # define PXA2XX_PIC_USBH2       2
  15 # define PXA2XX_PIC_USBH1       3
  16 # define PXA2XX_PIC_PWRI2C      6
  17 # define PXA25X_PIC_HWUART      7
  18 # define PXA27X_PIC_OST_4_11    7
  19 # define PXA2XX_PIC_GPIO_0      8
  20 # define PXA2XX_PIC_GPIO_1      9
  21 # define PXA2XX_PIC_GPIO_X      10
  22 # define PXA2XX_PIC_I2S         13
  23 # define PXA26X_PIC_ASSP        15
  24 # define PXA25X_PIC_NSSP        16
  25 # define PXA27X_PIC_SSP2        16
  26 # define PXA2XX_PIC_LCD         17
  27 # define PXA2XX_PIC_I2C         18
  28 # define PXA2XX_PIC_ICP         19
  29 # define PXA2XX_PIC_STUART      20
  30 # define PXA2XX_PIC_BTUART      21
  31 # define PXA2XX_PIC_FFUART      22
  32 # define PXA2XX_PIC_MMC         23
  33 # define PXA2XX_PIC_SSP         24
  34 # define PXA2XX_PIC_DMA         25
  35 # define PXA2XX_PIC_OST_0       26
  36 # define PXA2XX_PIC_RTC1HZ      30
  37 # define PXA2XX_PIC_RTCALARM    31
  38
  39 /* DMA requests */
  40 # define PXA2XX_RX_RQ_I2S       2
  41 # define PXA2XX_TX_RQ_I2S       3
  42 # define PXA2XX_RX_RQ_BTUART    4
  43 # define PXA2XX_TX_RQ_BTUART    5
  44 # define PXA2XX_RX_RQ_FFUART    6
  45 # define PXA2XX_TX_RQ_FFUART    7
  46 # define PXA2XX_RX_RQ_SSP1      13
  47 # define PXA2XX_TX_RQ_SSP1      14
  48 # define PXA2XX_RX_RQ_SSP2      15
  49 # define PXA2XX_TX_RQ_SSP2      16
  50 # define PXA2XX_RX_RQ_ICP       17
  51 # define PXA2XX_TX_RQ_ICP       18
  52 # define PXA2XX_RX_RQ_STUART    19
  53 # define PXA2XX_TX_RQ_STUART    20
  54 # define PXA2XX_RX_RQ_MMCI      21
  55 # define PXA2XX_TX_RQ_MMCI      22
  56 # define PXA2XX_USB_RQ(x)       ((x) + 24)
  57 # define PXA2XX_RX_RQ_SSP3      66
  58 # define PXA2XX_TX_RQ_SSP3      67
  59
  60 # define PXA2XX_SDRAM_BASE      0xa0000000
  61 # define PXA2XX_INTERNAL_BASE   0x5c000000
  62 # define PXA2XX_INTERNAL_SIZE   0x40000
  63
  64 /* pxa2xx_pic.c */
  65 qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
  66
  67 /* pxa2xx_timer.c */
  68 void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
  69 void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
  70
  71 /* pxa2xx_gpio.c */
  72 struct pxa2xx_gpio_info_s;
  73 struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
  74                 CPUState *env, qemu_irq *pic, int lines);
  75 qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s);
  76 void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
  77                 int line, qemu_irq handler);
  78 void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler);
  79
  80 /* pxa2xx_dma.c */
  81 struct pxa2xx_dma_state_s;
  82 struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
  83                 qemu_irq irq);
  84 struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
  85                 qemu_irq irq);
  86 void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);
  87
  88 /* pxa2xx_lcd.c */
  89 struct pxa2xx_lcdc_s;
  90 struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
  91                 qemu_irq irq, DisplayState *ds);
  92 void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler);
  93 void pxa2xx_lcdc_oritentation(void *opaque, int angle);
  94
  95 /* pxa2xx_mmci.c */
  96 struct pxa2xx_mmci_s;
  97 struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
  98                 qemu_irq irq, void *dma);
  99 void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
 100                 qemu_irq coverswitch);
 101
 102 /* pxa2xx_pcmcia.c */
 103 struct pxa2xx_pcmcia_s;
 104 struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
 105 int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card);
 106 int pxa2xx_pcmcia_dettach(void *opaque);
 107 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
 108
 109 /* pxa2xx.c */
 110 struct pxa2xx_ssp_s;
 111 void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
 112                 uint32_t (*readfn)(void *opaque),
 113                 void (*writefn)(void *opaque, uint32_t value), void *opaque);
 114
 115 struct pxa2xx_i2c_s;
 116 struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
 117                 qemu_irq irq, uint32_t page_size);
 118 i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s);
 119
 120 struct pxa2xx_i2s_s;
 121 struct pxa2xx_fir_s;
 122
 123 struct pxa2xx_state_s {
 124     CPUState *env;
 125     qemu_irq *pic;
 126     qemu_irq reset;
 127     struct pxa2xx_dma_state_s *dma;
 128     struct pxa2xx_gpio_info_s *gpio;
 129     struct pxa2xx_lcdc_s *lcd;
 130     struct pxa2xx_ssp_s **ssp;
 131     struct pxa2xx_i2c_s *i2c[2];
 132     struct pxa2xx_mmci_s *mmc;
 133     struct pxa2xx_pcmcia_s *pcmcia[2];
 134     struct pxa2xx_i2s_s *i2s;
 135     struct pxa2xx_fir_s *fir;
 136
 137     /* Power management */
 138     target_phys_addr_t pm_base;
 139     uint32_t pm_regs[0x40];
 140
 141     /* Clock management */
 142     target_phys_addr_t cm_base;
 143     uint32_t cm_regs[4];
 144     uint32_t clkcfg;
 145
 146     /* Memory management */
 147     target_phys_addr_t mm_base;
 148     uint32_t mm_regs[0x1a];
 149
 150     /* Performance monitoring */
 151     uint32_t pmnc;
 152
 153     /* Real-Time clock */
 154     target_phys_addr_t rtc_base;
 155     uint32_t rttr;
 156     uint32_t rtsr;
 157     uint32_t rtar;
 158     uint32_t rdar1;
 159     uint32_t rdar2;
 160     uint32_t ryar1;
 161     uint32_t ryar2;
 162     uint32_t swar1;
 163     uint32_t swar2;
 164     uint32_t piar;
 165     uint32_t last_rcnr;
 166     uint32_t last_rdcr;
 167     uint32_t last_rycr;
 168     uint32_t last_swcr;
 169     uint32_t last_rtcpicr;
 170     int64_t last_hz;
 171     int64_t last_sw;
 172     int64_t last_pi;
 173     QEMUTimer *rtc_hz;
 174     QEMUTimer *rtc_rdal1;
 175     QEMUTimer *rtc_rdal2;
 176     QEMUTimer *rtc_swal1;
 177     QEMUTimer *rtc_swal2;
 178     QEMUTimer *rtc_pi;
 179 };
 180
 181 struct pxa2xx_i2s_s {
 182     target_phys_addr_t base;
 183     qemu_irq irq;
 184     struct pxa2xx_dma_state_s *dma;
 185     void (*data_req)(void *, int, int);
 186
 187     uint32_t control[2];
 188     uint32_t status;
 189     uint32_t mask;
 190     uint32_t clk;
 191
 192     int enable;
 193     int rx_len;
 194     int tx_len;
 195     void (*codec_out)(void *, uint32_t);
 196     uint32_t (*codec_in)(void *);
 197     void *opaque;
 198
 199     int fifo_len;
 200     uint32_t fifo[16];
 201 };
 202
 203 # define PA_FMT                 "0x%08lx"
 204 # define REG_FMT                "0x" TARGET_FMT_plx
 205
 206 struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds,
 207                 const char *revision);
 208 struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds);
 209
 210 #endif  /* PXA_H */