target-unicore32/softmmu.c

   1 /*
   2  * Softmmu related functions
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11 #ifdef CONFIG_USER_ONLY
  12 #error This file only exist under softmmu circumstance
  13 #endif
  14
  15 #include "qemu/osdep.h"
  16 #include <cpu.h>
  17 #include "exec/exec-all.h"
  18
  19 #undef DEBUG_UC32
  20
  21 #ifdef DEBUG_UC32
  22 #define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
  23 #else
  24 #define DPRINTF(fmt, ...) do {} while (0)
  25 #endif
  26
  27 #define SUPERPAGE_SIZE             (1 << 22)
  28 #define UC32_PAGETABLE_READ        (1 << 8)
  29 #define UC32_PAGETABLE_WRITE       (1 << 7)
  30 #define UC32_PAGETABLE_EXEC        (1 << 6)
  31 #define UC32_PAGETABLE_EXIST       (1 << 2)
  32 #define PAGETABLE_TYPE(x)          ((x) & 3)
  33
  34
  35 /* Map CPU modes onto saved register banks.  */
  36 static inline int bank_number(CPUUniCore32State *env, int mode)
  37 {
  38     UniCore32CPU *cpu = uc32_env_get_cpu(env);
  39
  40     switch (mode) {
  41     case ASR_MODE_USER:
  42     case ASR_MODE_SUSR:
  43         return 0;
  44     case ASR_MODE_PRIV:
  45         return 1;
  46     case ASR_MODE_TRAP:
  47         return 2;
  48     case ASR_MODE_EXTN:
  49         return 3;
  50     case ASR_MODE_INTR:
  51         return 4;
  52     }
  53     cpu_abort(CPU(cpu), "Bad mode %x\n", mode);
  54     return -1;
  55 }
  56
  57 void switch_mode(CPUUniCore32State *env, int mode)
  58 {
  59     int old_mode;
  60     int i;
  61
  62     old_mode = env->uncached_asr & ASR_M;
  63     if (mode == old_mode) {
  64         return;
  65     }
  66
  67     i = bank_number(env, old_mode);
  68     env->banked_r29[i] = env->regs[29];
  69     env->banked_r30[i] = env->regs[30];
  70     env->banked_bsr[i] = env->bsr;
  71
  72     i = bank_number(env, mode);
  73     env->regs[29] = env->banked_r29[i];
  74     env->regs[30] = env->banked_r30[i];
  75     env->bsr = env->banked_bsr[i];
  76 }
  77
  78 /* Handle a CPU exception.  */
  79 void uc32_cpu_do_interrupt(CPUState *cs)
  80 {
  81     UniCore32CPU *cpu = UNICORE32_CPU(cs);
  82     CPUUniCore32State *env = &cpu->env;
  83     uint32_t addr;
  84     int new_mode;
  85
  86     switch (cs->exception_index) {
  87     case UC32_EXCP_PRIV:
  88         new_mode = ASR_MODE_PRIV;
  89         addr = 0x08;
  90         break;
  91     case UC32_EXCP_ITRAP:
  92         DPRINTF("itrap happened at %x\n", env->regs[31]);
  93         new_mode = ASR_MODE_TRAP;
  94         addr = 0x0c;
  95         break;
  96     case UC32_EXCP_DTRAP:
  97         DPRINTF("dtrap happened at %x\n", env->regs[31]);
  98         new_mode = ASR_MODE_TRAP;
  99         addr = 0x10;
 100         break;
 101     case UC32_EXCP_INTR:
 102         new_mode = ASR_MODE_INTR;
 103         addr = 0x18;
 104         break;
 105     default:
 106         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
 107         return;
 108     }
 109     /* High vectors.  */
 110     if (env->cp0.c1_sys & (1 << 13)) {
 111         addr += 0xffff0000;
 112     }
 113
 114     switch_mode(env, new_mode);
 115     env->bsr = cpu_asr_read(env);
 116     env->uncached_asr = (env->uncached_asr & ~ASR_M) | new_mode;
 117     env->uncached_asr |= ASR_I;
 118     /* The PC already points to the proper instruction.  */
 119     env->regs[30] = env->regs[31];
 120     env->regs[31] = addr;
 121     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 122 }
 123
 124 static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
 125         int access_type, int is_user, uint32_t *phys_ptr, int *prot,
 126         target_ulong *page_size)
 127 {
 128     UniCore32CPU *cpu = uc32_env_get_cpu(env);
 129     CPUState *cs = CPU(cpu);
 130     int code;
 131     uint32_t table;
 132     uint32_t desc;
 133     uint32_t phys_addr;
 134
 135     /* Pagetable walk.  */
 136     /* Lookup l1 descriptor.  */
 137     table = env->cp0.c2_base & 0xfffff000;
 138     table |= (address >> 20) & 0xffc;
 139     desc = ldl_phys(cs->as, table);
 140     code = 0;
 141     switch (PAGETABLE_TYPE(desc)) {
 142     case 3:
 143         /* Superpage  */
 144         if (!(desc & UC32_PAGETABLE_EXIST)) {
 145             code = 0x0b; /* superpage miss */
 146             goto do_fault;
 147         }
 148         phys_addr = (desc & 0xffc00000) | (address & 0x003fffff);
 149         *page_size = SUPERPAGE_SIZE;
 150         break;
 151     case 0:
 152         /* Lookup l2 entry.  */
 153         if (is_user) {
 154             DPRINTF("PGD address %x, desc %x\n", table, desc);
 155         }
 156         if (!(desc & UC32_PAGETABLE_EXIST)) {
 157             code = 0x05; /* second pagetable miss */
 158             goto do_fault;
 159         }
 160         table = (desc & 0xfffff000) | ((address >> 10) & 0xffc);
 161         desc = ldl_phys(cs->as, table);
 162         /* 4k page.  */
 163         if (is_user) {
 164             DPRINTF("PTE address %x, desc %x\n", table, desc);
 165         }
 166         if (!(desc & UC32_PAGETABLE_EXIST)) {
 167             code = 0x08; /* page miss */
 168             goto do_fault;
 169         }
 170         switch (PAGETABLE_TYPE(desc)) {
 171         case 0:
 172             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
 173             *page_size = TARGET_PAGE_SIZE;
 174             break;
 175         default:
 176             cpu_abort(CPU(cpu), "wrong page type!");
 177         }
 178         break;
 179     default:
 180         cpu_abort(CPU(cpu), "wrong page type!");
 181     }
 182
 183     *phys_ptr = phys_addr;
 184     *prot = 0;
 185     /* Check access permissions.  */
 186     if (desc & UC32_PAGETABLE_READ) {
 187         *prot |= PAGE_READ;
 188     } else {
 189         if (is_user && (access_type == 0)) {
 190             code = 0x11; /* access unreadable area */
 191             goto do_fault;
 192         }
 193     }
 194
 195     if (desc & UC32_PAGETABLE_WRITE) {
 196         *prot |= PAGE_WRITE;
 197     } else {
 198         if (is_user && (access_type == 1)) {
 199             code = 0x12; /* access unwritable area */
 200             goto do_fault;
 201         }
 202     }
 203
 204     if (desc & UC32_PAGETABLE_EXEC) {
 205         *prot |= PAGE_EXEC;
 206     } else {
 207         if (is_user && (access_type == 2)) {
 208             code = 0x13; /* access unexecutable area */
 209             goto do_fault;
 210         }
 211     }
 212
 213 do_fault:
 214     return code;
 215 }
 216
 217 int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
 218                               int access_type, int mmu_idx)
 219 {
 220     UniCore32CPU *cpu = UNICORE32_CPU(cs);
 221     CPUUniCore32State *env = &cpu->env;
 222     uint32_t phys_addr;
 223     target_ulong page_size;
 224     int prot;
 225     int ret, is_user;
 226
 227     ret = 1;
 228     is_user = mmu_idx == MMU_USER_IDX;
 229
 230     if ((env->cp0.c1_sys & 1) == 0) {
 231         /* MMU disabled.  */
 232         phys_addr = address;
 233         prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 234         page_size = TARGET_PAGE_SIZE;
 235         ret = 0;
 236     } else {
 237         if ((address & (1 << 31)) || (is_user)) {
 238             ret = get_phys_addr_ucv2(env, address, access_type, is_user,
 239                                     &phys_addr, &prot, &page_size);
 240             if (is_user) {
 241                 DPRINTF("user space access: ret %x, address %" VADDR_PRIx ", "
 242                         "access_type %x, phys_addr %x, prot %x\n",
 243                         ret, address, access_type, phys_addr, prot);
 244             }
 245         } else {
 246             /*IO memory */
 247             phys_addr = address | (1 << 31);
 248             prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 249             page_size = TARGET_PAGE_SIZE;
 250             ret = 0;
 251         }
 252     }
 253
 254     if (ret == 0) {
 255         /* Map a single page.  */
 256         phys_addr &= TARGET_PAGE_MASK;
 257         address &= TARGET_PAGE_MASK;
 258         tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
 259         return 0;
 260     }
 261
 262     env->cp0.c3_faultstatus = ret;
 263     env->cp0.c4_faultaddr = address;
 264     if (access_type == 2) {
 265         cs->exception_index = UC32_EXCP_ITRAP;
 266     } else {
 267         cs->exception_index = UC32_EXCP_DTRAP;
 268     }
 269     return ret;
 270 }
 271
 272 hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 273 {
 274     UniCore32CPU *cpu = UNICORE32_CPU(cs);
 275
 276     cpu_abort(CPU(cpu), "%s not supported yet\n", __func__);
 277     return addr;
 278 }