hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "qemu/osdep.h"
  22 #include "hw/hw.h"
  23 #include "hw/i386/pc.h"
  24 #include "hw/isa/apm.h"
  25 #include "hw/i2c/pm_smbus.h"
  26 #include "hw/pci/pci.h"
  27 #include "hw/acpi/acpi.h"
  28 #include "sysemu/sysemu.h"
  29 #include "qapi/error.h"
  30 #include "qemu/range.h"
  31 #include "exec/ioport.h"
  32 #include "hw/nvram/fw_cfg.h"
  33 #include "exec/address-spaces.h"
  34 #include "hw/acpi/piix4.h"
  35 #include "hw/acpi/pcihp.h"
  36 #include "hw/acpi/cpu_hotplug.h"
  37 #include "hw/hotplug.h"
  38 #include "hw/mem/pc-dimm.h"
  39 #include "hw/acpi/memory_hotplug.h"
  40 #include "hw/acpi/acpi_dev_interface.h"
  41 #include "hw/xen/xen.h"
  42 #include "qom/cpu.h"
  43
  44 //#define DEBUG
  45
  46 #ifdef DEBUG
  47 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  48 #else
  49 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  50 #endif
  51
  52 #define GPE_BASE 0xafe0
  53 #define GPE_LEN 4
  54
  55 struct pci_status {
  56     uint32_t up; /* deprecated, maintained for migration compatibility */
  57     uint32_t down;
  58 };
  59
  60 typedef struct PIIX4PMState {
  61     /*< private >*/
  62     PCIDevice parent_obj;
  63     /*< public >*/
  64
  65     MemoryRegion io;
  66     uint32_t io_base;
  67
  68     MemoryRegion io_gpe;
  69     ACPIREGS ar;
  70
  71     APMState apm;
  72
  73     PMSMBus smb;
  74     uint32_t smb_io_base;
  75
  76     qemu_irq irq;
  77     qemu_irq smi_irq;
  78     int smm_enabled;
  79     Notifier machine_ready;
  80     Notifier powerdown_notifier;
  81
  82     AcpiPciHpState acpi_pci_hotplug;
  83     bool use_acpi_pci_hotplug;
  84
  85     uint8_t disable_s3;
  86     uint8_t disable_s4;
  87     uint8_t s4_val;
  88
  89     AcpiCpuHotplug gpe_cpu;
  90
  91     MemHotplugState acpi_memory_hotplug;
  92 } PIIX4PMState;
  93
  94 #define TYPE_PIIX4_PM "PIIX4_PM"
  95
  96 #define PIIX4_PM(obj) \
  97     OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
  98
  99 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 100                                            PCIBus *bus, PIIX4PMState *s);
 101
 102 #define ACPI_ENABLE 0xf1
 103 #define ACPI_DISABLE 0xf0
 104
 105 static void pm_tmr_timer(ACPIREGS *ar)
 106 {
 107     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 108     acpi_update_sci(&s->ar, s->irq);
 109 }
 110
 111 static void apm_ctrl_changed(uint32_t val, void *arg)
 112 {
 113     PIIX4PMState *s = arg;
 114     PCIDevice *d = PCI_DEVICE(s);
 115
 116     /* ACPI specs 3.0, 4.7.2.5 */
 117     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 118     if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
 119         return;
 120     }
 121
 122     if (d->config[0x5b] & (1 << 1)) {
 123         if (s->smi_irq) {
 124             qemu_irq_raise(s->smi_irq);
 125         }
 126     }
 127 }
 128
 129 static void pm_io_space_update(PIIX4PMState *s)
 130 {
 131     PCIDevice *d = PCI_DEVICE(s);
 132
 133     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 134     s->io_base &= 0xffc0;
 135
 136     memory_region_transaction_begin();
 137     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 138     memory_region_set_address(&s->io, s->io_base);
 139     memory_region_transaction_commit();
 140 }
 141
 142 static void smbus_io_space_update(PIIX4PMState *s)
 143 {
 144     PCIDevice *d = PCI_DEVICE(s);
 145
 146     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 147     s->smb_io_base &= 0xffc0;
 148
 149     memory_region_transaction_begin();
 150     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 151     memory_region_set_address(&s->smb.io, s->smb_io_base);
 152     memory_region_transaction_commit();
 153 }
 154
 155 static void pm_write_config(PCIDevice *d,
 156                             uint32_t address, uint32_t val, int len)
 157 {
 158     pci_default_write_config(d, address, val, len);
 159     if (range_covers_byte(address, len, 0x80) ||
 160         ranges_overlap(address, len, 0x40, 4)) {
 161         pm_io_space_update((PIIX4PMState *)d);
 162     }
 163     if (range_covers_byte(address, len, 0xd2) ||
 164         ranges_overlap(address, len, 0x90, 4)) {
 165         smbus_io_space_update((PIIX4PMState *)d);
 166     }
 167 }
 168
 169 static int vmstate_acpi_post_load(void *opaque, int version_id)
 170 {
 171     PIIX4PMState *s = opaque;
 172
 173     pm_io_space_update(s);
 174     return 0;
 175 }
 176
 177 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 178  {                                                                   \
 179      .name       = (stringify(_field)),                              \
 180      .version_id = 0,                                                \
 181      .info       = &vmstate_info_uint16,                             \
 182      .size       = sizeof(uint16_t),                                 \
 183      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 184      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 185  }
 186
 187 static const VMStateDescription vmstate_gpe = {
 188     .name = "gpe",
 189     .version_id = 1,
 190     .minimum_version_id = 1,
 191     .fields = (VMStateField[]) {
 192         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 193         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 194         VMSTATE_END_OF_LIST()
 195     }
 196 };
 197
 198 static const VMStateDescription vmstate_pci_status = {
 199     .name = "pci_status",
 200     .version_id = 1,
 201     .minimum_version_id = 1,
 202     .fields = (VMStateField[]) {
 203         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 204         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 205         VMSTATE_END_OF_LIST()
 206     }
 207 };
 208
 209 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 210 {
 211     PIIX4PMState *s = opaque;
 212     int ret, i;
 213     uint16_t temp;
 214
 215     ret = pci_device_load(PCI_DEVICE(s), f);
 216     if (ret < 0) {
 217         return ret;
 218     }
 219     qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 220     qemu_get_be16s(f, &s->ar.pm1.evt.en);
 221     qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 222
 223     ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
 224     if (ret) {
 225         return ret;
 226     }
 227
 228     timer_get(f, s->ar.tmr.timer);
 229     qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 230
 231     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 232     for (i = 0; i < 3; i++) {
 233         qemu_get_be16s(f, &temp);
 234     }
 235
 236     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 237     for (i = 0; i < 3; i++) {
 238         qemu_get_be16s(f, &temp);
 239     }
 240
 241     ret = vmstate_load_state(f, &vmstate_pci_status,
 242         &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
 243     return ret;
 244 }
 245
 246 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 247 {
 248     PIIX4PMState *s = opaque;
 249     return s->use_acpi_pci_hotplug;
 250 }
 251
 252 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
 253 {
 254     PIIX4PMState *s = opaque;
 255     return !s->use_acpi_pci_hotplug;
 256 }
 257
 258 static bool vmstate_test_use_memhp(void *opaque)
 259 {
 260     PIIX4PMState *s = opaque;
 261     return s->acpi_memory_hotplug.is_enabled;
 262 }
 263
 264 static const VMStateDescription vmstate_memhp_state = {
 265     .name = "piix4_pm/memhp",
 266     .version_id = 1,
 267     .minimum_version_id = 1,
 268     .minimum_version_id_old = 1,
 269     .needed = vmstate_test_use_memhp,
 270     .fields      = (VMStateField[]) {
 271         VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
 272         VMSTATE_END_OF_LIST()
 273     }
 274 };
 275
 276 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 277  * To support incoming qemu-kvm 1.2 migration, change version_id
 278  * and minimum_version_id to 2 below (which breaks migration from
 279  * qemu 1.2).
 280  *
 281  */
 282 static const VMStateDescription vmstate_acpi = {
 283     .name = "piix4_pm",
 284     .version_id = 3,
 285     .minimum_version_id = 3,
 286     .minimum_version_id_old = 1,
 287     .load_state_old = acpi_load_old,
 288     .post_load = vmstate_acpi_post_load,
 289     .fields = (VMStateField[]) {
 290         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 291         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 292         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 293         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 294         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 295         VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
 296         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 297         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 298         VMSTATE_STRUCT_TEST(
 299             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 300             PIIX4PMState,
 301             vmstate_test_no_use_acpi_pci_hotplug,
 302             2, vmstate_pci_status,
 303             struct AcpiPciHpPciStatus),
 304         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 305                             vmstate_test_use_acpi_pci_hotplug),
 306         VMSTATE_END_OF_LIST()
 307     },
 308     .subsections = (const VMStateDescription*[]) {
 309          &vmstate_memhp_state,
 310          NULL
 311     }
 312 };
 313
 314 static void piix4_reset(void *opaque)
 315 {
 316     PIIX4PMState *s = opaque;
 317     PCIDevice *d = PCI_DEVICE(s);
 318     uint8_t *pci_conf = d->config;
 319
 320     pci_conf[0x58] = 0;
 321     pci_conf[0x59] = 0;
 322     pci_conf[0x5a] = 0;
 323     pci_conf[0x5b] = 0;
 324
 325     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 326     pci_conf[0x80] = 0;
 327
 328     if (!s->smm_enabled) {
 329         /* Mark SMM as already inited (until KVM supports SMM). */
 330         pci_conf[0x5B] = 0x02;
 331     }
 332     pm_io_space_update(s);
 333     acpi_pcihp_reset(&s->acpi_pci_hotplug);
 334 }
 335
 336 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 337 {
 338     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 339
 340     assert(s != NULL);
 341     acpi_pm1_evt_power_down(&s->ar);
 342 }
 343
 344 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
 345                                  DeviceState *dev, Error **errp)
 346 {
 347     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 348
 349     if (s->acpi_memory_hotplug.is_enabled &&
 350         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 351         acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, dev, errp);
 352     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 353         acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp);
 354     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 355         legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp);
 356     } else {
 357         error_setg(errp, "acpi: device plug request for not supported device"
 358                    " type: %s", object_get_typename(OBJECT(dev)));
 359     }
 360 }
 361
 362 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 363                                            DeviceState *dev, Error **errp)
 364 {
 365     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 366
 367     if (s->acpi_memory_hotplug.is_enabled &&
 368         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 369         acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug,
 370                                       dev, errp);
 371     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 372         acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev,
 373                                     errp);
 374     } else {
 375         error_setg(errp, "acpi: device unplug request for not supported device"
 376                    " type: %s", object_get_typename(OBJECT(dev)));
 377     }
 378 }
 379
 380 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
 381                                    DeviceState *dev, Error **errp)
 382 {
 383     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 384
 385     if (s->acpi_memory_hotplug.is_enabled &&
 386         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 387         acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
 388     } else {
 389         error_setg(errp, "acpi: device unplug for not supported device"
 390                    " type: %s", object_get_typename(OBJECT(dev)));
 391     }
 392 }
 393
 394 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
 395 {
 396     PIIX4PMState *s = opaque;
 397
 398     qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort);
 399 }
 400
 401 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 402 {
 403     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 404     PCIDevice *d = PCI_DEVICE(s);
 405     MemoryRegion *io_as = pci_address_space_io(d);
 406     uint8_t *pci_conf;
 407
 408     pci_conf = d->config;
 409     pci_conf[0x5f] = 0x10 |
 410         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 411     pci_conf[0x63] = 0x60;
 412     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 413         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 414
 415     if (s->use_acpi_pci_hotplug) {
 416         pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
 417     } else {
 418         piix4_update_bus_hotplug(d->bus, s);
 419     }
 420 }
 421
 422 static void piix4_pm_add_propeties(PIIX4PMState *s)
 423 {
 424     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 425     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 426     static const uint32_t gpe0_blk = GPE_BASE;
 427     static const uint32_t gpe0_blk_len = GPE_LEN;
 428     static const uint16_t sci_int = 9;
 429
 430     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 431                                   &acpi_enable_cmd, NULL);
 432     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 433                                   &acpi_disable_cmd, NULL);
 434     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 435                                   &gpe0_blk, NULL);
 436     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 437                                   &gpe0_blk_len, NULL);
 438     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 439                                   &sci_int, NULL);
 440     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 441                                   &s->io_base, NULL);
 442 }
 443
 444 static void piix4_pm_realize(PCIDevice *dev, Error **errp)
 445 {
 446     PIIX4PMState *s = PIIX4_PM(dev);
 447     uint8_t *pci_conf;
 448
 449     pci_conf = dev->config;
 450     pci_conf[0x06] = 0x80;
 451     pci_conf[0x07] = 0x02;
 452     pci_conf[0x09] = 0x00;
 453     pci_conf[0x3d] = 0x01; // interrupt pin 1
 454
 455     /* APM */
 456     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 457
 458     if (!s->smm_enabled) {
 459         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 460          * support SMM mode. */
 461         pci_conf[0x5B] = 0x02;
 462     }
 463
 464     /* XXX: which specification is used ? The i82731AB has different
 465        mappings */
 466     pci_conf[0x90] = s->smb_io_base | 1;
 467     pci_conf[0x91] = s->smb_io_base >> 8;
 468     pci_conf[0xd2] = 0x09;
 469     pm_smbus_init(DEVICE(dev), &s->smb);
 470     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 471     memory_region_add_subregion(pci_address_space_io(dev),
 472                                 s->smb_io_base, &s->smb.io);
 473
 474     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 475     memory_region_set_enabled(&s->io, false);
 476     memory_region_add_subregion(pci_address_space_io(dev),
 477                                 0, &s->io);
 478
 479     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 480     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 481     acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val);
 482     acpi_gpe_init(&s->ar, GPE_LEN);
 483
 484     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 485     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 486
 487     s->machine_ready.notify = piix4_pm_machine_ready;
 488     qemu_add_machine_init_done_notifier(&s->machine_ready);
 489     qemu_register_reset(piix4_reset, s);
 490
 491     piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
 492
 493     piix4_pm_add_propeties(s);
 494 }
 495
 496 Object *piix4_pm_find(void)
 497 {
 498     bool ambig;
 499     Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
 500
 501     if (ambig || !o) {
 502         return NULL;
 503     }
 504     return o;
 505 }
 506
 507 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 508                       qemu_irq sci_irq, qemu_irq smi_irq,
 509                       int smm_enabled, DeviceState **piix4_pm)
 510 {
 511     DeviceState *dev;
 512     PIIX4PMState *s;
 513
 514     dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
 515     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 516     if (piix4_pm) {
 517         *piix4_pm = dev;
 518     }
 519
 520     s = PIIX4_PM(dev);
 521     s->irq = sci_irq;
 522     s->smi_irq = smi_irq;
 523     s->smm_enabled = smm_enabled;
 524     if (xen_enabled()) {
 525         s->use_acpi_pci_hotplug = false;
 526     }
 527
 528     qdev_init_nofail(dev);
 529
 530     return s->smb.smbus;
 531 }
 532
 533 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 534 {
 535     PIIX4PMState *s = opaque;
 536     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 537
 538     PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
 539     return val;
 540 }
 541
 542 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 543                        unsigned width)
 544 {
 545     PIIX4PMState *s = opaque;
 546
 547     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 548     acpi_update_sci(&s->ar, s->irq);
 549
 550     PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
 551 }
 552
 553 static const MemoryRegionOps piix4_gpe_ops = {
 554     .read = gpe_readb,
 555     .write = gpe_writeb,
 556     .valid.min_access_size = 1,
 557     .valid.max_access_size = 4,
 558     .impl.min_access_size = 1,
 559     .impl.max_access_size = 1,
 560     .endianness = DEVICE_LITTLE_ENDIAN,
 561 };
 562
 563 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 564                                            PCIBus *bus, PIIX4PMState *s)
 565 {
 566     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 567                           "acpi-gpe0", GPE_LEN);
 568     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 569
 570     acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
 571                     s->use_acpi_pci_hotplug);
 572
 573     legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 574                                  PIIX4_CPU_HOTPLUG_IO_BASE);
 575
 576     if (s->acpi_memory_hotplug.is_enabled) {
 577         acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug);
 578     }
 579 }
 580
 581 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
 582 {
 583     PIIX4PMState *s = PIIX4_PM(adev);
 584
 585     acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
 586 }
 587
 588 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
 589 {
 590     PIIX4PMState *s = PIIX4_PM(adev);
 591
 592     acpi_send_gpe_event(&s->ar, s->irq, ev);
 593 }
 594
 595 static Property piix4_pm_properties[] = {
 596     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 597     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 598     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 599     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 600     DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
 601                      use_acpi_pci_hotplug, true),
 602     DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
 603                      acpi_memory_hotplug.is_enabled, true),
 604     DEFINE_PROP_END_OF_LIST(),
 605 };
 606
 607 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 608 {
 609     DeviceClass *dc = DEVICE_CLASS(klass);
 610     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 611     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 612     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 613
 614     k->realize = piix4_pm_realize;
 615     k->config_write = pm_write_config;
 616     k->vendor_id = PCI_VENDOR_ID_INTEL;
 617     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 618     k->revision = 0x03;
 619     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 620     dc->desc = "PM";
 621     dc->vmsd = &vmstate_acpi;
 622     dc->props = piix4_pm_properties;
 623     /*
 624      * Reason: part of PIIX4 southbridge, needs to be wired up,
 625      * e.g. by mips_malta_init()
 626      */
 627     dc->cannot_instantiate_with_device_add_yet = true;
 628     dc->hotpluggable = false;
 629     hc->plug = piix4_device_plug_cb;
 630     hc->unplug_request = piix4_device_unplug_request_cb;
 631     hc->unplug = piix4_device_unplug_cb;
 632     adevc->ospm_status = piix4_ospm_status;
 633     adevc->send_event = piix4_send_gpe;
 634 }
 635
 636 static const TypeInfo piix4_pm_info = {
 637     .name          = TYPE_PIIX4_PM,
 638     .parent        = TYPE_PCI_DEVICE,
 639     .instance_size = sizeof(PIIX4PMState),
 640     .class_init    = piix4_pm_class_init,
 641     .interfaces = (InterfaceInfo[]) {
 642         { TYPE_HOTPLUG_HANDLER },
 643         { TYPE_ACPI_DEVICE_IF },
 644         { }
 645     }
 646 };
 647
 648 static void piix4_pm_register_types(void)
 649 {
 650     type_register_static(&piix4_pm_info);
 651 }
 652
 653 type_init(piix4_pm_register_types)