hw/i386/x86-iommu.c

   1 /*
   2  * QEMU emulation of common X86 IOMMU
   3  *
   4  * Copyright (C) 2016 Peter Xu, Red Hat <peterx@redhat.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/sysbus.h"
  22 #include "hw/i386/x86-iommu.h"
  23 #include "hw/qdev-properties.h"
  24 #include "hw/i386/pc.h"
  25 #include "qapi/error.h"
  26 #include "qemu/error-report.h"
  27 #include "trace.h"
  28 #include "sysemu/kvm.h"
  29
  30 void x86_iommu_iec_register_notifier(X86IOMMUState *iommu,
  31                                      iec_notify_fn fn, void *data)
  32 {
  33     IEC_Notifier *notifier = g_new0(IEC_Notifier, 1);
  34
  35     notifier->iec_notify = fn;
  36     notifier->private = data;
  37
  38     QLIST_INSERT_HEAD(&iommu->iec_notifiers, notifier, list);
  39 }
  40
  41 void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global,
  42                               uint32_t index, uint32_t mask)
  43 {
  44     IEC_Notifier *notifier;
  45
  46     trace_x86_iommu_iec_notify(global, index, mask);
  47
  48     QLIST_FOREACH(notifier, &iommu->iec_notifiers, list) {
  49         if (notifier->iec_notify) {
  50             notifier->iec_notify(notifier->private, global,
  51                                  index, mask);
  52         }
  53     }
  54 }
  55
  56 /* Generate one MSI message from VTDIrq info */
  57 void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *msg_out)
  58 {
  59     X86IOMMU_MSIMessage msg = {};
  60
  61     /* Generate address bits */
  62     msg.dest_mode = irq->dest_mode;
  63     msg.redir_hint = irq->redir_hint;
  64     msg.dest = irq->dest;
  65     msg.__addr_hi = irq->dest & 0xffffff00;
  66     msg.__addr_head = 0xfee;
  67     /* Keep this from original MSI address bits */
  68     msg.__not_used = irq->msi_addr_last_bits;
  69
  70     /* Generate data bits */
  71     msg.vector = irq->vector;
  72     msg.delivery_mode = irq->delivery_mode;
  73     msg.level = 1;
  74     msg.trigger_mode = irq->trigger_mode;
  75
  76     msg_out->address = msg.msi_addr;
  77     msg_out->data = msg.msi_data;
  78 }
  79
  80 X86IOMMUState *x86_iommu_get_default(void)
  81 {
  82     MachineState *ms = MACHINE(qdev_get_machine());
  83     PCMachineState *pcms =
  84         PC_MACHINE(object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE));
  85
  86     if (pcms &&
  87         object_dynamic_cast(OBJECT(pcms->iommu), TYPE_X86_IOMMU_DEVICE)) {
  88         return X86_IOMMU_DEVICE(pcms->iommu);
  89     }
  90     return NULL;
  91 }
  92
  93 static void x86_iommu_realize(DeviceState *dev, Error **errp)
  94 {
  95     X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
  96     X86IOMMUClass *x86_class = X86_IOMMU_DEVICE_GET_CLASS(dev);
  97     MachineState *ms = MACHINE(qdev_get_machine());
  98     MachineClass *mc = MACHINE_GET_CLASS(ms);
  99     PCMachineState *pcms =
 100         PC_MACHINE(object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE));
 101     QLIST_INIT(&x86_iommu->iec_notifiers);
 102     bool irq_all_kernel = kvm_irqchip_in_kernel() && !kvm_irqchip_is_split();
 103
 104     if (!pcms || !pcms->pcibus) {
 105         error_setg(errp, "Machine-type '%s' not supported by IOMMU",
 106                    mc->name);
 107         return;
 108     }
 109
 110     /* If the user didn't specify IR, choose a default value for it */
 111     if (x86_iommu->intr_supported == ON_OFF_AUTO_AUTO) {
 112         x86_iommu->intr_supported = irq_all_kernel ?
 113             ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 114     }
 115
 116     /* Both Intel and AMD IOMMU IR only support "kernel-irqchip={off|split}" */
 117     if (x86_iommu_ir_supported(x86_iommu) && irq_all_kernel) {
 118         error_setg(errp, "Interrupt Remapping cannot work with "
 119                          "kernel-irqchip=on, please use 'split|off'.");
 120         return;
 121     }
 122
 123     if (x86_class->realize) {
 124         x86_class->realize(dev, errp);
 125     }
 126 }
 127
 128 static Property x86_iommu_properties[] = {
 129     DEFINE_PROP_ON_OFF_AUTO("intremap", X86IOMMUState,
 130                             intr_supported, ON_OFF_AUTO_AUTO),
 131     DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false),
 132     DEFINE_PROP_BOOL("pt", X86IOMMUState, pt_supported, true),
 133     DEFINE_PROP_END_OF_LIST(),
 134 };
 135
 136 static void x86_iommu_class_init(ObjectClass *klass, void *data)
 137 {
 138     DeviceClass *dc = DEVICE_CLASS(klass);
 139     dc->realize = x86_iommu_realize;
 140     device_class_set_props(dc, x86_iommu_properties);
 141 }
 142
 143 bool x86_iommu_ir_supported(X86IOMMUState *s)
 144 {
 145     return s->intr_supported == ON_OFF_AUTO_ON;
 146 }
 147
 148 static const TypeInfo x86_iommu_info = {
 149     .name          = TYPE_X86_IOMMU_DEVICE,
 150     .parent        = TYPE_SYS_BUS_DEVICE,
 151     .instance_size = sizeof(X86IOMMUState),
 152     .class_init    = x86_iommu_class_init,
 153     .class_size    = sizeof(X86IOMMUClass),
 154     .abstract      = true,
 155 };
 156
 157 static void x86_iommu_register_types(void)
 158 {
 159     type_register_static(&x86_iommu_info);
 160 }
 161
 162 type_init(x86_iommu_register_types)