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cirrus: add option to disable blitter
[qemu/kevin.git] / hw / display / cirrus_vga.c
blob326d511e6085c308da78cb2d60d381c02f498fad
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "trace.h"
32 #include "hw/hw.h"
33 #include "hw/pci/pci.h"
34 #include "ui/console.h"
35 #include "ui/pixel_ops.h"
36 #include "vga_int.h"
37 #include "hw/loader.h"
38
39 /*
40 * TODO:
41 * - destination write mask support not complete (bits 5..7)
42 * - optimize linear mappings
43 * - optimize bitblt functions
44 */
45
46 //#define DEBUG_CIRRUS
47 //#define DEBUG_BITBLT
48
49 /***************************************
50 *
51 * definitions
52 *
53 ***************************************/
54
55 // ID
56 #define CIRRUS_ID_CLGD5422 (0x23<<2)
57 #define CIRRUS_ID_CLGD5426 (0x24<<2)
58 #define CIRRUS_ID_CLGD5424 (0x25<<2)
59 #define CIRRUS_ID_CLGD5428 (0x26<<2)
60 #define CIRRUS_ID_CLGD5430 (0x28<<2)
61 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
62 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
63 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64
65 // sequencer 0x07
66 #define CIRRUS_SR7_BPP_VGA 0x00
67 #define CIRRUS_SR7_BPP_SVGA 0x01
68 #define CIRRUS_SR7_BPP_MASK 0x0e
69 #define CIRRUS_SR7_BPP_8 0x00
70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
71 #define CIRRUS_SR7_BPP_24 0x04
72 #define CIRRUS_SR7_BPP_16 0x06
73 #define CIRRUS_SR7_BPP_32 0x08
74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75
76 // sequencer 0x0f
77 #define CIRRUS_MEMSIZE_512k 0x08
78 #define CIRRUS_MEMSIZE_1M 0x10
79 #define CIRRUS_MEMSIZE_2M 0x18
80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81
82 // sequencer 0x12
83 #define CIRRUS_CURSOR_SHOW 0x01
84 #define CIRRUS_CURSOR_HIDDENPEL 0x02
85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86
87 // sequencer 0x17
88 #define CIRRUS_BUSTYPE_VLBFAST 0x10
89 #define CIRRUS_BUSTYPE_PCI 0x20
90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
91 #define CIRRUS_BUSTYPE_ISA 0x38
92 #define CIRRUS_MMIO_ENABLE 0x04
93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95
96 // control 0x0b
97 #define CIRRUS_BANKING_DUAL 0x01
98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99
100 // control 0x30
101 #define CIRRUS_BLTMODE_BACKWARDS 0x01
102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112
113 // control 0x31
114 #define CIRRUS_BLT_BUSY 0x01
115 #define CIRRUS_BLT_START 0x02
116 #define CIRRUS_BLT_RESET 0x04
117 #define CIRRUS_BLT_FIFOUSED 0x10
118 #define CIRRUS_BLT_AUTOSTART 0x80
119
120 // control 0x32
121 #define CIRRUS_ROP_0 0x00
122 #define CIRRUS_ROP_SRC_AND_DST 0x05
123 #define CIRRUS_ROP_NOP 0x06
124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
125 #define CIRRUS_ROP_NOTDST 0x0b
126 #define CIRRUS_ROP_SRC 0x0d
127 #define CIRRUS_ROP_1 0x0e
128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
129 #define CIRRUS_ROP_SRC_XOR_DST 0x59
130 #define CIRRUS_ROP_SRC_OR_DST 0x6d
131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
134 #define CIRRUS_ROP_NOTSRC 0xd0
135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
137
138 #define CIRRUS_ROP_NOP_INDEX 2
139 #define CIRRUS_ROP_SRC_INDEX 5
140
141 // control 0x33
142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145
146 // memory-mapped IO
147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
157 #define CIRRUS_MMIO_BLTROP 0x1a // byte
158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
176
177 #define CIRRUS_PNPMMIO_SIZE 0x1000
178
179 struct CirrusVGAState;
180 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
181 uint8_t * dst, const uint8_t * src,
182 int dstpitch, int srcpitch,
183 int bltwidth, int bltheight);
184 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
185 uint8_t *dst, int dst_pitch, int width, int height);
186
187 typedef struct CirrusVGAState {
188 VGACommonState vga;
189
190 MemoryRegion cirrus_vga_io;
191 MemoryRegion cirrus_linear_io;
192 MemoryRegion cirrus_linear_bitblt_io;
193 MemoryRegion cirrus_mmio_io;
194 MemoryRegion pci_bar;
195 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
196 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
197 MemoryRegion low_mem; /* always mapped, overridden by: */
198 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
199 uint32_t cirrus_addr_mask;
200 uint32_t linear_mmio_mask;
201 uint8_t cirrus_shadow_gr0;
202 uint8_t cirrus_shadow_gr1;
203 uint8_t cirrus_hidden_dac_lockindex;
204 uint8_t cirrus_hidden_dac_data;
205 uint32_t cirrus_bank_base[2];
206 uint32_t cirrus_bank_limit[2];
207 uint8_t cirrus_hidden_palette[48];
208 bool enable_blitter;
209 int cirrus_blt_pixelwidth;
210 int cirrus_blt_width;
211 int cirrus_blt_height;
212 int cirrus_blt_dstpitch;
213 int cirrus_blt_srcpitch;
214 uint32_t cirrus_blt_fgcol;
215 uint32_t cirrus_blt_bgcol;
216 uint32_t cirrus_blt_dstaddr;
217 uint32_t cirrus_blt_srcaddr;
218 uint8_t cirrus_blt_mode;
219 uint8_t cirrus_blt_modeext;
220 cirrus_bitblt_rop_t cirrus_rop;
221 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
222 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
223 uint8_t *cirrus_srcptr;
224 uint8_t *cirrus_srcptr_end;
225 uint32_t cirrus_srccounter;
226 /* hwcursor display state */
227 int last_hw_cursor_size;
228 int last_hw_cursor_x;
229 int last_hw_cursor_y;
230 int last_hw_cursor_y_start;
231 int last_hw_cursor_y_end;
232 int real_vram_size; /* XXX: suppress that */
233 int device_id;
234 int bustype;
235 } CirrusVGAState;
236
237 typedef struct PCICirrusVGAState {
238 PCIDevice dev;
239 CirrusVGAState cirrus_vga;
240 } PCICirrusVGAState;
241
242 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
243 #define PCI_CIRRUS_VGA(obj) \
244 OBJECT_CHECK(PCICirrusVGAState, (obj), TYPE_PCI_CIRRUS_VGA)
245
246 #define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga"
247 #define ISA_CIRRUS_VGA(obj) \
248 OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA)
249
250 typedef struct ISACirrusVGAState {
251 ISADevice parent_obj;
252
253 CirrusVGAState cirrus_vga;
254 } ISACirrusVGAState;
255
256 static uint8_t rop_to_index[256];
257
258 /***************************************
259 *
260 * prototypes.
261 *
262 ***************************************/
263
264
265 static void cirrus_bitblt_reset(CirrusVGAState *s);
266 static void cirrus_update_memory_access(CirrusVGAState *s);
267
268 /***************************************
269 *
270 * raster operations
271 *
272 ***************************************/
273
274 static bool blit_region_is_unsafe(struct CirrusVGAState *s,
275 int32_t pitch, int32_t addr)
276 {
277 if (!pitch) {
278 return true;
279 }
280 if (pitch < 0) {
281 int64_t min = addr
282 + ((int64_t)s->cirrus_blt_height - 1) * pitch
283 - s->cirrus_blt_width;
284 if (min < -1 || addr >= s->vga.vram_size) {
285 return true;
286 }
287 } else {
288 int64_t max = addr
289 + ((int64_t)s->cirrus_blt_height-1) * pitch
290 + s->cirrus_blt_width;
291 if (max > s->vga.vram_size) {
292 return true;
293 }
294 }
295 return false;
296 }
297
298 static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only)
299 {
300 /* should be the case, see cirrus_bitblt_start */
301 assert(s->cirrus_blt_width > 0);
302 assert(s->cirrus_blt_height > 0);
303
304 if (s->cirrus_blt_width > CIRRUS_BLTBUFSIZE) {
305 return true;
306 }
307
308 if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch,
309 s->cirrus_blt_dstaddr)) {
310 return true;
311 }
312 if (dst_only) {
313 return false;
314 }
315 if (blit_region_is_unsafe(s, s->cirrus_blt_srcpitch,
316 s->cirrus_blt_srcaddr)) {
317 return true;
318 }
319
320 return false;
321 }
322
323 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
324 uint8_t *dst,const uint8_t *src,
325 int dstpitch,int srcpitch,
326 int bltwidth,int bltheight)
327 {
328 }
329
330 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
331 uint8_t *dst,
332 int dstpitch, int bltwidth,int bltheight)
333 {
334 }
335
336 #define ROP_NAME 0
337 #define ROP_FN(d, s) 0
338 #include "cirrus_vga_rop.h"
339
340 #define ROP_NAME src_and_dst
341 #define ROP_FN(d, s) (s) & (d)
342 #include "cirrus_vga_rop.h"
343
344 #define ROP_NAME src_and_notdst
345 #define ROP_FN(d, s) (s) & (~(d))
346 #include "cirrus_vga_rop.h"
347
348 #define ROP_NAME notdst
349 #define ROP_FN(d, s) ~(d)
350 #include "cirrus_vga_rop.h"
351
352 #define ROP_NAME src
353 #define ROP_FN(d, s) s
354 #include "cirrus_vga_rop.h"
355
356 #define ROP_NAME 1
357 #define ROP_FN(d, s) ~0
358 #include "cirrus_vga_rop.h"
359
360 #define ROP_NAME notsrc_and_dst
361 #define ROP_FN(d, s) (~(s)) & (d)
362 #include "cirrus_vga_rop.h"
363
364 #define ROP_NAME src_xor_dst
365 #define ROP_FN(d, s) (s) ^ (d)
366 #include "cirrus_vga_rop.h"
367
368 #define ROP_NAME src_or_dst
369 #define ROP_FN(d, s) (s) | (d)
370 #include "cirrus_vga_rop.h"
371
372 #define ROP_NAME notsrc_or_notdst
373 #define ROP_FN(d, s) (~(s)) | (~(d))
374 #include "cirrus_vga_rop.h"
375
376 #define ROP_NAME src_notxor_dst
377 #define ROP_FN(d, s) ~((s) ^ (d))
378 #include "cirrus_vga_rop.h"
379
380 #define ROP_NAME src_or_notdst
381 #define ROP_FN(d, s) (s) | (~(d))
382 #include "cirrus_vga_rop.h"
383
384 #define ROP_NAME notsrc
385 #define ROP_FN(d, s) (~(s))
386 #include "cirrus_vga_rop.h"
387
388 #define ROP_NAME notsrc_or_dst
389 #define ROP_FN(d, s) (~(s)) | (d)
390 #include "cirrus_vga_rop.h"
391
392 #define ROP_NAME notsrc_and_notdst
393 #define ROP_FN(d, s) (~(s)) & (~(d))
394 #include "cirrus_vga_rop.h"
395
396 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
397 cirrus_bitblt_rop_fwd_0,
398 cirrus_bitblt_rop_fwd_src_and_dst,
399 cirrus_bitblt_rop_nop,
400 cirrus_bitblt_rop_fwd_src_and_notdst,
401 cirrus_bitblt_rop_fwd_notdst,
402 cirrus_bitblt_rop_fwd_src,
403 cirrus_bitblt_rop_fwd_1,
404 cirrus_bitblt_rop_fwd_notsrc_and_dst,
405 cirrus_bitblt_rop_fwd_src_xor_dst,
406 cirrus_bitblt_rop_fwd_src_or_dst,
407 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
408 cirrus_bitblt_rop_fwd_src_notxor_dst,
409 cirrus_bitblt_rop_fwd_src_or_notdst,
410 cirrus_bitblt_rop_fwd_notsrc,
411 cirrus_bitblt_rop_fwd_notsrc_or_dst,
412 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
413 };
414
415 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
416 cirrus_bitblt_rop_bkwd_0,
417 cirrus_bitblt_rop_bkwd_src_and_dst,
418 cirrus_bitblt_rop_nop,
419 cirrus_bitblt_rop_bkwd_src_and_notdst,
420 cirrus_bitblt_rop_bkwd_notdst,
421 cirrus_bitblt_rop_bkwd_src,
422 cirrus_bitblt_rop_bkwd_1,
423 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
424 cirrus_bitblt_rop_bkwd_src_xor_dst,
425 cirrus_bitblt_rop_bkwd_src_or_dst,
426 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
427 cirrus_bitblt_rop_bkwd_src_notxor_dst,
428 cirrus_bitblt_rop_bkwd_src_or_notdst,
429 cirrus_bitblt_rop_bkwd_notsrc,
430 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
431 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
432 };
433
434 #define TRANSP_ROP(name) {\
435 name ## _8,\
436 name ## _16,\
437 }
438 #define TRANSP_NOP(func) {\
439 func,\
440 func,\
441 }
442
443 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
446 TRANSP_NOP(cirrus_bitblt_rop_nop),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
455 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
456 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
457 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
458 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
459 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
460 };
461
462 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
465 TRANSP_NOP(cirrus_bitblt_rop_nop),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
474 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
475 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
476 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
477 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
478 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
479 };
480
481 #define ROP2(name) {\
482 name ## _8,\
483 name ## _16,\
484 name ## _24,\
485 name ## _32,\
486 }
487
488 #define ROP_NOP2(func) {\
489 func,\
490 func,\
491 func,\
492 func,\
493 }
494
495 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
496 ROP2(cirrus_patternfill_0),
497 ROP2(cirrus_patternfill_src_and_dst),
498 ROP_NOP2(cirrus_bitblt_rop_nop),
499 ROP2(cirrus_patternfill_src_and_notdst),
500 ROP2(cirrus_patternfill_notdst),
501 ROP2(cirrus_patternfill_src),
502 ROP2(cirrus_patternfill_1),
503 ROP2(cirrus_patternfill_notsrc_and_dst),
504 ROP2(cirrus_patternfill_src_xor_dst),
505 ROP2(cirrus_patternfill_src_or_dst),
506 ROP2(cirrus_patternfill_notsrc_or_notdst),
507 ROP2(cirrus_patternfill_src_notxor_dst),
508 ROP2(cirrus_patternfill_src_or_notdst),
509 ROP2(cirrus_patternfill_notsrc),
510 ROP2(cirrus_patternfill_notsrc_or_dst),
511 ROP2(cirrus_patternfill_notsrc_and_notdst),
512 };
513
514 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
515 ROP2(cirrus_colorexpand_transp_0),
516 ROP2(cirrus_colorexpand_transp_src_and_dst),
517 ROP_NOP2(cirrus_bitblt_rop_nop),
518 ROP2(cirrus_colorexpand_transp_src_and_notdst),
519 ROP2(cirrus_colorexpand_transp_notdst),
520 ROP2(cirrus_colorexpand_transp_src),
521 ROP2(cirrus_colorexpand_transp_1),
522 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
523 ROP2(cirrus_colorexpand_transp_src_xor_dst),
524 ROP2(cirrus_colorexpand_transp_src_or_dst),
525 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
526 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
527 ROP2(cirrus_colorexpand_transp_src_or_notdst),
528 ROP2(cirrus_colorexpand_transp_notsrc),
529 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
530 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
531 };
532
533 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
534 ROP2(cirrus_colorexpand_0),
535 ROP2(cirrus_colorexpand_src_and_dst),
536 ROP_NOP2(cirrus_bitblt_rop_nop),
537 ROP2(cirrus_colorexpand_src_and_notdst),
538 ROP2(cirrus_colorexpand_notdst),
539 ROP2(cirrus_colorexpand_src),
540 ROP2(cirrus_colorexpand_1),
541 ROP2(cirrus_colorexpand_notsrc_and_dst),
542 ROP2(cirrus_colorexpand_src_xor_dst),
543 ROP2(cirrus_colorexpand_src_or_dst),
544 ROP2(cirrus_colorexpand_notsrc_or_notdst),
545 ROP2(cirrus_colorexpand_src_notxor_dst),
546 ROP2(cirrus_colorexpand_src_or_notdst),
547 ROP2(cirrus_colorexpand_notsrc),
548 ROP2(cirrus_colorexpand_notsrc_or_dst),
549 ROP2(cirrus_colorexpand_notsrc_and_notdst),
550 };
551
552 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
553 ROP2(cirrus_colorexpand_pattern_transp_0),
554 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
555 ROP_NOP2(cirrus_bitblt_rop_nop),
556 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
557 ROP2(cirrus_colorexpand_pattern_transp_notdst),
558 ROP2(cirrus_colorexpand_pattern_transp_src),
559 ROP2(cirrus_colorexpand_pattern_transp_1),
560 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
561 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
562 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
563 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
564 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
565 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
566 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
567 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
568 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
569 };
570
571 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
572 ROP2(cirrus_colorexpand_pattern_0),
573 ROP2(cirrus_colorexpand_pattern_src_and_dst),
574 ROP_NOP2(cirrus_bitblt_rop_nop),
575 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
576 ROP2(cirrus_colorexpand_pattern_notdst),
577 ROP2(cirrus_colorexpand_pattern_src),
578 ROP2(cirrus_colorexpand_pattern_1),
579 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
580 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
581 ROP2(cirrus_colorexpand_pattern_src_or_dst),
582 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
583 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
584 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
585 ROP2(cirrus_colorexpand_pattern_notsrc),
586 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
587 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
588 };
589
590 static const cirrus_fill_t cirrus_fill[16][4] = {
591 ROP2(cirrus_fill_0),
592 ROP2(cirrus_fill_src_and_dst),
593 ROP_NOP2(cirrus_bitblt_fill_nop),
594 ROP2(cirrus_fill_src_and_notdst),
595 ROP2(cirrus_fill_notdst),
596 ROP2(cirrus_fill_src),
597 ROP2(cirrus_fill_1),
598 ROP2(cirrus_fill_notsrc_and_dst),
599 ROP2(cirrus_fill_src_xor_dst),
600 ROP2(cirrus_fill_src_or_dst),
601 ROP2(cirrus_fill_notsrc_or_notdst),
602 ROP2(cirrus_fill_src_notxor_dst),
603 ROP2(cirrus_fill_src_or_notdst),
604 ROP2(cirrus_fill_notsrc),
605 ROP2(cirrus_fill_notsrc_or_dst),
606 ROP2(cirrus_fill_notsrc_and_notdst),
607 };
608
609 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
610 {
611 unsigned int color;
612 switch (s->cirrus_blt_pixelwidth) {
613 case 1:
614 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
615 break;
616 case 2:
617 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
618 s->cirrus_blt_fgcol = le16_to_cpu(color);
619 break;
620 case 3:
621 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
622 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
623 break;
624 default:
625 case 4:
626 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
627 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
628 s->cirrus_blt_fgcol = le32_to_cpu(color);
629 break;
630 }
631 }
632
633 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
634 {
635 unsigned int color;
636 switch (s->cirrus_blt_pixelwidth) {
637 case 1:
638 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
639 break;
640 case 2:
641 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
642 s->cirrus_blt_bgcol = le16_to_cpu(color);
643 break;
644 case 3:
645 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
646 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
647 break;
648 default:
649 case 4:
650 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
651 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
652 s->cirrus_blt_bgcol = le32_to_cpu(color);
653 break;
654 }
655 }
656
657 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
658 int off_pitch, int bytesperline,
659 int lines)
660 {
661 int y;
662 int off_cur;
663 int off_cur_end;
664
665 if (off_pitch < 0) {
666 off_begin -= bytesperline - 1;
667 }
668
669 for (y = 0; y < lines; y++) {
670 off_cur = off_begin;
671 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
672 assert(off_cur_end >= off_cur);
673 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
674 off_begin += off_pitch;
675 }
676 }
677
678 static int cirrus_bitblt_common_patterncopy(CirrusVGAState *s, bool videosrc)
679 {
680 uint32_t patternsize;
681 uint8_t *dst;
682 uint8_t *src;
683
684 dst = s->vga.vram_ptr + s->cirrus_blt_dstaddr;
685
686 if (videosrc) {
687 switch (s->vga.get_bpp(&s->vga)) {
688 case 8:
689 patternsize = 64;
690 break;
691 case 15:
692 case 16:
693 patternsize = 128;
694 break;
695 case 24:
696 case 32:
697 default:
698 patternsize = 256;
699 break;
700 }
701 s->cirrus_blt_srcaddr &= ~(patternsize - 1);
702 if (s->cirrus_blt_srcaddr + patternsize > s->vga.vram_size) {
703 return 0;
704 }
705 src = s->vga.vram_ptr + s->cirrus_blt_srcaddr;
706 } else {
707 src = s->cirrus_bltbuf;
708 }
709
710 if (blit_is_unsafe(s, true)) {
711 return 0;
712 }
713
714 (*s->cirrus_rop) (s, dst, src,
715 s->cirrus_blt_dstpitch, 0,
716 s->cirrus_blt_width, s->cirrus_blt_height);
717 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
718 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
719 s->cirrus_blt_height);
720 return 1;
721 }
722
723 /* fill */
724
725 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
726 {
727 cirrus_fill_t rop_func;
728
729 if (blit_is_unsafe(s, true)) {
730 return 0;
731 }
732 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
733 rop_func(s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
734 s->cirrus_blt_dstpitch,
735 s->cirrus_blt_width, s->cirrus_blt_height);
736 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
737 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
738 s->cirrus_blt_height);
739 cirrus_bitblt_reset(s);
740 return 1;
741 }
742
743 /***************************************
744 *
745 * bitblt (video-to-video)
746 *
747 ***************************************/
748
749 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
750 {
751 return cirrus_bitblt_common_patterncopy(s, true);
752 }
753
754 static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
755 {
756 int sx = 0, sy = 0;
757 int dx = 0, dy = 0;
758 int depth = 0;
759 int notify = 0;
760
761 /* make sure to only copy if it's a plain copy ROP */
762 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
763 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
764
765 int width, height;
766
767 depth = s->vga.get_bpp(&s->vga) / 8;
768 if (!depth) {
769 return 0;
770 }
771 s->vga.get_resolution(&s->vga, &width, &height);
772
773 /* extra x, y */
774 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
775 sy = (src / ABS(s->cirrus_blt_srcpitch));
776 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
777 dy = (dst / ABS(s->cirrus_blt_dstpitch));
778
779 /* normalize width */
780 w /= depth;
781
782 /* if we're doing a backward copy, we have to adjust
783 our x/y to be the upper left corner (instead of the lower
784 right corner) */
785 if (s->cirrus_blt_dstpitch < 0) {
786 sx -= (s->cirrus_blt_width / depth) - 1;
787 dx -= (s->cirrus_blt_width / depth) - 1;
788 sy -= s->cirrus_blt_height - 1;
789 dy -= s->cirrus_blt_height - 1;
790 }
791
792 /* are we in the visible portion of memory? */
793 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
794 (sx + w) <= width && (sy + h) <= height &&
795 (dx + w) <= width && (dy + h) <= height) {
796 notify = 1;
797 }
798 }
799
800 (*s->cirrus_rop) (s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
801 s->vga.vram_ptr + s->cirrus_blt_srcaddr,
802 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
803 s->cirrus_blt_width, s->cirrus_blt_height);
804
805 if (notify) {
806 dpy_gfx_update(s->vga.con, dx, dy,
807 s->cirrus_blt_width / depth,
808 s->cirrus_blt_height);
809 }
810
811 /* we don't have to notify the display that this portion has
812 changed since qemu_console_copy implies this */
813
814 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
815 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
816 s->cirrus_blt_height);
817
818 return 1;
819 }
820
821 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
822 {
823 if (blit_is_unsafe(s, false))
824 return 0;
825
826 return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
827 s->cirrus_blt_srcaddr - s->vga.start_addr,
828 s->cirrus_blt_width, s->cirrus_blt_height);
829 }
830
831 /***************************************
832 *
833 * bitblt (cpu-to-video)
834 *
835 ***************************************/
836
837 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
838 {
839 int copy_count;
840 uint8_t *end_ptr;
841
842 if (s->cirrus_srccounter > 0) {
843 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
844 cirrus_bitblt_common_patterncopy(s, false);
845 the_end:
846 s->cirrus_srccounter = 0;
847 cirrus_bitblt_reset(s);
848 } else {
849 /* at least one scan line */
850 do {
851 (*s->cirrus_rop)(s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
852 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
853 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
854 s->cirrus_blt_width, 1);
855 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
856 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
857 if (s->cirrus_srccounter <= 0)
858 goto the_end;
859 /* more bytes than needed can be transferred because of
860 word alignment, so we keep them for the next line */
861 /* XXX: keep alignment to speed up transfer */
862 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
863 copy_count = s->cirrus_srcptr_end - end_ptr;
864 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
865 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
866 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
867 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
868 }
869 }
870 }
871
872 /***************************************
873 *
874 * bitblt wrapper
875 *
876 ***************************************/
877
878 static void cirrus_bitblt_reset(CirrusVGAState * s)
879 {
880 int need_update;
881
882 s->vga.gr[0x31] &=
883 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
884 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
885 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
886 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
887 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
888 s->cirrus_srccounter = 0;
889 if (!need_update)
890 return;
891 cirrus_update_memory_access(s);
892 }
893
894 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
895 {
896 int w;
897
898 if (blit_is_unsafe(s, true)) {
899 return 0;
900 }
901
902 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
903 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
904 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
905
906 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
907 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
908 s->cirrus_blt_srcpitch = 8;
909 } else {
910 /* XXX: check for 24 bpp */
911 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
912 }
913 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
914 } else {
915 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
916 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
917 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
918 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
919 else
920 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
921 } else {
922 /* always align input size to 32 bits */
923 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
924 }
925 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
926 }
927
928 /* the blit_is_unsafe call above should catch this */
929 assert(s->cirrus_blt_srcpitch <= CIRRUS_BLTBUFSIZE);
930
931 s->cirrus_srcptr = s->cirrus_bltbuf;
932 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
933 cirrus_update_memory_access(s);
934 return 1;
935 }
936
937 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
938 {
939 /* XXX */
940 #ifdef DEBUG_BITBLT
941 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
942 #endif
943 return 0;
944 }
945
946 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
947 {
948 int ret;
949
950 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
951 ret = cirrus_bitblt_videotovideo_patterncopy(s);
952 } else {
953 ret = cirrus_bitblt_videotovideo_copy(s);
954 }
955 if (ret)
956 cirrus_bitblt_reset(s);
957 return ret;
958 }
959
960 static void cirrus_bitblt_start(CirrusVGAState * s)
961 {
962 uint8_t blt_rop;
963
964 if (!s->enable_blitter) {
965 goto bitblt_ignore;
966 }
967
968 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
969
970 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
971 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
972 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
973 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
974 s->cirrus_blt_dstaddr =
975 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
976 s->cirrus_blt_srcaddr =
977 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
978 s->cirrus_blt_mode = s->vga.gr[0x30];
979 s->cirrus_blt_modeext = s->vga.gr[0x33];
980 blt_rop = s->vga.gr[0x32];
981
982 s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
983 s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
984
985 #ifdef DEBUG_BITBLT
986 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
987 blt_rop,
988 s->cirrus_blt_mode,
989 s->cirrus_blt_modeext,
990 s->cirrus_blt_width,
991 s->cirrus_blt_height,
992 s->cirrus_blt_dstpitch,
993 s->cirrus_blt_srcpitch,
994 s->cirrus_blt_dstaddr,
995 s->cirrus_blt_srcaddr,
996 s->vga.gr[0x2f]);
997 #endif
998
999 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
1000 case CIRRUS_BLTMODE_PIXELWIDTH8:
1001 s->cirrus_blt_pixelwidth = 1;
1002 break;
1003 case CIRRUS_BLTMODE_PIXELWIDTH16:
1004 s->cirrus_blt_pixelwidth = 2;
1005 break;
1006 case CIRRUS_BLTMODE_PIXELWIDTH24:
1007 s->cirrus_blt_pixelwidth = 3;
1008 break;
1009 case CIRRUS_BLTMODE_PIXELWIDTH32:
1010 s->cirrus_blt_pixelwidth = 4;
1011 break;
1012 default:
1013 #ifdef DEBUG_BITBLT
1014 printf("cirrus: bitblt - pixel width is unknown\n");
1015 #endif
1016 goto bitblt_ignore;
1017 }
1018 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
1019
1020 if ((s->
1021 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
1022 CIRRUS_BLTMODE_MEMSYSDEST))
1023 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
1024 #ifdef DEBUG_BITBLT
1025 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
1026 #endif
1027 goto bitblt_ignore;
1028 }
1029
1030 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
1031 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
1032 CIRRUS_BLTMODE_TRANSPARENTCOMP |
1033 CIRRUS_BLTMODE_PATTERNCOPY |
1034 CIRRUS_BLTMODE_COLOREXPAND)) ==
1035 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
1036 cirrus_bitblt_fgcol(s);
1037 cirrus_bitblt_solidfill(s, blt_rop);
1038 } else {
1039 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1040 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1041 CIRRUS_BLTMODE_COLOREXPAND) {
1042
1043 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1044 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1045 cirrus_bitblt_bgcol(s);
1046 else
1047 cirrus_bitblt_fgcol(s);
1048 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1049 } else {
1050 cirrus_bitblt_fgcol(s);
1051 cirrus_bitblt_bgcol(s);
1052 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1053 }
1054 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1055 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1056 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1057 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1058 cirrus_bitblt_bgcol(s);
1059 else
1060 cirrus_bitblt_fgcol(s);
1061 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1062 } else {
1063 cirrus_bitblt_fgcol(s);
1064 cirrus_bitblt_bgcol(s);
1065 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1066 }
1067 } else {
1068 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1069 }
1070 } else {
1071 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1072 if (s->cirrus_blt_pixelwidth > 2) {
1073 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1074 goto bitblt_ignore;
1075 }
1076 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1077 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1078 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1079 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1080 } else {
1081 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1082 }
1083 } else {
1084 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1085 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1086 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1087 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1088 } else {
1089 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1090 }
1091 }
1092 }
1093 // setup bitblt engine.
1094 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1095 if (!cirrus_bitblt_cputovideo(s))
1096 goto bitblt_ignore;
1097 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1098 if (!cirrus_bitblt_videotocpu(s))
1099 goto bitblt_ignore;
1100 } else {
1101 if (!cirrus_bitblt_videotovideo(s))
1102 goto bitblt_ignore;
1103 }
1104 }
1105 return;
1106 bitblt_ignore:;
1107 cirrus_bitblt_reset(s);
1108 }
1109
1110 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1111 {
1112 unsigned old_value;
1113
1114 old_value = s->vga.gr[0x31];
1115 s->vga.gr[0x31] = reg_value;
1116
1117 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1118 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1119 cirrus_bitblt_reset(s);
1120 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1121 ((reg_value & CIRRUS_BLT_START) != 0)) {
1122 cirrus_bitblt_start(s);
1123 }
1124 }
1125
1126
1127 /***************************************
1128 *
1129 * basic parameters
1130 *
1131 ***************************************/
1132
1133 static void cirrus_get_offsets(VGACommonState *s1,
1134 uint32_t *pline_offset,
1135 uint32_t *pstart_addr,
1136 uint32_t *pline_compare)
1137 {
1138 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1139 uint32_t start_addr, line_offset, line_compare;
1140
1141 line_offset = s->vga.cr[0x13]
1142 | ((s->vga.cr[0x1b] & 0x10) << 4);
1143 line_offset <<= 3;
1144 *pline_offset = line_offset;
1145
1146 start_addr = (s->vga.cr[0x0c] << 8)
1147 | s->vga.cr[0x0d]
1148 | ((s->vga.cr[0x1b] & 0x01) << 16)
1149 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1150 | ((s->vga.cr[0x1d] & 0x80) << 12);
1151 *pstart_addr = start_addr;
1152
1153 line_compare = s->vga.cr[0x18] |
1154 ((s->vga.cr[0x07] & 0x10) << 4) |
1155 ((s->vga.cr[0x09] & 0x40) << 3);
1156 *pline_compare = line_compare;
1157 }
1158
1159 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1160 {
1161 uint32_t ret = 16;
1162
1163 switch (s->cirrus_hidden_dac_data & 0xf) {
1164 case 0:
1165 ret = 15;
1166 break; /* Sierra HiColor */
1167 case 1:
1168 ret = 16;
1169 break; /* XGA HiColor */
1170 default:
1171 #ifdef DEBUG_CIRRUS
1172 printf("cirrus: invalid DAC value %x in 16bpp\n",
1173 (s->cirrus_hidden_dac_data & 0xf));
1174 #endif
1175 ret = 15; /* XXX */
1176 break;
1177 }
1178 return ret;
1179 }
1180
1181 static int cirrus_get_bpp(VGACommonState *s1)
1182 {
1183 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1184 uint32_t ret = 8;
1185
1186 if ((s->vga.sr[0x07] & 0x01) != 0) {
1187 /* Cirrus SVGA */
1188 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1189 case CIRRUS_SR7_BPP_8:
1190 ret = 8;
1191 break;
1192 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1193 ret = cirrus_get_bpp16_depth(s);
1194 break;
1195 case CIRRUS_SR7_BPP_24:
1196 ret = 24;
1197 break;
1198 case CIRRUS_SR7_BPP_16:
1199 ret = cirrus_get_bpp16_depth(s);
1200 break;
1201 case CIRRUS_SR7_BPP_32:
1202 ret = 32;
1203 break;
1204 default:
1205 #ifdef DEBUG_CIRRUS
1206 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1207 #endif
1208 ret = 8;
1209 break;
1210 }
1211 } else {
1212 /* VGA */
1213 ret = 0;
1214 }
1215
1216 return ret;
1217 }
1218
1219 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1220 {
1221 int width, height;
1222
1223 width = (s->cr[0x01] + 1) * 8;
1224 height = s->cr[0x12] |
1225 ((s->cr[0x07] & 0x02) << 7) |
1226 ((s->cr[0x07] & 0x40) << 3);
1227 height = (height + 1);
1228 /* interlace support */
1229 if (s->cr[0x1a] & 0x01)
1230 height = height * 2;
1231 *pwidth = width;
1232 *pheight = height;
1233 }
1234
1235 /***************************************
1236 *
1237 * bank memory
1238 *
1239 ***************************************/
1240
1241 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1242 {
1243 unsigned offset;
1244 unsigned limit;
1245
1246 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1247 offset = s->vga.gr[0x09 + bank_index];
1248 else /* single bank */
1249 offset = s->vga.gr[0x09];
1250
1251 if ((s->vga.gr[0x0b] & 0x20) != 0)
1252 offset <<= 14;
1253 else
1254 offset <<= 12;
1255
1256 if (s->real_vram_size <= offset)
1257 limit = 0;
1258 else
1259 limit = s->real_vram_size - offset;
1260
1261 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1262 if (limit > 0x8000) {
1263 offset += 0x8000;
1264 limit -= 0x8000;
1265 } else {
1266 limit = 0;
1267 }
1268 }
1269
1270 if (limit > 0) {
1271 s->cirrus_bank_base[bank_index] = offset;
1272 s->cirrus_bank_limit[bank_index] = limit;
1273 } else {
1274 s->cirrus_bank_base[bank_index] = 0;
1275 s->cirrus_bank_limit[bank_index] = 0;
1276 }
1277 }
1278
1279 /***************************************
1280 *
1281 * I/O access between 0x3c4-0x3c5
1282 *
1283 ***************************************/
1284
1285 static int cirrus_vga_read_sr(CirrusVGAState * s)
1286 {
1287 switch (s->vga.sr_index) {
1288 case 0x00: // Standard VGA
1289 case 0x01: // Standard VGA
1290 case 0x02: // Standard VGA
1291 case 0x03: // Standard VGA
1292 case 0x04: // Standard VGA
1293 return s->vga.sr[s->vga.sr_index];
1294 case 0x06: // Unlock Cirrus extensions
1295 return s->vga.sr[s->vga.sr_index];
1296 case 0x10:
1297 case 0x30:
1298 case 0x50:
1299 case 0x70: // Graphics Cursor X
1300 case 0x90:
1301 case 0xb0:
1302 case 0xd0:
1303 case 0xf0: // Graphics Cursor X
1304 return s->vga.sr[0x10];
1305 case 0x11:
1306 case 0x31:
1307 case 0x51:
1308 case 0x71: // Graphics Cursor Y
1309 case 0x91:
1310 case 0xb1:
1311 case 0xd1:
1312 case 0xf1: // Graphics Cursor Y
1313 return s->vga.sr[0x11];
1314 case 0x05: // ???
1315 case 0x07: // Extended Sequencer Mode
1316 case 0x08: // EEPROM Control
1317 case 0x09: // Scratch Register 0
1318 case 0x0a: // Scratch Register 1
1319 case 0x0b: // VCLK 0
1320 case 0x0c: // VCLK 1
1321 case 0x0d: // VCLK 2
1322 case 0x0e: // VCLK 3
1323 case 0x0f: // DRAM Control
1324 case 0x12: // Graphics Cursor Attribute
1325 case 0x13: // Graphics Cursor Pattern Address
1326 case 0x14: // Scratch Register 2
1327 case 0x15: // Scratch Register 3
1328 case 0x16: // Performance Tuning Register
1329 case 0x17: // Configuration Readback and Extended Control
1330 case 0x18: // Signature Generator Control
1331 case 0x19: // Signal Generator Result
1332 case 0x1a: // Signal Generator Result
1333 case 0x1b: // VCLK 0 Denominator & Post
1334 case 0x1c: // VCLK 1 Denominator & Post
1335 case 0x1d: // VCLK 2 Denominator & Post
1336 case 0x1e: // VCLK 3 Denominator & Post
1337 case 0x1f: // BIOS Write Enable and MCLK select
1338 #ifdef DEBUG_CIRRUS
1339 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
1340 #endif
1341 return s->vga.sr[s->vga.sr_index];
1342 default:
1343 #ifdef DEBUG_CIRRUS
1344 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
1345 #endif
1346 return 0xff;
1347 break;
1348 }
1349 }
1350
1351 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
1352 {
1353 switch (s->vga.sr_index) {
1354 case 0x00: // Standard VGA
1355 case 0x01: // Standard VGA
1356 case 0x02: // Standard VGA
1357 case 0x03: // Standard VGA
1358 case 0x04: // Standard VGA
1359 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1360 if (s->vga.sr_index == 1)
1361 s->vga.update_retrace_info(&s->vga);
1362 break;
1363 case 0x06: // Unlock Cirrus extensions
1364 val &= 0x17;
1365 if (val == 0x12) {
1366 s->vga.sr[s->vga.sr_index] = 0x12;
1367 } else {
1368 s->vga.sr[s->vga.sr_index] = 0x0f;
1369 }
1370 break;
1371 case 0x10:
1372 case 0x30:
1373 case 0x50:
1374 case 0x70: // Graphics Cursor X
1375 case 0x90:
1376 case 0xb0:
1377 case 0xd0:
1378 case 0xf0: // Graphics Cursor X
1379 s->vga.sr[0x10] = val;
1380 s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
1381 break;
1382 case 0x11:
1383 case 0x31:
1384 case 0x51:
1385 case 0x71: // Graphics Cursor Y
1386 case 0x91:
1387 case 0xb1:
1388 case 0xd1:
1389 case 0xf1: // Graphics Cursor Y
1390 s->vga.sr[0x11] = val;
1391 s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
1392 break;
1393 case 0x07: // Extended Sequencer Mode
1394 cirrus_update_memory_access(s);
1395 case 0x08: // EEPROM Control
1396 case 0x09: // Scratch Register 0
1397 case 0x0a: // Scratch Register 1
1398 case 0x0b: // VCLK 0
1399 case 0x0c: // VCLK 1
1400 case 0x0d: // VCLK 2
1401 case 0x0e: // VCLK 3
1402 case 0x0f: // DRAM Control
1403 case 0x13: // Graphics Cursor Pattern Address
1404 case 0x14: // Scratch Register 2
1405 case 0x15: // Scratch Register 3
1406 case 0x16: // Performance Tuning Register
1407 case 0x18: // Signature Generator Control
1408 case 0x19: // Signature Generator Result
1409 case 0x1a: // Signature Generator Result
1410 case 0x1b: // VCLK 0 Denominator & Post
1411 case 0x1c: // VCLK 1 Denominator & Post
1412 case 0x1d: // VCLK 2 Denominator & Post
1413 case 0x1e: // VCLK 3 Denominator & Post
1414 case 0x1f: // BIOS Write Enable and MCLK select
1415 s->vga.sr[s->vga.sr_index] = val;
1416 #ifdef DEBUG_CIRRUS
1417 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1418 s->vga.sr_index, val);
1419 #endif
1420 break;
1421 case 0x12: // Graphics Cursor Attribute
1422 s->vga.sr[0x12] = val;
1423 s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW);
1424 #ifdef DEBUG_CIRRUS
1425 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
1426 val, s->vga.force_shadow);
1427 #endif
1428 break;
1429 case 0x17: // Configuration Readback and Extended Control
1430 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1431 | (val & 0xc7);
1432 cirrus_update_memory_access(s);
1433 break;
1434 default:
1435 #ifdef DEBUG_CIRRUS
1436 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1437 s->vga.sr_index, val);
1438 #endif
1439 break;
1440 }
1441 }
1442
1443 /***************************************
1444 *
1445 * I/O access at 0x3c6
1446 *
1447 ***************************************/
1448
1449 static int cirrus_read_hidden_dac(CirrusVGAState * s)
1450 {
1451 if (++s->cirrus_hidden_dac_lockindex == 5) {
1452 s->cirrus_hidden_dac_lockindex = 0;
1453 return s->cirrus_hidden_dac_data;
1454 }
1455 return 0xff;
1456 }
1457
1458 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1459 {
1460 if (s->cirrus_hidden_dac_lockindex == 4) {
1461 s->cirrus_hidden_dac_data = reg_value;
1462 #if defined(DEBUG_CIRRUS)
1463 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1464 #endif
1465 }
1466 s->cirrus_hidden_dac_lockindex = 0;
1467 }
1468
1469 /***************************************
1470 *
1471 * I/O access at 0x3c9
1472 *
1473 ***************************************/
1474
1475 static int cirrus_vga_read_palette(CirrusVGAState * s)
1476 {
1477 int val;
1478
1479 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1480 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1481 s->vga.dac_sub_index];
1482 } else {
1483 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1484 }
1485 if (++s->vga.dac_sub_index == 3) {
1486 s->vga.dac_sub_index = 0;
1487 s->vga.dac_read_index++;
1488 }
1489 return val;
1490 }
1491
1492 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
1493 {
1494 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1495 if (++s->vga.dac_sub_index == 3) {
1496 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1497 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1498 s->vga.dac_cache, 3);
1499 } else {
1500 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1501 }
1502 /* XXX update cursor */
1503 s->vga.dac_sub_index = 0;
1504 s->vga.dac_write_index++;
1505 }
1506 }
1507
1508 /***************************************
1509 *
1510 * I/O access between 0x3ce-0x3cf
1511 *
1512 ***************************************/
1513
1514 static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
1515 {
1516 switch (reg_index) {
1517 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1518 return s->cirrus_shadow_gr0;
1519 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1520 return s->cirrus_shadow_gr1;
1521 case 0x02: // Standard VGA
1522 case 0x03: // Standard VGA
1523 case 0x04: // Standard VGA
1524 case 0x06: // Standard VGA
1525 case 0x07: // Standard VGA
1526 case 0x08: // Standard VGA
1527 return s->vga.gr[s->vga.gr_index];
1528 case 0x05: // Standard VGA, Cirrus extended mode
1529 default:
1530 break;
1531 }
1532
1533 if (reg_index < 0x3a) {
1534 return s->vga.gr[reg_index];
1535 } else {
1536 #ifdef DEBUG_CIRRUS
1537 printf("cirrus: inport gr_index %02x\n", reg_index);
1538 #endif
1539 return 0xff;
1540 }
1541 }
1542
1543 static void
1544 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1545 {
1546 #if defined(DEBUG_BITBLT) && 0
1547 printf("gr%02x: %02x\n", reg_index, reg_value);
1548 #endif
1549 switch (reg_index) {
1550 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1551 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1552 s->cirrus_shadow_gr0 = reg_value;
1553 break;
1554 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1555 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1556 s->cirrus_shadow_gr1 = reg_value;
1557 break;
1558 case 0x02: // Standard VGA
1559 case 0x03: // Standard VGA
1560 case 0x04: // Standard VGA
1561 case 0x06: // Standard VGA
1562 case 0x07: // Standard VGA
1563 case 0x08: // Standard VGA
1564 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1565 break;
1566 case 0x05: // Standard VGA, Cirrus extended mode
1567 s->vga.gr[reg_index] = reg_value & 0x7f;
1568 cirrus_update_memory_access(s);
1569 break;
1570 case 0x09: // bank offset #0
1571 case 0x0A: // bank offset #1
1572 s->vga.gr[reg_index] = reg_value;
1573 cirrus_update_bank_ptr(s, 0);
1574 cirrus_update_bank_ptr(s, 1);
1575 cirrus_update_memory_access(s);
1576 break;
1577 case 0x0B:
1578 s->vga.gr[reg_index] = reg_value;
1579 cirrus_update_bank_ptr(s, 0);
1580 cirrus_update_bank_ptr(s, 1);
1581 cirrus_update_memory_access(s);
1582 break;
1583 case 0x10: // BGCOLOR 0x0000ff00
1584 case 0x11: // FGCOLOR 0x0000ff00
1585 case 0x12: // BGCOLOR 0x00ff0000
1586 case 0x13: // FGCOLOR 0x00ff0000
1587 case 0x14: // BGCOLOR 0xff000000
1588 case 0x15: // FGCOLOR 0xff000000
1589 case 0x20: // BLT WIDTH 0x0000ff
1590 case 0x22: // BLT HEIGHT 0x0000ff
1591 case 0x24: // BLT DEST PITCH 0x0000ff
1592 case 0x26: // BLT SRC PITCH 0x0000ff
1593 case 0x28: // BLT DEST ADDR 0x0000ff
1594 case 0x29: // BLT DEST ADDR 0x00ff00
1595 case 0x2c: // BLT SRC ADDR 0x0000ff
1596 case 0x2d: // BLT SRC ADDR 0x00ff00
1597 case 0x2f: // BLT WRITEMASK
1598 case 0x30: // BLT MODE
1599 case 0x32: // RASTER OP
1600 case 0x33: // BLT MODEEXT
1601 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1602 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1603 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1604 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1605 s->vga.gr[reg_index] = reg_value;
1606 break;
1607 case 0x21: // BLT WIDTH 0x001f00
1608 case 0x23: // BLT HEIGHT 0x001f00
1609 case 0x25: // BLT DEST PITCH 0x001f00
1610 case 0x27: // BLT SRC PITCH 0x001f00
1611 s->vga.gr[reg_index] = reg_value & 0x1f;
1612 break;
1613 case 0x2a: // BLT DEST ADDR 0x3f0000
1614 s->vga.gr[reg_index] = reg_value & 0x3f;
1615 /* if auto start mode, starts bit blt now */
1616 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1617 cirrus_bitblt_start(s);
1618 }
1619 break;
1620 case 0x2e: // BLT SRC ADDR 0x3f0000
1621 s->vga.gr[reg_index] = reg_value & 0x3f;
1622 break;
1623 case 0x31: // BLT STATUS/START
1624 cirrus_write_bitblt(s, reg_value);
1625 break;
1626 default:
1627 #ifdef DEBUG_CIRRUS
1628 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1629 reg_value);
1630 #endif
1631 break;
1632 }
1633 }
1634
1635 /***************************************
1636 *
1637 * I/O access between 0x3d4-0x3d5
1638 *
1639 ***************************************/
1640
1641 static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
1642 {
1643 switch (reg_index) {
1644 case 0x00: // Standard VGA
1645 case 0x01: // Standard VGA
1646 case 0x02: // Standard VGA
1647 case 0x03: // Standard VGA
1648 case 0x04: // Standard VGA
1649 case 0x05: // Standard VGA
1650 case 0x06: // Standard VGA
1651 case 0x07: // Standard VGA
1652 case 0x08: // Standard VGA
1653 case 0x09: // Standard VGA
1654 case 0x0a: // Standard VGA
1655 case 0x0b: // Standard VGA
1656 case 0x0c: // Standard VGA
1657 case 0x0d: // Standard VGA
1658 case 0x0e: // Standard VGA
1659 case 0x0f: // Standard VGA
1660 case 0x10: // Standard VGA
1661 case 0x11: // Standard VGA
1662 case 0x12: // Standard VGA
1663 case 0x13: // Standard VGA
1664 case 0x14: // Standard VGA
1665 case 0x15: // Standard VGA
1666 case 0x16: // Standard VGA
1667 case 0x17: // Standard VGA
1668 case 0x18: // Standard VGA
1669 return s->vga.cr[s->vga.cr_index];
1670 case 0x24: // Attribute Controller Toggle Readback (R)
1671 return (s->vga.ar_flip_flop << 7);
1672 case 0x19: // Interlace End
1673 case 0x1a: // Miscellaneous Control
1674 case 0x1b: // Extended Display Control
1675 case 0x1c: // Sync Adjust and Genlock
1676 case 0x1d: // Overlay Extended Control
1677 case 0x22: // Graphics Data Latches Readback (R)
1678 case 0x25: // Part Status
1679 case 0x27: // Part ID (R)
1680 return s->vga.cr[s->vga.cr_index];
1681 case 0x26: // Attribute Controller Index Readback (R)
1682 return s->vga.ar_index & 0x3f;
1683 break;
1684 default:
1685 #ifdef DEBUG_CIRRUS
1686 printf("cirrus: inport cr_index %02x\n", reg_index);
1687 #endif
1688 return 0xff;
1689 }
1690 }
1691
1692 static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
1693 {
1694 switch (s->vga.cr_index) {
1695 case 0x00: // Standard VGA
1696 case 0x01: // Standard VGA
1697 case 0x02: // Standard VGA
1698 case 0x03: // Standard VGA
1699 case 0x04: // Standard VGA
1700 case 0x05: // Standard VGA
1701 case 0x06: // Standard VGA
1702 case 0x07: // Standard VGA
1703 case 0x08: // Standard VGA
1704 case 0x09: // Standard VGA
1705 case 0x0a: // Standard VGA
1706 case 0x0b: // Standard VGA
1707 case 0x0c: // Standard VGA
1708 case 0x0d: // Standard VGA
1709 case 0x0e: // Standard VGA
1710 case 0x0f: // Standard VGA
1711 case 0x10: // Standard VGA
1712 case 0x11: // Standard VGA
1713 case 0x12: // Standard VGA
1714 case 0x13: // Standard VGA
1715 case 0x14: // Standard VGA
1716 case 0x15: // Standard VGA
1717 case 0x16: // Standard VGA
1718 case 0x17: // Standard VGA
1719 case 0x18: // Standard VGA
1720 /* handle CR0-7 protection */
1721 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1722 /* can always write bit 4 of CR7 */
1723 if (s->vga.cr_index == 7)
1724 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1725 return;
1726 }
1727 s->vga.cr[s->vga.cr_index] = reg_value;
1728 switch(s->vga.cr_index) {
1729 case 0x00:
1730 case 0x04:
1731 case 0x05:
1732 case 0x06:
1733 case 0x07:
1734 case 0x11:
1735 case 0x17:
1736 s->vga.update_retrace_info(&s->vga);
1737 break;
1738 }
1739 break;
1740 case 0x19: // Interlace End
1741 case 0x1a: // Miscellaneous Control
1742 case 0x1b: // Extended Display Control
1743 case 0x1c: // Sync Adjust and Genlock
1744 case 0x1d: // Overlay Extended Control
1745 s->vga.cr[s->vga.cr_index] = reg_value;
1746 #ifdef DEBUG_CIRRUS
1747 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1748 s->vga.cr_index, reg_value);
1749 #endif
1750 break;
1751 case 0x22: // Graphics Data Latches Readback (R)
1752 case 0x24: // Attribute Controller Toggle Readback (R)
1753 case 0x26: // Attribute Controller Index Readback (R)
1754 case 0x27: // Part ID (R)
1755 break;
1756 case 0x25: // Part Status
1757 default:
1758 #ifdef DEBUG_CIRRUS
1759 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1760 s->vga.cr_index, reg_value);
1761 #endif
1762 break;
1763 }
1764 }
1765
1766 /***************************************
1767 *
1768 * memory-mapped I/O (bitblt)
1769 *
1770 ***************************************/
1771
1772 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1773 {
1774 int value = 0xff;
1775
1776 switch (address) {
1777 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1778 value = cirrus_vga_read_gr(s, 0x00);
1779 break;
1780 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1781 value = cirrus_vga_read_gr(s, 0x10);
1782 break;
1783 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1784 value = cirrus_vga_read_gr(s, 0x12);
1785 break;
1786 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1787 value = cirrus_vga_read_gr(s, 0x14);
1788 break;
1789 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1790 value = cirrus_vga_read_gr(s, 0x01);
1791 break;
1792 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1793 value = cirrus_vga_read_gr(s, 0x11);
1794 break;
1795 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1796 value = cirrus_vga_read_gr(s, 0x13);
1797 break;
1798 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1799 value = cirrus_vga_read_gr(s, 0x15);
1800 break;
1801 case (CIRRUS_MMIO_BLTWIDTH + 0):
1802 value = cirrus_vga_read_gr(s, 0x20);
1803 break;
1804 case (CIRRUS_MMIO_BLTWIDTH + 1):
1805 value = cirrus_vga_read_gr(s, 0x21);
1806 break;
1807 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1808 value = cirrus_vga_read_gr(s, 0x22);
1809 break;
1810 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1811 value = cirrus_vga_read_gr(s, 0x23);
1812 break;
1813 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1814 value = cirrus_vga_read_gr(s, 0x24);
1815 break;
1816 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1817 value = cirrus_vga_read_gr(s, 0x25);
1818 break;
1819 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1820 value = cirrus_vga_read_gr(s, 0x26);
1821 break;
1822 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1823 value = cirrus_vga_read_gr(s, 0x27);
1824 break;
1825 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1826 value = cirrus_vga_read_gr(s, 0x28);
1827 break;
1828 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1829 value = cirrus_vga_read_gr(s, 0x29);
1830 break;
1831 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1832 value = cirrus_vga_read_gr(s, 0x2a);
1833 break;
1834 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1835 value = cirrus_vga_read_gr(s, 0x2c);
1836 break;
1837 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1838 value = cirrus_vga_read_gr(s, 0x2d);
1839 break;
1840 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1841 value = cirrus_vga_read_gr(s, 0x2e);
1842 break;
1843 case CIRRUS_MMIO_BLTWRITEMASK:
1844 value = cirrus_vga_read_gr(s, 0x2f);
1845 break;
1846 case CIRRUS_MMIO_BLTMODE:
1847 value = cirrus_vga_read_gr(s, 0x30);
1848 break;
1849 case CIRRUS_MMIO_BLTROP:
1850 value = cirrus_vga_read_gr(s, 0x32);
1851 break;
1852 case CIRRUS_MMIO_BLTMODEEXT:
1853 value = cirrus_vga_read_gr(s, 0x33);
1854 break;
1855 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1856 value = cirrus_vga_read_gr(s, 0x34);
1857 break;
1858 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1859 value = cirrus_vga_read_gr(s, 0x35);
1860 break;
1861 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1862 value = cirrus_vga_read_gr(s, 0x38);
1863 break;
1864 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1865 value = cirrus_vga_read_gr(s, 0x39);
1866 break;
1867 case CIRRUS_MMIO_BLTSTATUS:
1868 value = cirrus_vga_read_gr(s, 0x31);
1869 break;
1870 default:
1871 #ifdef DEBUG_CIRRUS
1872 printf("cirrus: mmio read - address 0x%04x\n", address);
1873 #endif
1874 break;
1875 }
1876
1877 trace_vga_cirrus_write_blt(address, value);
1878 return (uint8_t) value;
1879 }
1880
1881 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1882 uint8_t value)
1883 {
1884 trace_vga_cirrus_write_blt(address, value);
1885 switch (address) {
1886 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1887 cirrus_vga_write_gr(s, 0x00, value);
1888 break;
1889 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1890 cirrus_vga_write_gr(s, 0x10, value);
1891 break;
1892 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1893 cirrus_vga_write_gr(s, 0x12, value);
1894 break;
1895 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1896 cirrus_vga_write_gr(s, 0x14, value);
1897 break;
1898 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1899 cirrus_vga_write_gr(s, 0x01, value);
1900 break;
1901 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1902 cirrus_vga_write_gr(s, 0x11, value);
1903 break;
1904 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1905 cirrus_vga_write_gr(s, 0x13, value);
1906 break;
1907 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1908 cirrus_vga_write_gr(s, 0x15, value);
1909 break;
1910 case (CIRRUS_MMIO_BLTWIDTH + 0):
1911 cirrus_vga_write_gr(s, 0x20, value);
1912 break;
1913 case (CIRRUS_MMIO_BLTWIDTH + 1):
1914 cirrus_vga_write_gr(s, 0x21, value);
1915 break;
1916 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1917 cirrus_vga_write_gr(s, 0x22, value);
1918 break;
1919 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1920 cirrus_vga_write_gr(s, 0x23, value);
1921 break;
1922 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1923 cirrus_vga_write_gr(s, 0x24, value);
1924 break;
1925 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1926 cirrus_vga_write_gr(s, 0x25, value);
1927 break;
1928 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1929 cirrus_vga_write_gr(s, 0x26, value);
1930 break;
1931 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1932 cirrus_vga_write_gr(s, 0x27, value);
1933 break;
1934 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1935 cirrus_vga_write_gr(s, 0x28, value);
1936 break;
1937 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1938 cirrus_vga_write_gr(s, 0x29, value);
1939 break;
1940 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1941 cirrus_vga_write_gr(s, 0x2a, value);
1942 break;
1943 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1944 /* ignored */
1945 break;
1946 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1947 cirrus_vga_write_gr(s, 0x2c, value);
1948 break;
1949 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1950 cirrus_vga_write_gr(s, 0x2d, value);
1951 break;
1952 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1953 cirrus_vga_write_gr(s, 0x2e, value);
1954 break;
1955 case CIRRUS_MMIO_BLTWRITEMASK:
1956 cirrus_vga_write_gr(s, 0x2f, value);
1957 break;
1958 case CIRRUS_MMIO_BLTMODE:
1959 cirrus_vga_write_gr(s, 0x30, value);
1960 break;
1961 case CIRRUS_MMIO_BLTROP:
1962 cirrus_vga_write_gr(s, 0x32, value);
1963 break;
1964 case CIRRUS_MMIO_BLTMODEEXT:
1965 cirrus_vga_write_gr(s, 0x33, value);
1966 break;
1967 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1968 cirrus_vga_write_gr(s, 0x34, value);
1969 break;
1970 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1971 cirrus_vga_write_gr(s, 0x35, value);
1972 break;
1973 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1974 cirrus_vga_write_gr(s, 0x38, value);
1975 break;
1976 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1977 cirrus_vga_write_gr(s, 0x39, value);
1978 break;
1979 case CIRRUS_MMIO_BLTSTATUS:
1980 cirrus_vga_write_gr(s, 0x31, value);
1981 break;
1982 default:
1983 #ifdef DEBUG_CIRRUS
1984 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1985 address, value);
1986 #endif
1987 break;
1988 }
1989 }
1990
1991 /***************************************
1992 *
1993 * write mode 4/5
1994 *
1995 ***************************************/
1996
1997 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1998 unsigned mode,
1999 unsigned offset,
2000 uint32_t mem_value)
2001 {
2002 int x;
2003 unsigned val = mem_value;
2004 uint8_t *dst;
2005
2006 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
2007 for (x = 0; x < 8; x++) {
2008 if (val & 0x80) {
2009 *dst = s->cirrus_shadow_gr1;
2010 } else if (mode == 5) {
2011 *dst = s->cirrus_shadow_gr0;
2012 }
2013 val <<= 1;
2014 dst++;
2015 }
2016 memory_region_set_dirty(&s->vga.vram, offset, 8);
2017 }
2018
2019 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
2020 unsigned mode,
2021 unsigned offset,
2022 uint32_t mem_value)
2023 {
2024 int x;
2025 unsigned val = mem_value;
2026 uint8_t *dst;
2027
2028 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
2029 for (x = 0; x < 8; x++) {
2030 if (val & 0x80) {
2031 *dst = s->cirrus_shadow_gr1;
2032 *(dst + 1) = s->vga.gr[0x11];
2033 } else if (mode == 5) {
2034 *dst = s->cirrus_shadow_gr0;
2035 *(dst + 1) = s->vga.gr[0x10];
2036 }
2037 val <<= 1;
2038 dst += 2;
2039 }
2040 memory_region_set_dirty(&s->vga.vram, offset, 16);
2041 }
2042
2043 /***************************************
2044 *
2045 * memory access between 0xa0000-0xbffff
2046 *
2047 ***************************************/
2048
2049 static uint64_t cirrus_vga_mem_read(void *opaque,
2050 hwaddr addr,
2051 uint32_t size)
2052 {
2053 CirrusVGAState *s = opaque;
2054 unsigned bank_index;
2055 unsigned bank_offset;
2056 uint32_t val;
2057
2058 if ((s->vga.sr[0x07] & 0x01) == 0) {
2059 return vga_mem_readb(&s->vga, addr);
2060 }
2061
2062 if (addr < 0x10000) {
2063 /* XXX handle bitblt */
2064 /* video memory */
2065 bank_index = addr >> 15;
2066 bank_offset = addr & 0x7fff;
2067 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2068 bank_offset += s->cirrus_bank_base[bank_index];
2069 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2070 bank_offset <<= 4;
2071 } else if (s->vga.gr[0x0B] & 0x02) {
2072 bank_offset <<= 3;
2073 }
2074 bank_offset &= s->cirrus_addr_mask;
2075 val = *(s->vga.vram_ptr + bank_offset);
2076 } else
2077 val = 0xff;
2078 } else if (addr >= 0x18000 && addr < 0x18100) {
2079 /* memory-mapped I/O */
2080 val = 0xff;
2081 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2082 val = cirrus_mmio_blt_read(s, addr & 0xff);
2083 }
2084 } else {
2085 val = 0xff;
2086 #ifdef DEBUG_CIRRUS
2087 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
2088 #endif
2089 }
2090 return val;
2091 }
2092
2093 static void cirrus_vga_mem_write(void *opaque,
2094 hwaddr addr,
2095 uint64_t mem_value,
2096 uint32_t size)
2097 {
2098 CirrusVGAState *s = opaque;
2099 unsigned bank_index;
2100 unsigned bank_offset;
2101 unsigned mode;
2102
2103 if ((s->vga.sr[0x07] & 0x01) == 0) {
2104 vga_mem_writeb(&s->vga, addr, mem_value);
2105 return;
2106 }
2107
2108 if (addr < 0x10000) {
2109 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2110 /* bitblt */
2111 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2112 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2113 cirrus_bitblt_cputovideo_next(s);
2114 }
2115 } else {
2116 /* video memory */
2117 bank_index = addr >> 15;
2118 bank_offset = addr & 0x7fff;
2119 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2120 bank_offset += s->cirrus_bank_base[bank_index];
2121 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2122 bank_offset <<= 4;
2123 } else if (s->vga.gr[0x0B] & 0x02) {
2124 bank_offset <<= 3;
2125 }
2126 bank_offset &= s->cirrus_addr_mask;
2127 mode = s->vga.gr[0x05] & 0x7;
2128 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2129 *(s->vga.vram_ptr + bank_offset) = mem_value;
2130 memory_region_set_dirty(&s->vga.vram, bank_offset,
2131 sizeof(mem_value));
2132 } else {
2133 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2134 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2135 bank_offset,
2136 mem_value);
2137 } else {
2138 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2139 bank_offset,
2140 mem_value);
2141 }
2142 }
2143 }
2144 }
2145 } else if (addr >= 0x18000 && addr < 0x18100) {
2146 /* memory-mapped I/O */
2147 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2148 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2149 }
2150 } else {
2151 #ifdef DEBUG_CIRRUS
2152 printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
2153 mem_value);
2154 #endif
2155 }
2156 }
2157
2158 static const MemoryRegionOps cirrus_vga_mem_ops = {
2159 .read = cirrus_vga_mem_read,
2160 .write = cirrus_vga_mem_write,
2161 .endianness = DEVICE_LITTLE_ENDIAN,
2162 .impl = {
2163 .min_access_size = 1,
2164 .max_access_size = 1,
2165 },
2166 };
2167
2168 /***************************************
2169 *
2170 * hardware cursor
2171 *
2172 ***************************************/
2173
2174 static inline void invalidate_cursor1(CirrusVGAState *s)
2175 {
2176 if (s->last_hw_cursor_size) {
2177 vga_invalidate_scanlines(&s->vga,
2178 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2179 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2180 }
2181 }
2182
2183 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2184 {
2185 const uint8_t *src;
2186 uint32_t content;
2187 int y, y_min, y_max;
2188
2189 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2190 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2191 src += (s->vga.sr[0x13] & 0x3c) * 256;
2192 y_min = 64;
2193 y_max = -1;
2194 for(y = 0; y < 64; y++) {
2195 content = ((uint32_t *)src)[0] |
2196 ((uint32_t *)src)[1] |
2197 ((uint32_t *)src)[2] |
2198 ((uint32_t *)src)[3];
2199 if (content) {
2200 if (y < y_min)
2201 y_min = y;
2202 if (y > y_max)
2203 y_max = y;
2204 }
2205 src += 16;
2206 }
2207 } else {
2208 src += (s->vga.sr[0x13] & 0x3f) * 256;
2209 y_min = 32;
2210 y_max = -1;
2211 for(y = 0; y < 32; y++) {
2212 content = ((uint32_t *)src)[0] |
2213 ((uint32_t *)(src + 128))[0];
2214 if (content) {
2215 if (y < y_min)
2216 y_min = y;
2217 if (y > y_max)
2218 y_max = y;
2219 }
2220 src += 4;
2221 }
2222 }
2223 if (y_min > y_max) {
2224 s->last_hw_cursor_y_start = 0;
2225 s->last_hw_cursor_y_end = 0;
2226 } else {
2227 s->last_hw_cursor_y_start = y_min;
2228 s->last_hw_cursor_y_end = y_max + 1;
2229 }
2230 }
2231
2232 /* NOTE: we do not currently handle the cursor bitmap change, so we
2233 update the cursor only if it moves. */
2234 static void cirrus_cursor_invalidate(VGACommonState *s1)
2235 {
2236 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2237 int size;
2238
2239 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2240 size = 0;
2241 } else {
2242 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2243 size = 64;
2244 else
2245 size = 32;
2246 }
2247 /* invalidate last cursor and new cursor if any change */
2248 if (s->last_hw_cursor_size != size ||
2249 s->last_hw_cursor_x != s->vga.hw_cursor_x ||
2250 s->last_hw_cursor_y != s->vga.hw_cursor_y) {
2251
2252 invalidate_cursor1(s);
2253
2254 s->last_hw_cursor_size = size;
2255 s->last_hw_cursor_x = s->vga.hw_cursor_x;
2256 s->last_hw_cursor_y = s->vga.hw_cursor_y;
2257 /* compute the real cursor min and max y */
2258 cirrus_cursor_compute_yrange(s);
2259 invalidate_cursor1(s);
2260 }
2261 }
2262
2263 static void vga_draw_cursor_line(uint8_t *d1,
2264 const uint8_t *src1,
2265 int poffset, int w,
2266 unsigned int color0,
2267 unsigned int color1,
2268 unsigned int color_xor)
2269 {
2270 const uint8_t *plane0, *plane1;
2271 int x, b0, b1;
2272 uint8_t *d;
2273
2274 d = d1;
2275 plane0 = src1;
2276 plane1 = src1 + poffset;
2277 for (x = 0; x < w; x++) {
2278 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1;
2279 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1;
2280 switch (b0 | (b1 << 1)) {
2281 case 0:
2282 break;
2283 case 1:
2284 ((uint32_t *)d)[0] ^= color_xor;
2285 break;
2286 case 2:
2287 ((uint32_t *)d)[0] = color0;
2288 break;
2289 case 3:
2290 ((uint32_t *)d)[0] = color1;
2291 break;
2292 }
2293 d += 4;
2294 }
2295 }
2296
2297 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2298 {
2299 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2300 int w, h, x1, x2, poffset;
2301 unsigned int color0, color1;
2302 const uint8_t *palette, *src;
2303 uint32_t content;
2304
2305 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2306 return;
2307 /* fast test to see if the cursor intersects with the scan line */
2308 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2309 h = 64;
2310 } else {
2311 h = 32;
2312 }
2313 if (scr_y < s->vga.hw_cursor_y ||
2314 scr_y >= (s->vga.hw_cursor_y + h)) {
2315 return;
2316 }
2317
2318 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2319 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2320 src += (s->vga.sr[0x13] & 0x3c) * 256;
2321 src += (scr_y - s->vga.hw_cursor_y) * 16;
2322 poffset = 8;
2323 content = ((uint32_t *)src)[0] |
2324 ((uint32_t *)src)[1] |
2325 ((uint32_t *)src)[2] |
2326 ((uint32_t *)src)[3];
2327 } else {
2328 src += (s->vga.sr[0x13] & 0x3f) * 256;
2329 src += (scr_y - s->vga.hw_cursor_y) * 4;
2330
2331
2332 poffset = 128;
2333 content = ((uint32_t *)src)[0] |
2334 ((uint32_t *)(src + 128))[0];
2335 }
2336 /* if nothing to draw, no need to continue */
2337 if (!content)
2338 return;
2339 w = h;
2340
2341 x1 = s->vga.hw_cursor_x;
2342 if (x1 >= s->vga.last_scr_width)
2343 return;
2344 x2 = s->vga.hw_cursor_x + w;
2345 if (x2 > s->vga.last_scr_width)
2346 x2 = s->vga.last_scr_width;
2347 w = x2 - x1;
2348 palette = s->cirrus_hidden_palette;
2349 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]),
2350 c6_to_8(palette[0x0 * 3 + 1]),
2351 c6_to_8(palette[0x0 * 3 + 2]));
2352 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]),
2353 c6_to_8(palette[0xf * 3 + 1]),
2354 c6_to_8(palette[0xf * 3 + 2]));
2355 d1 += x1 * 4;
2356 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff);
2357 }
2358
2359 /***************************************
2360 *
2361 * LFB memory access
2362 *
2363 ***************************************/
2364
2365 static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
2366 unsigned size)
2367 {
2368 CirrusVGAState *s = opaque;
2369 uint32_t ret;
2370
2371 addr &= s->cirrus_addr_mask;
2372
2373 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2374 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2375 /* memory-mapped I/O */
2376 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2377 } else if (0) {
2378 /* XXX handle bitblt */
2379 ret = 0xff;
2380 } else {
2381 /* video memory */
2382 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2383 addr <<= 4;
2384 } else if (s->vga.gr[0x0B] & 0x02) {
2385 addr <<= 3;
2386 }
2387 addr &= s->cirrus_addr_mask;
2388 ret = *(s->vga.vram_ptr + addr);
2389 }
2390
2391 return ret;
2392 }
2393
2394 static void cirrus_linear_write(void *opaque, hwaddr addr,
2395 uint64_t val, unsigned size)
2396 {
2397 CirrusVGAState *s = opaque;
2398 unsigned mode;
2399
2400 addr &= s->cirrus_addr_mask;
2401
2402 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2403 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2404 /* memory-mapped I/O */
2405 cirrus_mmio_blt_write(s, addr & 0xff, val);
2406 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2407 /* bitblt */
2408 *s->cirrus_srcptr++ = (uint8_t) val;
2409 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2410 cirrus_bitblt_cputovideo_next(s);
2411 }
2412 } else {
2413 /* video memory */
2414 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2415 addr <<= 4;
2416 } else if (s->vga.gr[0x0B] & 0x02) {
2417 addr <<= 3;
2418 }
2419 addr &= s->cirrus_addr_mask;
2420
2421 mode = s->vga.gr[0x05] & 0x7;
2422 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2423 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2424 memory_region_set_dirty(&s->vga.vram, addr, 1);
2425 } else {
2426 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2427 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2428 } else {
2429 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2430 }
2431 }
2432 }
2433 }
2434
2435 /***************************************
2436 *
2437 * system to screen memory access
2438 *
2439 ***************************************/
2440
2441
2442 static uint64_t cirrus_linear_bitblt_read(void *opaque,
2443 hwaddr addr,
2444 unsigned size)
2445 {
2446 CirrusVGAState *s = opaque;
2447 uint32_t ret;
2448
2449 /* XXX handle bitblt */
2450 (void)s;
2451 ret = 0xff;
2452 return ret;
2453 }
2454
2455 static void cirrus_linear_bitblt_write(void *opaque,
2456 hwaddr addr,
2457 uint64_t val,
2458 unsigned size)
2459 {
2460 CirrusVGAState *s = opaque;
2461
2462 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2463 /* bitblt */
2464 *s->cirrus_srcptr++ = (uint8_t) val;
2465 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2466 cirrus_bitblt_cputovideo_next(s);
2467 }
2468 }
2469 }
2470
2471 static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2472 .read = cirrus_linear_bitblt_read,
2473 .write = cirrus_linear_bitblt_write,
2474 .endianness = DEVICE_LITTLE_ENDIAN,
2475 .impl = {
2476 .min_access_size = 1,
2477 .max_access_size = 1,
2478 },
2479 };
2480
2481 static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2482 {
2483 MemoryRegion *mr = &s->cirrus_bank[bank];
2484 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2485 && !((s->vga.sr[0x07] & 0x01) == 0)
2486 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2487 && !(s->vga.gr[0x0B] & 0x02);
2488
2489 memory_region_set_enabled(mr, enabled);
2490 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
2491 }
2492
2493 static void map_linear_vram(CirrusVGAState *s)
2494 {
2495 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
2496 s->linear_vram = true;
2497 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2498 }
2499 map_linear_vram_bank(s, 0);
2500 map_linear_vram_bank(s, 1);
2501 }
2502
2503 static void unmap_linear_vram(CirrusVGAState *s)
2504 {
2505 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
2506 s->linear_vram = false;
2507 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
2508 }
2509 memory_region_set_enabled(&s->cirrus_bank[0], false);
2510 memory_region_set_enabled(&s->cirrus_bank[1], false);
2511 }
2512
2513 /* Compute the memory access functions */
2514 static void cirrus_update_memory_access(CirrusVGAState *s)
2515 {
2516 unsigned mode;
2517
2518 memory_region_transaction_begin();
2519 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2520 goto generic_io;
2521 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2522 goto generic_io;
2523 } else {
2524 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2525 goto generic_io;
2526 } else if (s->vga.gr[0x0B] & 0x02) {
2527 goto generic_io;
2528 }
2529
2530 mode = s->vga.gr[0x05] & 0x7;
2531 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2532 map_linear_vram(s);
2533 } else {
2534 generic_io:
2535 unmap_linear_vram(s);
2536 }
2537 }
2538 memory_region_transaction_commit();
2539 }
2540
2541
2542 /* I/O ports */
2543
2544 static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2545 unsigned size)
2546 {
2547 CirrusVGAState *c = opaque;
2548 VGACommonState *s = &c->vga;
2549 int val, index;
2550
2551 addr += 0x3b0;
2552
2553 if (vga_ioport_invalid(s, addr)) {
2554 val = 0xff;
2555 } else {
2556 switch (addr) {
2557 case 0x3c0:
2558 if (s->ar_flip_flop == 0) {
2559 val = s->ar_index;
2560 } else {
2561 val = 0;
2562 }
2563 break;
2564 case 0x3c1:
2565 index = s->ar_index & 0x1f;
2566 if (index < 21)
2567 val = s->ar[index];
2568 else
2569 val = 0;
2570 break;
2571 case 0x3c2:
2572 val = s->st00;
2573 break;
2574 case 0x3c4:
2575 val = s->sr_index;
2576 break;
2577 case 0x3c5:
2578 val = cirrus_vga_read_sr(c);
2579 break;
2580 #ifdef DEBUG_VGA_REG
2581 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2582 #endif
2583 break;
2584 case 0x3c6:
2585 val = cirrus_read_hidden_dac(c);
2586 break;
2587 case 0x3c7:
2588 val = s->dac_state;
2589 break;
2590 case 0x3c8:
2591 val = s->dac_write_index;
2592 c->cirrus_hidden_dac_lockindex = 0;
2593 break;
2594 case 0x3c9:
2595 val = cirrus_vga_read_palette(c);
2596 break;
2597 case 0x3ca:
2598 val = s->fcr;
2599 break;
2600 case 0x3cc:
2601 val = s->msr;
2602 break;
2603 case 0x3ce:
2604 val = s->gr_index;
2605 break;
2606 case 0x3cf:
2607 val = cirrus_vga_read_gr(c, s->gr_index);
2608 #ifdef DEBUG_VGA_REG
2609 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2610 #endif
2611 break;
2612 case 0x3b4:
2613 case 0x3d4:
2614 val = s->cr_index;
2615 break;
2616 case 0x3b5:
2617 case 0x3d5:
2618 val = cirrus_vga_read_cr(c, s->cr_index);
2619 #ifdef DEBUG_VGA_REG
2620 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2621 #endif
2622 break;
2623 case 0x3ba:
2624 case 0x3da:
2625 /* just toggle to fool polling */
2626 val = s->st01 = s->retrace(s);
2627 s->ar_flip_flop = 0;
2628 break;
2629 default:
2630 val = 0x00;
2631 break;
2632 }
2633 }
2634 trace_vga_cirrus_read_io(addr, val);
2635 return val;
2636 }
2637
2638 static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2639 unsigned size)
2640 {
2641 CirrusVGAState *c = opaque;
2642 VGACommonState *s = &c->vga;
2643 int index;
2644
2645 addr += 0x3b0;
2646
2647 /* check port range access depending on color/monochrome mode */
2648 if (vga_ioport_invalid(s, addr)) {
2649 return;
2650 }
2651 trace_vga_cirrus_write_io(addr, val);
2652
2653 switch (addr) {
2654 case 0x3c0:
2655 if (s->ar_flip_flop == 0) {
2656 val &= 0x3f;
2657 s->ar_index = val;
2658 } else {
2659 index = s->ar_index & 0x1f;
2660 switch (index) {
2661 case 0x00 ... 0x0f:
2662 s->ar[index] = val & 0x3f;
2663 break;
2664 case 0x10:
2665 s->ar[index] = val & ~0x10;
2666 break;
2667 case 0x11:
2668 s->ar[index] = val;
2669 break;
2670 case 0x12:
2671 s->ar[index] = val & ~0xc0;
2672 break;
2673 case 0x13:
2674 s->ar[index] = val & ~0xf0;
2675 break;
2676 case 0x14:
2677 s->ar[index] = val & ~0xf0;
2678 break;
2679 default:
2680 break;
2681 }
2682 }
2683 s->ar_flip_flop ^= 1;
2684 break;
2685 case 0x3c2:
2686 s->msr = val & ~0x10;
2687 s->update_retrace_info(s);
2688 break;
2689 case 0x3c4:
2690 s->sr_index = val;
2691 break;
2692 case 0x3c5:
2693 #ifdef DEBUG_VGA_REG
2694 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val);
2695 #endif
2696 cirrus_vga_write_sr(c, val);
2697 break;
2698 case 0x3c6:
2699 cirrus_write_hidden_dac(c, val);
2700 break;
2701 case 0x3c7:
2702 s->dac_read_index = val;
2703 s->dac_sub_index = 0;
2704 s->dac_state = 3;
2705 break;
2706 case 0x3c8:
2707 s->dac_write_index = val;
2708 s->dac_sub_index = 0;
2709 s->dac_state = 0;
2710 break;
2711 case 0x3c9:
2712 cirrus_vga_write_palette(c, val);
2713 break;
2714 case 0x3ce:
2715 s->gr_index = val;
2716 break;
2717 case 0x3cf:
2718 #ifdef DEBUG_VGA_REG
2719 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val);
2720 #endif
2721 cirrus_vga_write_gr(c, s->gr_index, val);
2722 break;
2723 case 0x3b4:
2724 case 0x3d4:
2725 s->cr_index = val;
2726 break;
2727 case 0x3b5:
2728 case 0x3d5:
2729 #ifdef DEBUG_VGA_REG
2730 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val);
2731 #endif
2732 cirrus_vga_write_cr(c, val);
2733 break;
2734 case 0x3ba:
2735 case 0x3da:
2736 s->fcr = val & 0x10;
2737 break;
2738 }
2739 }
2740
2741 /***************************************
2742 *
2743 * memory-mapped I/O access
2744 *
2745 ***************************************/
2746
2747 static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
2748 unsigned size)
2749 {
2750 CirrusVGAState *s = opaque;
2751
2752 if (addr >= 0x100) {
2753 return cirrus_mmio_blt_read(s, addr - 0x100);
2754 } else {
2755 return cirrus_vga_ioport_read(s, addr + 0x10, size);
2756 }
2757 }
2758
2759 static void cirrus_mmio_write(void *opaque, hwaddr addr,
2760 uint64_t val, unsigned size)
2761 {
2762 CirrusVGAState *s = opaque;
2763
2764 if (addr >= 0x100) {
2765 cirrus_mmio_blt_write(s, addr - 0x100, val);
2766 } else {
2767 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
2768 }
2769 }
2770
2771 static const MemoryRegionOps cirrus_mmio_io_ops = {
2772 .read = cirrus_mmio_read,
2773 .write = cirrus_mmio_write,
2774 .endianness = DEVICE_LITTLE_ENDIAN,
2775 .impl = {
2776 .min_access_size = 1,
2777 .max_access_size = 1,
2778 },
2779 };
2780
2781 /* load/save state */
2782
2783 static int cirrus_post_load(void *opaque, int version_id)
2784 {
2785 CirrusVGAState *s = opaque;
2786
2787 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2788 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2789
2790 cirrus_update_memory_access(s);
2791 /* force refresh */
2792 s->vga.graphic_mode = -1;
2793 cirrus_update_bank_ptr(s, 0);
2794 cirrus_update_bank_ptr(s, 1);
2795 return 0;
2796 }
2797
2798 static const VMStateDescription vmstate_cirrus_vga = {
2799 .name = "cirrus_vga",
2800 .version_id = 2,
2801 .minimum_version_id = 1,
2802 .post_load = cirrus_post_load,
2803 .fields = (VMStateField[]) {
2804 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2805 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2806 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2807 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2808 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2809 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2810 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2811 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2812 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2813 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2814 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2815 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2816 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2817 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2818 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2819 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2820 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2821 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2822 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2823 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2824 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2825 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2826 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2827 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2828 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2829 VMSTATE_UINT32(vga.hw_cursor_x, CirrusVGAState),
2830 VMSTATE_UINT32(vga.hw_cursor_y, CirrusVGAState),
2831 /* XXX: we do not save the bitblt state - we assume we do not save
2832 the state when the blitter is active */
2833 VMSTATE_END_OF_LIST()
2834 }
2835 };
2836
2837 static const VMStateDescription vmstate_pci_cirrus_vga = {
2838 .name = "cirrus_vga",
2839 .version_id = 2,
2840 .minimum_version_id = 2,
2841 .fields = (VMStateField[]) {
2842 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2843 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2844 vmstate_cirrus_vga, CirrusVGAState),
2845 VMSTATE_END_OF_LIST()
2846 }
2847 };
2848
2849 /***************************************
2850 *
2851 * initialize
2852 *
2853 ***************************************/
2854
2855 static void cirrus_reset(void *opaque)
2856 {
2857 CirrusVGAState *s = opaque;
2858
2859 vga_common_reset(&s->vga);
2860 unmap_linear_vram(s);
2861 s->vga.sr[0x06] = 0x0f;
2862 if (s->device_id == CIRRUS_ID_CLGD5446) {
2863 /* 4MB 64 bit memory config, always PCI */
2864 s->vga.sr[0x1F] = 0x2d; // MemClock
2865 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2866 s->vga.sr[0x0f] = 0x98;
2867 s->vga.sr[0x17] = 0x20;
2868 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2869 } else {
2870 s->vga.sr[0x1F] = 0x22; // MemClock
2871 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2872 s->vga.sr[0x17] = s->bustype;
2873 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2874 }
2875 s->vga.cr[0x27] = s->device_id;
2876
2877 s->cirrus_hidden_dac_lockindex = 5;
2878 s->cirrus_hidden_dac_data = 0;
2879 }
2880
2881 static const MemoryRegionOps cirrus_linear_io_ops = {
2882 .read = cirrus_linear_read,
2883 .write = cirrus_linear_write,
2884 .endianness = DEVICE_LITTLE_ENDIAN,
2885 .impl = {
2886 .min_access_size = 1,
2887 .max_access_size = 1,
2888 },
2889 };
2890
2891 static const MemoryRegionOps cirrus_vga_io_ops = {
2892 .read = cirrus_vga_ioport_read,
2893 .write = cirrus_vga_ioport_write,
2894 .endianness = DEVICE_LITTLE_ENDIAN,
2895 .impl = {
2896 .min_access_size = 1,
2897 .max_access_size = 1,
2898 },
2899 };
2900
2901 static void cirrus_init_common(CirrusVGAState *s, Object *owner,
2902 int device_id, int is_pci,
2903 MemoryRegion *system_memory,
2904 MemoryRegion *system_io)
2905 {
2906 int i;
2907 static int inited;
2908
2909 if (!inited) {
2910 inited = 1;
2911 for(i = 0;i < 256; i++)
2912 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2913 rop_to_index[CIRRUS_ROP_0] = 0;
2914 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2915 rop_to_index[CIRRUS_ROP_NOP] = 2;
2916 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2917 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2918 rop_to_index[CIRRUS_ROP_SRC] = 5;
2919 rop_to_index[CIRRUS_ROP_1] = 6;
2920 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2921 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2922 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2923 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2924 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2925 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2926 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2927 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2928 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2929 s->device_id = device_id;
2930 if (is_pci)
2931 s->bustype = CIRRUS_BUSTYPE_PCI;
2932 else
2933 s->bustype = CIRRUS_BUSTYPE_ISA;
2934 }
2935
2936 /* Register ioport 0x3b0 - 0x3df */
2937 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s,
2938 "cirrus-io", 0x30);
2939 memory_region_set_flush_coalesced(&s->cirrus_vga_io);
2940 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
2941
2942 memory_region_init(&s->low_mem_container, owner,
2943 "cirrus-lowmem-container",
2944 0x20000);
2945
2946 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s,
2947 "cirrus-low-memory", 0x20000);
2948 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
2949 for (i = 0; i < 2; ++i) {
2950 static const char *names[] = { "vga.bank0", "vga.bank1" };
2951 MemoryRegion *bank = &s->cirrus_bank[i];
2952 memory_region_init_alias(bank, owner, names[i], &s->vga.vram,
2953 0, 0x8000);
2954 memory_region_set_enabled(bank, false);
2955 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2956 bank, 1);
2957 }
2958 memory_region_add_subregion_overlap(system_memory,
2959 0x000a0000,
2960 &s->low_mem_container,
2961 1);
2962 memory_region_set_coalescing(&s->low_mem);
2963
2964 /* I/O handler for LFB */
2965 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
2966 "cirrus-linear-io", s->vga.vram_size_mb
2967 * 1024 * 1024);
2968 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
2969
2970 /* I/O handler for LFB */
2971 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner,
2972 &cirrus_linear_bitblt_io_ops,
2973 s,
2974 "cirrus-bitblt-mmio",
2975 0x400000);
2976 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
2977
2978 /* I/O handler for memory-mapped I/O */
2979 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s,
2980 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
2981 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
2982
2983 s->real_vram_size =
2984 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2985
2986 /* XXX: s->vga.vram_size must be a power of two */
2987 s->cirrus_addr_mask = s->real_vram_size - 1;
2988 s->linear_mmio_mask = s->real_vram_size - 256;
2989
2990 s->vga.get_bpp = cirrus_get_bpp;
2991 s->vga.get_offsets = cirrus_get_offsets;
2992 s->vga.get_resolution = cirrus_get_resolution;
2993 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2994 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
2995
2996 qemu_register_reset(cirrus_reset, s);
2997 }
2998
2999 /***************************************
3000 *
3001 * ISA bus support
3002 *
3003 ***************************************/
3004
3005 static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp)
3006 {
3007 ISADevice *isadev = ISA_DEVICE(dev);
3008 ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev);
3009 VGACommonState *s = &d->cirrus_vga.vga;
3010
3011 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3012 Also accept 8 MB/16 MB for backward compatibility. */
3013 if (s->vram_size_mb != 4 && s->vram_size_mb != 8 &&
3014 s->vram_size_mb != 16) {
3015 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
3016 s->vram_size_mb);
3017 return;
3018 }
3019 vga_common_init(s, OBJECT(dev), true);
3020 cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0,
3021 isa_address_space(isadev),
3022 isa_address_space_io(isadev));
3023 s->con = graphic_console_init(dev, 0, s->hw_ops, s);
3024 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
3025 /* XXX ISA-LFB support */
3026 /* FIXME not qdev yet */
3027 }
3028
3029 static Property isa_cirrus_vga_properties[] = {
3030 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
3031 cirrus_vga.vga.vram_size_mb, 4),
3032 DEFINE_PROP_BOOL("blitter", struct ISACirrusVGAState,
3033 cirrus_vga.enable_blitter, true),
3034 DEFINE_PROP_END_OF_LIST(),
3035 };
3036
3037 static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
3038 {
3039 DeviceClass *dc = DEVICE_CLASS(klass);
3040
3041 dc->vmsd = &vmstate_cirrus_vga;
3042 dc->realize = isa_cirrus_vga_realizefn;
3043 dc->props = isa_cirrus_vga_properties;
3044 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3045 }
3046
3047 static const TypeInfo isa_cirrus_vga_info = {
3048 .name = TYPE_ISA_CIRRUS_VGA,
3049 .parent = TYPE_ISA_DEVICE,
3050 .instance_size = sizeof(ISACirrusVGAState),
3051 .class_init = isa_cirrus_vga_class_init,
3052 };
3053
3054 /***************************************
3055 *
3056 * PCI bus support
3057 *
3058 ***************************************/
3059
3060 static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp)
3061 {
3062 PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev);
3063 CirrusVGAState *s = &d->cirrus_vga;
3064 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
3065 int16_t device_id = pc->device_id;
3066
3067 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3068 Also accept 8 MB/16 MB for backward compatibility. */
3069 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
3070 s->vga.vram_size_mb != 16) {
3071 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
3072 s->vga.vram_size_mb);
3073 return;
3074 }
3075 /* setup VGA */
3076 vga_common_init(&s->vga, OBJECT(dev), true);
3077 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
3078 pci_address_space_io(dev));
3079 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
3080
3081 /* setup PCI */
3082
3083 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
3084
3085 /* XXX: add byte swapping apertures */
3086 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
3087 memory_region_add_subregion(&s->pci_bar, 0x1000000,
3088 &s->cirrus_linear_bitblt_io);
3089
3090 /* setup memory space */
3091 /* memory #0 LFB */
3092 /* memory #1 memory-mapped I/O */
3093 /* XXX: s->vga.vram_size must be a power of two */
3094 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
3095 if (device_id == CIRRUS_ID_CLGD5446) {
3096 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
3097 }
3098 }
3099
3100 static Property pci_vga_cirrus_properties[] = {
3101 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
3102 cirrus_vga.vga.vram_size_mb, 4),
3103 DEFINE_PROP_BOOL("blitter", struct PCICirrusVGAState,
3104 cirrus_vga.enable_blitter, true),
3105 DEFINE_PROP_END_OF_LIST(),
3106 };
3107
3108 static void cirrus_vga_class_init(ObjectClass *klass, void *data)
3109 {
3110 DeviceClass *dc = DEVICE_CLASS(klass);
3111 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3112
3113 k->realize = pci_cirrus_vga_realize;
3114 k->romfile = VGABIOS_CIRRUS_FILENAME;
3115 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
3116 k->device_id = CIRRUS_ID_CLGD5446;
3117 k->class_id = PCI_CLASS_DISPLAY_VGA;
3118 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3119 dc->desc = "Cirrus CLGD 54xx VGA";
3120 dc->vmsd = &vmstate_pci_cirrus_vga;
3121 dc->props = pci_vga_cirrus_properties;
3122 dc->hotpluggable = false;
3123 }
3124
3125 static const TypeInfo cirrus_vga_info = {
3126 .name = TYPE_PCI_CIRRUS_VGA,
3127 .parent = TYPE_PCI_DEVICE,
3128 .instance_size = sizeof(PCICirrusVGAState),
3129 .class_init = cirrus_vga_class_init,
3130 };
3131
3132 static void cirrus_vga_register_types(void)
3133 {
3134 type_register_static(&isa_cirrus_vga_info);
3135 type_register_static(&cirrus_vga_info);
3136 }
3137
3138 type_init(cirrus_vga_register_types)
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