target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <signal.h>
  26 #include <assert.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30
  31 enum {
  32     TLBRET_DIRTY = -4,
  33     TLBRET_INVALID = -3,
  34     TLBRET_NOMATCH = -2,
  35     TLBRET_BADADDR = -1,
  36     TLBRET_MATCH = 0
  37 };
  38
  39 /* no MMU emulation */
  40 int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
  41                         target_ulong address, int rw, int access_type)
  42 {
  43     *physical = address;
  44     *prot = PAGE_READ | PAGE_WRITE;
  45     return TLBRET_MATCH;
  46 }
  47
  48 /* fixed mapping MMU emulation */
  49 int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
  50                            target_ulong address, int rw, int access_type)
  51 {
  52     if (address <= (int32_t)0x7FFFFFFFUL) {
  53         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  54             *physical = address + 0x40000000UL;
  55         else
  56             *physical = address;
  57     } else if (address <= (int32_t)0xBFFFFFFFUL)
  58         *physical = address & 0x1FFFFFFF;
  59     else
  60         *physical = address;
  61
  62     *prot = PAGE_READ | PAGE_WRITE;
  63     return TLBRET_MATCH;
  64 }
  65
  66 /* MIPS32/MIPS64 R4000-style MMU emulation */
  67 int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
  68                      target_ulong address, int rw, int access_type)
  69 {
  70     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  71     int i;
  72
  73     for (i = 0; i < env->tlb_in_use; i++) {
  74         r4k_tlb_t *tlb = &env->mmu.r4k.tlb[i];
  75         /* 1k pages are not supported. */
  76         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  77         target_ulong tag = address & ~mask;
  78         target_ulong VPN = tlb->VPN & ~mask;
  79 #ifdef TARGET_MIPS64
  80         tag &= env->SEGMask;
  81 #endif
  82
  83         /* Check ASID, virtual page number & size */
  84         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
  85             /* TLB match */
  86             int n = !!(address & mask & ~(mask >> 1));
  87             /* Check access rights */
  88             if (!(n ? tlb->V1 : tlb->V0))
  89                 return TLBRET_INVALID;
  90             if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
  91                 *physical = tlb->PFN[n] | (address & (mask >> 1));
  92                 *prot = PAGE_READ;
  93                 if (n ? tlb->D1 : tlb->D0)
  94                     *prot |= PAGE_WRITE;
  95                 return TLBRET_MATCH;
  96             }
  97             return TLBRET_DIRTY;
  98         }
  99     }
 100     return TLBRET_NOMATCH;
 101 }
 102
 103 static int get_physical_address (CPUState *env, target_ulong *physical,
 104                                 int *prot, target_ulong address,
 105                                 int rw, int access_type)
 106 {
 107     /* User mode can only access useg/xuseg */
 108     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 109 #ifdef TARGET_MIPS64
 110     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 111     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 112     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 113 #endif
 114     int ret = TLBRET_MATCH;
 115
 116 #if 0
 117     if (logfile) {
 118         fprintf(logfile, "user mode %d h %08x\n",
 119                 user_mode, env->hflags);
 120     }
 121 #endif
 122
 123 #ifdef TARGET_MIPS64
 124     if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
 125         return TLBRET_BADADDR;
 126 #else
 127     if (user_mode && address > 0x7FFFFFFFUL)
 128         return TLBRET_BADADDR;
 129 #endif
 130
 131     if (address <= (int32_t)0x7FFFFFFFUL) {
 132         /* useg */
 133         if (env->CP0_Status & (1 << CP0St_ERL)) {
 134             *physical = address & 0xFFFFFFFF;
 135             *prot = PAGE_READ | PAGE_WRITE;
 136         } else {
 137             ret = env->map_address(env, physical, prot, address, rw, access_type);
 138         }
 139 #ifdef TARGET_MIPS64
 140 /*
 141    XXX: Assuming :
 142    - PABITS = 36 (correct for MIPS64R1)
 143 */
 144     } else if (address < 0x3FFFFFFFFFFFFFFFULL) {
 145         /* xuseg */
 146         if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 147             ret = env->map_address(env, physical, prot, address, rw, access_type);
 148         } else {
 149             ret = TLBRET_BADADDR;
 150         }
 151     } else if (address < 0x7FFFFFFFFFFFFFFFULL) {
 152         /* xsseg */
 153         if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 154             ret = env->map_address(env, physical, prot, address, rw, access_type);
 155         } else {
 156             ret = TLBRET_BADADDR;
 157         }
 158     } else if (address < 0xBFFFFFFFFFFFFFFFULL) {
 159         /* xkphys */
 160         /* XXX: check supervisor mode */
 161         if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
 162         {
 163             *physical = address & 0X0000000FFFFFFFFFULL;
 164             *prot = PAGE_READ | PAGE_WRITE;
 165         } else {
 166             ret = TLBRET_BADADDR;
 167         }
 168     } else if (address < 0xFFFFFFFF7FFFFFFFULL) {
 169         /* xkseg */
 170         /* XXX: check supervisor mode */
 171         if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 172             ret = env->map_address(env, physical, prot, address, rw, access_type);
 173         } else {
 174             ret = TLBRET_BADADDR;
 175         }
 176 #endif
 177     } else if (address < (int32_t)0xA0000000UL) {
 178         /* kseg0 */
 179         /* XXX: check supervisor mode */
 180         *physical = address - (int32_t)0x80000000UL;
 181         *prot = PAGE_READ | PAGE_WRITE;
 182     } else if (address < (int32_t)0xC0000000UL) {
 183         /* kseg1 */
 184         /* XXX: check supervisor mode */
 185         *physical = address - (int32_t)0xA0000000UL;
 186         *prot = PAGE_READ | PAGE_WRITE;
 187     } else if (address < (int32_t)0xE0000000UL) {
 188         /* kseg2 */
 189         ret = env->map_address(env, physical, prot, address, rw, access_type);
 190     } else {
 191         /* kseg3 */
 192         /* XXX: check supervisor mode */
 193         /* XXX: debug segment is not emulated */
 194         ret = env->map_address(env, physical, prot, address, rw, access_type);
 195     }
 196 #if 0
 197     if (logfile) {
 198         fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
 199                 address, rw, access_type, *physical, *prot, ret);
 200     }
 201 #endif
 202
 203     return ret;
 204 }
 205
 206 #if defined(CONFIG_USER_ONLY)
 207 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 208 {
 209     return addr;
 210 }
 211 #else
 212 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 213 {
 214     target_ulong phys_addr;
 215     int prot;
 216
 217     if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
 218         return -1;
 219     return phys_addr;
 220 }
 221
 222 void cpu_mips_init_mmu (CPUState *env)
 223 {
 224 }
 225 #endif /* !defined(CONFIG_USER_ONLY) */
 226
 227 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 228                                int is_user, int is_softmmu)
 229 {
 230     target_ulong physical;
 231     int prot;
 232     int exception = 0, error_code = 0;
 233     int access_type;
 234     int ret = 0;
 235
 236     if (logfile) {
 237 #if 0
 238         cpu_dump_state(env, logfile, fprintf, 0);
 239 #endif
 240         fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
 241                 __func__, env->PC, address, rw, is_user, is_softmmu);
 242     }
 243
 244     rw &= 1;
 245
 246     /* data access */
 247     /* XXX: put correct access by using cpu_restore_state()
 248        correctly */
 249     access_type = ACCESS_INT;
 250     if (env->user_mode_only) {
 251         /* user mode only emulation */
 252         ret = TLBRET_NOMATCH;
 253         goto do_fault;
 254     }
 255     ret = get_physical_address(env, &physical, &prot,
 256                                address, rw, access_type);
 257     if (logfile) {
 258         fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
 259                 __func__, address, ret, physical, prot);
 260     }
 261     if (ret == TLBRET_MATCH) {
 262        ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
 263                           physical & TARGET_PAGE_MASK, prot,
 264                           is_user, is_softmmu);
 265     } else if (ret < 0) {
 266     do_fault:
 267         switch (ret) {
 268         default:
 269         case TLBRET_BADADDR:
 270             /* Reference to kernel address from user mode or supervisor mode */
 271             /* Reference to supervisor address from user mode */
 272             if (rw)
 273                 exception = EXCP_AdES;
 274             else
 275                 exception = EXCP_AdEL;
 276             break;
 277         case TLBRET_NOMATCH:
 278             /* No TLB match for a mapped address */
 279             if (rw)
 280                 exception = EXCP_TLBS;
 281             else
 282                 exception = EXCP_TLBL;
 283             error_code = 1;
 284             break;
 285         case TLBRET_INVALID:
 286             /* TLB match with no valid bit */
 287             if (rw)
 288                 exception = EXCP_TLBS;
 289             else
 290                 exception = EXCP_TLBL;
 291             break;
 292         case TLBRET_DIRTY:
 293             /* TLB match but 'D' bit is cleared */
 294             exception = EXCP_LTLBL;
 295             break;
 296
 297         }
 298         /* Raise exception */
 299         env->CP0_BadVAddr = address;
 300         env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 301                            ((address >> 9) &   0x007ffff0);
 302         env->CP0_EntryHi =
 303             (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 304 #ifdef TARGET_MIPS64
 305         env->CP0_EntryHi &= env->SEGMask;
 306         env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 307                             ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |
 308                             ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 309 #endif
 310         env->exception_index = exception;
 311         env->error_code = error_code;
 312         ret = 1;
 313     }
 314
 315     return ret;
 316 }
 317
 318 #if defined(CONFIG_USER_ONLY)
 319 void do_interrupt (CPUState *env)
 320 {
 321     env->exception_index = EXCP_NONE;
 322 }
 323 #else
 324 void do_interrupt (CPUState *env)
 325 {
 326     target_ulong offset;
 327     int cause = -1;
 328
 329     if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
 330         fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
 331                 __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
 332     }
 333     if (env->exception_index == EXCP_EXT_INTERRUPT &&
 334         (env->hflags & MIPS_HFLAG_DM))
 335         env->exception_index = EXCP_DINT;
 336     offset = 0x180;
 337     switch (env->exception_index) {
 338     case EXCP_DSS:
 339         env->CP0_Debug |= 1 << CP0DB_DSS;
 340         /* Debug single step cannot be raised inside a delay slot and
 341          * resume will always occur on the next instruction
 342          * (but we assume the pc has always been updated during
 343          *  code translation).
 344          */
 345         env->CP0_DEPC = env->PC;
 346         goto enter_debug_mode;
 347     case EXCP_DINT:
 348         env->CP0_Debug |= 1 << CP0DB_DINT;
 349         goto set_DEPC;
 350     case EXCP_DIB:
 351         env->CP0_Debug |= 1 << CP0DB_DIB;
 352         goto set_DEPC;
 353     case EXCP_DBp:
 354         env->CP0_Debug |= 1 << CP0DB_DBp;
 355         goto set_DEPC;
 356     case EXCP_DDBS:
 357         env->CP0_Debug |= 1 << CP0DB_DDBS;
 358         goto set_DEPC;
 359     case EXCP_DDBL:
 360         env->CP0_Debug |= 1 << CP0DB_DDBL;
 361     set_DEPC:
 362         if (env->hflags & MIPS_HFLAG_BMASK) {
 363             /* If the exception was raised from a delay slot,
 364                come back to the jump.  */
 365             env->CP0_DEPC = env->PC - 4;
 366             env->hflags &= ~MIPS_HFLAG_BMASK;
 367         } else {
 368             env->CP0_DEPC = env->PC;
 369         }
 370     enter_debug_mode:
 371         env->hflags |= MIPS_HFLAG_DM;
 372         if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
 373             env->hflags |= MIPS_HFLAG_64;
 374         env->hflags &= ~MIPS_HFLAG_UM;
 375         /* EJTAG probe trap enable is not implemented... */
 376         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 377             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 378         env->PC = (int32_t)0xBFC00480;
 379         break;
 380     case EXCP_RESET:
 381         cpu_reset(env);
 382         break;
 383     case EXCP_SRESET:
 384         env->CP0_Status |= (1 << CP0St_SR);
 385         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 386         goto set_error_EPC;
 387     case EXCP_NMI:
 388         env->CP0_Status |= (1 << CP0St_NMI);
 389     set_error_EPC:
 390         if (env->hflags & MIPS_HFLAG_BMASK) {
 391             /* If the exception was raised from a delay slot,
 392                come back to the jump.  */
 393             env->CP0_ErrorEPC = env->PC - 4;
 394             env->hflags &= ~MIPS_HFLAG_BMASK;
 395         } else {
 396             env->CP0_ErrorEPC = env->PC;
 397         }
 398         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 399         if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
 400             env->hflags |= MIPS_HFLAG_64;
 401         env->hflags &= ~MIPS_HFLAG_UM;
 402         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 403             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 404         env->PC = (int32_t)0xBFC00000;
 405         break;
 406     case EXCP_MCHECK:
 407         cause = 24;
 408         goto set_EPC;
 409     case EXCP_EXT_INTERRUPT:
 410         cause = 0;
 411         if (env->CP0_Cause & (1 << CP0Ca_IV))
 412             offset = 0x200;
 413         goto set_EPC;
 414     case EXCP_DWATCH:
 415         cause = 23;
 416         /* XXX: TODO: manage defered watch exceptions */
 417         goto set_EPC;
 418     case EXCP_AdEL:
 419         cause = 4;
 420         goto set_EPC;
 421     case EXCP_AdES:
 422         cause = 5;
 423         goto set_EPC;
 424     case EXCP_TLBL:
 425         cause = 2;
 426         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 427 #ifdef TARGET_MIPS64
 428             int R = env->CP0_BadVAddr >> 62;
 429             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 430             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 431             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 432
 433             if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
 434                 offset = 0x080;
 435             else
 436 #endif
 437                 offset = 0x000;
 438         }
 439         goto set_EPC;
 440     case EXCP_IBE:
 441         cause = 6;
 442         goto set_EPC;
 443     case EXCP_DBE:
 444         cause = 7;
 445         goto set_EPC;
 446     case EXCP_SYSCALL:
 447         cause = 8;
 448         goto set_EPC;
 449     case EXCP_BREAK:
 450         cause = 9;
 451         goto set_EPC;
 452     case EXCP_RI:
 453         cause = 10;
 454         goto set_EPC;
 455     case EXCP_CpU:
 456         cause = 11;
 457         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 458                          (env->error_code << CP0Ca_CE);
 459         goto set_EPC;
 460     case EXCP_OVERFLOW:
 461         cause = 12;
 462         goto set_EPC;
 463     case EXCP_TRAP:
 464         cause = 13;
 465         goto set_EPC;
 466     case EXCP_FPE:
 467         cause = 15;
 468         goto set_EPC;
 469     case EXCP_LTLBL:
 470         cause = 1;
 471         goto set_EPC;
 472     case EXCP_TLBS:
 473         cause = 3;
 474         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 475 #ifdef TARGET_MIPS64
 476             int R = env->CP0_BadVAddr >> 62;
 477             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 478             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 479             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 480
 481             if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
 482                 offset = 0x080;
 483             else
 484 #endif
 485                 offset = 0x000;
 486         }
 487     set_EPC:
 488         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 489             if (env->hflags & MIPS_HFLAG_BMASK) {
 490                 /* If the exception was raised from a delay slot,
 491                    come back to the jump.  */
 492                 env->CP0_EPC = env->PC - 4;
 493                 env->CP0_Cause |= (1 << CP0Ca_BD);
 494             } else {
 495                 env->CP0_EPC = env->PC;
 496                 env->CP0_Cause &= ~(1 << CP0Ca_BD);
 497             }
 498             env->CP0_Status |= (1 << CP0St_EXL);
 499             if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
 500                 env->hflags |= MIPS_HFLAG_64;
 501             env->hflags &= ~MIPS_HFLAG_UM;
 502         }
 503         env->hflags &= ~MIPS_HFLAG_BMASK;
 504         if (env->CP0_Status & (1 << CP0St_BEV)) {
 505             env->PC = (int32_t)0xBFC00200;
 506         } else {
 507             env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 508         }
 509         env->PC += offset;
 510         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 511         break;
 512     default:
 513         if (logfile) {
 514             fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
 515                     env->exception_index);
 516         }
 517         printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 518         exit(1);
 519     }
 520     if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
 521         fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
 522                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 523                 __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
 524                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 525                 env->CP0_DEPC);
 526     }
 527     env->exception_index = EXCP_NONE;
 528 }
 529 #endif /* !defined(CONFIG_USER_ONLY) */
 530
 531 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
 532 {
 533     r4k_tlb_t *tlb;
 534     target_ulong addr;
 535     target_ulong end;
 536     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 537     target_ulong mask;
 538
 539     tlb = &env->mmu.r4k.tlb[idx];
 540     /* The qemu TLB is flushed when the ASID changes, so no need to
 541        flush these entries again.  */
 542     if (tlb->G == 0 && tlb->ASID != ASID) {
 543         return;
 544     }
 545
 546     if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
 547         /* For tlbwr, we can shadow the discarded entry into
 548            a new (fake) TLB entry, as long as the guest can not
 549            tell that it's there.  */
 550         env->mmu.r4k.tlb[env->tlb_in_use] = *tlb;
 551         env->tlb_in_use++;
 552         return;
 553     }
 554
 555     /* 1k pages are not supported. */
 556     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 557     if (tlb->V0) {
 558         addr = tlb->VPN & ~mask;
 559 #ifdef TARGET_MIPS64
 560         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 561             addr |= 0x3FFFFF0000000000ULL;
 562         }
 563 #endif
 564         end = addr | (mask >> 1);
 565         while (addr < end) {
 566             tlb_flush_page (env, addr);
 567             addr += TARGET_PAGE_SIZE;
 568         }
 569     }
 570     if (tlb->V1) {
 571         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 572 #ifdef TARGET_MIPS64
 573         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 574             addr |= 0x3FFFFF0000000000ULL;
 575         }
 576 #endif
 577         end = addr | mask;
 578         while (addr < end) {
 579             tlb_flush_page (env, addr);
 580             addr += TARGET_PAGE_SIZE;
 581         }
 582     }
 583 }