target-m68k/cpu.h

   1 /*
   2  * m68k virtual CPU header
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery
   5  *  Written by Paul Brook
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #ifndef CPU_M68K_H
  22 #define CPU_M68K_H
  23
  24 #define TARGET_LONG_BITS 32
  25
  26 #include "cpu-defs.h"
  27
  28 #include "softfloat.h"
  29
  30 #define MAX_QREGS 32
  31
  32 #define TARGET_HAS_ICE 1
  33
  34 #define ELF_MACHINE     EM_68K
  35
  36 #define EXCP_ACCESS         2   /* Access (MMU) error.  */
  37 #define EXCP_ADDRESS        3   /* Address error.  */
  38 #define EXCP_ILLEGAL        4   /* Illegal instruction.  */
  39 #define EXCP_DIV0           5   /* Divide by zero */
  40 #define EXCP_PRIVILEGE      8   /* Privilege violation.  */
  41 #define EXCP_TRACE          9
  42 #define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
  43 #define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
  44 #define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
  45 #define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
  46 #define EXCP_FORMAT         14  /* RTE format error.  */
  47 #define EXCP_UNINITIALIZED  15
  48 #define EXCP_TRAP0          32   /* User trap #0.  */
  49 #define EXCP_TRAP15         47   /* User trap #15.  */
  50 #define EXCP_UNSUPPORTED    61
  51 #define EXCP_ICE            13
  52
  53 #define EXCP_RTE            0x100
  54 #define EXCP_HALT_INSN      0x101
  55
  56 typedef struct CPUM68KState {
  57     uint32_t dregs[8];
  58     uint32_t aregs[8];
  59     uint32_t pc;
  60     uint32_t sr;
  61
  62     /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
  63     int current_sp;
  64     uint32_t sp[2];
  65
  66     /* Condition flags.  */
  67     uint32_t cc_op;
  68     uint32_t cc_dest;
  69     uint32_t cc_src;
  70     uint32_t cc_x;
  71
  72     float64 fregs[8];
  73     float64 fp_result;
  74     uint32_t fpcr;
  75     uint32_t fpsr;
  76     float_status fp_status;
  77
  78     uint64_t mactmp;
  79     /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
  80        two 8-bit parts.  We store a single 64-bit value and
  81        rearrange/extend this when changing modes.  */
  82     uint64_t macc[4];
  83     uint32_t macsr;
  84     uint32_t mac_mask;
  85
  86     /* Temporary storage for DIV helpers.  */
  87     uint32_t div1;
  88     uint32_t div2;
  89
  90     /* MMU status.  */
  91     struct {
  92         uint32_t ar;
  93     } mmu;
  94
  95     /* Control registers.  */
  96     uint32_t vbr;
  97     uint32_t mbar;
  98     uint32_t rambar0;
  99     uint32_t cacr;
 100
 101     uint32_t features;
 102
 103     /* ??? remove this.  */
 104     uint32_t t1;
 105
 106     /* exception/interrupt handling */
 107     jmp_buf jmp_env;
 108     int exception_index;
 109     int interrupt_request;
 110     int user_mode_only;
 111     int halted;
 112
 113     int pending_vector;
 114     int pending_level;
 115
 116     uint32_t qregs[MAX_QREGS];
 117
 118     CPU_COMMON
 119 } CPUM68KState;
 120
 121 CPUM68KState *cpu_m68k_init(void);
 122 int cpu_m68k_exec(CPUM68KState *s);
 123 void cpu_m68k_close(CPUM68KState *s);
 124 void do_interrupt(int is_hw);
 125 /* you can call this signal handler from your SIGBUS and SIGSEGV
 126    signal handlers to inform the virtual CPU of exceptions. non zero
 127    is returned if the signal was handled by the virtual CPU.  */
 128 int cpu_m68k_signal_handler(int host_signum, void *pinfo,
 129                            void *puc);
 130 void cpu_m68k_flush_flags(CPUM68KState *, int);
 131
 132 enum {
 133     CC_OP_DYNAMIC, /* Use env->cc_op  */
 134     CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
 135     CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
 136     CC_OP_ADD,   /* CC_DEST = result, CC_SRC = source */
 137     CC_OP_SUB,   /* CC_DEST = result, CC_SRC = source */
 138     CC_OP_CMPB,  /* CC_DEST = result, CC_SRC = source */
 139     CC_OP_CMPW,  /* CC_DEST = result, CC_SRC = source */
 140     CC_OP_ADDX,  /* CC_DEST = result, CC_SRC = source */
 141     CC_OP_SUBX,  /* CC_DEST = result, CC_SRC = source */
 142     CC_OP_SHL,   /* CC_DEST = source, CC_SRC = shift */
 143     CC_OP_SHR,   /* CC_DEST = source, CC_SRC = shift */
 144     CC_OP_SAR,   /* CC_DEST = source, CC_SRC = shift */
 145 };
 146
 147 #define CCF_C 0x01
 148 #define CCF_V 0x02
 149 #define CCF_Z 0x04
 150 #define CCF_N 0x08
 151 #define CCF_X 0x10
 152
 153 #define SR_I_SHIFT 8
 154 #define SR_I  0x0700
 155 #define SR_M  0x1000
 156 #define SR_S  0x2000
 157 #define SR_T  0x8000
 158
 159 #define M68K_SSP    0
 160 #define M68K_USP    1
 161
 162 /* CACR fields are implementation defined, but some bits are common.  */
 163 #define M68K_CACR_EUSP  0x10
 164
 165 #define MACSR_PAV0  0x100
 166 #define MACSR_OMC   0x080
 167 #define MACSR_SU    0x040
 168 #define MACSR_FI    0x020
 169 #define MACSR_RT    0x010
 170 #define MACSR_N     0x008
 171 #define MACSR_Z     0x004
 172 #define MACSR_V     0x002
 173 #define MACSR_EV    0x001
 174
 175 typedef struct m68k_def_t m68k_def_t;
 176
 177 int cpu_m68k_set_model(CPUM68KState *env, const char * name);
 178
 179 void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector);
 180 void m68k_set_macsr(CPUM68KState *env, uint32_t val);
 181 void m68k_switch_sp(CPUM68KState *env);
 182
 183 #define M68K_FPCR_PREC (1 << 6)
 184
 185 void do_m68k_semihosting(CPUM68KState *env, int nr);
 186
 187 /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
 188    Each feature covers the subset of instructions common to the
 189    ISA revisions mentioned.  */
 190
 191 enum m68k_features {
 192     M68K_FEATURE_CF_ISA_A,
 193     M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
 194     M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
 195     M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
 196     M68K_FEATURE_CF_FPU,
 197     M68K_FEATURE_CF_MAC,
 198     M68K_FEATURE_CF_EMAC,
 199     M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
 200     M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
 201     M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
 202     M68K_FEATURE_WORD_INDEX /* word sized address index registers.  */
 203 };
 204
 205 static inline int m68k_feature(CPUM68KState *env, int feature)
 206 {
 207     return (env->features & (1u << feature)) != 0;
 208 }
 209
 210 void register_m68k_insns (CPUM68KState *env);
 211
 212 #ifdef CONFIG_USER_ONLY
 213 /* Linux uses 8k pages.  */
 214 #define TARGET_PAGE_BITS 13
 215 #else
 216 /* Smallest TLB entry size is 1k.  */
 217 #define TARGET_PAGE_BITS 10
 218 #endif
 219
 220 #define CPUState CPUM68KState
 221 #define cpu_init cpu_m68k_init
 222 #define cpu_exec cpu_m68k_exec
 223 #define cpu_gen_code cpu_m68k_gen_code
 224 #define cpu_signal_handler cpu_m68k_signal_handler
 225
 226 #include "cpu-all.h"
 227
 228 #endif