hw/sun4u.c

   1 /*
   2  * QEMU Sun4u System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25 #include "m48t59.h"
  26
  27 #define KERNEL_LOAD_ADDR     0x00404000
  28 #define CMDLINE_ADDR         0x003ff000
  29 #define INITRD_LOAD_ADDR     0x00300000
  30 #define PROM_SIZE_MAX        (512 * 1024)
  31 #define PROM_ADDR            0x1fff0000000ULL
  32 #define PROM_VADDR           0x000ffd00000ULL
  33 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  34 #define APB_MEM_BASE         0x1ff00000000ULL
  35 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  36 #define PROM_FILENAME        "openbios-sparc64"
  37 #define NVRAM_SIZE           0x2000
  38
  39 /* TSC handling */
  40
  41 uint64_t cpu_get_tsc()
  42 {
  43     return qemu_get_clock(vm_clock);
  44 }
  45
  46 int DMA_get_channel_mode (int nchan)
  47 {
  48     return 0;
  49 }
  50 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  51 {
  52     return 0;
  53 }
  54 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  55 {
  56     return 0;
  57 }
  58 void DMA_hold_DREQ (int nchan) {}
  59 void DMA_release_DREQ (int nchan) {}
  60 void DMA_schedule(int nchan) {}
  61 void DMA_run (void) {}
  62 void DMA_init (int high_page_enable) {}
  63 void DMA_register_channel (int nchan,
  64                            DMA_transfer_handler transfer_handler,
  65                            void *opaque)
  66 {
  67 }
  68
  69 /* NVRAM helpers */
  70 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
  71 {
  72     m48t59_write(nvram, addr, value);
  73 }
  74
  75 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
  76 {
  77     return m48t59_read(nvram, addr);
  78 }
  79
  80 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
  81 {
  82     m48t59_write(nvram, addr, value >> 8);
  83     m48t59_write(nvram, addr + 1, value & 0xFF);
  84 }
  85
  86 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
  87 {
  88     uint16_t tmp;
  89
  90     tmp = m48t59_read(nvram, addr) << 8;
  91     tmp |= m48t59_read(nvram, addr + 1);
  92
  93     return tmp;
  94 }
  95
  96 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
  97 {
  98     m48t59_write(nvram, addr, value >> 24);
  99     m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
 100     m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
 101     m48t59_write(nvram, addr + 3, value & 0xFF);
 102 }
 103
 104 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
 105 {
 106     uint32_t tmp;
 107
 108     tmp = m48t59_read(nvram, addr) << 24;
 109     tmp |= m48t59_read(nvram, addr + 1) << 16;
 110     tmp |= m48t59_read(nvram, addr + 2) << 8;
 111     tmp |= m48t59_read(nvram, addr + 3);
 112
 113     return tmp;
 114 }
 115
 116 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
 117                        const unsigned char *str, uint32_t max)
 118 {
 119     int i;
 120
 121     for (i = 0; i < max && str[i] != '\0'; i++) {
 122         m48t59_write(nvram, addr + i, str[i]);
 123     }
 124     m48t59_write(nvram, addr + max - 1, '\0');
 125 }
 126
 127 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
 128 {
 129     int i;
 130
 131     memset(dst, 0, max);
 132     for (i = 0; i < max; i++) {
 133         dst[i] = NVRAM_get_byte(nvram, addr + i);
 134         if (dst[i] == '\0')
 135             break;
 136     }
 137
 138     return i;
 139 }
 140
 141 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 142 {
 143     uint16_t tmp;
 144     uint16_t pd, pd1, pd2;
 145
 146     tmp = prev >> 8;
 147     pd = prev ^ value;
 148     pd1 = pd & 0x000F;
 149     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 150     tmp ^= (pd1 << 3) | (pd1 << 8);
 151     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 152
 153     return tmp;
 154 }
 155
 156 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
 157 {
 158     uint32_t i;
 159     uint16_t crc = 0xFFFF;
 160     int odd;
 161
 162     odd = count & 1;
 163     count &= ~1;
 164     for (i = 0; i != count; i++) {
 165         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 166     }
 167     if (odd) {
 168         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 169     }
 170
 171     return crc;
 172 }
 173
 174 static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
 175                                 const unsigned char *str)
 176 {
 177     uint32_t len;
 178
 179     len = strlen(str) + 1;
 180     NVRAM_set_string(nvram, addr, str, len);
 181
 182     return addr + len;
 183 }
 184
 185 static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
 186                                     uint32_t end)
 187 {
 188     unsigned int i, sum;
 189
 190     // Length divided by 16
 191     m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
 192     m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
 193     // Checksum
 194     sum = m48t59_read(nvram, start);
 195     for (i = 0; i < 14; i++) {
 196         sum += m48t59_read(nvram, start + 2 + i);
 197         sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
 198     }
 199     m48t59_write(nvram, start + 1, sum & 0xff);
 200 }
 201
 202 extern int nographic;
 203
 204 int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 205                           const unsigned char *arch,
 206                           uint32_t RAM_size, int boot_device,
 207                           uint32_t kernel_image, uint32_t kernel_size,
 208                           const char *cmdline,
 209                           uint32_t initrd_image, uint32_t initrd_size,
 210                           uint32_t NVRAM_image,
 211                           int width, int height, int depth)
 212 {
 213     uint16_t crc;
 214     unsigned int i;
 215     uint32_t start, end;
 216
 217     /* Set parameters for Open Hack'Ware BIOS */
 218     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 219     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
 220     NVRAM_set_word(nvram,   0x14, NVRAM_size);
 221     NVRAM_set_string(nvram, 0x20, arch, 16);
 222     NVRAM_set_byte(nvram,   0x2f, nographic & 0xff);
 223     NVRAM_set_lword(nvram,  0x30, RAM_size);
 224     NVRAM_set_byte(nvram,   0x34, boot_device);
 225     NVRAM_set_lword(nvram,  0x38, kernel_image);
 226     NVRAM_set_lword(nvram,  0x3C, kernel_size);
 227     if (cmdline) {
 228         /* XXX: put the cmdline in NVRAM too ? */
 229         strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
 230         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
 231         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
 232     } else {
 233         NVRAM_set_lword(nvram,  0x40, 0);
 234         NVRAM_set_lword(nvram,  0x44, 0);
 235     }
 236     NVRAM_set_lword(nvram,  0x48, initrd_image);
 237     NVRAM_set_lword(nvram,  0x4C, initrd_size);
 238     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
 239
 240     NVRAM_set_word(nvram,   0x54, width);
 241     NVRAM_set_word(nvram,   0x56, height);
 242     NVRAM_set_word(nvram,   0x58, depth);
 243     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
 244     NVRAM_set_word(nvram,  0xFC, crc);
 245
 246     // OpenBIOS nvram variables
 247     // Variable partition
 248     start = 256;
 249     m48t59_write(nvram, start, 0x70);
 250     NVRAM_set_string(nvram, start + 4, "system", 12);
 251
 252     end = start + 16;
 253     for (i = 0; i < nb_prom_envs; i++)
 254         end = nvram_set_var(nvram, end, prom_envs[i]);
 255
 256     m48t59_write(nvram, end++ , 0);
 257     end = start + ((end - start + 15) & ~15);
 258     nvram_finish_partition(nvram, start, end);
 259
 260     // free partition
 261     start = end;
 262     m48t59_write(nvram, start, 0x7f);
 263     NVRAM_set_string(nvram, start + 4, "free", 12);
 264
 265     end = 0x1fd0;
 266     nvram_finish_partition(nvram, start, end);
 267
 268     return 0;
 269 }
 270
 271 void pic_info()
 272 {
 273 }
 274
 275 void irq_info()
 276 {
 277 }
 278
 279 void qemu_system_powerdown(void)
 280 {
 281 }
 282
 283 static void main_cpu_reset(void *opaque)
 284 {
 285     CPUState *env = opaque;
 286
 287     cpu_reset(env);
 288     ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
 289     ptimer_run(env->tick, 0);
 290     ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
 291     ptimer_run(env->stick, 0);
 292     ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
 293     ptimer_run(env->hstick, 0);
 294 }
 295
 296 void tick_irq(void *opaque)
 297 {
 298     CPUState *env = opaque;
 299
 300     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 301 }
 302
 303 void stick_irq(void *opaque)
 304 {
 305     CPUState *env = opaque;
 306
 307     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 308 }
 309
 310 void hstick_irq(void *opaque)
 311 {
 312     CPUState *env = opaque;
 313
 314     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 315 }
 316
 317 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
 318 {
 319 }
 320
 321 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 322 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 323 static const int ide_irq[2] = { 14, 15 };
 324
 325 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 326 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 327
 328 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 329 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 330
 331 static fdctrl_t *floppy_controller;
 332
 333 /* Sun4u hardware initialisation */
 334 static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
 335              DisplayState *ds, const char **fd_filename, int snapshot,
 336              const char *kernel_filename, const char *kernel_cmdline,
 337              const char *initrd_filename, const char *cpu_model)
 338 {
 339     CPUState *env;
 340     char buf[1024];
 341     m48t59_t *nvram;
 342     int ret, linux_boot;
 343     unsigned int i;
 344     long prom_offset, initrd_size, kernel_size;
 345     PCIBus *pci_bus;
 346     const sparc_def_t *def;
 347     QEMUBH *bh;
 348     qemu_irq *irq;
 349
 350     linux_boot = (kernel_filename != NULL);
 351
 352     /* init CPUs */
 353     if (cpu_model == NULL)
 354         cpu_model = "TI UltraSparc II";
 355     sparc_find_by_name(cpu_model, &def);
 356     if (def == NULL) {
 357         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 358         exit(1);
 359     }
 360     env = cpu_init();
 361     cpu_sparc_register(env, def);
 362     bh = qemu_bh_new(tick_irq, env);
 363     env->tick = ptimer_init(bh);
 364     ptimer_set_period(env->tick, 1ULL);
 365
 366     bh = qemu_bh_new(stick_irq, env);
 367     env->stick = ptimer_init(bh);
 368     ptimer_set_period(env->stick, 1ULL);
 369
 370     bh = qemu_bh_new(hstick_irq, env);
 371     env->hstick = ptimer_init(bh);
 372     ptimer_set_period(env->hstick, 1ULL);
 373     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 374     qemu_register_reset(main_cpu_reset, env);
 375     main_cpu_reset(env);
 376
 377     /* allocate RAM */
 378     cpu_register_physical_memory(0, ram_size, 0);
 379
 380     prom_offset = ram_size + vga_ram_size;
 381     cpu_register_physical_memory(PROM_ADDR,
 382                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
 383                                  prom_offset | IO_MEM_ROM);
 384
 385     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
 386     ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
 387     if (ret < 0) {
 388         fprintf(stderr, "qemu: could not load prom '%s'\n",
 389                 buf);
 390         exit(1);
 391     }
 392
 393     kernel_size = 0;
 394     initrd_size = 0;
 395     if (linux_boot) {
 396         /* XXX: put correct offset */
 397         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 398         if (kernel_size < 0)
 399             kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
 400         if (kernel_size < 0)
 401             kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
 402         if (kernel_size < 0) {
 403             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 404                     kernel_filename);
 405             exit(1);
 406         }
 407
 408         /* load initrd */
 409         if (initrd_filename) {
 410             initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
 411             if (initrd_size < 0) {
 412                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 413                         initrd_filename);
 414                 exit(1);
 415             }
 416         }
 417         if (initrd_size > 0) {
 418             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 419                 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
 420                     == 0x48647253) { // HdrS
 421                     stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 422                     stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
 423                     break;
 424                 }
 425             }
 426         }
 427     }
 428     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
 429     isa_mem_base = VGA_BASE;
 430     pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
 431
 432     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 433         if (serial_hds[i]) {
 434             serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]);
 435         }
 436     }
 437
 438     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 439         if (parallel_hds[i]) {
 440             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
 441         }
 442     }
 443
 444     for(i = 0; i < nb_nics; i++) {
 445         if (!nd_table[i].model)
 446             nd_table[i].model = "ne2k_pci";
 447         pci_nic_init(pci_bus, &nd_table[i], -1);
 448     }
 449
 450     irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
 451     // XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
 452     pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
 453     /* FIXME: wire up interrupts.  */
 454     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 455     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
 456     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 457     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
 458                          KERNEL_LOAD_ADDR, kernel_size,
 459                          kernel_cmdline,
 460                          INITRD_LOAD_ADDR, initrd_size,
 461                          /* XXX: need an option to load a NVRAM image */
 462                          0,
 463                          graphic_width, graphic_height, graphic_depth);
 464
 465 }
 466
 467 QEMUMachine sun4u_machine = {
 468     "sun4u",
 469     "Sun4u platform",
 470     sun4u_init,
 471 };