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Fix typo in comment, by Andreas Faerber.
[qemu/dscho.git] / hw / spitz.c
blob540e1b2065c333f5ea7d314e7baadd7207b6a37e
1 /*
2 * PXA270-based Clamshell PDA platforms.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GNU GPL v2.
8 */
9
10 #include "vl.h"
11
12 #define spitz_printf(format, ...) \
13 fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__)
14 #undef REG_FMT
15 #define REG_FMT "0x%02lx"
16
17 /* Spitz Flash */
18 #define FLASH_BASE 0x0c000000
19 #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
20 #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
21 #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
22 #define FLASH_ECCCNTR 0x0c /* ECC byte counter */
23 #define FLASH_ECCCLRR 0x10 /* Clear ECC */
24 #define FLASH_FLASHIO 0x14 /* Flash I/O */
25 #define FLASH_FLASHCTL 0x18 /* Flash Control */
26
27 #define FLASHCTL_CE0 (1 << 0)
28 #define FLASHCTL_CLE (1 << 1)
29 #define FLASHCTL_ALE (1 << 2)
30 #define FLASHCTL_WP (1 << 3)
31 #define FLASHCTL_CE1 (1 << 4)
32 #define FLASHCTL_RYBY (1 << 5)
33 #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
34
35 struct sl_nand_s {
36 target_phys_addr_t target_base;
37 struct nand_flash_s *nand;
38 uint8_t ctl;
39 struct ecc_state_s ecc;
40 };
41
42 static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
43 {
44 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
45 int ryby;
46 addr -= s->target_base;
47
48 switch (addr) {
49 #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
50 case FLASH_ECCLPLB:
51 return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
52 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
53
54 #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
55 case FLASH_ECCLPUB:
56 return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
57 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
58
59 case FLASH_ECCCP:
60 return s->ecc.cp;
61
62 case FLASH_ECCCNTR:
63 return s->ecc.count & 0xff;
64
65 case FLASH_FLASHCTL:
66 nand_getpins(s->nand, &ryby);
67 if (ryby)
68 return s->ctl | FLASHCTL_RYBY;
69 else
70 return s->ctl;
71
72 case FLASH_FLASHIO:
73 return ecc_digest(&s->ecc, nand_getio(s->nand));
74
75 default:
76 spitz_printf("Bad register offset " REG_FMT "\n", addr);
77 }
78 return 0;
79 }
80
81 static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
82 {
83 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
84 addr -= s->target_base;
85
86 if (addr == FLASH_FLASHIO)
87 return ecc_digest(&s->ecc, nand_getio(s->nand)) |
88 (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
89
90 return sl_readb(opaque, addr);
91 }
92
93 static void sl_writeb(void *opaque, target_phys_addr_t addr,
94 uint32_t value)
95 {
96 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
97 addr -= s->target_base;
98
99 switch (addr) {
100 case FLASH_ECCCLRR:
101 /* Value is ignored. */
102 ecc_reset(&s->ecc);
103 break;
104
105 case FLASH_FLASHCTL:
106 s->ctl = value & 0xff & ~FLASHCTL_RYBY;
107 nand_setpins(s->nand,
108 s->ctl & FLASHCTL_CLE,
109 s->ctl & FLASHCTL_ALE,
110 s->ctl & FLASHCTL_NCE,
111 s->ctl & FLASHCTL_WP,
112 0);
113 break;
114
115 case FLASH_FLASHIO:
116 nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
117 break;
118
119 default:
120 spitz_printf("Bad register offset " REG_FMT "\n", addr);
121 }
122 }
123
124 static void sl_save(QEMUFile *f, void *opaque)
125 {
126 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
127
128 qemu_put_8s(f, &s->ctl);
129 ecc_put(f, &s->ecc);
130 }
131
132 static int sl_load(QEMUFile *f, void *opaque, int version_id)
133 {
134 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
135
136 qemu_get_8s(f, &s->ctl);
137 ecc_get(f, &s->ecc);
138
139 return 0;
140 }
141
142 enum {
143 FLASH_128M,
144 FLASH_1024M,
145 };
146
147 static void sl_flash_register(struct pxa2xx_state_s *cpu, int size)
148 {
149 int iomemtype;
150 struct sl_nand_s *s;
151 CPUReadMemoryFunc *sl_readfn[] = {
152 sl_readb,
153 sl_readb,
154 sl_readl,
155 };
156 CPUWriteMemoryFunc *sl_writefn[] = {
157 sl_writeb,
158 sl_writeb,
159 sl_writeb,
160 };
161
162 s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s));
163 s->target_base = FLASH_BASE;
164 s->ctl = 0;
165 if (size == FLASH_128M)
166 s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
167 else if (size == FLASH_1024M)
168 s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
169
170 iomemtype = cpu_register_io_memory(0, sl_readfn,
171 sl_writefn, s);
172 cpu_register_physical_memory(s->target_base, 0x40, iomemtype);
173
174 register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
175 }
176
177 /* Spitz Keyboard */
178
179 #define SPITZ_KEY_STROBE_NUM 11
180 #define SPITZ_KEY_SENSE_NUM 7
181
182 static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
183 12, 17, 91, 34, 36, 38, 39
184 };
185
186 static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
187 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
188 };
189
190 /* Eighth additional row maps the special keys */
191 static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
192 { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
193 { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
194 { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
195 { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
196 { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
197 { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x3d },
198 { 0x37, 0x38, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
199 { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
200 };
201
202 #define SPITZ_GPIO_AK_INT 13 /* Remote control */
203 #define SPITZ_GPIO_SYNC 16 /* Sync button */
204 #define SPITZ_GPIO_ON_KEY 95 /* Power button */
205 #define SPITZ_GPIO_SWA 97 /* Lid */
206 #define SPITZ_GPIO_SWB 96 /* Tablet mode */
207
208 /* The special buttons are mapped to unused keys */
209 static const int spitz_gpiomap[5] = {
210 SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
211 SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
212 };
213 static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
214
215 struct spitz_keyboard_s {
216 struct pxa2xx_state_s *cpu;
217 int keymap[0x80];
218 uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
219 uint16_t strobe_state;
220 uint16_t sense_state;
221
222 uint16_t pre_map[0x100];
223 uint16_t modifiers;
224 uint16_t imodifiers;
225 uint8_t fifo[16];
226 int fifopos, fifolen;
227 QEMUTimer *kbdtimer;
228 };
229
230 static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s)
231 {
232 int i;
233 uint16_t strobe, sense = 0;
234 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
235 strobe = s->keyrow[i] & s->strobe_state;
236 if (strobe) {
237 sense |= 1 << i;
238 if (!(s->sense_state & (1 << i)))
239 pxa2xx_gpio_set(s->cpu->gpio, spitz_gpio_key_sense[i], 1);
240 } else if (s->sense_state & (1 << i))
241 pxa2xx_gpio_set(s->cpu->gpio, spitz_gpio_key_sense[i], 0);
242 }
243
244 s->sense_state = sense;
245 }
246
247 static void spitz_keyboard_strobe(int line, int level,
248 struct spitz_keyboard_s *s)
249 {
250 int i;
251 for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
252 if (spitz_gpio_key_strobe[i] == line) {
253 if (level)
254 s->strobe_state |= 1 << i;
255 else
256 s->strobe_state &= ~(1 << i);
257
258 spitz_keyboard_sense_update(s);
259 break;
260 }
261 }
262
263 static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode)
264 {
265 int spitz_keycode = s->keymap[keycode & 0x7f];
266 if (spitz_keycode == -1)
267 return;
268
269 /* Handle the additional keys */
270 if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
271 pxa2xx_gpio_set(s->cpu->gpio, spitz_gpiomap[spitz_keycode & 0xf],
272 (keycode < 0x80) ^
273 spitz_gpio_invert[spitz_keycode & 0xf]);
274 return;
275 }
276
277 if (keycode & 0x80)
278 s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
279 else
280 s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
281
282 spitz_keyboard_sense_update(s);
283 }
284
285 #define SHIFT (1 << 7)
286 #define CTRL (1 << 8)
287 #define FN (1 << 9)
288
289 #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
290
291 static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode)
292 {
293 uint16_t code;
294 int mapcode;
295 switch (keycode) {
296 case 0x2a: /* Left Shift */
297 s->modifiers |= 1;
298 break;
299 case 0xaa:
300 s->modifiers &= ~1;
301 break;
302 case 0x36: /* Right Shift */
303 s->modifiers |= 2;
304 break;
305 case 0xb6:
306 s->modifiers &= ~2;
307 break;
308 case 0x1d: /* Control */
309 s->modifiers |= 4;
310 break;
311 case 0x9d:
312 s->modifiers &= ~4;
313 break;
314 case 0x38: /* Alt */
315 s->modifiers |= 8;
316 break;
317 case 0xb8:
318 s->modifiers &= ~8;
319 break;
320 }
321
322 code = s->pre_map[mapcode = ((s->modifiers & 3) ?
323 (keycode | SHIFT) :
324 (keycode & ~SHIFT))];
325
326 if (code != mapcode) {
327 #if 0
328 if ((code & SHIFT) && !(s->modifiers & 1))
329 QUEUE_KEY(0x2a | (keycode & 0x80));
330 if ((code & CTRL ) && !(s->modifiers & 4))
331 QUEUE_KEY(0x1d | (keycode & 0x80));
332 if ((code & FN ) && !(s->modifiers & 8))
333 QUEUE_KEY(0x38 | (keycode & 0x80));
334 if ((code & FN ) && (s->modifiers & 1))
335 QUEUE_KEY(0x2a | (~keycode & 0x80));
336 if ((code & FN ) && (s->modifiers & 2))
337 QUEUE_KEY(0x36 | (~keycode & 0x80));
338 #else
339 if (keycode & 0x80) {
340 if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
341 QUEUE_KEY(0x2a | 0x80);
342 if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
343 QUEUE_KEY(0x1d | 0x80);
344 if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
345 QUEUE_KEY(0x38 | 0x80);
346 if ((s->imodifiers & 0x10) && (s->modifiers & 1))
347 QUEUE_KEY(0x2a);
348 if ((s->imodifiers & 0x20) && (s->modifiers & 2))
349 QUEUE_KEY(0x36);
350 s->imodifiers = 0;
351 } else {
352 if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
353 QUEUE_KEY(0x2a);
354 s->imodifiers |= 1;
355 }
356 if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
357 QUEUE_KEY(0x1d);
358 s->imodifiers |= 4;
359 }
360 if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
361 QUEUE_KEY(0x38);
362 s->imodifiers |= 8;
363 }
364 if ((code & FN ) && (s->modifiers & 1) &&
365 !(s->imodifiers & 0x10)) {
366 QUEUE_KEY(0x2a | 0x80);
367 s->imodifiers |= 0x10;
368 }
369 if ((code & FN ) && (s->modifiers & 2) &&
370 !(s->imodifiers & 0x20)) {
371 QUEUE_KEY(0x36 | 0x80);
372 s->imodifiers |= 0x20;
373 }
374 }
375 #endif
376 }
377
378 QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
379 }
380
381 static void spitz_keyboard_tick(void *opaque)
382 {
383 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
384
385 if (s->fifolen) {
386 spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
387 s->fifolen --;
388 if (s->fifopos >= 16)
389 s->fifopos = 0;
390 }
391
392 qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
393 }
394
395 static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s)
396 {
397 int i;
398 for (i = 0; i < 0x100; i ++)
399 s->pre_map[i] = i;
400 s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
401 s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
402 s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
403 s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
404 s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
405 s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
406 s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
407 s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
408 s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
409 s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
410 s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
411 s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
412 s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
413 s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
414 s->pre_map[0x0d ] = 0x12 | FN; /* equal */
415 s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
416 s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
417 s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
418 s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
419 s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
420 s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
421 s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
422 s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
423 s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
424 s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
425 s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
426 s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
427 s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
428
429 s->modifiers = 0;
430 s->imodifiers = 0;
431 s->fifopos = 0;
432 s->fifolen = 0;
433 s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s);
434 spitz_keyboard_tick(s);
435 }
436
437 #undef SHIFT
438 #undef CTRL
439 #undef FN
440
441 static void spitz_keyboard_save(QEMUFile *f, void *opaque)
442 {
443 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
444 int i;
445
446 qemu_put_be16s(f, &s->sense_state);
447 qemu_put_be16s(f, &s->strobe_state);
448 for (i = 0; i < 5; i ++)
449 qemu_put_byte(f, spitz_gpio_invert[i]);
450 }
451
452 static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
453 {
454 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
455 int i;
456
457 qemu_get_be16s(f, &s->sense_state);
458 qemu_get_be16s(f, &s->strobe_state);
459 for (i = 0; i < 5; i ++)
460 spitz_gpio_invert[i] = qemu_get_byte(f);
461
462 /* Release all pressed keys */
463 memset(s->keyrow, 0, sizeof(s->keyrow));
464 spitz_keyboard_sense_update(s);
465 s->modifiers = 0;
466 s->imodifiers = 0;
467 s->fifopos = 0;
468 s->fifolen = 0;
469
470 return 0;
471 }
472
473 static void spitz_keyboard_register(struct pxa2xx_state_s *cpu)
474 {
475 int i, j;
476 struct spitz_keyboard_s *s;
477
478 s = (struct spitz_keyboard_s *)
479 qemu_mallocz(sizeof(struct spitz_keyboard_s));
480 memset(s, 0, sizeof(struct spitz_keyboard_s));
481 s->cpu = cpu;
482
483 for (i = 0; i < 0x80; i ++)
484 s->keymap[i] = -1;
485 for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
486 for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
487 if (spitz_keymap[i][j] != -1)
488 s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
489
490 for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
491 pxa2xx_gpio_handler_set(cpu->gpio, spitz_gpio_key_strobe[i],
492 (gpio_handler_t) spitz_keyboard_strobe, s);
493
494 spitz_keyboard_pre_map(s);
495 qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
496
497 register_savevm("spitz_keyboard", 0, 0,
498 spitz_keyboard_save, spitz_keyboard_load, s);
499 }
500
501 /* SCOOP devices */
502
503 struct scoop_info_s {
504 target_phys_addr_t target_base;
505 uint16_t status;
506 uint16_t power;
507 uint32_t gpio_level;
508 uint32_t gpio_dir;
509 uint32_t prev_level;
510 struct {
511 gpio_handler_t fn;
512 void *opaque;
513 } handler[16];
514
515 uint16_t mcr;
516 uint16_t cdr;
517 uint16_t ccr;
518 uint16_t irr;
519 uint16_t imr;
520 uint16_t isr;
521 uint16_t gprr;
522 };
523
524 #define SCOOP_MCR 0x00
525 #define SCOOP_CDR 0x04
526 #define SCOOP_CSR 0x08
527 #define SCOOP_CPR 0x0c
528 #define SCOOP_CCR 0x10
529 #define SCOOP_IRR_IRM 0x14
530 #define SCOOP_IMR 0x18
531 #define SCOOP_ISR 0x1c
532 #define SCOOP_GPCR 0x20
533 #define SCOOP_GPWR 0x24
534 #define SCOOP_GPRR 0x28
535
536 static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
537 uint32_t level, diff;
538 int bit;
539 level = s->gpio_level & s->gpio_dir;
540
541 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
542 bit = ffs(diff) - 1;
543 if (s->handler[bit].fn)
544 s->handler[bit].fn(bit, (level >> bit) & 1,
545 s->handler[bit].opaque);
546 }
547
548 s->prev_level = level;
549 }
550
551 static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
552 {
553 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
554 addr -= s->target_base;
555
556 switch (addr) {
557 case SCOOP_MCR:
558 return s->mcr;
559 case SCOOP_CDR:
560 return s->cdr;
561 case SCOOP_CSR:
562 return s->status;
563 case SCOOP_CPR:
564 return s->power;
565 case SCOOP_CCR:
566 return s->ccr;
567 case SCOOP_IRR_IRM:
568 return s->irr;
569 case SCOOP_IMR:
570 return s->imr;
571 case SCOOP_ISR:
572 return s->isr;
573 case SCOOP_GPCR:
574 return s->gpio_dir;
575 case SCOOP_GPWR:
576 return s->gpio_level;
577 case SCOOP_GPRR:
578 return s->gprr;
579 default:
580 spitz_printf("Bad register offset " REG_FMT "\n", addr);
581 }
582
583 return 0;
584 }
585
586 static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
587 {
588 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
589 addr -= s->target_base;
590 value &= 0xffff;
591
592 switch (addr) {
593 case SCOOP_MCR:
594 s->mcr = value;
595 break;
596 case SCOOP_CDR:
597 s->cdr = value;
598 break;
599 case SCOOP_CPR:
600 s->power = value;
601 if (value & 0x80)
602 s->power |= 0x8040;
603 break;
604 case SCOOP_CCR:
605 s->ccr = value;
606 break;
607 case SCOOP_IRR_IRM:
608 s->irr = value;
609 break;
610 case SCOOP_IMR:
611 s->imr = value;
612 break;
613 case SCOOP_ISR:
614 s->isr = value;
615 break;
616 case SCOOP_GPCR:
617 s->gpio_dir = value;
618 scoop_gpio_handler_update(s);
619 break;
620 case SCOOP_GPWR:
621 s->gpio_level = value & s->gpio_dir;
622 scoop_gpio_handler_update(s);
623 break;
624 case SCOOP_GPRR:
625 s->gprr = value;
626 break;
627 default:
628 spitz_printf("Bad register offset " REG_FMT "\n", addr);
629 }
630 }
631
632 CPUReadMemoryFunc *scoop_readfn[] = {
633 scoop_readb,
634 scoop_readb,
635 scoop_readb,
636 };
637 CPUWriteMemoryFunc *scoop_writefn[] = {
638 scoop_writeb,
639 scoop_writeb,
640 scoop_writeb,
641 };
642
643 static inline void scoop_gpio_set(struct scoop_info_s *s, int line, int level)
644 {
645 if (line >= 16) {
646 spitz_printf("No GPIO pin %i\n", line);
647 return;
648 }
649
650 if (level)
651 s->gpio_level |= (1 << line);
652 else
653 s->gpio_level &= ~(1 << line);
654 }
655
656 static inline void scoop_gpio_handler_set(struct scoop_info_s *s, int line,
657 gpio_handler_t handler, void *opaque) {
658 if (line >= 16) {
659 spitz_printf("No GPIO pin %i\n", line);
660 return;
661 }
662
663 s->handler[line].fn = handler;
664 s->handler[line].opaque = opaque;
665 }
666
667 static void scoop_save(QEMUFile *f, void *opaque)
668 {
669 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
670 qemu_put_be16s(f, &s->status);
671 qemu_put_be16s(f, &s->power);
672 qemu_put_be32s(f, &s->gpio_level);
673 qemu_put_be32s(f, &s->gpio_dir);
674 qemu_put_be32s(f, &s->prev_level);
675 qemu_put_be16s(f, &s->mcr);
676 qemu_put_be16s(f, &s->cdr);
677 qemu_put_be16s(f, &s->ccr);
678 qemu_put_be16s(f, &s->irr);
679 qemu_put_be16s(f, &s->imr);
680 qemu_put_be16s(f, &s->isr);
681 qemu_put_be16s(f, &s->gprr);
682 }
683
684 static int scoop_load(QEMUFile *f, void *opaque, int version_id)
685 {
686 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
687 qemu_get_be16s(f, &s->status);
688 qemu_get_be16s(f, &s->power);
689 qemu_get_be32s(f, &s->gpio_level);
690 qemu_get_be32s(f, &s->gpio_dir);
691 qemu_get_be32s(f, &s->prev_level);
692 qemu_get_be16s(f, &s->mcr);
693 qemu_get_be16s(f, &s->cdr);
694 qemu_get_be16s(f, &s->ccr);
695 qemu_get_be16s(f, &s->irr);
696 qemu_get_be16s(f, &s->imr);
697 qemu_get_be16s(f, &s->isr);
698 qemu_get_be16s(f, &s->gprr);
699
700 return 0;
701 }
702
703 static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu,
704 int count) {
705 int iomemtype;
706 struct scoop_info_s *s;
707
708 s = (struct scoop_info_s *)
709 qemu_mallocz(sizeof(struct scoop_info_s) * 2);
710 memset(s, 0, sizeof(struct scoop_info_s) * count);
711 s[0].target_base = 0x10800000;
712 s[1].target_base = 0x08800040;
713
714 /* Ready */
715 s[0].status = 0x02;
716 s[1].status = 0x02;
717
718 iomemtype = cpu_register_io_memory(0, scoop_readfn,
719 scoop_writefn, &s[0]);
720 cpu_register_physical_memory(s[0].target_base, 0x1000, iomemtype);
721 register_savevm("scoop", 0, 0, scoop_save, scoop_load, &s[0]);
722
723 if (count < 2)
724 return s;
725
726 iomemtype = cpu_register_io_memory(0, scoop_readfn,
727 scoop_writefn, &s[1]);
728 cpu_register_physical_memory(s[1].target_base, 0x1000, iomemtype);
729 register_savevm("scoop", 1, 0, scoop_save, scoop_load, &s[1]);
730
731 return s;
732 }
733
734 /* LCD backlight controller */
735
736 #define LCDTG_RESCTL 0x00
737 #define LCDTG_PHACTRL 0x01
738 #define LCDTG_DUTYCTRL 0x02
739 #define LCDTG_POWERREG0 0x03
740 #define LCDTG_POWERREG1 0x04
741 #define LCDTG_GPOR3 0x05
742 #define LCDTG_PICTRL 0x06
743 #define LCDTG_POLCTRL 0x07
744
745 static int bl_intensity, bl_power;
746
747 static void spitz_bl_update(struct pxa2xx_state_s *s)
748 {
749 if (bl_power && bl_intensity)
750 spitz_printf("LCD Backlight now at %i/63\n", bl_intensity);
751 else
752 spitz_printf("LCD Backlight now off\n");
753 }
754
755 static void spitz_bl_bit5(int line, int level, void *opaque)
756 {
757 int prev = bl_intensity;
758
759 if (level)
760 bl_intensity &= ~0x20;
761 else
762 bl_intensity |= 0x20;
763
764 if (bl_power && prev != bl_intensity)
765 spitz_bl_update((struct pxa2xx_state_s *) opaque);
766 }
767
768 static void spitz_bl_power(int line, int level, void *opaque)
769 {
770 bl_power = !!level;
771 spitz_bl_update((struct pxa2xx_state_s *) opaque);
772 }
773
774 static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd)
775 {
776 int addr, value;
777 addr = cmd >> 5;
778 value = cmd & 0x1f;
779
780 switch (addr) {
781 case LCDTG_RESCTL:
782 if (value)
783 spitz_printf("LCD in QVGA mode\n");
784 else
785 spitz_printf("LCD in VGA mode\n");
786 break;
787
788 case LCDTG_DUTYCTRL:
789 bl_intensity &= ~0x1f;
790 bl_intensity |= value;
791 if (bl_power)
792 spitz_bl_update((struct pxa2xx_state_s *) opaque);
793 break;
794
795 case LCDTG_POWERREG0:
796 /* Set common voltage to M62332FP */
797 break;
798 }
799 }
800
801 /* SSP devices */
802
803 #define CORGI_SSP_PORT 2
804
805 #define SPITZ_GPIO_LCDCON_CS 53
806 #define SPITZ_GPIO_ADS7846_CS 14
807 #define SPITZ_GPIO_MAX1111_CS 20
808 #define SPITZ_GPIO_TP_INT 11
809
810 static int lcd_en, ads_en, max_en;
811 static struct max111x_s *max1111;
812 static struct ads7846_state_s *ads7846;
813
814 /* "Demux" the signal based on current chipselect */
815 static uint32_t corgi_ssp_read(void *opaque)
816 {
817 if (lcd_en)
818 return 0;
819 if (ads_en)
820 return ads7846_read(ads7846);
821 if (max_en)
822 return max111x_read(max1111);
823 return 0;
824 }
825
826 static void corgi_ssp_write(void *opaque, uint32_t value)
827 {
828 if (lcd_en)
829 spitz_lcdtg_dac_put(opaque, value);
830 if (ads_en)
831 ads7846_write(ads7846, value);
832 if (max_en)
833 max111x_write(max1111, value);
834 }
835
836 static void corgi_ssp_gpio_cs(int line, int level, struct pxa2xx_state_s *s)
837 {
838 if (line == SPITZ_GPIO_LCDCON_CS)
839 lcd_en = !level;
840 else if (line == SPITZ_GPIO_ADS7846_CS)
841 ads_en = !level;
842 else if (line == SPITZ_GPIO_MAX1111_CS)
843 max_en = !level;
844 }
845
846 #define MAX1111_BATT_VOLT 1
847 #define MAX1111_BATT_TEMP 2
848 #define MAX1111_ACIN_VOLT 3
849
850 #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
851 #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
852 #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
853
854 static void spitz_adc_temp_on(int line, int level, void *opaque)
855 {
856 if (!max1111)
857 return;
858
859 if (level)
860 max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
861 else
862 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
863 }
864
865 static void spitz_pendown_set(void *opaque, int line, int level)
866 {
867 struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
868 pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_TP_INT, level);
869 }
870
871 static void spitz_ssp_save(QEMUFile *f, void *opaque)
872 {
873 qemu_put_be32(f, lcd_en);
874 qemu_put_be32(f, ads_en);
875 qemu_put_be32(f, max_en);
876 qemu_put_be32(f, bl_intensity);
877 qemu_put_be32(f, bl_power);
878 }
879
880 static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
881 {
882 lcd_en = qemu_get_be32(f);
883 ads_en = qemu_get_be32(f);
884 max_en = qemu_get_be32(f);
885 bl_intensity = qemu_get_be32(f);
886 bl_power = qemu_get_be32(f);
887
888 return 0;
889 }
890
891 static void spitz_ssp_attach(struct pxa2xx_state_s *cpu)
892 {
893 lcd_en = ads_en = max_en = 0;
894
895 ads7846 = ads7846_init(qemu_allocate_irqs(spitz_pendown_set, cpu, 1)[0]);
896
897 max1111 = max1111_init(0);
898 max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
899 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
900 max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
901
902 pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
903 corgi_ssp_write, cpu);
904
905 pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
906 (gpio_handler_t) corgi_ssp_gpio_cs, cpu);
907 pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
908 (gpio_handler_t) corgi_ssp_gpio_cs, cpu);
909 pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
910 (gpio_handler_t) corgi_ssp_gpio_cs, cpu);
911
912 bl_intensity = 0x20;
913 bl_power = 0;
914
915 register_savevm("spitz_ssp", 0, 0, spitz_ssp_save, spitz_ssp_load, cpu);
916 }
917
918 /* CF Microdrive */
919
920 static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu)
921 {
922 struct pcmcia_card_s *md;
923 BlockDriverState *bs = bs_table[0];
924
925 if (bs && bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
926 md = dscm1xxxx_init(bs);
927 pxa2xx_pcmcia_attach(cpu->pcmcia[1], md);
928 }
929 }
930
931 /* Wm8750 and Max7310 on I2C */
932
933 #define AKITA_MAX_ADDR 0x18
934 #define SPITZ_WM_ADDRL 0x1b
935 #define SPITZ_WM_ADDRH 0x1a
936
937 #define SPITZ_GPIO_WM 5
938
939 #ifdef HAS_AUDIO
940 static void spitz_wm8750_addr(int line, int level, void *opaque)
941 {
942 i2c_slave *wm = (i2c_slave *) opaque;
943 if (level)
944 i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
945 else
946 i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
947 }
948 #endif
949
950 static void spitz_i2c_setup(struct pxa2xx_state_s *cpu)
951 {
952 /* Attach the CPU on one end of our I2C bus. */
953 i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
954
955 #ifdef HAS_AUDIO
956 AudioState *audio;
957 i2c_slave *wm;
958
959 audio = AUD_init();
960 if (!audio)
961 return;
962 /* Attach a WM8750 to the bus */
963 wm = wm8750_init(bus, audio);
964
965 spitz_wm8750_addr(0, 0, wm);
966 pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_WM, spitz_wm8750_addr, wm);
967 /* .. and to the sound interface. */
968 cpu->i2s->opaque = wm;
969 cpu->i2s->codec_out = wm8750_dac_dat;
970 cpu->i2s->codec_in = wm8750_adc_dat;
971 wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
972 #endif
973 }
974
975 static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu)
976 {
977 /* Attach a Max7310 to Akita I2C bus. */
978 i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
979 AKITA_MAX_ADDR);
980 }
981
982 /* Other peripherals */
983
984 static void spitz_charge_switch(int line, int level, void *opaque)
985 {
986 spitz_printf("Charging %s.\n", level ? "off" : "on");
987 }
988
989 static void spitz_discharge_switch(int line, int level, void *opaque)
990 {
991 spitz_printf("Discharging %s.\n", level ? "on" : "off");
992 }
993
994 static void spitz_greenled_switch(int line, int level, void *opaque)
995 {
996 spitz_printf("Green LED %s.\n", level ? "on" : "off");
997 }
998
999 static void spitz_orangeled_switch(int line, int level, void *opaque)
1000 {
1001 spitz_printf("Orange LED %s.\n", level ? "on" : "off");
1002 }
1003
1004 #define SPITZ_SCP_LED_GREEN 1
1005 #define SPITZ_SCP_JK_B 2
1006 #define SPITZ_SCP_CHRG_ON 3
1007 #define SPITZ_SCP_MUTE_L 4
1008 #define SPITZ_SCP_MUTE_R 5
1009 #define SPITZ_SCP_CF_POWER 6
1010 #define SPITZ_SCP_LED_ORANGE 7
1011 #define SPITZ_SCP_JK_A 8
1012 #define SPITZ_SCP_ADC_TEMP_ON 9
1013 #define SPITZ_SCP2_IR_ON 1
1014 #define SPITZ_SCP2_AKIN_PULLUP 2
1015 #define SPITZ_SCP2_BACKLIGHT_CONT 7
1016 #define SPITZ_SCP2_BACKLIGHT_ON 8
1017 #define SPITZ_SCP2_MIC_BIAS 9
1018
1019 static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu,
1020 struct scoop_info_s *scp, int num)
1021 {
1022 scoop_gpio_handler_set(&scp[0], SPITZ_SCP_CHRG_ON,
1023 spitz_charge_switch, cpu);
1024 scoop_gpio_handler_set(&scp[0], SPITZ_SCP_JK_B,
1025 spitz_discharge_switch, cpu);
1026 scoop_gpio_handler_set(&scp[0], SPITZ_SCP_LED_GREEN,
1027 spitz_greenled_switch, cpu);
1028 scoop_gpio_handler_set(&scp[0], SPITZ_SCP_LED_ORANGE,
1029 spitz_orangeled_switch, cpu);
1030
1031 if (num >= 2) {
1032 scoop_gpio_handler_set(&scp[1], SPITZ_SCP2_BACKLIGHT_CONT,
1033 spitz_bl_bit5, cpu);
1034 scoop_gpio_handler_set(&scp[1], SPITZ_SCP2_BACKLIGHT_ON,
1035 spitz_bl_power, cpu);
1036 }
1037
1038 scoop_gpio_handler_set(&scp[0], SPITZ_SCP_ADC_TEMP_ON,
1039 spitz_adc_temp_on, cpu);
1040 }
1041
1042 #define SPITZ_GPIO_HSYNC 22
1043 #define SPITZ_GPIO_SD_DETECT 9
1044 #define SPITZ_GPIO_SD_WP 81
1045 #define SPITZ_GPIO_ON_RESET 89
1046 #define SPITZ_GPIO_BAT_COVER 90
1047 #define SPITZ_GPIO_CF1_IRQ 105
1048 #define SPITZ_GPIO_CF1_CD 94
1049 #define SPITZ_GPIO_CF2_IRQ 106
1050 #define SPITZ_GPIO_CF2_CD 93
1051
1052 int spitz_hsync;
1053
1054 static void spitz_lcd_hsync_handler(void *opaque)
1055 {
1056 struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
1057 pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_HSYNC, spitz_hsync);
1058 spitz_hsync ^= 1;
1059 }
1060
1061 static void spitz_mmc_coverswitch_change(void *opaque, int in)
1062 {
1063 struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
1064 pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SD_DETECT, in);
1065 }
1066
1067 static void spitz_mmc_writeprotect_change(void *opaque, int wp)
1068 {
1069 struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
1070 pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SD_WP, wp);
1071 }
1072
1073 static void spitz_pcmcia_cb(void *opaque, int line, int level)
1074 {
1075 struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
1076 static const int gpio_map[] = {
1077 SPITZ_GPIO_CF1_IRQ, SPITZ_GPIO_CF1_CD,
1078 SPITZ_GPIO_CF2_IRQ, SPITZ_GPIO_CF2_CD,
1079 };
1080 pxa2xx_gpio_set(cpu->gpio, gpio_map[line], level);
1081 }
1082
1083 static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots)
1084 {
1085 qemu_irq *pcmcia_cb;
1086 /*
1087 * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
1088 * read to satisfy broken guests that poll-wait for hsync.
1089 * Simulating a real hsync event would be less practical and
1090 * wouldn't guarantee that a guest ever exits the loop.
1091 */
1092 spitz_hsync = 0;
1093 pxa2xx_gpio_read_notifier(cpu->gpio, spitz_lcd_hsync_handler, cpu);
1094 pxa2xx_lcd_vsync_cb(cpu->lcd, spitz_lcd_hsync_handler, cpu);
1095
1096 /* MMC/SD host */
1097 pxa2xx_mmci_handlers(cpu->mmc, cpu, spitz_mmc_writeprotect_change,
1098 spitz_mmc_coverswitch_change);
1099
1100 /* Battery lock always closed */
1101 pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_BAT_COVER, 1);
1102
1103 /* Handle reset */
1104 pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_ON_RESET, pxa2xx_reset, cpu);
1105
1106 /* PCMCIA signals: card's IRQ and Card-Detect */
1107 pcmcia_cb = qemu_allocate_irqs(spitz_pcmcia_cb, cpu, slots * 2);
1108 if (slots >= 1)
1109 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0], pcmcia_cb[0], pcmcia_cb[1]);
1110 if (slots >= 2)
1111 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1], pcmcia_cb[2], pcmcia_cb[3]);
1112
1113 /* Initialise the screen rotation related signals */
1114 spitz_gpio_invert[3] = 0; /* Always open */
1115 if (graphic_rotate) { /* Tablet mode */
1116 spitz_gpio_invert[4] = 0;
1117 } else { /* Portrait mode */
1118 spitz_gpio_invert[4] = 1;
1119 }
1120 pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SWA, spitz_gpio_invert[3]);
1121 pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SWB, spitz_gpio_invert[4]);
1122 }
1123
1124 /* Write the bootloader parameters memory area. */
1125
1126 #define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
1127
1128 struct __attribute__ ((__packed__)) sl_param_info {
1129 uint32_t comadj_keyword;
1130 int32_t comadj;
1131
1132 uint32_t uuid_keyword;
1133 char uuid[16];
1134
1135 uint32_t touch_keyword;
1136 int32_t touch_xp;
1137 int32_t touch_yp;
1138 int32_t touch_xd;
1139 int32_t touch_yd;
1140
1141 uint32_t adadj_keyword;
1142 int32_t adadj;
1143
1144 uint32_t phad_keyword;
1145 int32_t phadadj;
1146 } spitz_bootparam = {
1147 .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
1148 .comadj = 125,
1149 .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
1150 .uuid = { -1 },
1151 .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
1152 .touch_xp = -1,
1153 .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
1154 .adadj = -1,
1155 .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
1156 .phadadj = 0x01,
1157 };
1158
1159 static void sl_bootparam_write(uint32_t ptr)
1160 {
1161 memcpy(phys_ram_base + ptr, &spitz_bootparam,
1162 sizeof(struct sl_param_info));
1163 }
1164
1165 #define SL_PXA_PARAM_BASE 0xa0000a00
1166
1167 /* Board init. */
1168 enum spitz_model_e { spitz, akita, borzoi, terrier };
1169
1170 static void spitz_common_init(int ram_size, int vga_ram_size,
1171 DisplayState *ds, const char *kernel_filename,
1172 const char *kernel_cmdline, const char *initrd_filename,
1173 const char *cpu_model, enum spitz_model_e model, int arm_id)
1174 {
1175 uint32_t spitz_ram = 0x04000000;
1176 uint32_t spitz_rom = 0x00800000;
1177 struct pxa2xx_state_s *cpu;
1178 struct scoop_info_s *scp;
1179
1180 if (!cpu_model)
1181 cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
1182
1183 /* Setup CPU & memory */
1184 if (ram_size < spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE) {
1185 fprintf(stderr, "This platform requires %i bytes of memory\n",
1186 spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE);
1187 exit(1);
1188 }
1189 cpu = pxa270_init(spitz_ram, ds, cpu_model);
1190
1191 sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
1192
1193 cpu_register_physical_memory(0, spitz_rom,
1194 qemu_ram_alloc(spitz_rom) | IO_MEM_ROM);
1195
1196 /* Setup peripherals */
1197 spitz_keyboard_register(cpu);
1198
1199 spitz_ssp_attach(cpu);
1200
1201 scp = spitz_scoop_init(cpu, (model == akita) ? 1 : 2);
1202
1203 spitz_scoop_gpio_setup(cpu, scp, (model == akita) ? 1 : 2);
1204
1205 spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
1206
1207 spitz_i2c_setup(cpu);
1208
1209 if (model == akita)
1210 spitz_akita_i2c_setup(cpu);
1211
1212 if (model == terrier)
1213 /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
1214 spitz_microdrive_attach(cpu);
1215 else if (model != akita)
1216 /* A 4.0 GB microdrive is permanently sitting in CF slot 1. */
1217 spitz_microdrive_attach(cpu);
1218
1219 /* Setup initial (reset) machine state */
1220 cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
1221
1222 arm_load_kernel(cpu->env, spitz_ram, kernel_filename, kernel_cmdline,
1223 initrd_filename, arm_id, PXA2XX_SDRAM_BASE);
1224 sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE);
1225 }
1226
1227 static void spitz_init(int ram_size, int vga_ram_size, int boot_device,
1228 DisplayState *ds, const char **fd_filename, int snapshot,
1229 const char *kernel_filename, const char *kernel_cmdline,
1230 const char *initrd_filename, const char *cpu_model)
1231 {
1232 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1233 kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
1234 }
1235
1236 static void borzoi_init(int ram_size, int vga_ram_size, int boot_device,
1237 DisplayState *ds, const char **fd_filename, int snapshot,
1238 const char *kernel_filename, const char *kernel_cmdline,
1239 const char *initrd_filename, const char *cpu_model)
1240 {
1241 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1242 kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
1243 }
1244
1245 static void akita_init(int ram_size, int vga_ram_size, int boot_device,
1246 DisplayState *ds, const char **fd_filename, int snapshot,
1247 const char *kernel_filename, const char *kernel_cmdline,
1248 const char *initrd_filename, const char *cpu_model)
1249 {
1250 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1251 kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
1252 }
1253
1254 static void terrier_init(int ram_size, int vga_ram_size, int boot_device,
1255 DisplayState *ds, const char **fd_filename, int snapshot,
1256 const char *kernel_filename, const char *kernel_cmdline,
1257 const char *initrd_filename, const char *cpu_model)
1258 {
1259 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1260 kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
1261 }
1262
1263 QEMUMachine akitapda_machine = {
1264 "akita",
1265 "Akita PDA (PXA270)",
1266 akita_init,
1267 };
1268
1269 QEMUMachine spitzpda_machine = {
1270 "spitz",
1271 "Spitz PDA (PXA270)",
1272 spitz_init,
1273 };
1274
1275 QEMUMachine borzoipda_machine = {
1276 "borzoi",
1277 "Borzoi PDA (PXA270)",
1278 borzoi_init,
1279 };
1280
1281 QEMUMachine terrierpda_machine = {
1282 "terrier",
1283 "Terrier PDA (PXA270)",
1284 terrier_init,
1285 };
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