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Fix typo in comment, by Andreas Faerber.
[qemu/dscho.git] / hw / rtl8139.c
blob210af449f8e7beeeadd0fa62aef9a3fb54c7038b
1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 */
45
46 #include "vl.h"
47
48 /* debug RTL8139 card */
49 //#define DEBUG_RTL8139 1
50
51 #define PCI_FREQUENCY 33000000L
52
53 /* debug RTL8139 card C+ mode only */
54 //#define DEBUG_RTL8139CP 1
55
56 /* Calculate CRCs properly on Rx packets */
57 #define RTL8139_CALCULATE_RXCRC 1
58
59 /* Uncomment to enable on-board timer interrupts */
60 //#define RTL8139_ONBOARD_TIMER 1
61
62 #if defined(RTL8139_CALCULATE_RXCRC)
63 /* For crc32 */
64 #include <zlib.h>
65 #endif
66
67 #define SET_MASKED(input, mask, curr) \
68 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
69
70 /* arg % size for size which is a power of 2 */
71 #define MOD2(input, size) \
72 ( ( input ) & ( size - 1 ) )
73
74 #if defined (DEBUG_RTL8139)
75 # define DEBUG_PRINT(x) do { printf x ; } while (0)
76 #else
77 # define DEBUG_PRINT(x)
78 #endif
79
80 /* Symbolic offsets to registers. */
81 enum RTL8139_registers {
82 MAC0 = 0, /* Ethernet hardware address. */
83 MAR0 = 8, /* Multicast filter. */
84 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
85 /* Dump Tally Conter control register(64bit). C+ mode only */
86 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
87 RxBuf = 0x30,
88 ChipCmd = 0x37,
89 RxBufPtr = 0x38,
90 RxBufAddr = 0x3A,
91 IntrMask = 0x3C,
92 IntrStatus = 0x3E,
93 TxConfig = 0x40,
94 RxConfig = 0x44,
95 Timer = 0x48, /* A general-purpose counter. */
96 RxMissed = 0x4C, /* 24 bits valid, write clears. */
97 Cfg9346 = 0x50,
98 Config0 = 0x51,
99 Config1 = 0x52,
100 FlashReg = 0x54,
101 MediaStatus = 0x58,
102 Config3 = 0x59,
103 Config4 = 0x5A, /* absent on RTL-8139A */
104 HltClk = 0x5B,
105 MultiIntr = 0x5C,
106 PCIRevisionID = 0x5E,
107 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
108 BasicModeCtrl = 0x62,
109 BasicModeStatus = 0x64,
110 NWayAdvert = 0x66,
111 NWayLPAR = 0x68,
112 NWayExpansion = 0x6A,
113 /* Undocumented registers, but required for proper operation. */
114 FIFOTMS = 0x70, /* FIFO Control and test. */
115 CSCR = 0x74, /* Chip Status and Configuration Register. */
116 PARA78 = 0x78,
117 PARA7c = 0x7c, /* Magic transceiver parameter register. */
118 Config5 = 0xD8, /* absent on RTL-8139A */
119 /* C+ mode */
120 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
121 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
122 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
123 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
124 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
125 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
126 TxThresh = 0xEC, /* Early Tx threshold */
127 };
128
129 enum ClearBitMasks {
130 MultiIntrClear = 0xF000,
131 ChipCmdClear = 0xE2,
132 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
133 };
134
135 enum ChipCmdBits {
136 CmdReset = 0x10,
137 CmdRxEnb = 0x08,
138 CmdTxEnb = 0x04,
139 RxBufEmpty = 0x01,
140 };
141
142 /* C+ mode */
143 enum CplusCmdBits {
144 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
145 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
146 CPlusRxEnb = 0x0002,
147 CPlusTxEnb = 0x0001,
148 };
149
150 /* Interrupt register bits, using my own meaningful names. */
151 enum IntrStatusBits {
152 PCIErr = 0x8000,
153 PCSTimeout = 0x4000,
154 RxFIFOOver = 0x40,
155 RxUnderrun = 0x20,
156 RxOverflow = 0x10,
157 TxErr = 0x08,
158 TxOK = 0x04,
159 RxErr = 0x02,
160 RxOK = 0x01,
161
162 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
163 };
164
165 enum TxStatusBits {
166 TxHostOwns = 0x2000,
167 TxUnderrun = 0x4000,
168 TxStatOK = 0x8000,
169 TxOutOfWindow = 0x20000000,
170 TxAborted = 0x40000000,
171 TxCarrierLost = 0x80000000,
172 };
173 enum RxStatusBits {
174 RxMulticast = 0x8000,
175 RxPhysical = 0x4000,
176 RxBroadcast = 0x2000,
177 RxBadSymbol = 0x0020,
178 RxRunt = 0x0010,
179 RxTooLong = 0x0008,
180 RxCRCErr = 0x0004,
181 RxBadAlign = 0x0002,
182 RxStatusOK = 0x0001,
183 };
184
185 /* Bits in RxConfig. */
186 enum rx_mode_bits {
187 AcceptErr = 0x20,
188 AcceptRunt = 0x10,
189 AcceptBroadcast = 0x08,
190 AcceptMulticast = 0x04,
191 AcceptMyPhys = 0x02,
192 AcceptAllPhys = 0x01,
193 };
194
195 /* Bits in TxConfig. */
196 enum tx_config_bits {
197
198 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
199 TxIFGShift = 24,
200 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
201 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
202 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
203 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
204
205 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
206 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
207 TxClearAbt = (1 << 0), /* Clear abort (WO) */
208 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
209 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
210
211 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
212 };
213
214
215 /* Transmit Status of All Descriptors (TSAD) Register */
216 enum TSAD_bits {
217 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
218 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
219 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
220 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
221 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
222 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
223 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
224 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
225 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
226 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
227 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
228 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
229 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
230 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
231 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
232 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
233 };
234
235
236 /* Bits in Config1 */
237 enum Config1Bits {
238 Cfg1_PM_Enable = 0x01,
239 Cfg1_VPD_Enable = 0x02,
240 Cfg1_PIO = 0x04,
241 Cfg1_MMIO = 0x08,
242 LWAKE = 0x10, /* not on 8139, 8139A */
243 Cfg1_Driver_Load = 0x20,
244 Cfg1_LED0 = 0x40,
245 Cfg1_LED1 = 0x80,
246 SLEEP = (1 << 1), /* only on 8139, 8139A */
247 PWRDN = (1 << 0), /* only on 8139, 8139A */
248 };
249
250 /* Bits in Config3 */
251 enum Config3Bits {
252 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
253 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
254 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
255 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
256 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
257 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
258 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
259 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
260 };
261
262 /* Bits in Config4 */
263 enum Config4Bits {
264 LWPTN = (1 << 2), /* not on 8139, 8139A */
265 };
266
267 /* Bits in Config5 */
268 enum Config5Bits {
269 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
270 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
271 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
272 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
273 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
274 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
275 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
276 };
277
278 enum RxConfigBits {
279 /* rx fifo threshold */
280 RxCfgFIFOShift = 13,
281 RxCfgFIFONone = (7 << RxCfgFIFOShift),
282
283 /* Max DMA burst */
284 RxCfgDMAShift = 8,
285 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
286
287 /* rx ring buffer length */
288 RxCfgRcv8K = 0,
289 RxCfgRcv16K = (1 << 11),
290 RxCfgRcv32K = (1 << 12),
291 RxCfgRcv64K = (1 << 11) | (1 << 12),
292
293 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
294 RxNoWrap = (1 << 7),
295 };
296
297 /* Twister tuning parameters from RealTek.
298 Completely undocumented, but required to tune bad links on some boards. */
299 /*
300 enum CSCRBits {
301 CSCR_LinkOKBit = 0x0400,
302 CSCR_LinkChangeBit = 0x0800,
303 CSCR_LinkStatusBits = 0x0f000,
304 CSCR_LinkDownOffCmd = 0x003c0,
305 CSCR_LinkDownCmd = 0x0f3c0,
306 */
307 enum CSCRBits {
308 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
309 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
310 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
311 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
312 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
313 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
314 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
315 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
316 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
317 };
318
319 enum Cfg9346Bits {
320 Cfg9346_Lock = 0x00,
321 Cfg9346_Unlock = 0xC0,
322 };
323
324 typedef enum {
325 CH_8139 = 0,
326 CH_8139_K,
327 CH_8139A,
328 CH_8139A_G,
329 CH_8139B,
330 CH_8130,
331 CH_8139C,
332 CH_8100,
333 CH_8100B_8139D,
334 CH_8101,
335 } chip_t;
336
337 enum chip_flags {
338 HasHltClk = (1 << 0),
339 HasLWake = (1 << 1),
340 };
341
342 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
343 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
344 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
345
346 #define RTL8139_PCI_REVID_8139 0x10
347 #define RTL8139_PCI_REVID_8139CPLUS 0x20
348
349 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
350
351 /* Size is 64 * 16bit words */
352 #define EEPROM_9346_ADDR_BITS 6
353 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
354 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
355
356 enum Chip9346Operation
357 {
358 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
359 Chip9346_op_read = 0x80, /* 10 AAAAAA */
360 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
361 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
362 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
363 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
364 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
365 };
366
367 enum Chip9346Mode
368 {
369 Chip9346_none = 0,
370 Chip9346_enter_command_mode,
371 Chip9346_read_command,
372 Chip9346_data_read, /* from output register */
373 Chip9346_data_write, /* to input register, then to contents at specified address */
374 Chip9346_data_write_all, /* to input register, then filling contents */
375 };
376
377 typedef struct EEprom9346
378 {
379 uint16_t contents[EEPROM_9346_SIZE];
380 int mode;
381 uint32_t tick;
382 uint8_t address;
383 uint16_t input;
384 uint16_t output;
385
386 uint8_t eecs;
387 uint8_t eesk;
388 uint8_t eedi;
389 uint8_t eedo;
390 } EEprom9346;
391
392 typedef struct RTL8139TallyCounters
393 {
394 /* Tally counters */
395 uint64_t TxOk;
396 uint64_t RxOk;
397 uint64_t TxERR;
398 uint32_t RxERR;
399 uint16_t MissPkt;
400 uint16_t FAE;
401 uint32_t Tx1Col;
402 uint32_t TxMCol;
403 uint64_t RxOkPhy;
404 uint64_t RxOkBrd;
405 uint32_t RxOkMul;
406 uint16_t TxAbt;
407 uint16_t TxUndrn;
408 } RTL8139TallyCounters;
409
410 /* Clears all tally counters */
411 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
412
413 /* Writes tally counters to specified physical memory address */
414 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
415
416 /* Loads values of tally counters from VM state file */
417 static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters);
418
419 /* Saves values of tally counters to VM state file */
420 static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters);
421
422 typedef struct RTL8139State {
423 uint8_t phys[8]; /* mac address */
424 uint8_t mult[8]; /* multicast mask array */
425
426 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
427 uint32_t TxAddr[4]; /* TxAddr0 */
428 uint32_t RxBuf; /* Receive buffer */
429 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
430 uint32_t RxBufPtr;
431 uint32_t RxBufAddr;
432
433 uint16_t IntrStatus;
434 uint16_t IntrMask;
435
436 uint32_t TxConfig;
437 uint32_t RxConfig;
438 uint32_t RxMissed;
439
440 uint16_t CSCR;
441
442 uint8_t Cfg9346;
443 uint8_t Config0;
444 uint8_t Config1;
445 uint8_t Config3;
446 uint8_t Config4;
447 uint8_t Config5;
448
449 uint8_t clock_enabled;
450 uint8_t bChipCmdState;
451
452 uint16_t MultiIntr;
453
454 uint16_t BasicModeCtrl;
455 uint16_t BasicModeStatus;
456 uint16_t NWayAdvert;
457 uint16_t NWayLPAR;
458 uint16_t NWayExpansion;
459
460 uint16_t CpCmd;
461 uint8_t TxThresh;
462
463 PCIDevice *pci_dev;
464 VLANClientState *vc;
465 uint8_t macaddr[6];
466 int rtl8139_mmio_io_addr;
467
468 /* C ring mode */
469 uint32_t currTxDesc;
470
471 /* C+ mode */
472 uint32_t currCPlusRxDesc;
473 uint32_t currCPlusTxDesc;
474
475 uint32_t RxRingAddrLO;
476 uint32_t RxRingAddrHI;
477
478 EEprom9346 eeprom;
479
480 uint32_t TCTR;
481 uint32_t TimerInt;
482 int64_t TCTR_base;
483
484 /* Tally counters */
485 RTL8139TallyCounters tally_counters;
486
487 /* Non-persistent data */
488 uint8_t *cplus_txbuffer;
489 int cplus_txbuffer_len;
490 int cplus_txbuffer_offset;
491
492 /* PCI interrupt timer */
493 QEMUTimer *timer;
494
495 } RTL8139State;
496
497 void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
498 {
499 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
500
501 switch (command & Chip9346_op_mask)
502 {
503 case Chip9346_op_read:
504 {
505 eeprom->address = command & EEPROM_9346_ADDR_MASK;
506 eeprom->output = eeprom->contents[eeprom->address];
507 eeprom->eedo = 0;
508 eeprom->tick = 0;
509 eeprom->mode = Chip9346_data_read;
510 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
511 eeprom->address, eeprom->output));
512 }
513 break;
514
515 case Chip9346_op_write:
516 {
517 eeprom->address = command & EEPROM_9346_ADDR_MASK;
518 eeprom->input = 0;
519 eeprom->tick = 0;
520 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
521 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
522 eeprom->address));
523 }
524 break;
525 default:
526 eeprom->mode = Chip9346_none;
527 switch (command & Chip9346_op_ext_mask)
528 {
529 case Chip9346_op_write_enable:
530 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
531 break;
532 case Chip9346_op_write_all:
533 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
534 break;
535 case Chip9346_op_write_disable:
536 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
537 break;
538 }
539 break;
540 }
541 }
542
543 void prom9346_shift_clock(EEprom9346 *eeprom)
544 {
545 int bit = eeprom->eedi?1:0;
546
547 ++ eeprom->tick;
548
549 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
550
551 switch (eeprom->mode)
552 {
553 case Chip9346_enter_command_mode:
554 if (bit)
555 {
556 eeprom->mode = Chip9346_read_command;
557 eeprom->tick = 0;
558 eeprom->input = 0;
559 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
560 }
561 break;
562
563 case Chip9346_read_command:
564 eeprom->input = (eeprom->input << 1) | (bit & 1);
565 if (eeprom->tick == 8)
566 {
567 prom9346_decode_command(eeprom, eeprom->input & 0xff);
568 }
569 break;
570
571 case Chip9346_data_read:
572 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
573 eeprom->output <<= 1;
574 if (eeprom->tick == 16)
575 {
576 #if 1
577 // the FreeBSD drivers (rl and re) don't explicitly toggle
578 // CS between reads (or does setting Cfg9346 to 0 count too?),
579 // so we need to enter wait-for-command state here
580 eeprom->mode = Chip9346_enter_command_mode;
581 eeprom->input = 0;
582 eeprom->tick = 0;
583
584 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
585 #else
586 // original behaviour
587 ++eeprom->address;
588 eeprom->address &= EEPROM_9346_ADDR_MASK;
589 eeprom->output = eeprom->contents[eeprom->address];
590 eeprom->tick = 0;
591
592 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
593 eeprom->address, eeprom->output));
594 #endif
595 }
596 break;
597
598 case Chip9346_data_write:
599 eeprom->input = (eeprom->input << 1) | (bit & 1);
600 if (eeprom->tick == 16)
601 {
602 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
603 eeprom->address, eeprom->input));
604
605 eeprom->contents[eeprom->address] = eeprom->input;
606 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
607 eeprom->tick = 0;
608 eeprom->input = 0;
609 }
610 break;
611
612 case Chip9346_data_write_all:
613 eeprom->input = (eeprom->input << 1) | (bit & 1);
614 if (eeprom->tick == 16)
615 {
616 int i;
617 for (i = 0; i < EEPROM_9346_SIZE; i++)
618 {
619 eeprom->contents[i] = eeprom->input;
620 }
621 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
622 eeprom->input));
623
624 eeprom->mode = Chip9346_enter_command_mode;
625 eeprom->tick = 0;
626 eeprom->input = 0;
627 }
628 break;
629
630 default:
631 break;
632 }
633 }
634
635 int prom9346_get_wire(RTL8139State *s)
636 {
637 EEprom9346 *eeprom = &s->eeprom;
638 if (!eeprom->eecs)
639 return 0;
640
641 return eeprom->eedo;
642 }
643
644 void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
645 {
646 EEprom9346 *eeprom = &s->eeprom;
647 uint8_t old_eecs = eeprom->eecs;
648 uint8_t old_eesk = eeprom->eesk;
649
650 eeprom->eecs = eecs;
651 eeprom->eesk = eesk;
652 eeprom->eedi = eedi;
653
654 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
655 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
656
657 if (!old_eecs && eecs)
658 {
659 /* Synchronize start */
660 eeprom->tick = 0;
661 eeprom->input = 0;
662 eeprom->output = 0;
663 eeprom->mode = Chip9346_enter_command_mode;
664
665 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
666 }
667
668 if (!eecs)
669 {
670 DEBUG_PRINT(("=== eeprom: end access\n"));
671 return;
672 }
673
674 if (!old_eesk && eesk)
675 {
676 /* SK front rules */
677 prom9346_shift_clock(eeprom);
678 }
679 }
680
681 static void rtl8139_update_irq(RTL8139State *s)
682 {
683 int isr;
684 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
685
686 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
687 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
688
689 qemu_set_irq(s->pci_dev->irq[0], (isr != 0));
690 }
691
692 #define POLYNOMIAL 0x04c11db6
693
694 /* From FreeBSD */
695 /* XXX: optimize */
696 static int compute_mcast_idx(const uint8_t *ep)
697 {
698 uint32_t crc;
699 int carry, i, j;
700 uint8_t b;
701
702 crc = 0xffffffff;
703 for (i = 0; i < 6; i++) {
704 b = *ep++;
705 for (j = 0; j < 8; j++) {
706 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
707 crc <<= 1;
708 b >>= 1;
709 if (carry)
710 crc = ((crc ^ POLYNOMIAL) | carry);
711 }
712 }
713 return (crc >> 26);
714 }
715
716 static int rtl8139_RxWrap(RTL8139State *s)
717 {
718 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
719 return (s->RxConfig & (1 << 7));
720 }
721
722 static int rtl8139_receiver_enabled(RTL8139State *s)
723 {
724 return s->bChipCmdState & CmdRxEnb;
725 }
726
727 static int rtl8139_transmitter_enabled(RTL8139State *s)
728 {
729 return s->bChipCmdState & CmdTxEnb;
730 }
731
732 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
733 {
734 return s->CpCmd & CPlusRxEnb;
735 }
736
737 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
738 {
739 return s->CpCmd & CPlusTxEnb;
740 }
741
742 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
743 {
744 if (s->RxBufAddr + size > s->RxBufferSize)
745 {
746 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
747
748 /* write packet data */
749 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
750 {
751 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
752
753 if (size > wrapped)
754 {
755 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
756 buf, size-wrapped );
757 }
758
759 /* reset buffer pointer */
760 s->RxBufAddr = 0;
761
762 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
763 buf + (size-wrapped), wrapped );
764
765 s->RxBufAddr = wrapped;
766
767 return;
768 }
769 }
770
771 /* non-wrapping path or overwrapping enabled */
772 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
773
774 s->RxBufAddr += size;
775 }
776
777 #define MIN_BUF_SIZE 60
778 static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
779 {
780 #if TARGET_PHYS_ADDR_BITS > 32
781 return low | ((target_phys_addr_t)high << 32);
782 #else
783 return low;
784 #endif
785 }
786
787 static int rtl8139_can_receive(void *opaque)
788 {
789 RTL8139State *s = opaque;
790 int avail;
791
792 /* Receive (drop) packets if card is disabled. */
793 if (!s->clock_enabled)
794 return 1;
795 if (!rtl8139_receiver_enabled(s))
796 return 1;
797
798 if (rtl8139_cp_receiver_enabled(s)) {
799 /* ??? Flow control not implemented in c+ mode.
800 This is a hack to work around slirp deficiencies anyway. */
801 return 1;
802 } else {
803 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
804 s->RxBufferSize);
805 return (avail == 0 || avail >= 1514);
806 }
807 }
808
809 static void rtl8139_do_receive(void *opaque, const uint8_t *buf, int size, int do_interrupt)
810 {
811 RTL8139State *s = opaque;
812
813 uint32_t packet_header = 0;
814
815 uint8_t buf1[60];
816 static const uint8_t broadcast_macaddr[6] =
817 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
818
819 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
820
821 /* test if board clock is stopped */
822 if (!s->clock_enabled)
823 {
824 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
825 return;
826 }
827
828 /* first check if receiver is enabled */
829
830 if (!rtl8139_receiver_enabled(s))
831 {
832 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
833 return;
834 }
835
836 /* XXX: check this */
837 if (s->RxConfig & AcceptAllPhys) {
838 /* promiscuous: receive all */
839 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
840
841 } else {
842 if (!memcmp(buf, broadcast_macaddr, 6)) {
843 /* broadcast address */
844 if (!(s->RxConfig & AcceptBroadcast))
845 {
846 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
847
848 /* update tally counter */
849 ++s->tally_counters.RxERR;
850
851 return;
852 }
853
854 packet_header |= RxBroadcast;
855
856 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
857
858 /* update tally counter */
859 ++s->tally_counters.RxOkBrd;
860
861 } else if (buf[0] & 0x01) {
862 /* multicast */
863 if (!(s->RxConfig & AcceptMulticast))
864 {
865 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
866
867 /* update tally counter */
868 ++s->tally_counters.RxERR;
869
870 return;
871 }
872
873 int mcast_idx = compute_mcast_idx(buf);
874
875 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
876 {
877 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
878
879 /* update tally counter */
880 ++s->tally_counters.RxERR;
881
882 return;
883 }
884
885 packet_header |= RxMulticast;
886
887 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
888
889 /* update tally counter */
890 ++s->tally_counters.RxOkMul;
891
892 } else if (s->phys[0] == buf[0] &&
893 s->phys[1] == buf[1] &&
894 s->phys[2] == buf[2] &&
895 s->phys[3] == buf[3] &&
896 s->phys[4] == buf[4] &&
897 s->phys[5] == buf[5]) {
898 /* match */
899 if (!(s->RxConfig & AcceptMyPhys))
900 {
901 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
902
903 /* update tally counter */
904 ++s->tally_counters.RxERR;
905
906 return;
907 }
908
909 packet_header |= RxPhysical;
910
911 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
912
913 /* update tally counter */
914 ++s->tally_counters.RxOkPhy;
915
916 } else {
917
918 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
919
920 /* update tally counter */
921 ++s->tally_counters.RxERR;
922
923 return;
924 }
925 }
926
927 /* if too small buffer, then expand it */
928 if (size < MIN_BUF_SIZE) {
929 memcpy(buf1, buf, size);
930 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
931 buf = buf1;
932 size = MIN_BUF_SIZE;
933 }
934
935 if (rtl8139_cp_receiver_enabled(s))
936 {
937 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
938
939 /* begin C+ receiver mode */
940
941 /* w0 ownership flag */
942 #define CP_RX_OWN (1<<31)
943 /* w0 end of ring flag */
944 #define CP_RX_EOR (1<<30)
945 /* w0 bits 0...12 : buffer size */
946 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
947 /* w1 tag available flag */
948 #define CP_RX_TAVA (1<<16)
949 /* w1 bits 0...15 : VLAN tag */
950 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
951 /* w2 low 32bit of Rx buffer ptr */
952 /* w3 high 32bit of Rx buffer ptr */
953
954 int descriptor = s->currCPlusRxDesc;
955 target_phys_addr_t cplus_rx_ring_desc;
956
957 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
958 cplus_rx_ring_desc += 16 * descriptor;
959
960 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
961 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
962
963 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
964
965 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
966 rxdw0 = le32_to_cpu(val);
967 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
968 rxdw1 = le32_to_cpu(val);
969 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
970 rxbufLO = le32_to_cpu(val);
971 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
972 rxbufHI = le32_to_cpu(val);
973
974 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
975 descriptor,
976 rxdw0, rxdw1, rxbufLO, rxbufHI));
977
978 if (!(rxdw0 & CP_RX_OWN))
979 {
980 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
981
982 s->IntrStatus |= RxOverflow;
983 ++s->RxMissed;
984
985 /* update tally counter */
986 ++s->tally_counters.RxERR;
987 ++s->tally_counters.MissPkt;
988
989 rtl8139_update_irq(s);
990 return;
991 }
992
993 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
994
995 /* TODO: scatter the packet over available receive ring descriptors space */
996
997 if (size+4 > rx_space)
998 {
999 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1000 descriptor, rx_space, size));
1001
1002 s->IntrStatus |= RxOverflow;
1003 ++s->RxMissed;
1004
1005 /* update tally counter */
1006 ++s->tally_counters.RxERR;
1007 ++s->tally_counters.MissPkt;
1008
1009 rtl8139_update_irq(s);
1010 return;
1011 }
1012
1013 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1014
1015 /* receive/copy to target memory */
1016 cpu_physical_memory_write( rx_addr, buf, size );
1017
1018 if (s->CpCmd & CPlusRxChkSum)
1019 {
1020 /* do some packet checksumming */
1021 }
1022
1023 /* write checksum */
1024 #if defined (RTL8139_CALCULATE_RXCRC)
1025 val = cpu_to_le32(crc32(0, buf, size));
1026 #else
1027 val = 0;
1028 #endif
1029 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1030
1031 /* first segment of received packet flag */
1032 #define CP_RX_STATUS_FS (1<<29)
1033 /* last segment of received packet flag */
1034 #define CP_RX_STATUS_LS (1<<28)
1035 /* multicast packet flag */
1036 #define CP_RX_STATUS_MAR (1<<26)
1037 /* physical-matching packet flag */
1038 #define CP_RX_STATUS_PAM (1<<25)
1039 /* broadcast packet flag */
1040 #define CP_RX_STATUS_BAR (1<<24)
1041 /* runt packet flag */
1042 #define CP_RX_STATUS_RUNT (1<<19)
1043 /* crc error flag */
1044 #define CP_RX_STATUS_CRC (1<<18)
1045 /* IP checksum error flag */
1046 #define CP_RX_STATUS_IPF (1<<15)
1047 /* UDP checksum error flag */
1048 #define CP_RX_STATUS_UDPF (1<<14)
1049 /* TCP checksum error flag */
1050 #define CP_RX_STATUS_TCPF (1<<13)
1051
1052 /* transfer ownership to target */
1053 rxdw0 &= ~CP_RX_OWN;
1054
1055 /* set first segment bit */
1056 rxdw0 |= CP_RX_STATUS_FS;
1057
1058 /* set last segment bit */
1059 rxdw0 |= CP_RX_STATUS_LS;
1060
1061 /* set received packet type flags */
1062 if (packet_header & RxBroadcast)
1063 rxdw0 |= CP_RX_STATUS_BAR;
1064 if (packet_header & RxMulticast)
1065 rxdw0 |= CP_RX_STATUS_MAR;
1066 if (packet_header & RxPhysical)
1067 rxdw0 |= CP_RX_STATUS_PAM;
1068
1069 /* set received size */
1070 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1071 rxdw0 |= (size+4);
1072
1073 /* reset VLAN tag flag */
1074 rxdw1 &= ~CP_RX_TAVA;
1075
1076 /* update ring data */
1077 val = cpu_to_le32(rxdw0);
1078 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1079 val = cpu_to_le32(rxdw1);
1080 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1081
1082 /* update tally counter */
1083 ++s->tally_counters.RxOk;
1084
1085 /* seek to next Rx descriptor */
1086 if (rxdw0 & CP_RX_EOR)
1087 {
1088 s->currCPlusRxDesc = 0;
1089 }
1090 else
1091 {
1092 ++s->currCPlusRxDesc;
1093 }
1094
1095 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
1096
1097 }
1098 else
1099 {
1100 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1101
1102 /* begin ring receiver mode */
1103 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1104
1105 /* if receiver buffer is empty then avail == 0 */
1106
1107 if (avail != 0 && size + 8 >= avail)
1108 {
1109 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1110 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1111
1112 s->IntrStatus |= RxOverflow;
1113 ++s->RxMissed;
1114 rtl8139_update_irq(s);
1115 return;
1116 }
1117
1118 packet_header |= RxStatusOK;
1119
1120 packet_header |= (((size+4) << 16) & 0xffff0000);
1121
1122 /* write header */
1123 uint32_t val = cpu_to_le32(packet_header);
1124
1125 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1126
1127 rtl8139_write_buffer(s, buf, size);
1128
1129 /* write checksum */
1130 #if defined (RTL8139_CALCULATE_RXCRC)
1131 val = cpu_to_le32(crc32(0, buf, size));
1132 #else
1133 val = 0;
1134 #endif
1135
1136 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1137
1138 /* correct buffer write pointer */
1139 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1140
1141 /* now we can signal we have received something */
1142
1143 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1144 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
1145 }
1146
1147 s->IntrStatus |= RxOK;
1148
1149 if (do_interrupt)
1150 {
1151 rtl8139_update_irq(s);
1152 }
1153 }
1154
1155 static void rtl8139_receive(void *opaque, const uint8_t *buf, int size)
1156 {
1157 rtl8139_do_receive(opaque, buf, size, 1);
1158 }
1159
1160 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1161 {
1162 s->RxBufferSize = bufferSize;
1163 s->RxBufPtr = 0;
1164 s->RxBufAddr = 0;
1165 }
1166
1167 static void rtl8139_reset(RTL8139State *s)
1168 {
1169 int i;
1170
1171 /* restore MAC address */
1172 memcpy(s->phys, s->macaddr, 6);
1173
1174 /* reset interrupt mask */
1175 s->IntrStatus = 0;
1176 s->IntrMask = 0;
1177
1178 rtl8139_update_irq(s);
1179
1180 /* prepare eeprom */
1181 s->eeprom.contents[0] = 0x8129;
1182 #if 1
1183 // PCI vendor and device ID should be mirrored here
1184 s->eeprom.contents[1] = 0x10ec;
1185 s->eeprom.contents[2] = 0x8139;
1186 #endif
1187
1188 s->eeprom.contents[7] = s->macaddr[0] | s->macaddr[1] << 8;
1189 s->eeprom.contents[8] = s->macaddr[2] | s->macaddr[3] << 8;
1190 s->eeprom.contents[9] = s->macaddr[4] | s->macaddr[5] << 8;
1191
1192 /* mark all status registers as owned by host */
1193 for (i = 0; i < 4; ++i)
1194 {
1195 s->TxStatus[i] = TxHostOwns;
1196 }
1197
1198 s->currTxDesc = 0;
1199 s->currCPlusRxDesc = 0;
1200 s->currCPlusTxDesc = 0;
1201
1202 s->RxRingAddrLO = 0;
1203 s->RxRingAddrHI = 0;
1204
1205 s->RxBuf = 0;
1206
1207 rtl8139_reset_rxring(s, 8192);
1208
1209 /* ACK the reset */
1210 s->TxConfig = 0;
1211
1212 #if 0
1213 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1214 s->clock_enabled = 0;
1215 #else
1216 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1217 s->clock_enabled = 1;
1218 #endif
1219
1220 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1221
1222 /* set initial state data */
1223 s->Config0 = 0x0; /* No boot ROM */
1224 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1225 s->Config3 = 0x1; /* fast back-to-back compatible */
1226 s->Config5 = 0x0;
1227
1228 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1229
1230 s->CpCmd = 0x0; /* reset C+ mode */
1231
1232 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1233 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1234 s->BasicModeCtrl = 0x1000; // autonegotiation
1235
1236 s->BasicModeStatus = 0x7809;
1237 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1238 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1239 s->BasicModeStatus |= 0x0004; /* link is up */
1240
1241 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1242 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1243 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1244
1245 /* also reset timer and disable timer interrupt */
1246 s->TCTR = 0;
1247 s->TimerInt = 0;
1248 s->TCTR_base = 0;
1249
1250 /* reset tally counters */
1251 RTL8139TallyCounters_clear(&s->tally_counters);
1252 }
1253
1254 void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1255 {
1256 counters->TxOk = 0;
1257 counters->RxOk = 0;
1258 counters->TxERR = 0;
1259 counters->RxERR = 0;
1260 counters->MissPkt = 0;
1261 counters->FAE = 0;
1262 counters->Tx1Col = 0;
1263 counters->TxMCol = 0;
1264 counters->RxOkPhy = 0;
1265 counters->RxOkBrd = 0;
1266 counters->RxOkMul = 0;
1267 counters->TxAbt = 0;
1268 counters->TxUndrn = 0;
1269 }
1270
1271 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1272 {
1273 uint16_t val16;
1274 uint32_t val32;
1275 uint64_t val64;
1276
1277 val64 = cpu_to_le64(tally_counters->TxOk);
1278 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1279
1280 val64 = cpu_to_le64(tally_counters->RxOk);
1281 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1282
1283 val64 = cpu_to_le64(tally_counters->TxERR);
1284 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1285
1286 val32 = cpu_to_le32(tally_counters->RxERR);
1287 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1288
1289 val16 = cpu_to_le16(tally_counters->MissPkt);
1290 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1291
1292 val16 = cpu_to_le16(tally_counters->FAE);
1293 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1294
1295 val32 = cpu_to_le32(tally_counters->Tx1Col);
1296 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1297
1298 val32 = cpu_to_le32(tally_counters->TxMCol);
1299 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1300
1301 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1302 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1303
1304 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1305 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1306
1307 val32 = cpu_to_le32(tally_counters->RxOkMul);
1308 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1309
1310 val16 = cpu_to_le16(tally_counters->TxAbt);
1311 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1312
1313 val16 = cpu_to_le16(tally_counters->TxUndrn);
1314 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1315 }
1316
1317 /* Loads values of tally counters from VM state file */
1318 static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1319 {
1320 qemu_get_be64s(f, &tally_counters->TxOk);
1321 qemu_get_be64s(f, &tally_counters->RxOk);
1322 qemu_get_be64s(f, &tally_counters->TxERR);
1323 qemu_get_be32s(f, &tally_counters->RxERR);
1324 qemu_get_be16s(f, &tally_counters->MissPkt);
1325 qemu_get_be16s(f, &tally_counters->FAE);
1326 qemu_get_be32s(f, &tally_counters->Tx1Col);
1327 qemu_get_be32s(f, &tally_counters->TxMCol);
1328 qemu_get_be64s(f, &tally_counters->RxOkPhy);
1329 qemu_get_be64s(f, &tally_counters->RxOkBrd);
1330 qemu_get_be32s(f, &tally_counters->RxOkMul);
1331 qemu_get_be16s(f, &tally_counters->TxAbt);
1332 qemu_get_be16s(f, &tally_counters->TxUndrn);
1333 }
1334
1335 /* Saves values of tally counters to VM state file */
1336 static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1337 {
1338 qemu_put_be64s(f, &tally_counters->TxOk);
1339 qemu_put_be64s(f, &tally_counters->RxOk);
1340 qemu_put_be64s(f, &tally_counters->TxERR);
1341 qemu_put_be32s(f, &tally_counters->RxERR);
1342 qemu_put_be16s(f, &tally_counters->MissPkt);
1343 qemu_put_be16s(f, &tally_counters->FAE);
1344 qemu_put_be32s(f, &tally_counters->Tx1Col);
1345 qemu_put_be32s(f, &tally_counters->TxMCol);
1346 qemu_put_be64s(f, &tally_counters->RxOkPhy);
1347 qemu_put_be64s(f, &tally_counters->RxOkBrd);
1348 qemu_put_be32s(f, &tally_counters->RxOkMul);
1349 qemu_put_be16s(f, &tally_counters->TxAbt);
1350 qemu_put_be16s(f, &tally_counters->TxUndrn);
1351 }
1352
1353 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1354 {
1355 val &= 0xff;
1356
1357 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
1358
1359 if (val & CmdReset)
1360 {
1361 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
1362 rtl8139_reset(s);
1363 }
1364 if (val & CmdRxEnb)
1365 {
1366 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
1367
1368 s->currCPlusRxDesc = 0;
1369 }
1370 if (val & CmdTxEnb)
1371 {
1372 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
1373
1374 s->currCPlusTxDesc = 0;
1375 }
1376
1377 /* mask unwriteable bits */
1378 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1379
1380 /* Deassert reset pin before next read */
1381 val &= ~CmdReset;
1382
1383 s->bChipCmdState = val;
1384 }
1385
1386 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1387 {
1388 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1389
1390 if (unread != 0)
1391 {
1392 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
1393 return 0;
1394 }
1395
1396 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
1397
1398 return 1;
1399 }
1400
1401 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1402 {
1403 uint32_t ret = s->bChipCmdState;
1404
1405 if (rtl8139_RxBufferEmpty(s))
1406 ret |= RxBufEmpty;
1407
1408 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
1409
1410 return ret;
1411 }
1412
1413 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1414 {
1415 val &= 0xffff;
1416
1417 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
1418
1419 /* mask unwriteable bits */
1420 val = SET_MASKED(val, 0xff84, s->CpCmd);
1421
1422 s->CpCmd = val;
1423 }
1424
1425 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1426 {
1427 uint32_t ret = s->CpCmd;
1428
1429 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1430
1431 return ret;
1432 }
1433
1434 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1435 {
1436 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1437 }
1438
1439 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1440 {
1441 uint32_t ret = 0;
1442
1443 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
1444
1445 return ret;
1446 }
1447
1448 int rtl8139_config_writeable(RTL8139State *s)
1449 {
1450 if (s->Cfg9346 & Cfg9346_Unlock)
1451 {
1452 return 1;
1453 }
1454
1455 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
1456
1457 return 0;
1458 }
1459
1460 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1461 {
1462 val &= 0xffff;
1463
1464 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
1465
1466 /* mask unwriteable bits */
1467 uint32 mask = 0x4cff;
1468
1469 if (1 || !rtl8139_config_writeable(s))
1470 {
1471 /* Speed setting and autonegotiation enable bits are read-only */
1472 mask |= 0x3000;
1473 /* Duplex mode setting is read-only */
1474 mask |= 0x0100;
1475 }
1476
1477 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1478
1479 s->BasicModeCtrl = val;
1480 }
1481
1482 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1483 {
1484 uint32_t ret = s->BasicModeCtrl;
1485
1486 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
1487
1488 return ret;
1489 }
1490
1491 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1492 {
1493 val &= 0xffff;
1494
1495 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
1496
1497 /* mask unwriteable bits */
1498 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1499
1500 s->BasicModeStatus = val;
1501 }
1502
1503 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1504 {
1505 uint32_t ret = s->BasicModeStatus;
1506
1507 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
1508
1509 return ret;
1510 }
1511
1512 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1513 {
1514 val &= 0xff;
1515
1516 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
1517
1518 /* mask unwriteable bits */
1519 val = SET_MASKED(val, 0x31, s->Cfg9346);
1520
1521 uint32_t opmode = val & 0xc0;
1522 uint32_t eeprom_val = val & 0xf;
1523
1524 if (opmode == 0x80) {
1525 /* eeprom access */
1526 int eecs = (eeprom_val & 0x08)?1:0;
1527 int eesk = (eeprom_val & 0x04)?1:0;
1528 int eedi = (eeprom_val & 0x02)?1:0;
1529 prom9346_set_wire(s, eecs, eesk, eedi);
1530 } else if (opmode == 0x40) {
1531 /* Reset. */
1532 val = 0;
1533 rtl8139_reset(s);
1534 }
1535
1536 s->Cfg9346 = val;
1537 }
1538
1539 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1540 {
1541 uint32_t ret = s->Cfg9346;
1542
1543 uint32_t opmode = ret & 0xc0;
1544
1545 if (opmode == 0x80)
1546 {
1547 /* eeprom access */
1548 int eedo = prom9346_get_wire(s);
1549 if (eedo)
1550 {
1551 ret |= 0x01;
1552 }
1553 else
1554 {
1555 ret &= ~0x01;
1556 }
1557 }
1558
1559 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
1560
1561 return ret;
1562 }
1563
1564 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1565 {
1566 val &= 0xff;
1567
1568 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
1569
1570 if (!rtl8139_config_writeable(s))
1571 return;
1572
1573 /* mask unwriteable bits */
1574 val = SET_MASKED(val, 0xf8, s->Config0);
1575
1576 s->Config0 = val;
1577 }
1578
1579 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1580 {
1581 uint32_t ret = s->Config0;
1582
1583 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
1584
1585 return ret;
1586 }
1587
1588 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1589 {
1590 val &= 0xff;
1591
1592 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
1593
1594 if (!rtl8139_config_writeable(s))
1595 return;
1596
1597 /* mask unwriteable bits */
1598 val = SET_MASKED(val, 0xC, s->Config1);
1599
1600 s->Config1 = val;
1601 }
1602
1603 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1604 {
1605 uint32_t ret = s->Config1;
1606
1607 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
1608
1609 return ret;
1610 }
1611
1612 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1613 {
1614 val &= 0xff;
1615
1616 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
1617
1618 if (!rtl8139_config_writeable(s))
1619 return;
1620
1621 /* mask unwriteable bits */
1622 val = SET_MASKED(val, 0x8F, s->Config3);
1623
1624 s->Config3 = val;
1625 }
1626
1627 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1628 {
1629 uint32_t ret = s->Config3;
1630
1631 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
1632
1633 return ret;
1634 }
1635
1636 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1637 {
1638 val &= 0xff;
1639
1640 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
1641
1642 if (!rtl8139_config_writeable(s))
1643 return;
1644
1645 /* mask unwriteable bits */
1646 val = SET_MASKED(val, 0x0a, s->Config4);
1647
1648 s->Config4 = val;
1649 }
1650
1651 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1652 {
1653 uint32_t ret = s->Config4;
1654
1655 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
1656
1657 return ret;
1658 }
1659
1660 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1661 {
1662 val &= 0xff;
1663
1664 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
1665
1666 /* mask unwriteable bits */
1667 val = SET_MASKED(val, 0x80, s->Config5);
1668
1669 s->Config5 = val;
1670 }
1671
1672 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1673 {
1674 uint32_t ret = s->Config5;
1675
1676 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
1677
1678 return ret;
1679 }
1680
1681 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1682 {
1683 if (!rtl8139_transmitter_enabled(s))
1684 {
1685 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
1686 return;
1687 }
1688
1689 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
1690
1691 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1692
1693 s->TxConfig = val;
1694 }
1695
1696 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1697 {
1698 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1699
1700 uint32_t tc = s->TxConfig;
1701 tc &= 0xFFFFFF00;
1702 tc |= (val & 0x000000FF);
1703 rtl8139_TxConfig_write(s, tc);
1704 }
1705
1706 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1707 {
1708 uint32_t ret = s->TxConfig;
1709
1710 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
1711
1712 return ret;
1713 }
1714
1715 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1716 {
1717 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
1718
1719 /* mask unwriteable bits */
1720 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1721
1722 s->RxConfig = val;
1723
1724 /* reset buffer size and read/write pointers */
1725 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1726
1727 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
1728 }
1729
1730 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1731 {
1732 uint32_t ret = s->RxConfig;
1733
1734 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
1735
1736 return ret;
1737 }
1738
1739 static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1740 {
1741 if (!size)
1742 {
1743 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1744 return;
1745 }
1746
1747 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1748 {
1749 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1750 rtl8139_do_receive(s, buf, size, do_interrupt);
1751 }
1752 else
1753 {
1754 qemu_send_packet(s->vc, buf, size);
1755 }
1756 }
1757
1758 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1759 {
1760 if (!rtl8139_transmitter_enabled(s))
1761 {
1762 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1763 descriptor));
1764 return 0;
1765 }
1766
1767 if (s->TxStatus[descriptor] & TxHostOwns)
1768 {
1769 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1770 descriptor, s->TxStatus[descriptor]));
1771 return 0;
1772 }
1773
1774 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
1775
1776 int txsize = s->TxStatus[descriptor] & 0x1fff;
1777 uint8_t txbuffer[0x2000];
1778
1779 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1780 txsize, s->TxAddr[descriptor]));
1781
1782 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
1783
1784 /* Mark descriptor as transferred */
1785 s->TxStatus[descriptor] |= TxHostOwns;
1786 s->TxStatus[descriptor] |= TxStatOK;
1787
1788 rtl8139_transfer_frame(s, txbuffer, txsize, 0);
1789
1790 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
1791
1792 /* update interrupt */
1793 s->IntrStatus |= TxOK;
1794 rtl8139_update_irq(s);
1795
1796 return 1;
1797 }
1798
1799 /* structures and macros for task offloading */
1800 typedef struct ip_header
1801 {
1802 uint8_t ip_ver_len; /* version and header length */
1803 uint8_t ip_tos; /* type of service */
1804 uint16_t ip_len; /* total length */
1805 uint16_t ip_id; /* identification */
1806 uint16_t ip_off; /* fragment offset field */
1807 uint8_t ip_ttl; /* time to live */
1808 uint8_t ip_p; /* protocol */
1809 uint16_t ip_sum; /* checksum */
1810 uint32_t ip_src,ip_dst; /* source and dest address */
1811 } ip_header;
1812
1813 #define IP_HEADER_VERSION_4 4
1814 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1815 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1816
1817 typedef struct tcp_header
1818 {
1819 uint16_t th_sport; /* source port */
1820 uint16_t th_dport; /* destination port */
1821 uint32_t th_seq; /* sequence number */
1822 uint32_t th_ack; /* acknowledgement number */
1823 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1824 uint16_t th_win; /* window */
1825 uint16_t th_sum; /* checksum */
1826 uint16_t th_urp; /* urgent pointer */
1827 } tcp_header;
1828
1829 typedef struct udp_header
1830 {
1831 uint16_t uh_sport; /* source port */
1832 uint16_t uh_dport; /* destination port */
1833 uint16_t uh_ulen; /* udp length */
1834 uint16_t uh_sum; /* udp checksum */
1835 } udp_header;
1836
1837 typedef struct ip_pseudo_header
1838 {
1839 uint32_t ip_src;
1840 uint32_t ip_dst;
1841 uint8_t zeros;
1842 uint8_t ip_proto;
1843 uint16_t ip_payload;
1844 } ip_pseudo_header;
1845
1846 #define IP_PROTO_TCP 6
1847 #define IP_PROTO_UDP 17
1848
1849 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1850 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1851 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1852
1853 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1854
1855 #define TCP_FLAG_FIN 0x01
1856 #define TCP_FLAG_PUSH 0x08
1857
1858 /* produces ones' complement sum of data */
1859 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1860 {
1861 uint32_t result = 0;
1862
1863 for (; len > 1; data+=2, len-=2)
1864 {
1865 result += *(uint16_t*)data;
1866 }
1867
1868 /* add the remainder byte */
1869 if (len)
1870 {
1871 uint8_t odd[2] = {*data, 0};
1872 result += *(uint16_t*)odd;
1873 }
1874
1875 while (result>>16)
1876 result = (result & 0xffff) + (result >> 16);
1877
1878 return result;
1879 }
1880
1881 static uint16_t ip_checksum(void *data, size_t len)
1882 {
1883 return ~ones_complement_sum((uint8_t*)data, len);
1884 }
1885
1886 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1887 {
1888 if (!rtl8139_transmitter_enabled(s))
1889 {
1890 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
1891 return 0;
1892 }
1893
1894 if (!rtl8139_cp_transmitter_enabled(s))
1895 {
1896 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
1897 return 0 ;
1898 }
1899
1900 int descriptor = s->currCPlusTxDesc;
1901
1902 target_phys_addr_t cplus_tx_ring_desc =
1903 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1904
1905 /* Normal priority ring */
1906 cplus_tx_ring_desc += 16 * descriptor;
1907
1908 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1909 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
1910
1911 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1912
1913 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1914 txdw0 = le32_to_cpu(val);
1915 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1916 txdw1 = le32_to_cpu(val);
1917 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1918 txbufLO = le32_to_cpu(val);
1919 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1920 txbufHI = le32_to_cpu(val);
1921
1922 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
1923 descriptor,
1924 txdw0, txdw1, txbufLO, txbufHI));
1925
1926 /* w0 ownership flag */
1927 #define CP_TX_OWN (1<<31)
1928 /* w0 end of ring flag */
1929 #define CP_TX_EOR (1<<30)
1930 /* first segment of received packet flag */
1931 #define CP_TX_FS (1<<29)
1932 /* last segment of received packet flag */
1933 #define CP_TX_LS (1<<28)
1934 /* large send packet flag */
1935 #define CP_TX_LGSEN (1<<27)
1936 /* large send MSS mask, bits 16...25 */
1937 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1938
1939 /* IP checksum offload flag */
1940 #define CP_TX_IPCS (1<<18)
1941 /* UDP checksum offload flag */
1942 #define CP_TX_UDPCS (1<<17)
1943 /* TCP checksum offload flag */
1944 #define CP_TX_TCPCS (1<<16)
1945
1946 /* w0 bits 0...15 : buffer size */
1947 #define CP_TX_BUFFER_SIZE (1<<16)
1948 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1949 /* w1 tag available flag */
1950 #define CP_RX_TAGC (1<<17)
1951 /* w1 bits 0...15 : VLAN tag */
1952 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1953 /* w2 low 32bit of Rx buffer ptr */
1954 /* w3 high 32bit of Rx buffer ptr */
1955
1956 /* set after transmission */
1957 /* FIFO underrun flag */
1958 #define CP_TX_STATUS_UNF (1<<25)
1959 /* transmit error summary flag, valid if set any of three below */
1960 #define CP_TX_STATUS_TES (1<<23)
1961 /* out-of-window collision flag */
1962 #define CP_TX_STATUS_OWC (1<<22)
1963 /* link failure flag */
1964 #define CP_TX_STATUS_LNKF (1<<21)
1965 /* excessive collisions flag */
1966 #define CP_TX_STATUS_EXC (1<<20)
1967
1968 if (!(txdw0 & CP_TX_OWN))
1969 {
1970 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
1971 return 0 ;
1972 }
1973
1974 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1975
1976 if (txdw0 & CP_TX_FS)
1977 {
1978 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1979
1980 /* reset internal buffer offset */
1981 s->cplus_txbuffer_offset = 0;
1982 }
1983
1984 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1985 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1986
1987 /* make sure we have enough space to assemble the packet */
1988 if (!s->cplus_txbuffer)
1989 {
1990 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
1991 s->cplus_txbuffer = malloc(s->cplus_txbuffer_len);
1992 s->cplus_txbuffer_offset = 0;
1993
1994 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
1995 }
1996
1997 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
1998 {
1999 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2000 s->cplus_txbuffer = realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
2001
2002 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2003 }
2004
2005 if (!s->cplus_txbuffer)
2006 {
2007 /* out of memory */
2008
2009 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2010
2011 /* update tally counter */
2012 ++s->tally_counters.TxERR;
2013 ++s->tally_counters.TxAbt;
2014
2015 return 0;
2016 }
2017
2018 /* append more data to the packet */
2019
2020 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2021 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2022
2023 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2024 s->cplus_txbuffer_offset += txsize;
2025
2026 /* seek to next Rx descriptor */
2027 if (txdw0 & CP_TX_EOR)
2028 {
2029 s->currCPlusTxDesc = 0;
2030 }
2031 else
2032 {
2033 ++s->currCPlusTxDesc;
2034 if (s->currCPlusTxDesc >= 64)
2035 s->currCPlusTxDesc = 0;
2036 }
2037
2038 /* transfer ownership to target */
2039 txdw0 &= ~CP_RX_OWN;
2040
2041 /* reset error indicator bits */
2042 txdw0 &= ~CP_TX_STATUS_UNF;
2043 txdw0 &= ~CP_TX_STATUS_TES;
2044 txdw0 &= ~CP_TX_STATUS_OWC;
2045 txdw0 &= ~CP_TX_STATUS_LNKF;
2046 txdw0 &= ~CP_TX_STATUS_EXC;
2047
2048 /* update ring data */
2049 val = cpu_to_le32(txdw0);
2050 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
2051 // val = cpu_to_le32(txdw1);
2052 // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2053
2054 /* Now decide if descriptor being processed is holding the last segment of packet */
2055 if (txdw0 & CP_TX_LS)
2056 {
2057 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2058
2059 /* can transfer fully assembled packet */
2060
2061 uint8_t *saved_buffer = s->cplus_txbuffer;
2062 int saved_size = s->cplus_txbuffer_offset;
2063 int saved_buffer_len = s->cplus_txbuffer_len;
2064
2065 /* reset the card space to protect from recursive call */
2066 s->cplus_txbuffer = NULL;
2067 s->cplus_txbuffer_offset = 0;
2068 s->cplus_txbuffer_len = 0;
2069
2070 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2071 {
2072 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2073
2074 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2075 #define ETH_HLEN 14
2076 #define ETH_MTU 1500
2077
2078 /* ip packet header */
2079 ip_header *ip = 0;
2080 int hlen = 0;
2081 uint8_t ip_protocol = 0;
2082 uint16_t ip_data_len = 0;
2083
2084 uint8_t *eth_payload_data = 0;
2085 size_t eth_payload_len = 0;
2086
2087 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2088 if (proto == ETH_P_IP)
2089 {
2090 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2091
2092 /* not aligned */
2093 eth_payload_data = saved_buffer + ETH_HLEN;
2094 eth_payload_len = saved_size - ETH_HLEN;
2095
2096 ip = (ip_header*)eth_payload_data;
2097
2098 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2099 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
2100 ip = NULL;
2101 } else {
2102 hlen = IP_HEADER_LENGTH(ip);
2103 ip_protocol = ip->ip_p;
2104 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
2105 }
2106 }
2107
2108 if (ip)
2109 {
2110 if (txdw0 & CP_TX_IPCS)
2111 {
2112 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2113
2114 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
2115 /* bad packet header len */
2116 /* or packet too short */
2117 }
2118 else
2119 {
2120 ip->ip_sum = 0;
2121 ip->ip_sum = ip_checksum(ip, hlen);
2122 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2123 }
2124 }
2125
2126 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2127 {
2128 #if defined (DEBUG_RTL8139)
2129 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2130 #endif
2131 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2132 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
2133
2134 int tcp_send_offset = 0;
2135 int send_count = 0;
2136
2137 /* maximum IP header length is 60 bytes */
2138 uint8_t saved_ip_header[60];
2139
2140 /* save IP header template; data area is used in tcp checksum calculation */
2141 memcpy(saved_ip_header, eth_payload_data, hlen);
2142
2143 /* a placeholder for checksum calculation routine in tcp case */
2144 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2145 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2146
2147 /* pointer to TCP header */
2148 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2149
2150 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2151
2152 /* ETH_MTU = ip header len + tcp header len + payload */
2153 int tcp_data_len = ip_data_len - tcp_hlen;
2154 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2155
2156 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2157 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2158
2159 /* note the cycle below overwrites IP header data,
2160 but restores it from saved_ip_header before sending packet */
2161
2162 int is_last_frame = 0;
2163
2164 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2165 {
2166 uint16_t chunk_size = tcp_chunk_size;
2167
2168 /* check if this is the last frame */
2169 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2170 {
2171 is_last_frame = 1;
2172 chunk_size = tcp_data_len - tcp_send_offset;
2173 }
2174
2175 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2176
2177 /* add 4 TCP pseudoheader fields */
2178 /* copy IP source and destination fields */
2179 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2180
2181 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2182
2183 if (tcp_send_offset)
2184 {
2185 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2186 }
2187
2188 /* keep PUSH and FIN flags only for the last frame */
2189 if (!is_last_frame)
2190 {
2191 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2192 }
2193
2194 /* recalculate TCP checksum */
2195 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2196 p_tcpip_hdr->zeros = 0;
2197 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2198 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2199
2200 p_tcp_hdr->th_sum = 0;
2201
2202 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2203 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2204
2205 p_tcp_hdr->th_sum = tcp_checksum;
2206
2207 /* restore IP header */
2208 memcpy(eth_payload_data, saved_ip_header, hlen);
2209
2210 /* set IP data length and recalculate IP checksum */
2211 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2212
2213 /* increment IP id for subsequent frames */
2214 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2215
2216 ip->ip_sum = 0;
2217 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2218 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2219
2220 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2221 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2222 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2223
2224 /* add transferred count to TCP sequence number */
2225 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2226 ++send_count;
2227 }
2228
2229 /* Stop sending this frame */
2230 saved_size = 0;
2231 }
2232 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2233 {
2234 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2235
2236 /* maximum IP header length is 60 bytes */
2237 uint8_t saved_ip_header[60];
2238 memcpy(saved_ip_header, eth_payload_data, hlen);
2239
2240 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2241 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2242
2243 /* add 4 TCP pseudoheader fields */
2244 /* copy IP source and destination fields */
2245 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2246
2247 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2248 {
2249 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2250
2251 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2252 p_tcpip_hdr->zeros = 0;
2253 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2254 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2255
2256 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2257
2258 p_tcp_hdr->th_sum = 0;
2259
2260 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2261 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2262
2263 p_tcp_hdr->th_sum = tcp_checksum;
2264 }
2265 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2266 {
2267 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2268
2269 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2270 p_udpip_hdr->zeros = 0;
2271 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2272 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2273
2274 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2275
2276 p_udp_hdr->uh_sum = 0;
2277
2278 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2279 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2280
2281 p_udp_hdr->uh_sum = udp_checksum;
2282 }
2283
2284 /* restore IP header */
2285 memcpy(eth_payload_data, saved_ip_header, hlen);
2286 }
2287 }
2288 }
2289
2290 /* update tally counter */
2291 ++s->tally_counters.TxOk;
2292
2293 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2294
2295 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
2296
2297 /* restore card space if there was no recursion and reset offset */
2298 if (!s->cplus_txbuffer)
2299 {
2300 s->cplus_txbuffer = saved_buffer;
2301 s->cplus_txbuffer_len = saved_buffer_len;
2302 s->cplus_txbuffer_offset = 0;
2303 }
2304 else
2305 {
2306 free(saved_buffer);
2307 }
2308 }
2309 else
2310 {
2311 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
2312 }
2313
2314 return 1;
2315 }
2316
2317 static void rtl8139_cplus_transmit(RTL8139State *s)
2318 {
2319 int txcount = 0;
2320
2321 while (rtl8139_cplus_transmit_one(s))
2322 {
2323 ++txcount;
2324 }
2325
2326 /* Mark transfer completed */
2327 if (!txcount)
2328 {
2329 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2330 s->currCPlusTxDesc));
2331 }
2332 else
2333 {
2334 /* update interrupt status */
2335 s->IntrStatus |= TxOK;
2336 rtl8139_update_irq(s);
2337 }
2338 }
2339
2340 static void rtl8139_transmit(RTL8139State *s)
2341 {
2342 int descriptor = s->currTxDesc, txcount = 0;
2343
2344 /*while*/
2345 if (rtl8139_transmit_one(s, descriptor))
2346 {
2347 ++s->currTxDesc;
2348 s->currTxDesc %= 4;
2349 ++txcount;
2350 }
2351
2352 /* Mark transfer completed */
2353 if (!txcount)
2354 {
2355 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
2356 }
2357 }
2358
2359 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2360 {
2361
2362 int descriptor = txRegOffset/4;
2363
2364 /* handle C+ transmit mode register configuration */
2365
2366 if (rtl8139_cp_transmitter_enabled(s))
2367 {
2368 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2369
2370 /* handle Dump Tally Counters command */
2371 s->TxStatus[descriptor] = val;
2372
2373 if (descriptor == 0 && (val & 0x8))
2374 {
2375 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2376
2377 /* dump tally counters to specified memory location */
2378 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2379
2380 /* mark dump completed */
2381 s->TxStatus[0] &= ~0x8;
2382 }
2383
2384 return;
2385 }
2386
2387 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2388
2389 /* mask only reserved bits */
2390 val &= ~0xff00c000; /* these bits are reset on write */
2391 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2392
2393 s->TxStatus[descriptor] = val;
2394
2395 /* attempt to start transmission */
2396 rtl8139_transmit(s);
2397 }
2398
2399 static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2400 {
2401 uint32_t ret = s->TxStatus[txRegOffset/4];
2402
2403 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
2404
2405 return ret;
2406 }
2407
2408 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2409 {
2410 uint16_t ret = 0;
2411
2412 /* Simulate TSAD, it is read only anyway */
2413
2414 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2415 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2416 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2417 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2418
2419 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2420 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2421 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2422 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2423
2424 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2425 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2426 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2427 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2428
2429 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2430 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2431 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2432 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2433
2434
2435 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
2436
2437 return ret;
2438 }
2439
2440 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2441 {
2442 uint16_t ret = s->CSCR;
2443
2444 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
2445
2446 return ret;
2447 }
2448
2449 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2450 {
2451 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
2452
2453 s->TxAddr[txAddrOffset/4] = val;
2454 }
2455
2456 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2457 {
2458 uint32_t ret = s->TxAddr[txAddrOffset/4];
2459
2460 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
2461
2462 return ret;
2463 }
2464
2465 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2466 {
2467 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
2468
2469 /* this value is off by 16 */
2470 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2471
2472 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2473 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
2474 }
2475
2476 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2477 {
2478 /* this value is off by 16 */
2479 uint32_t ret = s->RxBufPtr - 0x10;
2480
2481 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2482
2483 return ret;
2484 }
2485
2486 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2487 {
2488 /* this value is NOT off by 16 */
2489 uint32_t ret = s->RxBufAddr;
2490
2491 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
2492
2493 return ret;
2494 }
2495
2496 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2497 {
2498 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
2499
2500 s->RxBuf = val;
2501
2502 /* may need to reset rxring here */
2503 }
2504
2505 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2506 {
2507 uint32_t ret = s->RxBuf;
2508
2509 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
2510
2511 return ret;
2512 }
2513
2514 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2515 {
2516 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
2517
2518 /* mask unwriteable bits */
2519 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2520
2521 s->IntrMask = val;
2522
2523 rtl8139_update_irq(s);
2524 }
2525
2526 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2527 {
2528 uint32_t ret = s->IntrMask;
2529
2530 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
2531
2532 return ret;
2533 }
2534
2535 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2536 {
2537 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
2538
2539 #if 0
2540
2541 /* writing to ISR has no effect */
2542
2543 return;
2544
2545 #else
2546 uint16_t newStatus = s->IntrStatus & ~val;
2547
2548 /* mask unwriteable bits */
2549 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2550
2551 /* writing 1 to interrupt status register bit clears it */
2552 s->IntrStatus = 0;
2553 rtl8139_update_irq(s);
2554
2555 s->IntrStatus = newStatus;
2556 rtl8139_update_irq(s);
2557 #endif
2558 }
2559
2560 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2561 {
2562 uint32_t ret = s->IntrStatus;
2563
2564 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
2565
2566 #if 0
2567
2568 /* reading ISR clears all interrupts */
2569 s->IntrStatus = 0;
2570
2571 rtl8139_update_irq(s);
2572
2573 #endif
2574
2575 return ret;
2576 }
2577
2578 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2579 {
2580 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
2581
2582 /* mask unwriteable bits */
2583 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2584
2585 s->MultiIntr = val;
2586 }
2587
2588 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2589 {
2590 uint32_t ret = s->MultiIntr;
2591
2592 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
2593
2594 return ret;
2595 }
2596
2597 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2598 {
2599 RTL8139State *s = opaque;
2600
2601 addr &= 0xff;
2602
2603 switch (addr)
2604 {
2605 case MAC0 ... MAC0+5:
2606 s->phys[addr - MAC0] = val;
2607 break;
2608 case MAC0+6 ... MAC0+7:
2609 /* reserved */
2610 break;
2611 case MAR0 ... MAR0+7:
2612 s->mult[addr - MAR0] = val;
2613 break;
2614 case ChipCmd:
2615 rtl8139_ChipCmd_write(s, val);
2616 break;
2617 case Cfg9346:
2618 rtl8139_Cfg9346_write(s, val);
2619 break;
2620 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2621 rtl8139_TxConfig_writeb(s, val);
2622 break;
2623 case Config0:
2624 rtl8139_Config0_write(s, val);
2625 break;
2626 case Config1:
2627 rtl8139_Config1_write(s, val);
2628 break;
2629 case Config3:
2630 rtl8139_Config3_write(s, val);
2631 break;
2632 case Config4:
2633 rtl8139_Config4_write(s, val);
2634 break;
2635 case Config5:
2636 rtl8139_Config5_write(s, val);
2637 break;
2638 case MediaStatus:
2639 /* ignore */
2640 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
2641 break;
2642
2643 case HltClk:
2644 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
2645 if (val == 'R')
2646 {
2647 s->clock_enabled = 1;
2648 }
2649 else if (val == 'H')
2650 {
2651 s->clock_enabled = 0;
2652 }
2653 break;
2654
2655 case TxThresh:
2656 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
2657 s->TxThresh = val;
2658 break;
2659
2660 case TxPoll:
2661 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
2662 if (val & (1 << 7))
2663 {
2664 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
2665 //rtl8139_cplus_transmit(s);
2666 }
2667 if (val & (1 << 6))
2668 {
2669 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
2670 rtl8139_cplus_transmit(s);
2671 }
2672
2673 break;
2674
2675 default:
2676 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
2677 break;
2678 }
2679 }
2680
2681 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2682 {
2683 RTL8139State *s = opaque;
2684
2685 addr &= 0xfe;
2686
2687 switch (addr)
2688 {
2689 case IntrMask:
2690 rtl8139_IntrMask_write(s, val);
2691 break;
2692
2693 case IntrStatus:
2694 rtl8139_IntrStatus_write(s, val);
2695 break;
2696
2697 case MultiIntr:
2698 rtl8139_MultiIntr_write(s, val);
2699 break;
2700
2701 case RxBufPtr:
2702 rtl8139_RxBufPtr_write(s, val);
2703 break;
2704
2705 case BasicModeCtrl:
2706 rtl8139_BasicModeCtrl_write(s, val);
2707 break;
2708 case BasicModeStatus:
2709 rtl8139_BasicModeStatus_write(s, val);
2710 break;
2711 case NWayAdvert:
2712 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
2713 s->NWayAdvert = val;
2714 break;
2715 case NWayLPAR:
2716 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
2717 break;
2718 case NWayExpansion:
2719 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
2720 s->NWayExpansion = val;
2721 break;
2722
2723 case CpCmd:
2724 rtl8139_CpCmd_write(s, val);
2725 break;
2726
2727 case IntrMitigate:
2728 rtl8139_IntrMitigate_write(s, val);
2729 break;
2730
2731 default:
2732 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
2733
2734 #ifdef TARGET_WORDS_BIGENDIAN
2735 rtl8139_io_writeb(opaque, addr, (val >> 8) & 0xff);
2736 rtl8139_io_writeb(opaque, addr + 1, val & 0xff);
2737 #else
2738 rtl8139_io_writeb(opaque, addr, val & 0xff);
2739 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2740 #endif
2741 break;
2742 }
2743 }
2744
2745 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2746 {
2747 RTL8139State *s = opaque;
2748
2749 addr &= 0xfc;
2750
2751 switch (addr)
2752 {
2753 case RxMissed:
2754 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
2755 s->RxMissed = 0;
2756 break;
2757
2758 case TxConfig:
2759 rtl8139_TxConfig_write(s, val);
2760 break;
2761
2762 case RxConfig:
2763 rtl8139_RxConfig_write(s, val);
2764 break;
2765
2766 case TxStatus0 ... TxStatus0+4*4-1:
2767 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2768 break;
2769
2770 case TxAddr0 ... TxAddr0+4*4-1:
2771 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2772 break;
2773
2774 case RxBuf:
2775 rtl8139_RxBuf_write(s, val);
2776 break;
2777
2778 case RxRingAddrLO:
2779 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
2780 s->RxRingAddrLO = val;
2781 break;
2782
2783 case RxRingAddrHI:
2784 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
2785 s->RxRingAddrHI = val;
2786 break;
2787
2788 case Timer:
2789 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2790 s->TCTR = 0;
2791 s->TCTR_base = qemu_get_clock(vm_clock);
2792 break;
2793
2794 case FlashReg:
2795 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2796 s->TimerInt = val;
2797 break;
2798
2799 default:
2800 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
2801 #ifdef TARGET_WORDS_BIGENDIAN
2802 rtl8139_io_writeb(opaque, addr, (val >> 24) & 0xff);
2803 rtl8139_io_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2804 rtl8139_io_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2805 rtl8139_io_writeb(opaque, addr + 3, val & 0xff);
2806 #else
2807 rtl8139_io_writeb(opaque, addr, val & 0xff);
2808 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2809 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2810 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2811 #endif
2812 break;
2813 }
2814 }
2815
2816 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2817 {
2818 RTL8139State *s = opaque;
2819 int ret;
2820
2821 addr &= 0xff;
2822
2823 switch (addr)
2824 {
2825 case MAC0 ... MAC0+5:
2826 ret = s->phys[addr - MAC0];
2827 break;
2828 case MAC0+6 ... MAC0+7:
2829 ret = 0;
2830 break;
2831 case MAR0 ... MAR0+7:
2832 ret = s->mult[addr - MAR0];
2833 break;
2834 case ChipCmd:
2835 ret = rtl8139_ChipCmd_read(s);
2836 break;
2837 case Cfg9346:
2838 ret = rtl8139_Cfg9346_read(s);
2839 break;
2840 case Config0:
2841 ret = rtl8139_Config0_read(s);
2842 break;
2843 case Config1:
2844 ret = rtl8139_Config1_read(s);
2845 break;
2846 case Config3:
2847 ret = rtl8139_Config3_read(s);
2848 break;
2849 case Config4:
2850 ret = rtl8139_Config4_read(s);
2851 break;
2852 case Config5:
2853 ret = rtl8139_Config5_read(s);
2854 break;
2855
2856 case MediaStatus:
2857 ret = 0xd0;
2858 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
2859 break;
2860
2861 case HltClk:
2862 ret = s->clock_enabled;
2863 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
2864 break;
2865
2866 case PCIRevisionID:
2867 ret = RTL8139_PCI_REVID;
2868 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
2869 break;
2870
2871 case TxThresh:
2872 ret = s->TxThresh;
2873 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
2874 break;
2875
2876 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2877 ret = s->TxConfig >> 24;
2878 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
2879 break;
2880
2881 default:
2882 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
2883 ret = 0;
2884 break;
2885 }
2886
2887 return ret;
2888 }
2889
2890 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2891 {
2892 RTL8139State *s = opaque;
2893 uint32_t ret;
2894
2895 addr &= 0xfe; /* mask lower bit */
2896
2897 switch (addr)
2898 {
2899 case IntrMask:
2900 ret = rtl8139_IntrMask_read(s);
2901 break;
2902
2903 case IntrStatus:
2904 ret = rtl8139_IntrStatus_read(s);
2905 break;
2906
2907 case MultiIntr:
2908 ret = rtl8139_MultiIntr_read(s);
2909 break;
2910
2911 case RxBufPtr:
2912 ret = rtl8139_RxBufPtr_read(s);
2913 break;
2914
2915 case RxBufAddr:
2916 ret = rtl8139_RxBufAddr_read(s);
2917 break;
2918
2919 case BasicModeCtrl:
2920 ret = rtl8139_BasicModeCtrl_read(s);
2921 break;
2922 case BasicModeStatus:
2923 ret = rtl8139_BasicModeStatus_read(s);
2924 break;
2925 case NWayAdvert:
2926 ret = s->NWayAdvert;
2927 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
2928 break;
2929 case NWayLPAR:
2930 ret = s->NWayLPAR;
2931 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
2932 break;
2933 case NWayExpansion:
2934 ret = s->NWayExpansion;
2935 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
2936 break;
2937
2938 case CpCmd:
2939 ret = rtl8139_CpCmd_read(s);
2940 break;
2941
2942 case IntrMitigate:
2943 ret = rtl8139_IntrMitigate_read(s);
2944 break;
2945
2946 case TxSummary:
2947 ret = rtl8139_TSAD_read(s);
2948 break;
2949
2950 case CSCR:
2951 ret = rtl8139_CSCR_read(s);
2952 break;
2953
2954 default:
2955 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
2956
2957 #ifdef TARGET_WORDS_BIGENDIAN
2958 ret = rtl8139_io_readb(opaque, addr) << 8;
2959 ret |= rtl8139_io_readb(opaque, addr + 1);
2960 #else
2961 ret = rtl8139_io_readb(opaque, addr);
2962 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
2963 #endif
2964
2965 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
2966 break;
2967 }
2968
2969 return ret;
2970 }
2971
2972 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
2973 {
2974 RTL8139State *s = opaque;
2975 uint32_t ret;
2976
2977 addr &= 0xfc; /* also mask low 2 bits */
2978
2979 switch (addr)
2980 {
2981 case RxMissed:
2982 ret = s->RxMissed;
2983
2984 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
2985 break;
2986
2987 case TxConfig:
2988 ret = rtl8139_TxConfig_read(s);
2989 break;
2990
2991 case RxConfig:
2992 ret = rtl8139_RxConfig_read(s);
2993 break;
2994
2995 case TxStatus0 ... TxStatus0+4*4-1:
2996 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
2997 break;
2998
2999 case TxAddr0 ... TxAddr0+4*4-1:
3000 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3001 break;
3002
3003 case RxBuf:
3004 ret = rtl8139_RxBuf_read(s);
3005 break;
3006
3007 case RxRingAddrLO:
3008 ret = s->RxRingAddrLO;
3009 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
3010 break;
3011
3012 case RxRingAddrHI:
3013 ret = s->RxRingAddrHI;
3014 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3015 break;
3016
3017 case Timer:
3018 ret = s->TCTR;
3019 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3020 break;
3021
3022 case FlashReg:
3023 ret = s->TimerInt;
3024 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
3025 break;
3026
3027 default:
3028 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
3029
3030 #ifdef TARGET_WORDS_BIGENDIAN
3031 ret = rtl8139_io_readb(opaque, addr) << 24;
3032 ret |= rtl8139_io_readb(opaque, addr + 1) << 16;
3033 ret |= rtl8139_io_readb(opaque, addr + 2) << 8;
3034 ret |= rtl8139_io_readb(opaque, addr + 3);
3035 #else
3036 ret = rtl8139_io_readb(opaque, addr);
3037 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3038 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3039 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3040 #endif
3041
3042 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
3043 break;
3044 }
3045
3046 return ret;
3047 }
3048
3049 /* */
3050
3051 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3052 {
3053 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3054 }
3055
3056 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3057 {
3058 rtl8139_io_writew(opaque, addr & 0xFF, val);
3059 }
3060
3061 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3062 {
3063 rtl8139_io_writel(opaque, addr & 0xFF, val);
3064 }
3065
3066 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3067 {
3068 return rtl8139_io_readb(opaque, addr & 0xFF);
3069 }
3070
3071 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3072 {
3073 return rtl8139_io_readw(opaque, addr & 0xFF);
3074 }
3075
3076 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3077 {
3078 return rtl8139_io_readl(opaque, addr & 0xFF);
3079 }
3080
3081 /* */
3082
3083 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3084 {
3085 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3086 }
3087
3088 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3089 {
3090 rtl8139_io_writew(opaque, addr & 0xFF, val);
3091 }
3092
3093 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3094 {
3095 rtl8139_io_writel(opaque, addr & 0xFF, val);
3096 }
3097
3098 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3099 {
3100 return rtl8139_io_readb(opaque, addr & 0xFF);
3101 }
3102
3103 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3104 {
3105 return rtl8139_io_readw(opaque, addr & 0xFF);
3106 }
3107
3108 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3109 {
3110 return rtl8139_io_readl(opaque, addr & 0xFF);
3111 }
3112
3113 /* */
3114
3115 static void rtl8139_save(QEMUFile* f,void* opaque)
3116 {
3117 RTL8139State* s=(RTL8139State*)opaque;
3118 int i;
3119
3120 pci_device_save(s->pci_dev, f);
3121
3122 qemu_put_buffer(f, s->phys, 6);
3123 qemu_put_buffer(f, s->mult, 8);
3124
3125 for (i=0; i<4; ++i)
3126 {
3127 qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3128 }
3129 for (i=0; i<4; ++i)
3130 {
3131 qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3132 }
3133
3134 qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
3135 qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3136 qemu_put_be32s(f, &s->RxBufPtr);
3137 qemu_put_be32s(f, &s->RxBufAddr);
3138
3139 qemu_put_be16s(f, &s->IntrStatus);
3140 qemu_put_be16s(f, &s->IntrMask);
3141
3142 qemu_put_be32s(f, &s->TxConfig);
3143 qemu_put_be32s(f, &s->RxConfig);
3144 qemu_put_be32s(f, &s->RxMissed);
3145 qemu_put_be16s(f, &s->CSCR);
3146
3147 qemu_put_8s(f, &s->Cfg9346);
3148 qemu_put_8s(f, &s->Config0);
3149 qemu_put_8s(f, &s->Config1);
3150 qemu_put_8s(f, &s->Config3);
3151 qemu_put_8s(f, &s->Config4);
3152 qemu_put_8s(f, &s->Config5);
3153
3154 qemu_put_8s(f, &s->clock_enabled);
3155 qemu_put_8s(f, &s->bChipCmdState);
3156
3157 qemu_put_be16s(f, &s->MultiIntr);
3158
3159 qemu_put_be16s(f, &s->BasicModeCtrl);
3160 qemu_put_be16s(f, &s->BasicModeStatus);
3161 qemu_put_be16s(f, &s->NWayAdvert);
3162 qemu_put_be16s(f, &s->NWayLPAR);
3163 qemu_put_be16s(f, &s->NWayExpansion);
3164
3165 qemu_put_be16s(f, &s->CpCmd);
3166 qemu_put_8s(f, &s->TxThresh);
3167
3168 i = 0;
3169 qemu_put_be32s(f, &i); /* unused. */
3170 qemu_put_buffer(f, s->macaddr, 6);
3171 qemu_put_be32s(f, &s->rtl8139_mmio_io_addr);
3172
3173 qemu_put_be32s(f, &s->currTxDesc);
3174 qemu_put_be32s(f, &s->currCPlusRxDesc);
3175 qemu_put_be32s(f, &s->currCPlusTxDesc);
3176 qemu_put_be32s(f, &s->RxRingAddrLO);
3177 qemu_put_be32s(f, &s->RxRingAddrHI);
3178
3179 for (i=0; i<EEPROM_9346_SIZE; ++i)
3180 {
3181 qemu_put_be16s(f, &s->eeprom.contents[i]);
3182 }
3183 qemu_put_be32s(f, &s->eeprom.mode);
3184 qemu_put_be32s(f, &s->eeprom.tick);
3185 qemu_put_8s(f, &s->eeprom.address);
3186 qemu_put_be16s(f, &s->eeprom.input);
3187 qemu_put_be16s(f, &s->eeprom.output);
3188
3189 qemu_put_8s(f, &s->eeprom.eecs);
3190 qemu_put_8s(f, &s->eeprom.eesk);
3191 qemu_put_8s(f, &s->eeprom.eedi);
3192 qemu_put_8s(f, &s->eeprom.eedo);
3193
3194 qemu_put_be32s(f, &s->TCTR);
3195 qemu_put_be32s(f, &s->TimerInt);
3196 qemu_put_be64s(f, &s->TCTR_base);
3197
3198 RTL8139TallyCounters_save(f, &s->tally_counters);
3199 }
3200
3201 static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
3202 {
3203 RTL8139State* s=(RTL8139State*)opaque;
3204 int i, ret;
3205
3206 /* just 2 versions for now */
3207 if (version_id > 3)
3208 return -EINVAL;
3209
3210 if (version_id >= 3) {
3211 ret = pci_device_load(s->pci_dev, f);
3212 if (ret < 0)
3213 return ret;
3214 }
3215
3216 /* saved since version 1 */
3217 qemu_get_buffer(f, s->phys, 6);
3218 qemu_get_buffer(f, s->mult, 8);
3219
3220 for (i=0; i<4; ++i)
3221 {
3222 qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3223 }
3224 for (i=0; i<4; ++i)
3225 {
3226 qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3227 }
3228
3229 qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
3230 qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3231 qemu_get_be32s(f, &s->RxBufPtr);
3232 qemu_get_be32s(f, &s->RxBufAddr);
3233
3234 qemu_get_be16s(f, &s->IntrStatus);
3235 qemu_get_be16s(f, &s->IntrMask);
3236
3237 qemu_get_be32s(f, &s->TxConfig);
3238 qemu_get_be32s(f, &s->RxConfig);
3239 qemu_get_be32s(f, &s->RxMissed);
3240 qemu_get_be16s(f, &s->CSCR);
3241
3242 qemu_get_8s(f, &s->Cfg9346);
3243 qemu_get_8s(f, &s->Config0);
3244 qemu_get_8s(f, &s->Config1);
3245 qemu_get_8s(f, &s->Config3);
3246 qemu_get_8s(f, &s->Config4);
3247 qemu_get_8s(f, &s->Config5);
3248
3249 qemu_get_8s(f, &s->clock_enabled);
3250 qemu_get_8s(f, &s->bChipCmdState);
3251
3252 qemu_get_be16s(f, &s->MultiIntr);
3253
3254 qemu_get_be16s(f, &s->BasicModeCtrl);
3255 qemu_get_be16s(f, &s->BasicModeStatus);
3256 qemu_get_be16s(f, &s->NWayAdvert);
3257 qemu_get_be16s(f, &s->NWayLPAR);
3258 qemu_get_be16s(f, &s->NWayExpansion);
3259
3260 qemu_get_be16s(f, &s->CpCmd);
3261 qemu_get_8s(f, &s->TxThresh);
3262
3263 qemu_get_be32s(f, &i); /* unused. */
3264 qemu_get_buffer(f, s->macaddr, 6);
3265 qemu_get_be32s(f, &s->rtl8139_mmio_io_addr);
3266
3267 qemu_get_be32s(f, &s->currTxDesc);
3268 qemu_get_be32s(f, &s->currCPlusRxDesc);
3269 qemu_get_be32s(f, &s->currCPlusTxDesc);
3270 qemu_get_be32s(f, &s->RxRingAddrLO);
3271 qemu_get_be32s(f, &s->RxRingAddrHI);
3272
3273 for (i=0; i<EEPROM_9346_SIZE; ++i)
3274 {
3275 qemu_get_be16s(f, &s->eeprom.contents[i]);
3276 }
3277 qemu_get_be32s(f, &s->eeprom.mode);
3278 qemu_get_be32s(f, &s->eeprom.tick);
3279 qemu_get_8s(f, &s->eeprom.address);
3280 qemu_get_be16s(f, &s->eeprom.input);
3281 qemu_get_be16s(f, &s->eeprom.output);
3282
3283 qemu_get_8s(f, &s->eeprom.eecs);
3284 qemu_get_8s(f, &s->eeprom.eesk);
3285 qemu_get_8s(f, &s->eeprom.eedi);
3286 qemu_get_8s(f, &s->eeprom.eedo);
3287
3288 /* saved since version 2 */
3289 if (version_id >= 2)
3290 {
3291 qemu_get_be32s(f, &s->TCTR);
3292 qemu_get_be32s(f, &s->TimerInt);
3293 qemu_get_be64s(f, &s->TCTR_base);
3294
3295 RTL8139TallyCounters_load(f, &s->tally_counters);
3296 }
3297 else
3298 {
3299 /* not saved, use default */
3300 s->TCTR = 0;
3301 s->TimerInt = 0;
3302 s->TCTR_base = 0;
3303
3304 RTL8139TallyCounters_clear(&s->tally_counters);
3305 }
3306
3307 return 0;
3308 }
3309
3310 /***********************************************************/
3311 /* PCI RTL8139 definitions */
3312
3313 typedef struct PCIRTL8139State {
3314 PCIDevice dev;
3315 RTL8139State rtl8139;
3316 } PCIRTL8139State;
3317
3318 static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
3319 uint32_t addr, uint32_t size, int type)
3320 {
3321 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3322 RTL8139State *s = &d->rtl8139;
3323
3324 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3325 }
3326
3327 static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
3328 uint32_t addr, uint32_t size, int type)
3329 {
3330 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3331 RTL8139State *s = &d->rtl8139;
3332
3333 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3334 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3335
3336 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3337 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3338
3339 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3340 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3341 }
3342
3343 static CPUReadMemoryFunc *rtl8139_mmio_read[3] = {
3344 rtl8139_mmio_readb,
3345 rtl8139_mmio_readw,
3346 rtl8139_mmio_readl,
3347 };
3348
3349 static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = {
3350 rtl8139_mmio_writeb,
3351 rtl8139_mmio_writew,
3352 rtl8139_mmio_writel,
3353 };
3354
3355 static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
3356 {
3357 int64_t next_time = current_time +
3358 muldiv64(1, ticks_per_sec, PCI_FREQUENCY);
3359 if (next_time <= current_time)
3360 next_time = current_time + 1;
3361 return next_time;
3362 }
3363
3364 #if RTL8139_ONBOARD_TIMER
3365 static void rtl8139_timer(void *opaque)
3366 {
3367 RTL8139State *s = opaque;
3368
3369 int is_timeout = 0;
3370
3371 int64_t curr_time;
3372 uint32_t curr_tick;
3373
3374 if (!s->clock_enabled)
3375 {
3376 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3377 return;
3378 }
3379
3380 curr_time = qemu_get_clock(vm_clock);
3381
3382 curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, ticks_per_sec);
3383
3384 if (s->TimerInt && curr_tick >= s->TimerInt)
3385 {
3386 if (s->TCTR < s->TimerInt || curr_tick < s->TCTR)
3387 {
3388 is_timeout = 1;
3389 }
3390 }
3391
3392 s->TCTR = curr_tick;
3393
3394 // DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3395
3396 if (is_timeout)
3397 {
3398 DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR));
3399 s->IntrStatus |= PCSTimeout;
3400 rtl8139_update_irq(s);
3401 }
3402
3403 qemu_mod_timer(s->timer,
3404 rtl8139_get_next_tctr_time(s,curr_time));
3405 }
3406 #endif /* RTL8139_ONBOARD_TIMER */
3407
3408 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn)
3409 {
3410 PCIRTL8139State *d;
3411 RTL8139State *s;
3412 uint8_t *pci_conf;
3413
3414 d = (PCIRTL8139State *)pci_register_device(bus,
3415 "RTL8139", sizeof(PCIRTL8139State),
3416 devfn,
3417 NULL, NULL);
3418 pci_conf = d->dev.config;
3419 pci_conf[0x00] = 0xec; /* Realtek 8139 */
3420 pci_conf[0x01] = 0x10;
3421 pci_conf[0x02] = 0x39;
3422 pci_conf[0x03] = 0x81;
3423 pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
3424 pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
3425 pci_conf[0x0a] = 0x00; /* ethernet network controller */
3426 pci_conf[0x0b] = 0x02;
3427 pci_conf[0x0e] = 0x00; /* header_type */
3428 pci_conf[0x3d] = 1; /* interrupt pin 0 */
3429 pci_conf[0x34] = 0xdc;
3430
3431 s = &d->rtl8139;
3432
3433 /* I/O handler for memory-mapped I/O */
3434 s->rtl8139_mmio_io_addr =
3435 cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
3436
3437 pci_register_io_region(&d->dev, 0, 0x100,
3438 PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map);
3439
3440 pci_register_io_region(&d->dev, 1, 0x100,
3441 PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
3442
3443 s->pci_dev = (PCIDevice *)d;
3444 memcpy(s->macaddr, nd->macaddr, 6);
3445 rtl8139_reset(s);
3446 s->vc = qemu_new_vlan_client(nd->vlan, rtl8139_receive,
3447 rtl8139_can_receive, s);
3448
3449 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
3450 "rtl8139 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
3451 s->macaddr[0],
3452 s->macaddr[1],
3453 s->macaddr[2],
3454 s->macaddr[3],
3455 s->macaddr[4],
3456 s->macaddr[5]);
3457
3458 s->cplus_txbuffer = NULL;
3459 s->cplus_txbuffer_len = 0;
3460 s->cplus_txbuffer_offset = 0;
3461
3462 /* XXX: instance number ? */
3463 register_savevm("rtl8139", 0, 3, rtl8139_save, rtl8139_load, s);
3464
3465 #if RTL8139_ONBOARD_TIMER
3466 s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
3467
3468 qemu_mod_timer(s->timer,
3469 rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
3470 #endif /* RTL8139_ONBOARD_TIMER */
3471 }
3472
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