hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define HARD_DEBUG_PPC_IO
  27 //#define DEBUG_PPC_IO
  28
  29 #define BIOS_FILENAME "ppc_rom.bin"
  30 #define KERNEL_LOAD_ADDR 0x01000000
  31 #define INITRD_LOAD_ADDR 0x01800000
  32
  33 extern int loglevel;
  34 extern FILE *logfile;
  35
  36 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  37 #define DEBUG_PPC_IO
  38 #endif
  39
  40 #if defined (HARD_DEBUG_PPC_IO)
  41 #define PPC_IO_DPRINTF(fmt, args...)                     \
  42 do {                                                     \
  43     if (loglevel & CPU_LOG_IOPORT) {                     \
  44         fprintf(logfile, "%s: " fmt, __func__ , ##args); \
  45     } else {                                             \
  46         printf("%s : " fmt, __func__ , ##args);          \
  47     }                                                    \
  48 } while (0)
  49 #elif defined (DEBUG_PPC_IO)
  50 #define PPC_IO_DPRINTF(fmt, args...)                     \
  51 do {                                                     \
  52     if (loglevel & CPU_LOG_IOPORT) {                     \
  53         fprintf(logfile, "%s: " fmt, __func__ , ##args); \
  54     }                                                    \
  55 } while (0)
  56 #else
  57 #define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
  58 #endif
  59
  60 /* Constants for devices init */
  61 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  62 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  63 static const int ide_irq[2] = { 13, 13 };
  64
  65 #define NE2000_NB_MAX 6
  66
  67 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  68 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  69
  70 //static PITState *pit;
  71
  72 /* ISA IO ports bridge */
  73 #define PPC_IO_BASE 0x80000000
  74
  75 /* Speaker port 0x61 */
  76 int speaker_data_on;
  77 int dummy_refresh_clock;
  78
  79 static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
  80 {
  81 #if 0
  82     speaker_data_on = (val >> 1) & 1;
  83     pit_set_gate(pit, 2, val & 1);
  84 #endif
  85 }
  86
  87 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
  88 {
  89 #if 0
  90     int out;
  91     out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
  92     dummy_refresh_clock ^= 1;
  93     return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
  94         (dummy_refresh_clock << 4);
  95 #endif
  96     return 0;
  97 }
  98
  99 /* PCI intack register */
 100 /* Read-only register (?) */
 101 static void _PPC_intack_write (void *opaque,
 102                                target_phys_addr_t addr, uint32_t value)
 103 {
 104     //    printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
 105 }
 106
 107 static inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
 108 {
 109     uint32_t retval = 0;
 110
 111     if (addr == 0xBFFFFFF0)
 112         retval = pic_intack_read(isa_pic);
 113        //   printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
 114
 115     return retval;
 116 }
 117
 118 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
 119 {
 120     return _PPC_intack_read(addr);
 121 }
 122
 123 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
 124 {
 125 #ifdef TARGET_WORDS_BIGENDIAN
 126     return bswap16(_PPC_intack_read(addr));
 127 #else
 128     return _PPC_intack_read(addr);
 129 #endif
 130 }
 131
 132 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
 133 {
 134 #ifdef TARGET_WORDS_BIGENDIAN
 135     return bswap32(_PPC_intack_read(addr));
 136 #else
 137     return _PPC_intack_read(addr);
 138 #endif
 139 }
 140
 141 static CPUWriteMemoryFunc *PPC_intack_write[] = {
 142     &_PPC_intack_write,
 143     &_PPC_intack_write,
 144     &_PPC_intack_write,
 145 };
 146
 147 static CPUReadMemoryFunc *PPC_intack_read[] = {
 148     &PPC_intack_readb,
 149     &PPC_intack_readw,
 150     &PPC_intack_readl,
 151 };
 152
 153 /* PowerPC control and status registers */
 154 #if 0 // Not used
 155 static struct {
 156     /* IDs */
 157     uint32_t veni_devi;
 158     uint32_t revi;
 159     /* Control and status */
 160     uint32_t gcsr;
 161     uint32_t xcfr;
 162     uint32_t ct32;
 163     uint32_t mcsr;
 164     /* General purpose registers */
 165     uint32_t gprg[6];
 166     /* Exceptions */
 167     uint32_t feen;
 168     uint32_t fest;
 169     uint32_t fema;
 170     uint32_t fecl;
 171     uint32_t eeen;
 172     uint32_t eest;
 173     uint32_t eecl;
 174     uint32_t eeint;
 175     uint32_t eemck0;
 176     uint32_t eemck1;
 177     /* Error diagnostic */
 178 } XCSR;
 179
 180 static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
 181 {
 182     printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
 183 }
 184
 185 static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 186 {
 187 #ifdef TARGET_WORDS_BIGENDIAN
 188     value = bswap16(value);
 189 #endif
 190     printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
 191 }
 192
 193 static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 194 {
 195 #ifdef TARGET_WORDS_BIGENDIAN
 196     value = bswap32(value);
 197 #endif
 198     printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
 199 }
 200
 201 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 202 {
 203     uint32_t retval = 0;
 204
 205     printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
 206
 207     return retval;
 208 }
 209
 210 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 211 {
 212     uint32_t retval = 0;
 213
 214     printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
 215 #ifdef TARGET_WORDS_BIGENDIAN
 216     retval = bswap16(retval);
 217 #endif
 218
 219     return retval;
 220 }
 221
 222 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 223 {
 224     uint32_t retval = 0;
 225
 226     printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
 227 #ifdef TARGET_WORDS_BIGENDIAN
 228     retval = bswap32(retval);
 229 #endif
 230
 231     return retval;
 232 }
 233
 234 static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
 235     &PPC_XCSR_writeb,
 236     &PPC_XCSR_writew,
 237     &PPC_XCSR_writel,
 238 };
 239
 240 static CPUReadMemoryFunc *PPC_XCSR_read[] = {
 241     &PPC_XCSR_readb,
 242     &PPC_XCSR_readw,
 243     &PPC_XCSR_readl,
 244 };
 245 #endif
 246
 247 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 248 typedef struct sysctrl_t {
 249     m48t59_t *nvram;
 250     uint8_t state;
 251     uint8_t syscontrol;
 252     uint8_t fake_io[2];
 253     int contiguous_map;
 254     int endian;
 255 } sysctrl_t;
 256
 257 enum {
 258     STATE_HARDFILE = 0x01,
 259 };
 260
 261 static sysctrl_t *sysctrl;
 262
 263 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 264 {
 265     sysctrl_t *sysctrl = opaque;
 266
 267     PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
 268     sysctrl->fake_io[addr - 0x0398] = val;
 269 }
 270
 271 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 272 {
 273     sysctrl_t *sysctrl = opaque;
 274
 275     PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
 276                    sysctrl->fake_io[addr - 0x0398]);
 277     return sysctrl->fake_io[addr - 0x0398];
 278 }
 279
 280 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 281 {
 282     sysctrl_t *sysctrl = opaque;
 283
 284     PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
 285     switch (addr) {
 286     case 0x0092:
 287         /* Special port 92 */
 288         /* Check soft reset asked */
 289         if (val & 0x01) {
 290             //            cpu_interrupt(first_cpu, PPC_INTERRUPT_RESET);
 291         }
 292         /* Check LE mode */
 293         if (val & 0x02) {
 294             sysctrl->endian = 1;
 295         } else {
 296             sysctrl->endian = 0;
 297         }
 298         break;
 299     case 0x0800:
 300         /* Motorola CPU configuration register : read-only */
 301         break;
 302     case 0x0802:
 303         /* Motorola base module feature register : read-only */
 304         break;
 305     case 0x0803:
 306         /* Motorola base module status register : read-only */
 307         break;
 308     case 0x0808:
 309         /* Hardfile light register */
 310         if (val & 1)
 311             sysctrl->state |= STATE_HARDFILE;
 312         else
 313             sysctrl->state &= ~STATE_HARDFILE;
 314         break;
 315     case 0x0810:
 316         /* Password protect 1 register */
 317         if (sysctrl->nvram != NULL)
 318             m48t59_toggle_lock(sysctrl->nvram, 1);
 319         break;
 320     case 0x0812:
 321         /* Password protect 2 register */
 322         if (sysctrl->nvram != NULL)
 323             m48t59_toggle_lock(sysctrl->nvram, 2);
 324         break;
 325     case 0x0814:
 326         /* L2 invalidate register */
 327         //        tlb_flush(first_cpu, 1);
 328         break;
 329     case 0x081C:
 330         /* system control register */
 331         sysctrl->syscontrol = val & 0x0F;
 332         break;
 333     case 0x0850:
 334         /* I/O map type register */
 335         sysctrl->contiguous_map = val & 0x01;
 336         break;
 337     default:
 338         printf("ERROR: unaffected IO port write: %04lx => %02x\n",
 339                (long)addr, val);
 340         break;
 341     }
 342 }
 343
 344 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 345 {
 346     sysctrl_t *sysctrl = opaque;
 347     uint32_t retval = 0xFF;
 348
 349     switch (addr) {
 350     case 0x0092:
 351         /* Special port 92 */
 352         retval = 0x00;
 353         break;
 354     case 0x0800:
 355         /* Motorola CPU configuration register */
 356         retval = 0xEF; /* MPC750 */
 357         break;
 358     case 0x0802:
 359         /* Motorola Base module feature register */
 360         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 361         break;
 362     case 0x0803:
 363         /* Motorola base module status register */
 364         retval = 0xE0; /* Standard MPC750 */
 365         break;
 366     case 0x080C:
 367         /* Equipment present register:
 368          *  no L2 cache
 369          *  no upgrade processor
 370          *  no cards in PCI slots
 371          *  SCSI fuse is bad
 372          */
 373         retval = 0x3C;
 374         break;
 375     case 0x0810:
 376         /* Motorola base module extended feature register */
 377         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 378         break;
 379     case 0x0814:
 380         /* L2 invalidate: don't care */
 381         break;
 382     case 0x0818:
 383         /* Keylock */
 384         retval = 0x00;
 385         break;
 386     case 0x081C:
 387         /* system control register
 388          * 7 - 6 / 1 - 0: L2 cache enable
 389          */
 390         retval = sysctrl->syscontrol;
 391         break;
 392     case 0x0823:
 393         /* */
 394         retval = 0x03; /* no L2 cache */
 395         break;
 396     case 0x0850:
 397         /* I/O map type register */
 398         retval = sysctrl->contiguous_map;
 399         break;
 400     default:
 401         printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
 402         break;
 403     }
 404     PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);
 405
 406     return retval;
 407 }
 408
 409 static inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
 410                                                   target_phys_addr_t addr)
 411 {
 412     if (sysctrl->contiguous_map == 0) {
 413         /* 64 KB contiguous space for IOs */
 414         addr &= 0xFFFF;
 415     } else {
 416         /* 8 MB non-contiguous space for IOs */
 417         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 418     }
 419
 420     return addr;
 421 }
 422
 423 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 424                                 uint32_t value)
 425 {
 426     sysctrl_t *sysctrl = opaque;
 427
 428     addr = prep_IO_address(sysctrl, addr);
 429     cpu_outb(NULL, addr, value);
 430 }
 431
 432 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 433 {
 434     sysctrl_t *sysctrl = opaque;
 435     uint32_t ret;
 436
 437     addr = prep_IO_address(sysctrl, addr);
 438     ret = cpu_inb(NULL, addr);
 439
 440     return ret;
 441 }
 442
 443 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 444                                 uint32_t value)
 445 {
 446     sysctrl_t *sysctrl = opaque;
 447
 448     addr = prep_IO_address(sysctrl, addr);
 449 #ifdef TARGET_WORDS_BIGENDIAN
 450     value = bswap16(value);
 451 #endif
 452     PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
 453     cpu_outw(NULL, addr, value);
 454 }
 455
 456 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 457 {
 458     sysctrl_t *sysctrl = opaque;
 459     uint32_t ret;
 460
 461     addr = prep_IO_address(sysctrl, addr);
 462     ret = cpu_inw(NULL, addr);
 463 #ifdef TARGET_WORDS_BIGENDIAN
 464     ret = bswap16(ret);
 465 #endif
 466     PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
 467
 468     return ret;
 469 }
 470
 471 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 472                                 uint32_t value)
 473 {
 474     sysctrl_t *sysctrl = opaque;
 475
 476     addr = prep_IO_address(sysctrl, addr);
 477 #ifdef TARGET_WORDS_BIGENDIAN
 478     value = bswap32(value);
 479 #endif
 480     PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
 481     cpu_outl(NULL, addr, value);
 482 }
 483
 484 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 485 {
 486     sysctrl_t *sysctrl = opaque;
 487     uint32_t ret;
 488
 489     addr = prep_IO_address(sysctrl, addr);
 490     ret = cpu_inl(NULL, addr);
 491 #ifdef TARGET_WORDS_BIGENDIAN
 492     ret = bswap32(ret);
 493 #endif
 494     PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
 495
 496     return ret;
 497 }
 498
 499 CPUWriteMemoryFunc *PPC_prep_io_write[] = {
 500     &PPC_prep_io_writeb,
 501     &PPC_prep_io_writew,
 502     &PPC_prep_io_writel,
 503 };
 504
 505 CPUReadMemoryFunc *PPC_prep_io_read[] = {
 506     &PPC_prep_io_readb,
 507     &PPC_prep_io_readw,
 508     &PPC_prep_io_readl,
 509 };
 510
 511 #define NVRAM_SIZE        0x2000
 512
 513 /* PowerPC PREP hardware initialisation */
 514 static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
 515                            DisplayState *ds, const char **fd_filename,
 516                            int snapshot, const char *kernel_filename,
 517                            const char *kernel_cmdline,
 518                            const char *initrd_filename,
 519                            const char *cpu_model)
 520 {
 521     CPUState *env;
 522     char buf[1024];
 523     m48t59_t *nvram;
 524     int PPC_io_memory;
 525     int linux_boot, i, nb_nics1, bios_size;
 526     unsigned long bios_offset;
 527     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 528     ppc_def_t *def;
 529     PCIBus *pci_bus;
 530     qemu_irq *i8259;
 531
 532     sysctrl = qemu_mallocz(sizeof(sysctrl_t));
 533     if (sysctrl == NULL)
 534         return;
 535
 536     linux_boot = (kernel_filename != NULL);
 537
 538     /* init CPUs */
 539
 540     env = cpu_init();
 541     qemu_register_reset(&cpu_ppc_reset, env);
 542     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 543
 544     /* Default CPU is a 604 */
 545     if (cpu_model == NULL)
 546         cpu_model = "604";
 547     ppc_find_by_name(cpu_model, &def);
 548     if (def == NULL) {
 549         cpu_abort(env, "Unable to find PowerPC CPU definition\n");
 550     }
 551     cpu_ppc_register(env, def);
 552     /* Set time-base frequency to 100 Mhz */
 553     cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 554
 555     /* allocate RAM */
 556     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 557
 558     /* allocate and load BIOS */
 559     bios_offset = ram_size + vga_ram_size;
 560     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
 561     bios_size = load_image(buf, phys_ram_base + bios_offset);
 562     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 563         cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
 564         exit(1);
 565     }
 566     bios_size = (bios_size + 0xfff) & ~0xfff;
 567     cpu_register_physical_memory((uint32_t)(-bios_size),
 568                                  bios_size, bios_offset | IO_MEM_ROM);
 569
 570     if (linux_boot) {
 571         kernel_base = KERNEL_LOAD_ADDR;
 572         /* now we can load the kernel */
 573         kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
 574         if (kernel_size < 0) {
 575             cpu_abort(env, "qemu: could not load kernel '%s'\n",
 576                       kernel_filename);
 577             exit(1);
 578         }
 579         /* load initrd */
 580         if (initrd_filename) {
 581             initrd_base = INITRD_LOAD_ADDR;
 582             initrd_size = load_image(initrd_filename,
 583                                      phys_ram_base + initrd_base);
 584             if (initrd_size < 0) {
 585                 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
 586                           initrd_filename);
 587                 exit(1);
 588             }
 589         } else {
 590             initrd_base = 0;
 591             initrd_size = 0;
 592         }
 593         boot_device = 'm';
 594     } else {
 595         kernel_base = 0;
 596         kernel_size = 0;
 597         initrd_base = 0;
 598         initrd_size = 0;
 599     }
 600
 601     isa_mem_base = 0xc0000000;
 602     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 603         cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
 604         exit(1);
 605     }
 606     i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 607     pci_bus = pci_prep_init(i8259);
 608     //    pci_bus = i440fx_init();
 609     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 610     PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
 611                                            PPC_prep_io_write, sysctrl);
 612     cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
 613
 614     /* init basic PC hardware */
 615     pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
 616                  vga_ram_size, 0, 0);
 617     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 618     //    pit = pit_init(0x40, i8259[0]);
 619     rtc_init(0x70, i8259[8]);
 620
 621     serial_init(0x3f8, i8259[4], serial_hds[0]);
 622     nb_nics1 = nb_nics;
 623     if (nb_nics1 > NE2000_NB_MAX)
 624         nb_nics1 = NE2000_NB_MAX;
 625     for(i = 0; i < nb_nics1; i++) {
 626         if (nd_table[0].model == NULL
 627             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 628             isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
 629         } else if (strcmp(nd_table[0].model, "?") == 0) {
 630             fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n");
 631             exit (1);
 632         } else {
 633             /* Why ? */
 634             cpu_abort(env, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 635             exit (1);
 636         }
 637     }
 638
 639     for(i = 0; i < 2; i++) {
 640         isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 641                      bs_table[2 * i], bs_table[2 * i + 1]);
 642     }
 643     i8042_init(i8259[1], i8259[12], 0x60);
 644     DMA_init(1);
 645     //    AUD_init();
 646     //    SB16_init();
 647
 648     fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table);
 649
 650     /* Register speaker port */
 651     register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
 652     register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
 653     /* Register fake IO ports for PREP */
 654     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 655     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 656     /* System control ports */
 657     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 658     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 659     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 660     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 661     /* PCI intack location */
 662     PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
 663                                            PPC_intack_write, NULL);
 664     cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
 665     /* PowerPC control and status register group */
 666 #if 0
 667     PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL);
 668     cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
 669 #endif
 670
 671     if (usb_enabled) {
 672         usb_ohci_init_pci(pci_bus, 3, -1);
 673     }
 674
 675     nvram = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
 676     if (nvram == NULL)
 677         return;
 678     sysctrl->nvram = nvram;
 679
 680     /* Initialise NVRAM */
 681     PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
 682                          kernel_base, kernel_size,
 683                          kernel_cmdline,
 684                          initrd_base, initrd_size,
 685                          /* XXX: need an option to load a NVRAM image */
 686                          0,
 687                          graphic_width, graphic_height, graphic_depth);
 688
 689     /* Special port to get debug messages from Open-Firmware */
 690     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 691 }
 692
 693 QEMUMachine prep_machine = {
 694     "prep",
 695     "PowerPC PREP platform",
 696     ppc_prep_init,
 697 };