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Fix typo in comment, by Andreas Faerber.
[qemu/dscho.git] / hw / ppc405_uc.c
blob384eb0d3ee931ae50d7b3743c25a49a5374e19bb
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25 #include "ppc405.h"
26
27 extern int loglevel;
28 extern FILE *logfile;
29
30 //#define DEBUG_MMIO
31 #define DEBUG_OPBA
32 #define DEBUG_SDRAM
33 #define DEBUG_GPIO
34 #define DEBUG_SERIAL
35 #define DEBUG_OCM
36 //#define DEBUG_I2C
37 #define DEBUG_GPT
38 #define DEBUG_MAL
39 #define DEBUG_UIC
40 #define DEBUG_CLOCKS
41 //#define DEBUG_UNASSIGNED
42
43 /*****************************************************************************/
44 /* Generic PowerPC 405 processor instanciation */
45 CPUState *ppc405_init (const unsigned char *cpu_model,
46 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
47 uint32_t sysclk)
48 {
49 CPUState *env;
50 ppc_def_t *def;
51
52 /* init CPUs */
53 env = cpu_init();
54 qemu_register_reset(&cpu_ppc_reset, env);
55 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
56 ppc_find_by_name(cpu_model, &def);
57 if (def == NULL) {
58 cpu_abort(env, "Unable to find PowerPC %s CPU definition\n",
59 cpu_model);
60 }
61 cpu_ppc_register(env, def);
62 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
63 cpu_clk->opaque = env;
64 /* Set time-base frequency to sysclk */
65 tb_clk->cb = ppc_emb_timers_init(env, sysclk);
66 tb_clk->opaque = env;
67 ppc_dcr_init(env, NULL, NULL);
68
69 return env;
70 }
71
72 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd)
73 {
74 ram_addr_t bdloc;
75 int i, n;
76
77 /* We put the bd structure at the top of memory */
78 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
79 stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
80 stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
81 stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
82 stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
83 stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
84 stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
85 stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
86 stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
87 stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
88 for (i = 0; i < 6; i++)
89 stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
90 stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
91 stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
92 stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
93 stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
94 for (i = 0; i < 4; i++)
95 stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
96 for (i = 0; i < 32; i++)
97 stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
98 stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
99 stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
100 for (i = 0; i < 6; i++)
101 stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
102 n = 0x6A;
103 if (env->spr[SPR_PVR] == CPU_PPC_405EP) {
104 for (i = 0; i < 6; i++)
105 stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);
106 }
107 stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq);
108 n += 4;
109 for (i = 0; i < 2; i++) {
110 stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]);
111 n += 4;
112 }
113
114 return bdloc;
115 }
116
117 /*****************************************************************************/
118 /* Shared peripherals */
119
120 /*****************************************************************************/
121 /* Fake device used to map multiple devices in a single memory page */
122 #define MMIO_AREA_BITS 8
123 #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
124 #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
125 #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
126 struct ppc4xx_mmio_t {
127 target_phys_addr_t base;
128 CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
129 CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
130 void *opaque[MMIO_AREA_NB];
131 };
132
133 static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
134 {
135 #ifdef DEBUG_UNASSIGNED
136 ppc4xx_mmio_t *mmio;
137
138 mmio = opaque;
139 printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
140 addr, mmio->base);
141 #endif
142
143 return 0;
144 }
145
146 static void unassigned_mmio_writeb (void *opaque,
147 target_phys_addr_t addr, uint32_t val)
148 {
149 #ifdef DEBUG_UNASSIGNED
150 ppc4xx_mmio_t *mmio;
151
152 mmio = opaque;
153 printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
154 addr, val, mmio->base);
155 #endif
156 }
157
158 static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
159 unassigned_mmio_readb,
160 unassigned_mmio_readb,
161 unassigned_mmio_readb,
162 };
163
164 static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
165 unassigned_mmio_writeb,
166 unassigned_mmio_writeb,
167 unassigned_mmio_writeb,
168 };
169
170 static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
171 target_phys_addr_t addr, int len)
172 {
173 CPUReadMemoryFunc **mem_read;
174 uint32_t ret;
175 int idx;
176
177 idx = MMIO_IDX(addr - mmio->base);
178 #if defined(DEBUG_MMIO)
179 printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
180 mmio, len, addr, idx);
181 #endif
182 mem_read = mmio->mem_read[idx];
183 ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);
184
185 return ret;
186 }
187
188 static void mmio_writelen (ppc4xx_mmio_t *mmio,
189 target_phys_addr_t addr, uint32_t value, int len)
190 {
191 CPUWriteMemoryFunc **mem_write;
192 int idx;
193
194 idx = MMIO_IDX(addr - mmio->base);
195 #if defined(DEBUG_MMIO)
196 printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__,
197 mmio, len, addr, idx, value);
198 #endif
199 mem_write = mmio->mem_write[idx];
200 (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
201 }
202
203 static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
204 {
205 #if defined(DEBUG_MMIO)
206 printf("%s: addr " PADDRX "\n", __func__, addr);
207 #endif
208
209 return mmio_readlen(opaque, addr, 0);
210 }
211
212 static void mmio_writeb (void *opaque,
213 target_phys_addr_t addr, uint32_t value)
214 {
215 #if defined(DEBUG_MMIO)
216 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
217 #endif
218 mmio_writelen(opaque, addr, value, 0);
219 }
220
221 static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
222 {
223 #if defined(DEBUG_MMIO)
224 printf("%s: addr " PADDRX "\n", __func__, addr);
225 #endif
226
227 return mmio_readlen(opaque, addr, 1);
228 }
229
230 static void mmio_writew (void *opaque,
231 target_phys_addr_t addr, uint32_t value)
232 {
233 #if defined(DEBUG_MMIO)
234 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
235 #endif
236 mmio_writelen(opaque, addr, value, 1);
237 }
238
239 static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
240 {
241 #if defined(DEBUG_MMIO)
242 printf("%s: addr " PADDRX "\n", __func__, addr);
243 #endif
244
245 return mmio_readlen(opaque, addr, 2);
246 }
247
248 static void mmio_writel (void *opaque,
249 target_phys_addr_t addr, uint32_t value)
250 {
251 #if defined(DEBUG_MMIO)
252 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
253 #endif
254 mmio_writelen(opaque, addr, value, 2);
255 }
256
257 static CPUReadMemoryFunc *mmio_read[] = {
258 &mmio_readb,
259 &mmio_readw,
260 &mmio_readl,
261 };
262
263 static CPUWriteMemoryFunc *mmio_write[] = {
264 &mmio_writeb,
265 &mmio_writew,
266 &mmio_writel,
267 };
268
269 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
270 target_phys_addr_t offset, uint32_t len,
271 CPUReadMemoryFunc **mem_read,
272 CPUWriteMemoryFunc **mem_write, void *opaque)
273 {
274 uint32_t end;
275 int idx, eidx;
276
277 if ((offset + len) > TARGET_PAGE_SIZE)
278 return -1;
279 idx = MMIO_IDX(offset);
280 end = offset + len - 1;
281 eidx = MMIO_IDX(end);
282 #if defined(DEBUG_MMIO)
283 printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
284 end, idx, eidx);
285 #endif
286 for (; idx <= eidx; idx++) {
287 mmio->mem_read[idx] = mem_read;
288 mmio->mem_write[idx] = mem_write;
289 mmio->opaque[idx] = opaque;
290 }
291
292 return 0;
293 }
294
295 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
296 {
297 ppc4xx_mmio_t *mmio;
298 int mmio_memory;
299
300 mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
301 if (mmio != NULL) {
302 mmio->base = base;
303 mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
304 #if defined(DEBUG_MMIO)
305 printf("%s: %p base %08x len %08x %d\n", __func__,
306 mmio, base, TARGET_PAGE_SIZE, mmio_memory);
307 #endif
308 cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
309 ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
310 unassigned_mmio_read, unassigned_mmio_write,
311 mmio);
312 }
313
314 return mmio;
315 }
316
317 /*****************************************************************************/
318 /* Peripheral local bus arbitrer */
319 enum {
320 PLB0_BESR = 0x084,
321 PLB0_BEAR = 0x086,
322 PLB0_ACR = 0x087,
323 };
324
325 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
326 struct ppc4xx_plb_t {
327 uint32_t acr;
328 uint32_t bear;
329 uint32_t besr;
330 };
331
332 static target_ulong dcr_read_plb (void *opaque, int dcrn)
333 {
334 ppc4xx_plb_t *plb;
335 target_ulong ret;
336
337 plb = opaque;
338 switch (dcrn) {
339 case PLB0_ACR:
340 ret = plb->acr;
341 break;
342 case PLB0_BEAR:
343 ret = plb->bear;
344 break;
345 case PLB0_BESR:
346 ret = plb->besr;
347 break;
348 default:
349 /* Avoid gcc warning */
350 ret = 0;
351 break;
352 }
353
354 return ret;
355 }
356
357 static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
358 {
359 ppc4xx_plb_t *plb;
360
361 plb = opaque;
362 switch (dcrn) {
363 case PLB0_ACR:
364 /* We don't care about the actual parameters written as
365 * we don't manage any priorities on the bus
366 */
367 plb->acr = val & 0xF8000000;
368 break;
369 case PLB0_BEAR:
370 /* Read only */
371 break;
372 case PLB0_BESR:
373 /* Write-clear */
374 plb->besr &= ~val;
375 break;
376 }
377 }
378
379 static void ppc4xx_plb_reset (void *opaque)
380 {
381 ppc4xx_plb_t *plb;
382
383 plb = opaque;
384 plb->acr = 0x00000000;
385 plb->bear = 0x00000000;
386 plb->besr = 0x00000000;
387 }
388
389 void ppc4xx_plb_init (CPUState *env)
390 {
391 ppc4xx_plb_t *plb;
392
393 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
394 if (plb != NULL) {
395 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
396 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
397 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
398 ppc4xx_plb_reset(plb);
399 qemu_register_reset(ppc4xx_plb_reset, plb);
400 }
401 }
402
403 /*****************************************************************************/
404 /* PLB to OPB bridge */
405 enum {
406 POB0_BESR0 = 0x0A0,
407 POB0_BESR1 = 0x0A2,
408 POB0_BEAR = 0x0A4,
409 };
410
411 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
412 struct ppc4xx_pob_t {
413 uint32_t bear;
414 uint32_t besr[2];
415 };
416
417 static target_ulong dcr_read_pob (void *opaque, int dcrn)
418 {
419 ppc4xx_pob_t *pob;
420 target_ulong ret;
421
422 pob = opaque;
423 switch (dcrn) {
424 case POB0_BEAR:
425 ret = pob->bear;
426 break;
427 case POB0_BESR0:
428 case POB0_BESR1:
429 ret = pob->besr[dcrn - POB0_BESR0];
430 break;
431 default:
432 /* Avoid gcc warning */
433 ret = 0;
434 break;
435 }
436
437 return ret;
438 }
439
440 static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
441 {
442 ppc4xx_pob_t *pob;
443
444 pob = opaque;
445 switch (dcrn) {
446 case POB0_BEAR:
447 /* Read only */
448 break;
449 case POB0_BESR0:
450 case POB0_BESR1:
451 /* Write-clear */
452 pob->besr[dcrn - POB0_BESR0] &= ~val;
453 break;
454 }
455 }
456
457 static void ppc4xx_pob_reset (void *opaque)
458 {
459 ppc4xx_pob_t *pob;
460
461 pob = opaque;
462 /* No error */
463 pob->bear = 0x00000000;
464 pob->besr[0] = 0x0000000;
465 pob->besr[1] = 0x0000000;
466 }
467
468 void ppc4xx_pob_init (CPUState *env)
469 {
470 ppc4xx_pob_t *pob;
471
472 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
473 if (pob != NULL) {
474 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
475 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
476 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
477 qemu_register_reset(ppc4xx_pob_reset, pob);
478 ppc4xx_pob_reset(env);
479 }
480 }
481
482 /*****************************************************************************/
483 /* OPB arbitrer */
484 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
485 struct ppc4xx_opba_t {
486 target_phys_addr_t base;
487 uint8_t cr;
488 uint8_t pr;
489 };
490
491 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
492 {
493 ppc4xx_opba_t *opba;
494 uint32_t ret;
495
496 #ifdef DEBUG_OPBA
497 printf("%s: addr " PADDRX "\n", __func__, addr);
498 #endif
499 opba = opaque;
500 switch (addr - opba->base) {
501 case 0x00:
502 ret = opba->cr;
503 break;
504 case 0x01:
505 ret = opba->pr;
506 break;
507 default:
508 ret = 0x00;
509 break;
510 }
511
512 return ret;
513 }
514
515 static void opba_writeb (void *opaque,
516 target_phys_addr_t addr, uint32_t value)
517 {
518 ppc4xx_opba_t *opba;
519
520 #ifdef DEBUG_OPBA
521 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
522 #endif
523 opba = opaque;
524 switch (addr - opba->base) {
525 case 0x00:
526 opba->cr = value & 0xF8;
527 break;
528 case 0x01:
529 opba->pr = value & 0xFF;
530 break;
531 default:
532 break;
533 }
534 }
535
536 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
537 {
538 uint32_t ret;
539
540 #ifdef DEBUG_OPBA
541 printf("%s: addr " PADDRX "\n", __func__, addr);
542 #endif
543 ret = opba_readb(opaque, addr) << 8;
544 ret |= opba_readb(opaque, addr + 1);
545
546 return ret;
547 }
548
549 static void opba_writew (void *opaque,
550 target_phys_addr_t addr, uint32_t value)
551 {
552 #ifdef DEBUG_OPBA
553 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
554 #endif
555 opba_writeb(opaque, addr, value >> 8);
556 opba_writeb(opaque, addr + 1, value);
557 }
558
559 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
560 {
561 uint32_t ret;
562
563 #ifdef DEBUG_OPBA
564 printf("%s: addr " PADDRX "\n", __func__, addr);
565 #endif
566 ret = opba_readb(opaque, addr) << 24;
567 ret |= opba_readb(opaque, addr + 1) << 16;
568
569 return ret;
570 }
571
572 static void opba_writel (void *opaque,
573 target_phys_addr_t addr, uint32_t value)
574 {
575 #ifdef DEBUG_OPBA
576 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
577 #endif
578 opba_writeb(opaque, addr, value >> 24);
579 opba_writeb(opaque, addr + 1, value >> 16);
580 }
581
582 static CPUReadMemoryFunc *opba_read[] = {
583 &opba_readb,
584 &opba_readw,
585 &opba_readl,
586 };
587
588 static CPUWriteMemoryFunc *opba_write[] = {
589 &opba_writeb,
590 &opba_writew,
591 &opba_writel,
592 };
593
594 static void ppc4xx_opba_reset (void *opaque)
595 {
596 ppc4xx_opba_t *opba;
597
598 opba = opaque;
599 opba->cr = 0x00; /* No dynamic priorities - park disabled */
600 opba->pr = 0x11;
601 }
602
603 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
604 target_phys_addr_t offset)
605 {
606 ppc4xx_opba_t *opba;
607
608 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
609 if (opba != NULL) {
610 opba->base = offset;
611 #ifdef DEBUG_OPBA
612 printf("%s: offset=" PADDRX "\n", __func__, offset);
613 #endif
614 ppc4xx_mmio_register(env, mmio, offset, 0x002,
615 opba_read, opba_write, opba);
616 qemu_register_reset(ppc4xx_opba_reset, opba);
617 ppc4xx_opba_reset(opba);
618 }
619 }
620
621 /*****************************************************************************/
622 /* "Universal" Interrupt controller */
623 enum {
624 DCR_UICSR = 0x000,
625 DCR_UICSRS = 0x001,
626 DCR_UICER = 0x002,
627 DCR_UICCR = 0x003,
628 DCR_UICPR = 0x004,
629 DCR_UICTR = 0x005,
630 DCR_UICMSR = 0x006,
631 DCR_UICVR = 0x007,
632 DCR_UICVCR = 0x008,
633 DCR_UICMAX = 0x009,
634 };
635
636 #define UIC_MAX_IRQ 32
637 typedef struct ppcuic_t ppcuic_t;
638 struct ppcuic_t {
639 uint32_t dcr_base;
640 int use_vectors;
641 uint32_t uicsr; /* Status register */
642 uint32_t uicer; /* Enable register */
643 uint32_t uiccr; /* Critical register */
644 uint32_t uicpr; /* Polarity register */
645 uint32_t uictr; /* Triggering register */
646 uint32_t uicvcr; /* Vector configuration register */
647 uint32_t uicvr;
648 qemu_irq *irqs;
649 };
650
651 static void ppcuic_trigger_irq (ppcuic_t *uic)
652 {
653 uint32_t ir, cr;
654 int start, end, inc, i;
655
656 /* Trigger interrupt if any is pending */
657 ir = uic->uicsr & uic->uicer & (~uic->uiccr);
658 cr = uic->uicsr & uic->uicer & uic->uiccr;
659 #ifdef DEBUG_UIC
660 if (loglevel & CPU_LOG_INT) {
661 fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"
662 " %08x ir %08x cr %08x\n", __func__,
663 uic->uicsr, uic->uicer, uic->uiccr,
664 uic->uicsr & uic->uicer, ir, cr);
665 }
666 #endif
667 if (ir != 0x0000000) {
668 #ifdef DEBUG_UIC
669 if (loglevel & CPU_LOG_INT) {
670 fprintf(logfile, "Raise UIC interrupt\n");
671 }
672 #endif
673 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
674 } else {
675 #ifdef DEBUG_UIC
676 if (loglevel & CPU_LOG_INT) {
677 fprintf(logfile, "Lower UIC interrupt\n");
678 }
679 #endif
680 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
681 }
682 /* Trigger critical interrupt if any is pending and update vector */
683 if (cr != 0x0000000) {
684 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
685 if (uic->use_vectors) {
686 /* Compute critical IRQ vector */
687 if (uic->uicvcr & 1) {
688 start = 31;
689 end = 0;
690 inc = -1;
691 } else {
692 start = 0;
693 end = 31;
694 inc = 1;
695 }
696 uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
697 for (i = start; i <= end; i += inc) {
698 if (cr & (1 << i)) {
699 uic->uicvr += (i - start) * 512 * inc;
700 break;
701 }
702 }
703 }
704 #ifdef DEBUG_UIC
705 if (loglevel & CPU_LOG_INT) {
706 fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",
707 uic->uicvr);
708 }
709 #endif
710 } else {
711 #ifdef DEBUG_UIC
712 if (loglevel & CPU_LOG_INT) {
713 fprintf(logfile, "Lower UIC critical interrupt\n");
714 }
715 #endif
716 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
717 uic->uicvr = 0x00000000;
718 }
719 }
720
721 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
722 {
723 ppcuic_t *uic;
724 uint32_t mask, sr;
725
726 uic = opaque;
727 mask = 1 << irq_num;
728 #ifdef DEBUG_UIC
729 if (loglevel & CPU_LOG_INT) {
730 fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "
731 "%08x\n", __func__, irq_num, level,
732 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
733 }
734 #endif
735 if (irq_num < 0 || irq_num > 31)
736 return;
737 sr = uic->uicsr;
738 if (!(uic->uicpr & mask)) {
739 /* Negatively asserted IRQ */
740 level = level == 0 ? 1 : 0;
741 }
742 /* Update status register */
743 if (uic->uictr & mask) {
744 /* Edge sensitive interrupt */
745 if (level == 1)
746 uic->uicsr |= mask;
747 } else {
748 /* Level sensitive interrupt */
749 if (level == 1)
750 uic->uicsr |= mask;
751 else
752 uic->uicsr &= ~mask;
753 }
754 #ifdef DEBUG_UIC
755 if (loglevel & CPU_LOG_INT) {
756 fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,
757 irq_num, level, uic->uicsr, sr);
758 }
759 #endif
760 if (sr != uic->uicsr)
761 ppcuic_trigger_irq(uic);
762 }
763
764 static target_ulong dcr_read_uic (void *opaque, int dcrn)
765 {
766 ppcuic_t *uic;
767 target_ulong ret;
768
769 uic = opaque;
770 dcrn -= uic->dcr_base;
771 switch (dcrn) {
772 case DCR_UICSR:
773 case DCR_UICSRS:
774 ret = uic->uicsr;
775 break;
776 case DCR_UICER:
777 ret = uic->uicer;
778 break;
779 case DCR_UICCR:
780 ret = uic->uiccr;
781 break;
782 case DCR_UICPR:
783 ret = uic->uicpr;
784 break;
785 case DCR_UICTR:
786 ret = uic->uictr;
787 break;
788 case DCR_UICMSR:
789 ret = uic->uicsr & uic->uicer;
790 break;
791 case DCR_UICVR:
792 if (!uic->use_vectors)
793 goto no_read;
794 ret = uic->uicvr;
795 break;
796 case DCR_UICVCR:
797 if (!uic->use_vectors)
798 goto no_read;
799 ret = uic->uicvcr;
800 break;
801 default:
802 no_read:
803 ret = 0x00000000;
804 break;
805 }
806
807 return ret;
808 }
809
810 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
811 {
812 ppcuic_t *uic;
813
814 uic = opaque;
815 dcrn -= uic->dcr_base;
816 #ifdef DEBUG_UIC
817 if (loglevel & CPU_LOG_INT) {
818 fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
819 }
820 #endif
821 switch (dcrn) {
822 case DCR_UICSR:
823 uic->uicsr &= ~val;
824 ppcuic_trigger_irq(uic);
825 break;
826 case DCR_UICSRS:
827 uic->uicsr |= val;
828 ppcuic_trigger_irq(uic);
829 break;
830 case DCR_UICER:
831 uic->uicer = val;
832 ppcuic_trigger_irq(uic);
833 break;
834 case DCR_UICCR:
835 uic->uiccr = val;
836 ppcuic_trigger_irq(uic);
837 break;
838 case DCR_UICPR:
839 uic->uicpr = val;
840 ppcuic_trigger_irq(uic);
841 break;
842 case DCR_UICTR:
843 uic->uictr = val;
844 ppcuic_trigger_irq(uic);
845 break;
846 case DCR_UICMSR:
847 break;
848 case DCR_UICVR:
849 break;
850 case DCR_UICVCR:
851 uic->uicvcr = val & 0xFFFFFFFD;
852 ppcuic_trigger_irq(uic);
853 break;
854 }
855 }
856
857 static void ppcuic_reset (void *opaque)
858 {
859 ppcuic_t *uic;
860
861 uic = opaque;
862 uic->uiccr = 0x00000000;
863 uic->uicer = 0x00000000;
864 uic->uicpr = 0x00000000;
865 uic->uicsr = 0x00000000;
866 uic->uictr = 0x00000000;
867 if (uic->use_vectors) {
868 uic->uicvcr = 0x00000000;
869 uic->uicvr = 0x0000000;
870 }
871 }
872
873 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
874 uint32_t dcr_base, int has_ssr, int has_vr)
875 {
876 ppcuic_t *uic;
877 int i;
878
879 uic = qemu_mallocz(sizeof(ppcuic_t));
880 if (uic != NULL) {
881 uic->dcr_base = dcr_base;
882 uic->irqs = irqs;
883 if (has_vr)
884 uic->use_vectors = 1;
885 for (i = 0; i < DCR_UICMAX; i++) {
886 ppc_dcr_register(env, dcr_base + i, uic,
887 &dcr_read_uic, &dcr_write_uic);
888 }
889 qemu_register_reset(ppcuic_reset, uic);
890 ppcuic_reset(uic);
891 }
892
893 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
894 }
895
896 /*****************************************************************************/
897 /* Code decompression controller */
898 /* XXX: TODO */
899
900 /*****************************************************************************/
901 /* SDRAM controller */
902 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
903 struct ppc4xx_sdram_t {
904 uint32_t addr;
905 int nbanks;
906 target_phys_addr_t ram_bases[4];
907 target_phys_addr_t ram_sizes[4];
908 uint32_t besr0;
909 uint32_t besr1;
910 uint32_t bear;
911 uint32_t cfg;
912 uint32_t status;
913 uint32_t rtr;
914 uint32_t pmit;
915 uint32_t bcr[4];
916 uint32_t tr;
917 uint32_t ecccfg;
918 uint32_t eccesr;
919 qemu_irq irq;
920 };
921
922 enum {
923 SDRAM0_CFGADDR = 0x010,
924 SDRAM0_CFGDATA = 0x011,
925 };
926
927 static uint32_t sdram_bcr (target_phys_addr_t ram_base, target_phys_addr_t ram_size)
928 {
929 uint32_t bcr;
930
931 switch (ram_size) {
932 case (4 * 1024 * 1024):
933 bcr = 0x00000000;
934 break;
935 case (8 * 1024 * 1024):
936 bcr = 0x00020000;
937 break;
938 case (16 * 1024 * 1024):
939 bcr = 0x00040000;
940 break;
941 case (32 * 1024 * 1024):
942 bcr = 0x00060000;
943 break;
944 case (64 * 1024 * 1024):
945 bcr = 0x00080000;
946 break;
947 case (128 * 1024 * 1024):
948 bcr = 0x000A0000;
949 break;
950 case (256 * 1024 * 1024):
951 bcr = 0x000C0000;
952 break;
953 default:
954 printf("%s: invalid RAM size " TARGET_FMT_ld "\n", __func__, ram_size);
955 return 0x00000000;
956 }
957 bcr |= ram_base & 0xFF800000;
958 bcr |= 1;
959
960 return bcr;
961 }
962
963 static inline target_phys_addr_t sdram_base (uint32_t bcr)
964 {
965 return bcr & 0xFF800000;
966 }
967
968 static target_ulong sdram_size (uint32_t bcr)
969 {
970 target_ulong size;
971 int sh;
972
973 sh = (bcr >> 17) & 0x7;
974 if (sh == 7)
975 size = -1;
976 else
977 size = (4 * 1024 * 1024) << sh;
978
979 return size;
980 }
981
982 static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
983 {
984 if (*bcrp & 0x00000001) {
985 /* Unmap RAM */
986 #ifdef DEBUG_SDRAM
987 printf("%s: unmap RAM area " ADDRX " " ADDRX "\n", __func__,
988 sdram_base(*bcrp), sdram_size(*bcrp));
989 #endif
990 cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
991 IO_MEM_UNASSIGNED);
992 }
993 *bcrp = bcr & 0xFFDEE001;
994 if (enabled && (bcr & 0x00000001)) {
995 #ifdef DEBUG_SDRAM
996 printf("%s: Map RAM area " ADDRX " " ADDRX "\n", __func__,
997 sdram_base(bcr), sdram_size(bcr));
998 #endif
999 cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
1000 sdram_base(bcr) | IO_MEM_RAM);
1001 }
1002 }
1003
1004 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
1005 {
1006 int i;
1007
1008 for (i = 0; i < sdram->nbanks; i++) {
1009 if (sdram->ram_sizes[i] != 0) {
1010 sdram_set_bcr(&sdram->bcr[i],
1011 sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
1012 1);
1013 } else {
1014 sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
1015 }
1016 }
1017 }
1018
1019 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
1020 {
1021 int i;
1022
1023 for (i = 0; i < sdram->nbanks; i++) {
1024 #ifdef DEBUG_SDRAM
1025 printf("%s: Unmap RAM area " ADDRX " " ADDRX "\n", __func__,
1026 sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
1027 #endif
1028 cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
1029 sdram_size(sdram->bcr[i]),
1030 IO_MEM_UNASSIGNED);
1031 }
1032 }
1033
1034 static target_ulong dcr_read_sdram (void *opaque, int dcrn)
1035 {
1036 ppc4xx_sdram_t *sdram;
1037 target_ulong ret;
1038
1039 sdram = opaque;
1040 switch (dcrn) {
1041 case SDRAM0_CFGADDR:
1042 ret = sdram->addr;
1043 break;
1044 case SDRAM0_CFGDATA:
1045 switch (sdram->addr) {
1046 case 0x00: /* SDRAM_BESR0 */
1047 ret = sdram->besr0;
1048 break;
1049 case 0x08: /* SDRAM_BESR1 */
1050 ret = sdram->besr1;
1051 break;
1052 case 0x10: /* SDRAM_BEAR */
1053 ret = sdram->bear;
1054 break;
1055 case 0x20: /* SDRAM_CFG */
1056 ret = sdram->cfg;
1057 break;
1058 case 0x24: /* SDRAM_STATUS */
1059 ret = sdram->status;
1060 break;
1061 case 0x30: /* SDRAM_RTR */
1062 ret = sdram->rtr;
1063 break;
1064 case 0x34: /* SDRAM_PMIT */
1065 ret = sdram->pmit;
1066 break;
1067 case 0x40: /* SDRAM_B0CR */
1068 ret = sdram->bcr[0];
1069 break;
1070 case 0x44: /* SDRAM_B1CR */
1071 ret = sdram->bcr[1];
1072 break;
1073 case 0x48: /* SDRAM_B2CR */
1074 ret = sdram->bcr[2];
1075 break;
1076 case 0x4C: /* SDRAM_B3CR */
1077 ret = sdram->bcr[3];
1078 break;
1079 case 0x80: /* SDRAM_TR */
1080 ret = -1; /* ? */
1081 break;
1082 case 0x94: /* SDRAM_ECCCFG */
1083 ret = sdram->ecccfg;
1084 break;
1085 case 0x98: /* SDRAM_ECCESR */
1086 ret = sdram->eccesr;
1087 break;
1088 default: /* Error */
1089 ret = -1;
1090 break;
1091 }
1092 break;
1093 default:
1094 /* Avoid gcc warning */
1095 ret = 0x00000000;
1096 break;
1097 }
1098
1099 return ret;
1100 }
1101
1102 static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
1103 {
1104 ppc4xx_sdram_t *sdram;
1105
1106 sdram = opaque;
1107 switch (dcrn) {
1108 case SDRAM0_CFGADDR:
1109 sdram->addr = val;
1110 break;
1111 case SDRAM0_CFGDATA:
1112 switch (sdram->addr) {
1113 case 0x00: /* SDRAM_BESR0 */
1114 sdram->besr0 &= ~val;
1115 break;
1116 case 0x08: /* SDRAM_BESR1 */
1117 sdram->besr1 &= ~val;
1118 break;
1119 case 0x10: /* SDRAM_BEAR */
1120 sdram->bear = val;
1121 break;
1122 case 0x20: /* SDRAM_CFG */
1123 val &= 0xFFE00000;
1124 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
1125 #ifdef DEBUG_SDRAM
1126 printf("%s: enable SDRAM controller\n", __func__);
1127 #endif
1128 /* validate all RAM mappings */
1129 sdram_map_bcr(sdram);
1130 sdram->status &= ~0x80000000;
1131 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
1132 #ifdef DEBUG_SDRAM
1133 printf("%s: disable SDRAM controller\n", __func__);
1134 #endif
1135 /* invalidate all RAM mappings */
1136 sdram_unmap_bcr(sdram);
1137 sdram->status |= 0x80000000;
1138 }
1139 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
1140 sdram->status |= 0x40000000;
1141 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
1142 sdram->status &= ~0x40000000;
1143 sdram->cfg = val;
1144 break;
1145 case 0x24: /* SDRAM_STATUS */
1146 /* Read-only register */
1147 break;
1148 case 0x30: /* SDRAM_RTR */
1149 sdram->rtr = val & 0x3FF80000;
1150 break;
1151 case 0x34: /* SDRAM_PMIT */
1152 sdram->pmit = (val & 0xF8000000) | 0x07C00000;
1153 break;
1154 case 0x40: /* SDRAM_B0CR */
1155 sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
1156 break;
1157 case 0x44: /* SDRAM_B1CR */
1158 sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
1159 break;
1160 case 0x48: /* SDRAM_B2CR */
1161 sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
1162 break;
1163 case 0x4C: /* SDRAM_B3CR */
1164 sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
1165 break;
1166 case 0x80: /* SDRAM_TR */
1167 sdram->tr = val & 0x018FC01F;
1168 break;
1169 case 0x94: /* SDRAM_ECCCFG */
1170 sdram->ecccfg = val & 0x00F00000;
1171 break;
1172 case 0x98: /* SDRAM_ECCESR */
1173 val &= 0xFFF0F000;
1174 if (sdram->eccesr == 0 && val != 0)
1175 qemu_irq_raise(sdram->irq);
1176 else if (sdram->eccesr != 0 && val == 0)
1177 qemu_irq_lower(sdram->irq);
1178 sdram->eccesr = val;
1179 break;
1180 default: /* Error */
1181 break;
1182 }
1183 break;
1184 }
1185 }
1186
1187 static void sdram_reset (void *opaque)
1188 {
1189 ppc4xx_sdram_t *sdram;
1190
1191 sdram = opaque;
1192 sdram->addr = 0x00000000;
1193 sdram->bear = 0x00000000;
1194 sdram->besr0 = 0x00000000; /* No error */
1195 sdram->besr1 = 0x00000000; /* No error */
1196 sdram->cfg = 0x00000000;
1197 sdram->ecccfg = 0x00000000; /* No ECC */
1198 sdram->eccesr = 0x00000000; /* No error */
1199 sdram->pmit = 0x07C00000;
1200 sdram->rtr = 0x05F00000;
1201 sdram->tr = 0x00854009;
1202 /* We pre-initialize RAM banks */
1203 sdram->status = 0x00000000;
1204 sdram->cfg = 0x00800000;
1205 sdram_unmap_bcr(sdram);
1206 }
1207
1208 void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
1209 target_phys_addr_t *ram_bases,
1210 target_phys_addr_t *ram_sizes,
1211 int do_init)
1212 {
1213 ppc4xx_sdram_t *sdram;
1214
1215 sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
1216 if (sdram != NULL) {
1217 sdram->irq = irq;
1218 sdram->nbanks = nbanks;
1219 memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
1220 memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_phys_addr_t));
1221 memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
1222 memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_phys_addr_t));
1223 sdram_reset(sdram);
1224 qemu_register_reset(&sdram_reset, sdram);
1225 ppc_dcr_register(env, SDRAM0_CFGADDR,
1226 sdram, &dcr_read_sdram, &dcr_write_sdram);
1227 ppc_dcr_register(env, SDRAM0_CFGDATA,
1228 sdram, &dcr_read_sdram, &dcr_write_sdram);
1229 if (do_init)
1230 sdram_map_bcr(sdram);
1231 }
1232 }
1233
1234 /*****************************************************************************/
1235 /* Peripheral controller */
1236 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
1237 struct ppc4xx_ebc_t {
1238 uint32_t addr;
1239 uint32_t bcr[8];
1240 uint32_t bap[8];
1241 uint32_t bear;
1242 uint32_t besr0;
1243 uint32_t besr1;
1244 uint32_t cfg;
1245 };
1246
1247 enum {
1248 EBC0_CFGADDR = 0x012,
1249 EBC0_CFGDATA = 0x013,
1250 };
1251
1252 static target_ulong dcr_read_ebc (void *opaque, int dcrn)
1253 {
1254 ppc4xx_ebc_t *ebc;
1255 target_ulong ret;
1256
1257 ebc = opaque;
1258 switch (dcrn) {
1259 case EBC0_CFGADDR:
1260 ret = ebc->addr;
1261 break;
1262 case EBC0_CFGDATA:
1263 switch (ebc->addr) {
1264 case 0x00: /* B0CR */
1265 ret = ebc->bcr[0];
1266 break;
1267 case 0x01: /* B1CR */
1268 ret = ebc->bcr[1];
1269 break;
1270 case 0x02: /* B2CR */
1271 ret = ebc->bcr[2];
1272 break;
1273 case 0x03: /* B3CR */
1274 ret = ebc->bcr[3];
1275 break;
1276 case 0x04: /* B4CR */
1277 ret = ebc->bcr[4];
1278 break;
1279 case 0x05: /* B5CR */
1280 ret = ebc->bcr[5];
1281 break;
1282 case 0x06: /* B6CR */
1283 ret = ebc->bcr[6];
1284 break;
1285 case 0x07: /* B7CR */
1286 ret = ebc->bcr[7];
1287 break;
1288 case 0x10: /* B0AP */
1289 ret = ebc->bap[0];
1290 break;
1291 case 0x11: /* B1AP */
1292 ret = ebc->bap[1];
1293 break;
1294 case 0x12: /* B2AP */
1295 ret = ebc->bap[2];
1296 break;
1297 case 0x13: /* B3AP */
1298 ret = ebc->bap[3];
1299 break;
1300 case 0x14: /* B4AP */
1301 ret = ebc->bap[4];
1302 break;
1303 case 0x15: /* B5AP */
1304 ret = ebc->bap[5];
1305 break;
1306 case 0x16: /* B6AP */
1307 ret = ebc->bap[6];
1308 break;
1309 case 0x17: /* B7AP */
1310 ret = ebc->bap[7];
1311 break;
1312 case 0x20: /* BEAR */
1313 ret = ebc->bear;
1314 break;
1315 case 0x21: /* BESR0 */
1316 ret = ebc->besr0;
1317 break;
1318 case 0x22: /* BESR1 */
1319 ret = ebc->besr1;
1320 break;
1321 case 0x23: /* CFG */
1322 ret = ebc->cfg;
1323 break;
1324 default:
1325 ret = 0x00000000;
1326 break;
1327 }
1328 default:
1329 ret = 0x00000000;
1330 break;
1331 }
1332
1333 return ret;
1334 }
1335
1336 static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
1337 {
1338 ppc4xx_ebc_t *ebc;
1339
1340 ebc = opaque;
1341 switch (dcrn) {
1342 case EBC0_CFGADDR:
1343 ebc->addr = val;
1344 break;
1345 case EBC0_CFGDATA:
1346 switch (ebc->addr) {
1347 case 0x00: /* B0CR */
1348 break;
1349 case 0x01: /* B1CR */
1350 break;
1351 case 0x02: /* B2CR */
1352 break;
1353 case 0x03: /* B3CR */
1354 break;
1355 case 0x04: /* B4CR */
1356 break;
1357 case 0x05: /* B5CR */
1358 break;
1359 case 0x06: /* B6CR */
1360 break;
1361 case 0x07: /* B7CR */
1362 break;
1363 case 0x10: /* B0AP */
1364 break;
1365 case 0x11: /* B1AP */
1366 break;
1367 case 0x12: /* B2AP */
1368 break;
1369 case 0x13: /* B3AP */
1370 break;
1371 case 0x14: /* B4AP */
1372 break;
1373 case 0x15: /* B5AP */
1374 break;
1375 case 0x16: /* B6AP */
1376 break;
1377 case 0x17: /* B7AP */
1378 break;
1379 case 0x20: /* BEAR */
1380 break;
1381 case 0x21: /* BESR0 */
1382 break;
1383 case 0x22: /* BESR1 */
1384 break;
1385 case 0x23: /* CFG */
1386 break;
1387 default:
1388 break;
1389 }
1390 break;
1391 default:
1392 break;
1393 }
1394 }
1395
1396 static void ebc_reset (void *opaque)
1397 {
1398 ppc4xx_ebc_t *ebc;
1399 int i;
1400
1401 ebc = opaque;
1402 ebc->addr = 0x00000000;
1403 ebc->bap[0] = 0x7F8FFE80;
1404 ebc->bcr[0] = 0xFFE28000;
1405 for (i = 0; i < 8; i++) {
1406 ebc->bap[i] = 0x00000000;
1407 ebc->bcr[i] = 0x00000000;
1408 }
1409 ebc->besr0 = 0x00000000;
1410 ebc->besr1 = 0x00000000;
1411 ebc->cfg = 0x80400000;
1412 }
1413
1414 void ppc405_ebc_init (CPUState *env)
1415 {
1416 ppc4xx_ebc_t *ebc;
1417
1418 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
1419 if (ebc != NULL) {
1420 ebc_reset(ebc);
1421 qemu_register_reset(&ebc_reset, ebc);
1422 ppc_dcr_register(env, EBC0_CFGADDR,
1423 ebc, &dcr_read_ebc, &dcr_write_ebc);
1424 ppc_dcr_register(env, EBC0_CFGDATA,
1425 ebc, &dcr_read_ebc, &dcr_write_ebc);
1426 }
1427 }
1428
1429 /*****************************************************************************/
1430 /* DMA controller */
1431 enum {
1432 DMA0_CR0 = 0x100,
1433 DMA0_CT0 = 0x101,
1434 DMA0_DA0 = 0x102,
1435 DMA0_SA0 = 0x103,
1436 DMA0_SG0 = 0x104,
1437 DMA0_CR1 = 0x108,
1438 DMA0_CT1 = 0x109,
1439 DMA0_DA1 = 0x10A,
1440 DMA0_SA1 = 0x10B,
1441 DMA0_SG1 = 0x10C,
1442 DMA0_CR2 = 0x110,
1443 DMA0_CT2 = 0x111,
1444 DMA0_DA2 = 0x112,
1445 DMA0_SA2 = 0x113,
1446 DMA0_SG2 = 0x114,
1447 DMA0_CR3 = 0x118,
1448 DMA0_CT3 = 0x119,
1449 DMA0_DA3 = 0x11A,
1450 DMA0_SA3 = 0x11B,
1451 DMA0_SG3 = 0x11C,
1452 DMA0_SR = 0x120,
1453 DMA0_SGC = 0x123,
1454 DMA0_SLP = 0x125,
1455 DMA0_POL = 0x126,
1456 };
1457
1458 typedef struct ppc405_dma_t ppc405_dma_t;
1459 struct ppc405_dma_t {
1460 qemu_irq irqs[4];
1461 uint32_t cr[4];
1462 uint32_t ct[4];
1463 uint32_t da[4];
1464 uint32_t sa[4];
1465 uint32_t sg[4];
1466 uint32_t sr;
1467 uint32_t sgc;
1468 uint32_t slp;
1469 uint32_t pol;
1470 };
1471
1472 static target_ulong dcr_read_dma (void *opaque, int dcrn)
1473 {
1474 ppc405_dma_t *dma;
1475
1476 dma = opaque;
1477
1478 return 0;
1479 }
1480
1481 static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
1482 {
1483 ppc405_dma_t *dma;
1484
1485 dma = opaque;
1486 }
1487
1488 static void ppc405_dma_reset (void *opaque)
1489 {
1490 ppc405_dma_t *dma;
1491 int i;
1492
1493 dma = opaque;
1494 for (i = 0; i < 4; i++) {
1495 dma->cr[i] = 0x00000000;
1496 dma->ct[i] = 0x00000000;
1497 dma->da[i] = 0x00000000;
1498 dma->sa[i] = 0x00000000;
1499 dma->sg[i] = 0x00000000;
1500 }
1501 dma->sr = 0x00000000;
1502 dma->sgc = 0x00000000;
1503 dma->slp = 0x7C000000;
1504 dma->pol = 0x00000000;
1505 }
1506
1507 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
1508 {
1509 ppc405_dma_t *dma;
1510
1511 dma = qemu_mallocz(sizeof(ppc405_dma_t));
1512 if (dma != NULL) {
1513 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
1514 ppc405_dma_reset(dma);
1515 qemu_register_reset(&ppc405_dma_reset, dma);
1516 ppc_dcr_register(env, DMA0_CR0,
1517 dma, &dcr_read_dma, &dcr_write_dma);
1518 ppc_dcr_register(env, DMA0_CT0,
1519 dma, &dcr_read_dma, &dcr_write_dma);
1520 ppc_dcr_register(env, DMA0_DA0,
1521 dma, &dcr_read_dma, &dcr_write_dma);
1522 ppc_dcr_register(env, DMA0_SA0,
1523 dma, &dcr_read_dma, &dcr_write_dma);
1524 ppc_dcr_register(env, DMA0_SG0,
1525 dma, &dcr_read_dma, &dcr_write_dma);
1526 ppc_dcr_register(env, DMA0_CR1,
1527 dma, &dcr_read_dma, &dcr_write_dma);
1528 ppc_dcr_register(env, DMA0_CT1,
1529 dma, &dcr_read_dma, &dcr_write_dma);
1530 ppc_dcr_register(env, DMA0_DA1,
1531 dma, &dcr_read_dma, &dcr_write_dma);
1532 ppc_dcr_register(env, DMA0_SA1,
1533 dma, &dcr_read_dma, &dcr_write_dma);
1534 ppc_dcr_register(env, DMA0_SG1,
1535 dma, &dcr_read_dma, &dcr_write_dma);
1536 ppc_dcr_register(env, DMA0_CR2,
1537 dma, &dcr_read_dma, &dcr_write_dma);
1538 ppc_dcr_register(env, DMA0_CT2,
1539 dma, &dcr_read_dma, &dcr_write_dma);
1540 ppc_dcr_register(env, DMA0_DA2,
1541 dma, &dcr_read_dma, &dcr_write_dma);
1542 ppc_dcr_register(env, DMA0_SA2,
1543 dma, &dcr_read_dma, &dcr_write_dma);
1544 ppc_dcr_register(env, DMA0_SG2,
1545 dma, &dcr_read_dma, &dcr_write_dma);
1546 ppc_dcr_register(env, DMA0_CR3,
1547 dma, &dcr_read_dma, &dcr_write_dma);
1548 ppc_dcr_register(env, DMA0_CT3,
1549 dma, &dcr_read_dma, &dcr_write_dma);
1550 ppc_dcr_register(env, DMA0_DA3,
1551 dma, &dcr_read_dma, &dcr_write_dma);
1552 ppc_dcr_register(env, DMA0_SA3,
1553 dma, &dcr_read_dma, &dcr_write_dma);
1554 ppc_dcr_register(env, DMA0_SG3,
1555 dma, &dcr_read_dma, &dcr_write_dma);
1556 ppc_dcr_register(env, DMA0_SR,
1557 dma, &dcr_read_dma, &dcr_write_dma);
1558 ppc_dcr_register(env, DMA0_SGC,
1559 dma, &dcr_read_dma, &dcr_write_dma);
1560 ppc_dcr_register(env, DMA0_SLP,
1561 dma, &dcr_read_dma, &dcr_write_dma);
1562 ppc_dcr_register(env, DMA0_POL,
1563 dma, &dcr_read_dma, &dcr_write_dma);
1564 }
1565 }
1566
1567 /*****************************************************************************/
1568 /* GPIO */
1569 typedef struct ppc405_gpio_t ppc405_gpio_t;
1570 struct ppc405_gpio_t {
1571 target_phys_addr_t base;
1572 uint32_t or;
1573 uint32_t tcr;
1574 uint32_t osrh;
1575 uint32_t osrl;
1576 uint32_t tsrh;
1577 uint32_t tsrl;
1578 uint32_t odr;
1579 uint32_t ir;
1580 uint32_t rr1;
1581 uint32_t isr1h;
1582 uint32_t isr1l;
1583 };
1584
1585 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
1586 {
1587 ppc405_gpio_t *gpio;
1588
1589 gpio = opaque;
1590 #ifdef DEBUG_GPIO
1591 printf("%s: addr " PADDRX "\n", __func__, addr);
1592 #endif
1593
1594 return 0;
1595 }
1596
1597 static void ppc405_gpio_writeb (void *opaque,
1598 target_phys_addr_t addr, uint32_t value)
1599 {
1600 ppc405_gpio_t *gpio;
1601
1602 gpio = opaque;
1603 #ifdef DEBUG_GPIO
1604 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1605 #endif
1606 }
1607
1608 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
1609 {
1610 ppc405_gpio_t *gpio;
1611
1612 gpio = opaque;
1613 #ifdef DEBUG_GPIO
1614 printf("%s: addr " PADDRX "\n", __func__, addr);
1615 #endif
1616
1617 return 0;
1618 }
1619
1620 static void ppc405_gpio_writew (void *opaque,
1621 target_phys_addr_t addr, uint32_t value)
1622 {
1623 ppc405_gpio_t *gpio;
1624
1625 gpio = opaque;
1626 #ifdef DEBUG_GPIO
1627 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1628 #endif
1629 }
1630
1631 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
1632 {
1633 ppc405_gpio_t *gpio;
1634
1635 gpio = opaque;
1636 #ifdef DEBUG_GPIO
1637 printf("%s: addr " PADDRX "\n", __func__, addr);
1638 #endif
1639
1640 return 0;
1641 }
1642
1643 static void ppc405_gpio_writel (void *opaque,
1644 target_phys_addr_t addr, uint32_t value)
1645 {
1646 ppc405_gpio_t *gpio;
1647
1648 gpio = opaque;
1649 #ifdef DEBUG_GPIO
1650 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1651 #endif
1652 }
1653
1654 static CPUReadMemoryFunc *ppc405_gpio_read[] = {
1655 &ppc405_gpio_readb,
1656 &ppc405_gpio_readw,
1657 &ppc405_gpio_readl,
1658 };
1659
1660 static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
1661 &ppc405_gpio_writeb,
1662 &ppc405_gpio_writew,
1663 &ppc405_gpio_writel,
1664 };
1665
1666 static void ppc405_gpio_reset (void *opaque)
1667 {
1668 ppc405_gpio_t *gpio;
1669
1670 gpio = opaque;
1671 }
1672
1673 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
1674 target_phys_addr_t offset)
1675 {
1676 ppc405_gpio_t *gpio;
1677
1678 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
1679 if (gpio != NULL) {
1680 gpio->base = offset;
1681 ppc405_gpio_reset(gpio);
1682 qemu_register_reset(&ppc405_gpio_reset, gpio);
1683 #ifdef DEBUG_GPIO
1684 printf("%s: offset=" PADDRX "\n", __func__, offset);
1685 #endif
1686 ppc4xx_mmio_register(env, mmio, offset, 0x038,
1687 ppc405_gpio_read, ppc405_gpio_write, gpio);
1688 }
1689 }
1690
1691 /*****************************************************************************/
1692 /* Serial ports */
1693 static CPUReadMemoryFunc *serial_mm_read[] = {
1694 &serial_mm_readb,
1695 &serial_mm_readw,
1696 &serial_mm_readl,
1697 };
1698
1699 static CPUWriteMemoryFunc *serial_mm_write[] = {
1700 &serial_mm_writeb,
1701 &serial_mm_writew,
1702 &serial_mm_writel,
1703 };
1704
1705 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
1706 target_phys_addr_t offset, qemu_irq irq,
1707 CharDriverState *chr)
1708 {
1709 void *serial;
1710
1711 #ifdef DEBUG_SERIAL
1712 printf("%s: offset=" PADDRX "\n", __func__, offset);
1713 #endif
1714 serial = serial_mm_init(offset, 0, irq, chr, 0);
1715 ppc4xx_mmio_register(env, mmio, offset, 0x008,
1716 serial_mm_read, serial_mm_write, serial);
1717 }
1718
1719 /*****************************************************************************/
1720 /* On Chip Memory */
1721 enum {
1722 OCM0_ISARC = 0x018,
1723 OCM0_ISACNTL = 0x019,
1724 OCM0_DSARC = 0x01A,
1725 OCM0_DSACNTL = 0x01B,
1726 };
1727
1728 typedef struct ppc405_ocm_t ppc405_ocm_t;
1729 struct ppc405_ocm_t {
1730 target_ulong offset;
1731 uint32_t isarc;
1732 uint32_t isacntl;
1733 uint32_t dsarc;
1734 uint32_t dsacntl;
1735 };
1736
1737 static void ocm_update_mappings (ppc405_ocm_t *ocm,
1738 uint32_t isarc, uint32_t isacntl,
1739 uint32_t dsarc, uint32_t dsacntl)
1740 {
1741 #ifdef DEBUG_OCM
1742 printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n",
1743 isarc, isacntl, dsarc, dsacntl,
1744 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
1745 #endif
1746 if (ocm->isarc != isarc ||
1747 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
1748 if (ocm->isacntl & 0x80000000) {
1749 /* Unmap previously assigned memory region */
1750 printf("OCM unmap ISA %08x\n", ocm->isarc);
1751 cpu_register_physical_memory(ocm->isarc, 0x04000000,
1752 IO_MEM_UNASSIGNED);
1753 }
1754 if (isacntl & 0x80000000) {
1755 /* Map new instruction memory region */
1756 #ifdef DEBUG_OCM
1757 printf("OCM map ISA %08x\n", isarc);
1758 #endif
1759 cpu_register_physical_memory(isarc, 0x04000000,
1760 ocm->offset | IO_MEM_RAM);
1761 }
1762 }
1763 if (ocm->dsarc != dsarc ||
1764 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
1765 if (ocm->dsacntl & 0x80000000) {
1766 /* Beware not to unmap the region we just mapped */
1767 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
1768 /* Unmap previously assigned memory region */
1769 #ifdef DEBUG_OCM
1770 printf("OCM unmap DSA %08x\n", ocm->dsarc);
1771 #endif
1772 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
1773 IO_MEM_UNASSIGNED);
1774 }
1775 }
1776 if (dsacntl & 0x80000000) {
1777 /* Beware not to remap the region we just mapped */
1778 if (!(isacntl & 0x80000000) || dsarc != isarc) {
1779 /* Map new data memory region */
1780 #ifdef DEBUG_OCM
1781 printf("OCM map DSA %08x\n", dsarc);
1782 #endif
1783 cpu_register_physical_memory(dsarc, 0x04000000,
1784 ocm->offset | IO_MEM_RAM);
1785 }
1786 }
1787 }
1788 }
1789
1790 static target_ulong dcr_read_ocm (void *opaque, int dcrn)
1791 {
1792 ppc405_ocm_t *ocm;
1793 target_ulong ret;
1794
1795 ocm = opaque;
1796 switch (dcrn) {
1797 case OCM0_ISARC:
1798 ret = ocm->isarc;
1799 break;
1800 case OCM0_ISACNTL:
1801 ret = ocm->isacntl;
1802 break;
1803 case OCM0_DSARC:
1804 ret = ocm->dsarc;
1805 break;
1806 case OCM0_DSACNTL:
1807 ret = ocm->dsacntl;
1808 break;
1809 default:
1810 ret = 0;
1811 break;
1812 }
1813
1814 return ret;
1815 }
1816
1817 static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
1818 {
1819 ppc405_ocm_t *ocm;
1820 uint32_t isarc, dsarc, isacntl, dsacntl;
1821
1822 ocm = opaque;
1823 isarc = ocm->isarc;
1824 dsarc = ocm->dsarc;
1825 isacntl = ocm->isacntl;
1826 dsacntl = ocm->dsacntl;
1827 switch (dcrn) {
1828 case OCM0_ISARC:
1829 isarc = val & 0xFC000000;
1830 break;
1831 case OCM0_ISACNTL:
1832 isacntl = val & 0xC0000000;
1833 break;
1834 case OCM0_DSARC:
1835 isarc = val & 0xFC000000;
1836 break;
1837 case OCM0_DSACNTL:
1838 isacntl = val & 0xC0000000;
1839 break;
1840 }
1841 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1842 ocm->isarc = isarc;
1843 ocm->dsarc = dsarc;
1844 ocm->isacntl = isacntl;
1845 ocm->dsacntl = dsacntl;
1846 }
1847
1848 static void ocm_reset (void *opaque)
1849 {
1850 ppc405_ocm_t *ocm;
1851 uint32_t isarc, dsarc, isacntl, dsacntl;
1852
1853 ocm = opaque;
1854 isarc = 0x00000000;
1855 isacntl = 0x00000000;
1856 dsarc = 0x00000000;
1857 dsacntl = 0x00000000;
1858 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1859 ocm->isarc = isarc;
1860 ocm->dsarc = dsarc;
1861 ocm->isacntl = isacntl;
1862 ocm->dsacntl = dsacntl;
1863 }
1864
1865 void ppc405_ocm_init (CPUState *env, unsigned long offset)
1866 {
1867 ppc405_ocm_t *ocm;
1868
1869 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
1870 if (ocm != NULL) {
1871 ocm->offset = offset;
1872 ocm_reset(ocm);
1873 qemu_register_reset(&ocm_reset, ocm);
1874 ppc_dcr_register(env, OCM0_ISARC,
1875 ocm, &dcr_read_ocm, &dcr_write_ocm);
1876 ppc_dcr_register(env, OCM0_ISACNTL,
1877 ocm, &dcr_read_ocm, &dcr_write_ocm);
1878 ppc_dcr_register(env, OCM0_DSARC,
1879 ocm, &dcr_read_ocm, &dcr_write_ocm);
1880 ppc_dcr_register(env, OCM0_DSACNTL,
1881 ocm, &dcr_read_ocm, &dcr_write_ocm);
1882 }
1883 }
1884
1885 /*****************************************************************************/
1886 /* I2C controller */
1887 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
1888 struct ppc4xx_i2c_t {
1889 target_phys_addr_t base;
1890 qemu_irq irq;
1891 uint8_t mdata;
1892 uint8_t lmadr;
1893 uint8_t hmadr;
1894 uint8_t cntl;
1895 uint8_t mdcntl;
1896 uint8_t sts;
1897 uint8_t extsts;
1898 uint8_t sdata;
1899 uint8_t lsadr;
1900 uint8_t hsadr;
1901 uint8_t clkdiv;
1902 uint8_t intrmsk;
1903 uint8_t xfrcnt;
1904 uint8_t xtcntlss;
1905 uint8_t directcntl;
1906 };
1907
1908 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1909 {
1910 ppc4xx_i2c_t *i2c;
1911 uint32_t ret;
1912
1913 #ifdef DEBUG_I2C
1914 printf("%s: addr " PADDRX "\n", __func__, addr);
1915 #endif
1916 i2c = opaque;
1917 switch (addr - i2c->base) {
1918 case 0x00:
1919 // i2c_readbyte(&i2c->mdata);
1920 ret = i2c->mdata;
1921 break;
1922 case 0x02:
1923 ret = i2c->sdata;
1924 break;
1925 case 0x04:
1926 ret = i2c->lmadr;
1927 break;
1928 case 0x05:
1929 ret = i2c->hmadr;
1930 break;
1931 case 0x06:
1932 ret = i2c->cntl;
1933 break;
1934 case 0x07:
1935 ret = i2c->mdcntl;
1936 break;
1937 case 0x08:
1938 ret = i2c->sts;
1939 break;
1940 case 0x09:
1941 ret = i2c->extsts;
1942 break;
1943 case 0x0A:
1944 ret = i2c->lsadr;
1945 break;
1946 case 0x0B:
1947 ret = i2c->hsadr;
1948 break;
1949 case 0x0C:
1950 ret = i2c->clkdiv;
1951 break;
1952 case 0x0D:
1953 ret = i2c->intrmsk;
1954 break;
1955 case 0x0E:
1956 ret = i2c->xfrcnt;
1957 break;
1958 case 0x0F:
1959 ret = i2c->xtcntlss;
1960 break;
1961 case 0x10:
1962 ret = i2c->directcntl;
1963 break;
1964 default:
1965 ret = 0x00;
1966 break;
1967 }
1968 #ifdef DEBUG_I2C
1969 printf("%s: addr " PADDRX " %02x\n", __func__, addr, ret);
1970 #endif
1971
1972 return ret;
1973 }
1974
1975 static void ppc4xx_i2c_writeb (void *opaque,
1976 target_phys_addr_t addr, uint32_t value)
1977 {
1978 ppc4xx_i2c_t *i2c;
1979
1980 #ifdef DEBUG_I2C
1981 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1982 #endif
1983 i2c = opaque;
1984 switch (addr - i2c->base) {
1985 case 0x00:
1986 i2c->mdata = value;
1987 // i2c_sendbyte(&i2c->mdata);
1988 break;
1989 case 0x02:
1990 i2c->sdata = value;
1991 break;
1992 case 0x04:
1993 i2c->lmadr = value;
1994 break;
1995 case 0x05:
1996 i2c->hmadr = value;
1997 break;
1998 case 0x06:
1999 i2c->cntl = value;
2000 break;
2001 case 0x07:
2002 i2c->mdcntl = value & 0xDF;
2003 break;
2004 case 0x08:
2005 i2c->sts &= ~(value & 0x0A);
2006 break;
2007 case 0x09:
2008 i2c->extsts &= ~(value & 0x8F);
2009 break;
2010 case 0x0A:
2011 i2c->lsadr = value;
2012 break;
2013 case 0x0B:
2014 i2c->hsadr = value;
2015 break;
2016 case 0x0C:
2017 i2c->clkdiv = value;
2018 break;
2019 case 0x0D:
2020 i2c->intrmsk = value;
2021 break;
2022 case 0x0E:
2023 i2c->xfrcnt = value & 0x77;
2024 break;
2025 case 0x0F:
2026 i2c->xtcntlss = value;
2027 break;
2028 case 0x10:
2029 i2c->directcntl = value & 0x7;
2030 break;
2031 }
2032 }
2033
2034 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
2035 {
2036 uint32_t ret;
2037
2038 #ifdef DEBUG_I2C
2039 printf("%s: addr " PADDRX "\n", __func__, addr);
2040 #endif
2041 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
2042 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
2043
2044 return ret;
2045 }
2046
2047 static void ppc4xx_i2c_writew (void *opaque,
2048 target_phys_addr_t addr, uint32_t value)
2049 {
2050 #ifdef DEBUG_I2C
2051 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2052 #endif
2053 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
2054 ppc4xx_i2c_writeb(opaque, addr + 1, value);
2055 }
2056
2057 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
2058 {
2059 uint32_t ret;
2060
2061 #ifdef DEBUG_I2C
2062 printf("%s: addr " PADDRX "\n", __func__, addr);
2063 #endif
2064 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
2065 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
2066 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
2067 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
2068
2069 return ret;
2070 }
2071
2072 static void ppc4xx_i2c_writel (void *opaque,
2073 target_phys_addr_t addr, uint32_t value)
2074 {
2075 #ifdef DEBUG_I2C
2076 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2077 #endif
2078 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
2079 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
2080 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
2081 ppc4xx_i2c_writeb(opaque, addr + 3, value);
2082 }
2083
2084 static CPUReadMemoryFunc *i2c_read[] = {
2085 &ppc4xx_i2c_readb,
2086 &ppc4xx_i2c_readw,
2087 &ppc4xx_i2c_readl,
2088 };
2089
2090 static CPUWriteMemoryFunc *i2c_write[] = {
2091 &ppc4xx_i2c_writeb,
2092 &ppc4xx_i2c_writew,
2093 &ppc4xx_i2c_writel,
2094 };
2095
2096 static void ppc4xx_i2c_reset (void *opaque)
2097 {
2098 ppc4xx_i2c_t *i2c;
2099
2100 i2c = opaque;
2101 i2c->mdata = 0x00;
2102 i2c->sdata = 0x00;
2103 i2c->cntl = 0x00;
2104 i2c->mdcntl = 0x00;
2105 i2c->sts = 0x00;
2106 i2c->extsts = 0x00;
2107 i2c->clkdiv = 0x00;
2108 i2c->xfrcnt = 0x00;
2109 i2c->directcntl = 0x0F;
2110 }
2111
2112 void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
2113 target_phys_addr_t offset, qemu_irq irq)
2114 {
2115 ppc4xx_i2c_t *i2c;
2116
2117 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
2118 if (i2c != NULL) {
2119 i2c->base = offset;
2120 i2c->irq = irq;
2121 ppc4xx_i2c_reset(i2c);
2122 #ifdef DEBUG_I2C
2123 printf("%s: offset=" PADDRX "\n", __func__, offset);
2124 #endif
2125 ppc4xx_mmio_register(env, mmio, offset, 0x011,
2126 i2c_read, i2c_write, i2c);
2127 qemu_register_reset(ppc4xx_i2c_reset, i2c);
2128 }
2129 }
2130
2131 /*****************************************************************************/
2132 /* General purpose timers */
2133 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
2134 struct ppc4xx_gpt_t {
2135 target_phys_addr_t base;
2136 int64_t tb_offset;
2137 uint32_t tb_freq;
2138 struct QEMUTimer *timer;
2139 qemu_irq irqs[5];
2140 uint32_t oe;
2141 uint32_t ol;
2142 uint32_t im;
2143 uint32_t is;
2144 uint32_t ie;
2145 uint32_t comp[5];
2146 uint32_t mask[5];
2147 };
2148
2149 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
2150 {
2151 #ifdef DEBUG_GPT
2152 printf("%s: addr " PADDRX "\n", __func__, addr);
2153 #endif
2154 /* XXX: generate a bus fault */
2155 return -1;
2156 }
2157
2158 static void ppc4xx_gpt_writeb (void *opaque,
2159 target_phys_addr_t addr, uint32_t value)
2160 {
2161 #ifdef DEBUG_I2C
2162 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2163 #endif
2164 /* XXX: generate a bus fault */
2165 }
2166
2167 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
2168 {
2169 #ifdef DEBUG_GPT
2170 printf("%s: addr " PADDRX "\n", __func__, addr);
2171 #endif
2172 /* XXX: generate a bus fault */
2173 return -1;
2174 }
2175
2176 static void ppc4xx_gpt_writew (void *opaque,
2177 target_phys_addr_t addr, uint32_t value)
2178 {
2179 #ifdef DEBUG_I2C
2180 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2181 #endif
2182 /* XXX: generate a bus fault */
2183 }
2184
2185 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
2186 {
2187 /* XXX: TODO */
2188 return 0;
2189 }
2190
2191 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
2192 {
2193 /* XXX: TODO */
2194 }
2195
2196 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
2197 {
2198 uint32_t mask;
2199 int i;
2200
2201 mask = 0x80000000;
2202 for (i = 0; i < 5; i++) {
2203 if (gpt->oe & mask) {
2204 /* Output is enabled */
2205 if (ppc4xx_gpt_compare(gpt, i)) {
2206 /* Comparison is OK */
2207 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
2208 } else {
2209 /* Comparison is KO */
2210 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
2211 }
2212 }
2213 mask = mask >> 1;
2214 }
2215
2216 }
2217
2218 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
2219 {
2220 uint32_t mask;
2221 int i;
2222
2223 mask = 0x00008000;
2224 for (i = 0; i < 5; i++) {
2225 if (gpt->is & gpt->im & mask)
2226 qemu_irq_raise(gpt->irqs[i]);
2227 else
2228 qemu_irq_lower(gpt->irqs[i]);
2229 mask = mask >> 1;
2230 }
2231
2232 }
2233
2234 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
2235 {
2236 /* XXX: TODO */
2237 }
2238
2239 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
2240 {
2241 ppc4xx_gpt_t *gpt;
2242 uint32_t ret;
2243 int idx;
2244
2245 #ifdef DEBUG_GPT
2246 printf("%s: addr " PADDRX "\n", __func__, addr);
2247 #endif
2248 gpt = opaque;
2249 switch (addr - gpt->base) {
2250 case 0x00:
2251 /* Time base counter */
2252 ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
2253 gpt->tb_freq, ticks_per_sec);
2254 break;
2255 case 0x10:
2256 /* Output enable */
2257 ret = gpt->oe;
2258 break;
2259 case 0x14:
2260 /* Output level */
2261 ret = gpt->ol;
2262 break;
2263 case 0x18:
2264 /* Interrupt mask */
2265 ret = gpt->im;
2266 break;
2267 case 0x1C:
2268 case 0x20:
2269 /* Interrupt status */
2270 ret = gpt->is;
2271 break;
2272 case 0x24:
2273 /* Interrupt enable */
2274 ret = gpt->ie;
2275 break;
2276 case 0x80 ... 0x90:
2277 /* Compare timer */
2278 idx = ((addr - gpt->base) - 0x80) >> 2;
2279 ret = gpt->comp[idx];
2280 break;
2281 case 0xC0 ... 0xD0:
2282 /* Compare mask */
2283 idx = ((addr - gpt->base) - 0xC0) >> 2;
2284 ret = gpt->mask[idx];
2285 break;
2286 default:
2287 ret = -1;
2288 break;
2289 }
2290
2291 return ret;
2292 }
2293
2294 static void ppc4xx_gpt_writel (void *opaque,
2295 target_phys_addr_t addr, uint32_t value)
2296 {
2297 ppc4xx_gpt_t *gpt;
2298 int idx;
2299
2300 #ifdef DEBUG_I2C
2301 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2302 #endif
2303 gpt = opaque;
2304 switch (addr - gpt->base) {
2305 case 0x00:
2306 /* Time base counter */
2307 gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq)
2308 - qemu_get_clock(vm_clock);
2309 ppc4xx_gpt_compute_timer(gpt);
2310 break;
2311 case 0x10:
2312 /* Output enable */
2313 gpt->oe = value & 0xF8000000;
2314 ppc4xx_gpt_set_outputs(gpt);
2315 break;
2316 case 0x14:
2317 /* Output level */
2318 gpt->ol = value & 0xF8000000;
2319 ppc4xx_gpt_set_outputs(gpt);
2320 break;
2321 case 0x18:
2322 /* Interrupt mask */
2323 gpt->im = value & 0x0000F800;
2324 break;
2325 case 0x1C:
2326 /* Interrupt status set */
2327 gpt->is |= value & 0x0000F800;
2328 ppc4xx_gpt_set_irqs(gpt);
2329 break;
2330 case 0x20:
2331 /* Interrupt status clear */
2332 gpt->is &= ~(value & 0x0000F800);
2333 ppc4xx_gpt_set_irqs(gpt);
2334 break;
2335 case 0x24:
2336 /* Interrupt enable */
2337 gpt->ie = value & 0x0000F800;
2338 ppc4xx_gpt_set_irqs(gpt);
2339 break;
2340 case 0x80 ... 0x90:
2341 /* Compare timer */
2342 idx = ((addr - gpt->base) - 0x80) >> 2;
2343 gpt->comp[idx] = value & 0xF8000000;
2344 ppc4xx_gpt_compute_timer(gpt);
2345 break;
2346 case 0xC0 ... 0xD0:
2347 /* Compare mask */
2348 idx = ((addr - gpt->base) - 0xC0) >> 2;
2349 gpt->mask[idx] = value & 0xF8000000;
2350 ppc4xx_gpt_compute_timer(gpt);
2351 break;
2352 }
2353 }
2354
2355 static CPUReadMemoryFunc *gpt_read[] = {
2356 &ppc4xx_gpt_readb,
2357 &ppc4xx_gpt_readw,
2358 &ppc4xx_gpt_readl,
2359 };
2360
2361 static CPUWriteMemoryFunc *gpt_write[] = {
2362 &ppc4xx_gpt_writeb,
2363 &ppc4xx_gpt_writew,
2364 &ppc4xx_gpt_writel,
2365 };
2366
2367 static void ppc4xx_gpt_cb (void *opaque)
2368 {
2369 ppc4xx_gpt_t *gpt;
2370
2371 gpt = opaque;
2372 ppc4xx_gpt_set_irqs(gpt);
2373 ppc4xx_gpt_set_outputs(gpt);
2374 ppc4xx_gpt_compute_timer(gpt);
2375 }
2376
2377 static void ppc4xx_gpt_reset (void *opaque)
2378 {
2379 ppc4xx_gpt_t *gpt;
2380 int i;
2381
2382 gpt = opaque;
2383 qemu_del_timer(gpt->timer);
2384 gpt->oe = 0x00000000;
2385 gpt->ol = 0x00000000;
2386 gpt->im = 0x00000000;
2387 gpt->is = 0x00000000;
2388 gpt->ie = 0x00000000;
2389 for (i = 0; i < 5; i++) {
2390 gpt->comp[i] = 0x00000000;
2391 gpt->mask[i] = 0x00000000;
2392 }
2393 }
2394
2395 void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
2396 target_phys_addr_t offset, qemu_irq irqs[5])
2397 {
2398 ppc4xx_gpt_t *gpt;
2399 int i;
2400
2401 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
2402 if (gpt != NULL) {
2403 gpt->base = offset;
2404 for (i = 0; i < 5; i++)
2405 gpt->irqs[i] = irqs[i];
2406 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
2407 ppc4xx_gpt_reset(gpt);
2408 #ifdef DEBUG_GPT
2409 printf("%s: offset=" PADDRX "\n", __func__, offset);
2410 #endif
2411 ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
2412 gpt_read, gpt_write, gpt);
2413 qemu_register_reset(ppc4xx_gpt_reset, gpt);
2414 }
2415 }
2416
2417 /*****************************************************************************/
2418 /* MAL */
2419 enum {
2420 MAL0_CFG = 0x180,
2421 MAL0_ESR = 0x181,
2422 MAL0_IER = 0x182,
2423 MAL0_TXCASR = 0x184,
2424 MAL0_TXCARR = 0x185,
2425 MAL0_TXEOBISR = 0x186,
2426 MAL0_TXDEIR = 0x187,
2427 MAL0_RXCASR = 0x190,
2428 MAL0_RXCARR = 0x191,
2429 MAL0_RXEOBISR = 0x192,
2430 MAL0_RXDEIR = 0x193,
2431 MAL0_TXCTP0R = 0x1A0,
2432 MAL0_TXCTP1R = 0x1A1,
2433 MAL0_TXCTP2R = 0x1A2,
2434 MAL0_TXCTP3R = 0x1A3,
2435 MAL0_RXCTP0R = 0x1C0,
2436 MAL0_RXCTP1R = 0x1C1,
2437 MAL0_RCBS0 = 0x1E0,
2438 MAL0_RCBS1 = 0x1E1,
2439 };
2440
2441 typedef struct ppc40x_mal_t ppc40x_mal_t;
2442 struct ppc40x_mal_t {
2443 qemu_irq irqs[4];
2444 uint32_t cfg;
2445 uint32_t esr;
2446 uint32_t ier;
2447 uint32_t txcasr;
2448 uint32_t txcarr;
2449 uint32_t txeobisr;
2450 uint32_t txdeir;
2451 uint32_t rxcasr;
2452 uint32_t rxcarr;
2453 uint32_t rxeobisr;
2454 uint32_t rxdeir;
2455 uint32_t txctpr[4];
2456 uint32_t rxctpr[2];
2457 uint32_t rcbs[2];
2458 };
2459
2460 static void ppc40x_mal_reset (void *opaque);
2461
2462 static target_ulong dcr_read_mal (void *opaque, int dcrn)
2463 {
2464 ppc40x_mal_t *mal;
2465 target_ulong ret;
2466
2467 mal = opaque;
2468 switch (dcrn) {
2469 case MAL0_CFG:
2470 ret = mal->cfg;
2471 break;
2472 case MAL0_ESR:
2473 ret = mal->esr;
2474 break;
2475 case MAL0_IER:
2476 ret = mal->ier;
2477 break;
2478 case MAL0_TXCASR:
2479 ret = mal->txcasr;
2480 break;
2481 case MAL0_TXCARR:
2482 ret = mal->txcarr;
2483 break;
2484 case MAL0_TXEOBISR:
2485 ret = mal->txeobisr;
2486 break;
2487 case MAL0_TXDEIR:
2488 ret = mal->txdeir;
2489 break;
2490 case MAL0_RXCASR:
2491 ret = mal->rxcasr;
2492 break;
2493 case MAL0_RXCARR:
2494 ret = mal->rxcarr;
2495 break;
2496 case MAL0_RXEOBISR:
2497 ret = mal->rxeobisr;
2498 break;
2499 case MAL0_RXDEIR:
2500 ret = mal->rxdeir;
2501 break;
2502 case MAL0_TXCTP0R:
2503 ret = mal->txctpr[0];
2504 break;
2505 case MAL0_TXCTP1R:
2506 ret = mal->txctpr[1];
2507 break;
2508 case MAL0_TXCTP2R:
2509 ret = mal->txctpr[2];
2510 break;
2511 case MAL0_TXCTP3R:
2512 ret = mal->txctpr[3];
2513 break;
2514 case MAL0_RXCTP0R:
2515 ret = mal->rxctpr[0];
2516 break;
2517 case MAL0_RXCTP1R:
2518 ret = mal->rxctpr[1];
2519 break;
2520 case MAL0_RCBS0:
2521 ret = mal->rcbs[0];
2522 break;
2523 case MAL0_RCBS1:
2524 ret = mal->rcbs[1];
2525 break;
2526 default:
2527 ret = 0;
2528 break;
2529 }
2530
2531 return ret;
2532 }
2533
2534 static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
2535 {
2536 ppc40x_mal_t *mal;
2537 int idx;
2538
2539 mal = opaque;
2540 switch (dcrn) {
2541 case MAL0_CFG:
2542 if (val & 0x80000000)
2543 ppc40x_mal_reset(mal);
2544 mal->cfg = val & 0x00FFC087;
2545 break;
2546 case MAL0_ESR:
2547 /* Read/clear */
2548 mal->esr &= ~val;
2549 break;
2550 case MAL0_IER:
2551 mal->ier = val & 0x0000001F;
2552 break;
2553 case MAL0_TXCASR:
2554 mal->txcasr = val & 0xF0000000;
2555 break;
2556 case MAL0_TXCARR:
2557 mal->txcarr = val & 0xF0000000;
2558 break;
2559 case MAL0_TXEOBISR:
2560 /* Read/clear */
2561 mal->txeobisr &= ~val;
2562 break;
2563 case MAL0_TXDEIR:
2564 /* Read/clear */
2565 mal->txdeir &= ~val;
2566 break;
2567 case MAL0_RXCASR:
2568 mal->rxcasr = val & 0xC0000000;
2569 break;
2570 case MAL0_RXCARR:
2571 mal->rxcarr = val & 0xC0000000;
2572 break;
2573 case MAL0_RXEOBISR:
2574 /* Read/clear */
2575 mal->rxeobisr &= ~val;
2576 break;
2577 case MAL0_RXDEIR:
2578 /* Read/clear */
2579 mal->rxdeir &= ~val;
2580 break;
2581 case MAL0_TXCTP0R:
2582 idx = 0;
2583 goto update_tx_ptr;
2584 case MAL0_TXCTP1R:
2585 idx = 1;
2586 goto update_tx_ptr;
2587 case MAL0_TXCTP2R:
2588 idx = 2;
2589 goto update_tx_ptr;
2590 case MAL0_TXCTP3R:
2591 idx = 3;
2592 update_tx_ptr:
2593 mal->txctpr[idx] = val;
2594 break;
2595 case MAL0_RXCTP0R:
2596 idx = 0;
2597 goto update_rx_ptr;
2598 case MAL0_RXCTP1R:
2599 idx = 1;
2600 update_rx_ptr:
2601 mal->rxctpr[idx] = val;
2602 break;
2603 case MAL0_RCBS0:
2604 idx = 0;
2605 goto update_rx_size;
2606 case MAL0_RCBS1:
2607 idx = 1;
2608 update_rx_size:
2609 mal->rcbs[idx] = val & 0x000000FF;
2610 break;
2611 }
2612 }
2613
2614 static void ppc40x_mal_reset (void *opaque)
2615 {
2616 ppc40x_mal_t *mal;
2617
2618 mal = opaque;
2619 mal->cfg = 0x0007C000;
2620 mal->esr = 0x00000000;
2621 mal->ier = 0x00000000;
2622 mal->rxcasr = 0x00000000;
2623 mal->rxdeir = 0x00000000;
2624 mal->rxeobisr = 0x00000000;
2625 mal->txcasr = 0x00000000;
2626 mal->txdeir = 0x00000000;
2627 mal->txeobisr = 0x00000000;
2628 }
2629
2630 void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
2631 {
2632 ppc40x_mal_t *mal;
2633 int i;
2634
2635 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
2636 if (mal != NULL) {
2637 for (i = 0; i < 4; i++)
2638 mal->irqs[i] = irqs[i];
2639 ppc40x_mal_reset(mal);
2640 qemu_register_reset(&ppc40x_mal_reset, mal);
2641 ppc_dcr_register(env, MAL0_CFG,
2642 mal, &dcr_read_mal, &dcr_write_mal);
2643 ppc_dcr_register(env, MAL0_ESR,
2644 mal, &dcr_read_mal, &dcr_write_mal);
2645 ppc_dcr_register(env, MAL0_IER,
2646 mal, &dcr_read_mal, &dcr_write_mal);
2647 ppc_dcr_register(env, MAL0_TXCASR,
2648 mal, &dcr_read_mal, &dcr_write_mal);
2649 ppc_dcr_register(env, MAL0_TXCARR,
2650 mal, &dcr_read_mal, &dcr_write_mal);
2651 ppc_dcr_register(env, MAL0_TXEOBISR,
2652 mal, &dcr_read_mal, &dcr_write_mal);
2653 ppc_dcr_register(env, MAL0_TXDEIR,
2654 mal, &dcr_read_mal, &dcr_write_mal);
2655 ppc_dcr_register(env, MAL0_RXCASR,
2656 mal, &dcr_read_mal, &dcr_write_mal);
2657 ppc_dcr_register(env, MAL0_RXCARR,
2658 mal, &dcr_read_mal, &dcr_write_mal);
2659 ppc_dcr_register(env, MAL0_RXEOBISR,
2660 mal, &dcr_read_mal, &dcr_write_mal);
2661 ppc_dcr_register(env, MAL0_RXDEIR,
2662 mal, &dcr_read_mal, &dcr_write_mal);
2663 ppc_dcr_register(env, MAL0_TXCTP0R,
2664 mal, &dcr_read_mal, &dcr_write_mal);
2665 ppc_dcr_register(env, MAL0_TXCTP1R,
2666 mal, &dcr_read_mal, &dcr_write_mal);
2667 ppc_dcr_register(env, MAL0_TXCTP2R,
2668 mal, &dcr_read_mal, &dcr_write_mal);
2669 ppc_dcr_register(env, MAL0_TXCTP3R,
2670 mal, &dcr_read_mal, &dcr_write_mal);
2671 ppc_dcr_register(env, MAL0_RXCTP0R,
2672 mal, &dcr_read_mal, &dcr_write_mal);
2673 ppc_dcr_register(env, MAL0_RXCTP1R,
2674 mal, &dcr_read_mal, &dcr_write_mal);
2675 ppc_dcr_register(env, MAL0_RCBS0,
2676 mal, &dcr_read_mal, &dcr_write_mal);
2677 ppc_dcr_register(env, MAL0_RCBS1,
2678 mal, &dcr_read_mal, &dcr_write_mal);
2679 }
2680 }
2681
2682 /*****************************************************************************/
2683 /* SPR */
2684 void ppc40x_core_reset (CPUState *env)
2685 {
2686 target_ulong dbsr;
2687
2688 printf("Reset PowerPC core\n");
2689 cpu_ppc_reset(env);
2690 dbsr = env->spr[SPR_40x_DBSR];
2691 dbsr &= ~0x00000300;
2692 dbsr |= 0x00000100;
2693 env->spr[SPR_40x_DBSR] = dbsr;
2694 cpu_loop_exit();
2695 }
2696
2697 void ppc40x_chip_reset (CPUState *env)
2698 {
2699 target_ulong dbsr;
2700
2701 printf("Reset PowerPC chip\n");
2702 cpu_ppc_reset(env);
2703 /* XXX: TODO reset all internal peripherals */
2704 dbsr = env->spr[SPR_40x_DBSR];
2705 dbsr &= ~0x00000300;
2706 dbsr |= 0x00000200;
2707 env->spr[SPR_40x_DBSR] = dbsr;
2708 cpu_loop_exit();
2709 }
2710
2711 void ppc40x_system_reset (CPUState *env)
2712 {
2713 printf("Reset PowerPC system\n");
2714 qemu_system_reset_request();
2715 }
2716
2717 void store_40x_dbcr0 (CPUState *env, uint32_t val)
2718 {
2719 switch ((val >> 28) & 0x3) {
2720 case 0x0:
2721 /* No action */
2722 break;
2723 case 0x1:
2724 /* Core reset */
2725 ppc40x_core_reset(env);
2726 break;
2727 case 0x2:
2728 /* Chip reset */
2729 ppc40x_chip_reset(env);
2730 break;
2731 case 0x3:
2732 /* System reset */
2733 ppc40x_system_reset(env);
2734 break;
2735 }
2736 }
2737
2738 /*****************************************************************************/
2739 /* PowerPC 405CR */
2740 enum {
2741 PPC405CR_CPC0_PLLMR = 0x0B0,
2742 PPC405CR_CPC0_CR0 = 0x0B1,
2743 PPC405CR_CPC0_CR1 = 0x0B2,
2744 PPC405CR_CPC0_PSR = 0x0B4,
2745 PPC405CR_CPC0_JTAGID = 0x0B5,
2746 PPC405CR_CPC0_ER = 0x0B9,
2747 PPC405CR_CPC0_FR = 0x0BA,
2748 PPC405CR_CPC0_SR = 0x0BB,
2749 };
2750
2751 enum {
2752 PPC405CR_CPU_CLK = 0,
2753 PPC405CR_TMR_CLK = 1,
2754 PPC405CR_PLB_CLK = 2,
2755 PPC405CR_SDRAM_CLK = 3,
2756 PPC405CR_OPB_CLK = 4,
2757 PPC405CR_EXT_CLK = 5,
2758 PPC405CR_UART_CLK = 6,
2759 PPC405CR_CLK_NB = 7,
2760 };
2761
2762 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
2763 struct ppc405cr_cpc_t {
2764 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2765 uint32_t sysclk;
2766 uint32_t psr;
2767 uint32_t cr0;
2768 uint32_t cr1;
2769 uint32_t jtagid;
2770 uint32_t pllmr;
2771 uint32_t er;
2772 uint32_t fr;
2773 };
2774
2775 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
2776 {
2777 uint64_t VCO_out, PLL_out;
2778 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
2779 int M, D0, D1, D2;
2780
2781 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
2782 if (cpc->pllmr & 0x80000000) {
2783 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
2784 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
2785 M = D0 * D1 * D2;
2786 VCO_out = cpc->sysclk * M;
2787 if (VCO_out < 400000000 || VCO_out > 800000000) {
2788 /* PLL cannot lock */
2789 cpc->pllmr &= ~0x80000000;
2790 goto bypass_pll;
2791 }
2792 PLL_out = VCO_out / D2;
2793 } else {
2794 /* Bypass PLL */
2795 bypass_pll:
2796 M = D0;
2797 PLL_out = cpc->sysclk * M;
2798 }
2799 CPU_clk = PLL_out;
2800 if (cpc->cr1 & 0x00800000)
2801 TMR_clk = cpc->sysclk; /* Should have a separate clock */
2802 else
2803 TMR_clk = CPU_clk;
2804 PLB_clk = CPU_clk / D0;
2805 SDRAM_clk = PLB_clk;
2806 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
2807 OPB_clk = PLB_clk / D0;
2808 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
2809 EXT_clk = PLB_clk / D0;
2810 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
2811 UART_clk = CPU_clk / D0;
2812 /* Setup CPU clocks */
2813 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
2814 /* Setup time-base clock */
2815 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
2816 /* Setup PLB clock */
2817 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
2818 /* Setup SDRAM clock */
2819 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
2820 /* Setup OPB clock */
2821 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
2822 /* Setup external clock */
2823 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
2824 /* Setup UART clock */
2825 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
2826 }
2827
2828 static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
2829 {
2830 ppc405cr_cpc_t *cpc;
2831 target_ulong ret;
2832
2833 cpc = opaque;
2834 switch (dcrn) {
2835 case PPC405CR_CPC0_PLLMR:
2836 ret = cpc->pllmr;
2837 break;
2838 case PPC405CR_CPC0_CR0:
2839 ret = cpc->cr0;
2840 break;
2841 case PPC405CR_CPC0_CR1:
2842 ret = cpc->cr1;
2843 break;
2844 case PPC405CR_CPC0_PSR:
2845 ret = cpc->psr;
2846 break;
2847 case PPC405CR_CPC0_JTAGID:
2848 ret = cpc->jtagid;
2849 break;
2850 case PPC405CR_CPC0_ER:
2851 ret = cpc->er;
2852 break;
2853 case PPC405CR_CPC0_FR:
2854 ret = cpc->fr;
2855 break;
2856 case PPC405CR_CPC0_SR:
2857 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
2858 break;
2859 default:
2860 /* Avoid gcc warning */
2861 ret = 0;
2862 break;
2863 }
2864
2865 return ret;
2866 }
2867
2868 static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
2869 {
2870 ppc405cr_cpc_t *cpc;
2871
2872 cpc = opaque;
2873 switch (dcrn) {
2874 case PPC405CR_CPC0_PLLMR:
2875 cpc->pllmr = val & 0xFFF77C3F;
2876 break;
2877 case PPC405CR_CPC0_CR0:
2878 cpc->cr0 = val & 0x0FFFFFFE;
2879 break;
2880 case PPC405CR_CPC0_CR1:
2881 cpc->cr1 = val & 0x00800000;
2882 break;
2883 case PPC405CR_CPC0_PSR:
2884 /* Read-only */
2885 break;
2886 case PPC405CR_CPC0_JTAGID:
2887 /* Read-only */
2888 break;
2889 case PPC405CR_CPC0_ER:
2890 cpc->er = val & 0xBFFC0000;
2891 break;
2892 case PPC405CR_CPC0_FR:
2893 cpc->fr = val & 0xBFFC0000;
2894 break;
2895 case PPC405CR_CPC0_SR:
2896 /* Read-only */
2897 break;
2898 }
2899 }
2900
2901 static void ppc405cr_cpc_reset (void *opaque)
2902 {
2903 ppc405cr_cpc_t *cpc;
2904 int D;
2905
2906 cpc = opaque;
2907 /* Compute PLLMR value from PSR settings */
2908 cpc->pllmr = 0x80000000;
2909 /* PFWD */
2910 switch ((cpc->psr >> 30) & 3) {
2911 case 0:
2912 /* Bypass */
2913 cpc->pllmr &= ~0x80000000;
2914 break;
2915 case 1:
2916 /* Divide by 3 */
2917 cpc->pllmr |= 5 << 16;
2918 break;
2919 case 2:
2920 /* Divide by 4 */
2921 cpc->pllmr |= 4 << 16;
2922 break;
2923 case 3:
2924 /* Divide by 6 */
2925 cpc->pllmr |= 2 << 16;
2926 break;
2927 }
2928 /* PFBD */
2929 D = (cpc->psr >> 28) & 3;
2930 cpc->pllmr |= (D + 1) << 20;
2931 /* PT */
2932 D = (cpc->psr >> 25) & 7;
2933 switch (D) {
2934 case 0x2:
2935 cpc->pllmr |= 0x13;
2936 break;
2937 case 0x4:
2938 cpc->pllmr |= 0x15;
2939 break;
2940 case 0x5:
2941 cpc->pllmr |= 0x16;
2942 break;
2943 default:
2944 break;
2945 }
2946 /* PDC */
2947 D = (cpc->psr >> 23) & 3;
2948 cpc->pllmr |= D << 26;
2949 /* ODP */
2950 D = (cpc->psr >> 21) & 3;
2951 cpc->pllmr |= D << 10;
2952 /* EBPD */
2953 D = (cpc->psr >> 17) & 3;
2954 cpc->pllmr |= D << 24;
2955 cpc->cr0 = 0x0000003C;
2956 cpc->cr1 = 0x2B0D8800;
2957 cpc->er = 0x00000000;
2958 cpc->fr = 0x00000000;
2959 ppc405cr_clk_setup(cpc);
2960 }
2961
2962 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2963 {
2964 int D;
2965
2966 /* XXX: this should be read from IO pins */
2967 cpc->psr = 0x00000000; /* 8 bits ROM */
2968 /* PFWD */
2969 D = 0x2; /* Divide by 4 */
2970 cpc->psr |= D << 30;
2971 /* PFBD */
2972 D = 0x1; /* Divide by 2 */
2973 cpc->psr |= D << 28;
2974 /* PDC */
2975 D = 0x1; /* Divide by 2 */
2976 cpc->psr |= D << 23;
2977 /* PT */
2978 D = 0x5; /* M = 16 */
2979 cpc->psr |= D << 25;
2980 /* ODP */
2981 D = 0x1; /* Divide by 2 */
2982 cpc->psr |= D << 21;
2983 /* EBDP */
2984 D = 0x2; /* Divide by 4 */
2985 cpc->psr |= D << 17;
2986 }
2987
2988 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2989 uint32_t sysclk)
2990 {
2991 ppc405cr_cpc_t *cpc;
2992
2993 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2994 if (cpc != NULL) {
2995 memcpy(cpc->clk_setup, clk_setup,
2996 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2997 cpc->sysclk = sysclk;
2998 cpc->jtagid = 0x42051049;
2999 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
3000 &dcr_read_crcpc, &dcr_write_crcpc);
3001 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
3002 &dcr_read_crcpc, &dcr_write_crcpc);
3003 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
3004 &dcr_read_crcpc, &dcr_write_crcpc);
3005 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
3006 &dcr_read_crcpc, &dcr_write_crcpc);
3007 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
3008 &dcr_read_crcpc, &dcr_write_crcpc);
3009 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
3010 &dcr_read_crcpc, &dcr_write_crcpc);
3011 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
3012 &dcr_read_crcpc, &dcr_write_crcpc);
3013 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
3014 &dcr_read_crcpc, &dcr_write_crcpc);
3015 ppc405cr_clk_init(cpc);
3016 qemu_register_reset(ppc405cr_cpc_reset, cpc);
3017 ppc405cr_cpc_reset(cpc);
3018 }
3019 }
3020
3021 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
3022 target_phys_addr_t ram_sizes[4],
3023 uint32_t sysclk, qemu_irq **picp,
3024 ram_addr_t *offsetp, int do_init)
3025 {
3026 clk_setup_t clk_setup[PPC405CR_CLK_NB];
3027 qemu_irq dma_irqs[4];
3028 CPUState *env;
3029 ppc4xx_mmio_t *mmio;
3030 qemu_irq *pic, *irqs;
3031 ram_addr_t offset;
3032 int i;
3033
3034 memset(clk_setup, 0, sizeof(clk_setup));
3035 env = ppc405_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
3036 &clk_setup[PPC405CR_TMR_CLK], sysclk);
3037 /* Memory mapped devices registers */
3038 mmio = ppc4xx_mmio_init(env, 0xEF600000);
3039 /* PLB arbitrer */
3040 ppc4xx_plb_init(env);
3041 /* PLB to OPB bridge */
3042 ppc4xx_pob_init(env);
3043 /* OBP arbitrer */
3044 ppc4xx_opba_init(env, mmio, 0x600);
3045 /* Universal interrupt controller */
3046 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
3047 irqs[PPCUIC_OUTPUT_INT] =
3048 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_INT];
3049 irqs[PPCUIC_OUTPUT_CINT] =
3050 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_CINT];
3051 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
3052 *picp = pic;
3053 /* SDRAM controller */
3054 ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
3055 offset = 0;
3056 for (i = 0; i < 4; i++)
3057 offset += ram_sizes[i];
3058 /* External bus controller */
3059 ppc405_ebc_init(env);
3060 /* DMA controller */
3061 dma_irqs[0] = pic[26];
3062 dma_irqs[1] = pic[25];
3063 dma_irqs[2] = pic[24];
3064 dma_irqs[3] = pic[23];
3065 ppc405_dma_init(env, dma_irqs);
3066 /* Serial ports */
3067 if (serial_hds[0] != NULL) {
3068 ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
3069 }
3070 if (serial_hds[1] != NULL) {
3071 ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
3072 }
3073 /* IIC controller */
3074 ppc405_i2c_init(env, mmio, 0x500, pic[29]);
3075 /* GPIO */
3076 ppc405_gpio_init(env, mmio, 0x700);
3077 /* CPU control */
3078 ppc405cr_cpc_init(env, clk_setup, sysclk);
3079 *offsetp = offset;
3080
3081 return env;
3082 }
3083
3084 /*****************************************************************************/
3085 /* PowerPC 405EP */
3086 /* CPU control */
3087 enum {
3088 PPC405EP_CPC0_PLLMR0 = 0x0F0,
3089 PPC405EP_CPC0_BOOT = 0x0F1,
3090 PPC405EP_CPC0_EPCTL = 0x0F3,
3091 PPC405EP_CPC0_PLLMR1 = 0x0F4,
3092 PPC405EP_CPC0_UCR = 0x0F5,
3093 PPC405EP_CPC0_SRR = 0x0F6,
3094 PPC405EP_CPC0_JTAGID = 0x0F7,
3095 PPC405EP_CPC0_PCI = 0x0F9,
3096 #if 0
3097 PPC405EP_CPC0_ER = xxx,
3098 PPC405EP_CPC0_FR = xxx,
3099 PPC405EP_CPC0_SR = xxx,
3100 #endif
3101 };
3102
3103 enum {
3104 PPC405EP_CPU_CLK = 0,
3105 PPC405EP_PLB_CLK = 1,
3106 PPC405EP_OPB_CLK = 2,
3107 PPC405EP_EBC_CLK = 3,
3108 PPC405EP_MAL_CLK = 4,
3109 PPC405EP_PCI_CLK = 5,
3110 PPC405EP_UART0_CLK = 6,
3111 PPC405EP_UART1_CLK = 7,
3112 PPC405EP_CLK_NB = 8,
3113 };
3114
3115 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
3116 struct ppc405ep_cpc_t {
3117 uint32_t sysclk;
3118 clk_setup_t clk_setup[PPC405EP_CLK_NB];
3119 uint32_t boot;
3120 uint32_t epctl;
3121 uint32_t pllmr[2];
3122 uint32_t ucr;
3123 uint32_t srr;
3124 uint32_t jtagid;
3125 uint32_t pci;
3126 /* Clock and power management */
3127 uint32_t er;
3128 uint32_t fr;
3129 uint32_t sr;
3130 };
3131
3132 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
3133 {
3134 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
3135 uint32_t UART0_clk, UART1_clk;
3136 uint64_t VCO_out, PLL_out;
3137 int M, D;
3138
3139 VCO_out = 0;
3140 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
3141 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
3142 // printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
3143 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
3144 // printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
3145 VCO_out = cpc->sysclk * M * D;
3146 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
3147 /* Error - unlock the PLL */
3148 printf("VCO out of range %" PRIu64 "\n", VCO_out);
3149 #if 0
3150 cpc->pllmr[1] &= ~0x80000000;
3151 goto pll_bypass;
3152 #endif
3153 }
3154 PLL_out = VCO_out / D;
3155 /* Pretend the PLL is locked */
3156 cpc->boot |= 0x00000001;
3157 } else {
3158 #if 0
3159 pll_bypass:
3160 #endif
3161 PLL_out = cpc->sysclk;
3162 if (cpc->pllmr[1] & 0x40000000) {
3163 /* Pretend the PLL is not locked */
3164 cpc->boot &= ~0x00000001;
3165 }
3166 }
3167 /* Now, compute all other clocks */
3168 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
3169 #ifdef DEBUG_CLOCKS
3170 // printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
3171 #endif
3172 CPU_clk = PLL_out / D;
3173 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
3174 #ifdef DEBUG_CLOCKS
3175 // printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
3176 #endif
3177 PLB_clk = CPU_clk / D;
3178 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
3179 #ifdef DEBUG_CLOCKS
3180 // printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
3181 #endif
3182 OPB_clk = PLB_clk / D;
3183 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
3184 #ifdef DEBUG_CLOCKS
3185 // printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
3186 #endif
3187 EBC_clk = PLB_clk / D;
3188 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
3189 #ifdef DEBUG_CLOCKS
3190 // printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
3191 #endif
3192 MAL_clk = PLB_clk / D;
3193 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
3194 #ifdef DEBUG_CLOCKS
3195 // printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D);
3196 #endif
3197 PCI_clk = PLB_clk / D;
3198 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
3199 #ifdef DEBUG_CLOCKS
3200 // printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D);
3201 #endif
3202 UART0_clk = PLL_out / D;
3203 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
3204 #ifdef DEBUG_CLOCKS
3205 // printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D);
3206 #endif
3207 UART1_clk = PLL_out / D;
3208 #ifdef DEBUG_CLOCKS
3209 printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64
3210 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
3211 printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n",
3212 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
3213 UART0_clk, UART1_clk);
3214 printf("CB %p opaque %p\n", cpc->clk_setup[PPC405EP_CPU_CLK].cb,
3215 cpc->clk_setup[PPC405EP_CPU_CLK].opaque);
3216 #endif
3217 /* Setup CPU clocks */
3218 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
3219 /* Setup PLB clock */
3220 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
3221 /* Setup OPB clock */
3222 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
3223 /* Setup external clock */
3224 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
3225 /* Setup MAL clock */
3226 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
3227 /* Setup PCI clock */
3228 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
3229 /* Setup UART0 clock */
3230 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
3231 /* Setup UART1 clock */
3232 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
3233 }
3234
3235 static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
3236 {
3237 ppc405ep_cpc_t *cpc;
3238 target_ulong ret;
3239
3240 cpc = opaque;
3241 switch (dcrn) {
3242 case PPC405EP_CPC0_BOOT:
3243 ret = cpc->boot;
3244 break;
3245 case PPC405EP_CPC0_EPCTL:
3246 ret = cpc->epctl;
3247 break;
3248 case PPC405EP_CPC0_PLLMR0:
3249 ret = cpc->pllmr[0];
3250 break;
3251 case PPC405EP_CPC0_PLLMR1:
3252 ret = cpc->pllmr[1];
3253 break;
3254 case PPC405EP_CPC0_UCR:
3255 ret = cpc->ucr;
3256 break;
3257 case PPC405EP_CPC0_SRR:
3258 ret = cpc->srr;
3259 break;
3260 case PPC405EP_CPC0_JTAGID:
3261 ret = cpc->jtagid;
3262 break;
3263 case PPC405EP_CPC0_PCI:
3264 ret = cpc->pci;
3265 break;
3266 default:
3267 /* Avoid gcc warning */
3268 ret = 0;
3269 break;
3270 }
3271
3272 return ret;
3273 }
3274
3275 static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
3276 {
3277 ppc405ep_cpc_t *cpc;
3278
3279 cpc = opaque;
3280 switch (dcrn) {
3281 case PPC405EP_CPC0_BOOT:
3282 /* Read-only register */
3283 break;
3284 case PPC405EP_CPC0_EPCTL:
3285 /* Don't care for now */
3286 cpc->epctl = val & 0xC00000F3;
3287 break;
3288 case PPC405EP_CPC0_PLLMR0:
3289 cpc->pllmr[0] = val & 0x00633333;
3290 ppc405ep_compute_clocks(cpc);
3291 break;
3292 case PPC405EP_CPC0_PLLMR1:
3293 cpc->pllmr[1] = val & 0xC0F73FFF;
3294 ppc405ep_compute_clocks(cpc);
3295 break;
3296 case PPC405EP_CPC0_UCR:
3297 /* UART control - don't care for now */
3298 cpc->ucr = val & 0x003F7F7F;
3299 break;
3300 case PPC405EP_CPC0_SRR:
3301 cpc->srr = val;
3302 break;
3303 case PPC405EP_CPC0_JTAGID:
3304 /* Read-only */
3305 break;
3306 case PPC405EP_CPC0_PCI:
3307 cpc->pci = val;
3308 break;
3309 }
3310 }
3311
3312 static void ppc405ep_cpc_reset (void *opaque)
3313 {
3314 ppc405ep_cpc_t *cpc = opaque;
3315
3316 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
3317 cpc->epctl = 0x00000000;
3318 cpc->pllmr[0] = 0x00011010;
3319 cpc->pllmr[1] = 0x40000000;
3320 cpc->ucr = 0x00000000;
3321 cpc->srr = 0x00040000;
3322 cpc->pci = 0x00000000;
3323 cpc->er = 0x00000000;
3324 cpc->fr = 0x00000000;
3325 cpc->sr = 0x00000000;
3326 ppc405ep_compute_clocks(cpc);
3327 }
3328
3329 /* XXX: sysclk should be between 25 and 100 MHz */
3330 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
3331 uint32_t sysclk)
3332 {
3333 ppc405ep_cpc_t *cpc;
3334
3335 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
3336 if (cpc != NULL) {
3337 memcpy(cpc->clk_setup, clk_setup,
3338 PPC405EP_CLK_NB * sizeof(clk_setup_t));
3339 cpc->jtagid = 0x20267049;
3340 cpc->sysclk = sysclk;
3341 ppc405ep_cpc_reset(cpc);
3342 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
3343 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
3344 &dcr_read_epcpc, &dcr_write_epcpc);
3345 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
3346 &dcr_read_epcpc, &dcr_write_epcpc);
3347 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
3348 &dcr_read_epcpc, &dcr_write_epcpc);
3349 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
3350 &dcr_read_epcpc, &dcr_write_epcpc);
3351 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
3352 &dcr_read_epcpc, &dcr_write_epcpc);
3353 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
3354 &dcr_read_epcpc, &dcr_write_epcpc);
3355 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
3356 &dcr_read_epcpc, &dcr_write_epcpc);
3357 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
3358 &dcr_read_epcpc, &dcr_write_epcpc);
3359 #if 0
3360 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
3361 &dcr_read_epcpc, &dcr_write_epcpc);
3362 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
3363 &dcr_read_epcpc, &dcr_write_epcpc);
3364 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
3365 &dcr_read_epcpc, &dcr_write_epcpc);
3366 #endif
3367 }
3368 }
3369
3370 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
3371 target_phys_addr_t ram_sizes[2],
3372 uint32_t sysclk, qemu_irq **picp,
3373 ram_addr_t *offsetp, int do_init)
3374 {
3375 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
3376 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
3377 CPUState *env;
3378 ppc4xx_mmio_t *mmio;
3379 qemu_irq *pic, *irqs;
3380 ram_addr_t offset;
3381 int i;
3382
3383 memset(clk_setup, 0, sizeof(clk_setup));
3384 /* init CPUs */
3385 env = ppc405_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
3386 &tlb_clk_setup, sysclk);
3387 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
3388 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
3389 /* Internal devices init */
3390 /* Memory mapped devices registers */
3391 mmio = ppc4xx_mmio_init(env, 0xEF600000);
3392 /* PLB arbitrer */
3393 ppc4xx_plb_init(env);
3394 /* PLB to OPB bridge */
3395 ppc4xx_pob_init(env);
3396 /* OBP arbitrer */
3397 ppc4xx_opba_init(env, mmio, 0x600);
3398 /* Universal interrupt controller */
3399 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
3400 irqs[PPCUIC_OUTPUT_INT] =
3401 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_INT];
3402 irqs[PPCUIC_OUTPUT_CINT] =
3403 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_CINT];
3404 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
3405 *picp = pic;
3406 /* SDRAM controller */
3407 ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init);
3408 offset = 0;
3409 for (i = 0; i < 2; i++)
3410 offset += ram_sizes[i];
3411 /* External bus controller */
3412 ppc405_ebc_init(env);
3413 /* DMA controller */
3414 dma_irqs[0] = pic[26];
3415 dma_irqs[1] = pic[25];
3416 dma_irqs[2] = pic[24];
3417 dma_irqs[3] = pic[23];
3418 ppc405_dma_init(env, dma_irqs);
3419 /* IIC controller */
3420 ppc405_i2c_init(env, mmio, 0x500, pic[29]);
3421 /* GPIO */
3422 ppc405_gpio_init(env, mmio, 0x700);
3423 /* Serial ports */
3424 if (serial_hds[0] != NULL) {
3425 ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
3426 }
3427 if (serial_hds[1] != NULL) {
3428 ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
3429 }
3430 /* OCM */
3431 ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]);
3432 offset += 4096;
3433 /* GPT */
3434 gpt_irqs[0] = pic[12];
3435 gpt_irqs[1] = pic[11];
3436 gpt_irqs[2] = pic[10];
3437 gpt_irqs[3] = pic[9];
3438 gpt_irqs[4] = pic[8];
3439 ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
3440 /* PCI */
3441 /* Uses pic[28], pic[15], pic[13] */
3442 /* MAL */
3443 mal_irqs[0] = pic[20];
3444 mal_irqs[1] = pic[19];
3445 mal_irqs[2] = pic[18];
3446 mal_irqs[3] = pic[17];
3447 ppc405_mal_init(env, mal_irqs);
3448 /* Ethernet */
3449 /* Uses pic[22], pic[16], pic[14] */
3450 /* CPU control */
3451 ppc405ep_cpc_init(env, clk_setup, sysclk);
3452 *offsetp = offset;
3453
3454 return env;
3455 }
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