hw/ppc405.h

   1 /*
   2  * QEMU PowerPC 405 shared definitions
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #if !defined(PPC_405_H)
  26 #define PPC_405_H
  27
  28 /* Bootinfo as set-up by u-boot */
  29 typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
  30 struct ppc4xx_bd_info_t {
  31     uint32_t bi_memstart;
  32     uint32_t bi_memsize;
  33     uint32_t bi_flashstart;
  34     uint32_t bi_flashsize;
  35     uint32_t bi_flashoffset; /* 0x10 */
  36     uint32_t bi_sramstart;
  37     uint32_t bi_sramsize;
  38     uint32_t bi_bootflags;
  39     uint32_t bi_ipaddr; /* 0x20 */
  40     uint8_t  bi_enetaddr[6];
  41     uint16_t bi_ethspeed;
  42     uint32_t bi_intfreq;
  43     uint32_t bi_busfreq; /* 0x30 */
  44     uint32_t bi_baudrate;
  45     uint8_t  bi_s_version[4];
  46     uint8_t  bi_r_version[32];
  47     uint32_t bi_procfreq;
  48     uint32_t bi_plb_busfreq;
  49     uint32_t bi_pci_busfreq;
  50     uint8_t  bi_pci_enetaddr[6];
  51     uint32_t bi_pci_enetaddr2[6];
  52     uint32_t bi_opbfreq;
  53     uint32_t bi_iic_fast[2];
  54 };
  55
  56 /* PowerPC 405 core */
  57 CPUState *ppc405_init (const unsigned char *cpu_model,
  58                        clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
  59                        uint32_t sysclk);
  60 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd);
  61
  62 /* */
  63 typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
  64 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
  65                           target_phys_addr_t offset, uint32_t len,
  66                           CPUReadMemoryFunc **mem_read,
  67                           CPUWriteMemoryFunc **mem_write, void *opaque);
  68 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base);
  69 /* PowerPC 4xx peripheral local bus arbitrer */
  70 void ppc4xx_plb_init (CPUState *env);
  71 /* PLB to OPB bridge */
  72 void ppc4xx_pob_init (CPUState *env);
  73 /* OPB arbitrer */
  74 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
  75                        target_phys_addr_t offset);
  76 /* PowerPC 4xx universal interrupt controller */
  77 enum {
  78     PPCUIC_OUTPUT_INT = 0,
  79     PPCUIC_OUTPUT_CINT = 1,
  80     PPCUIC_OUTPUT_NB,
  81 };
  82 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
  83                        uint32_t dcr_base, int has_ssr, int has_vr);
  84 /* SDRAM controller */
  85 void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
  86                         target_phys_addr_t *ram_bases,
  87                         target_phys_addr_t *ram_sizes,
  88                         int do_init);
  89 /* Peripheral controller */
  90 void ppc405_ebc_init (CPUState *env);
  91 /* DMA controller */
  92 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]);
  93 /* GPIO */
  94 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
  95                        target_phys_addr_t offset);
  96 /* Serial ports */
  97 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
  98                          target_phys_addr_t offset, qemu_irq irq,
  99                          CharDriverState *chr);
 100 /* On Chip Memory */
 101 void ppc405_ocm_init (CPUState *env, unsigned long offset);
 102 /* I2C controller */
 103 void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
 104                       target_phys_addr_t offset, qemu_irq irq);
 105 /* General purpose timers */
 106 void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
 107                       target_phys_addr_t offset, qemu_irq irq[5]);
 108 /* Memory access layer */
 109 void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]);
 110 /* PowerPC 405 microcontrollers */
 111 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
 112                          target_phys_addr_t ram_sizes[4],
 113                          uint32_t sysclk, qemu_irq **picp,
 114                          ram_addr_t *offsetp, int do_init);
 115 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
 116                          target_phys_addr_t ram_sizes[2],
 117                          uint32_t sysclk, qemu_irq **picp,
 118                          ram_addr_t *offsetp, int do_init);
 119 /* IBM STBxxx microcontrollers */
 120 CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
 121                            target_phys_addr_t ram_sizes[2],
 122                            uint32_t sysclk, qemu_irq **picp,
 123                            ram_addr_t *offsetp);
 124
 125 #endif /* !defined(PPC_405_H) */