pxb: cleanup
[qemu/cris-port.git] / target-arm / cpu64.c
blobfa5eda2cd158d898e50220efce1d8f2d884fd4cd
1 /*
2 * QEMU AArch64 CPU
4 * Copyright (c) 2013 Linaro Ltd
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "qemu-common.h"
24 #if !defined(CONFIG_USER_ONLY)
25 #include "hw/loader.h"
26 #endif
27 #include "hw/arm/arm.h"
28 #include "sysemu/sysemu.h"
29 #include "sysemu/kvm.h"
31 static inline void set_feature(CPUARMState *env, int feature)
33 env->features |= 1ULL << feature;
36 static inline void unset_feature(CPUARMState *env, int feature)
38 env->features &= ~(1ULL << feature);
41 #ifndef CONFIG_USER_ONLY
42 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
44 /* Number of processors is in [25:24]; otherwise we RAZ */
45 return (smp_cpus - 1) << 24;
47 #endif
49 static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
50 #ifndef CONFIG_USER_ONLY
51 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
52 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
53 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
54 .writefn = arm_cp_write_ignore },
55 { .name = "L2CTLR",
56 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
57 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
58 .writefn = arm_cp_write_ignore },
59 #endif
60 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
61 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
62 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
63 { .name = "L2ECTLR",
64 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
65 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
66 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
67 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
68 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
69 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
70 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
71 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
72 { .name = "CPUACTLR",
73 .cp = 15, .opc1 = 0, .crm = 15,
74 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
75 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
76 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
77 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
78 { .name = "CPUECTLR",
79 .cp = 15, .opc1 = 1, .crm = 15,
80 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
81 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
82 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
83 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
84 { .name = "CPUMERRSR",
85 .cp = 15, .opc1 = 2, .crm = 15,
86 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
87 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
88 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
89 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
90 { .name = "L2MERRSR",
91 .cp = 15, .opc1 = 3, .crm = 15,
92 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
93 REGINFO_SENTINEL
96 static void aarch64_a57_initfn(Object *obj)
98 ARMCPU *cpu = ARM_CPU(obj);
100 cpu->dtb_compatible = "arm,cortex-a57";
101 set_feature(&cpu->env, ARM_FEATURE_V8);
102 set_feature(&cpu->env, ARM_FEATURE_VFP4);
103 set_feature(&cpu->env, ARM_FEATURE_NEON);
104 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
105 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
106 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
107 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
108 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
109 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
110 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
111 set_feature(&cpu->env, ARM_FEATURE_CRC);
112 set_feature(&cpu->env, ARM_FEATURE_EL3);
113 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
114 cpu->midr = 0x411fd070;
115 cpu->revidr = 0x00000000;
116 cpu->reset_fpsid = 0x41034070;
117 cpu->mvfr0 = 0x10110222;
118 cpu->mvfr1 = 0x12111111;
119 cpu->mvfr2 = 0x00000043;
120 cpu->ctr = 0x8444c004;
121 cpu->reset_sctlr = 0x00c50838;
122 cpu->id_pfr0 = 0x00000131;
123 cpu->id_pfr1 = 0x00011011;
124 cpu->id_dfr0 = 0x03010066;
125 cpu->id_afr0 = 0x00000000;
126 cpu->id_mmfr0 = 0x10101105;
127 cpu->id_mmfr1 = 0x40000000;
128 cpu->id_mmfr2 = 0x01260000;
129 cpu->id_mmfr3 = 0x02102211;
130 cpu->id_isar0 = 0x02101110;
131 cpu->id_isar1 = 0x13112111;
132 cpu->id_isar2 = 0x21232042;
133 cpu->id_isar3 = 0x01112131;
134 cpu->id_isar4 = 0x00011142;
135 cpu->id_isar5 = 0x00011121;
136 cpu->id_aa64pfr0 = 0x00002222;
137 cpu->id_aa64dfr0 = 0x10305106;
138 cpu->pmceid0 = 0x00000000;
139 cpu->pmceid1 = 0x00000000;
140 cpu->id_aa64isar0 = 0x00011120;
141 cpu->id_aa64mmfr0 = 0x00001124;
142 cpu->dbgdidr = 0x3516d000;
143 cpu->clidr = 0x0a200023;
144 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
145 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
146 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
147 cpu->dcz_blocksize = 4; /* 64 bytes */
148 define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
151 static void aarch64_a53_initfn(Object *obj)
153 ARMCPU *cpu = ARM_CPU(obj);
155 cpu->dtb_compatible = "arm,cortex-a53";
156 set_feature(&cpu->env, ARM_FEATURE_V8);
157 set_feature(&cpu->env, ARM_FEATURE_VFP4);
158 set_feature(&cpu->env, ARM_FEATURE_NEON);
159 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
160 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
161 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
162 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
163 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
164 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
165 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
166 set_feature(&cpu->env, ARM_FEATURE_CRC);
167 set_feature(&cpu->env, ARM_FEATURE_EL3);
168 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
169 cpu->midr = 0x410fd034;
170 cpu->revidr = 0x00000000;
171 cpu->reset_fpsid = 0x41034070;
172 cpu->mvfr0 = 0x10110222;
173 cpu->mvfr1 = 0x12111111;
174 cpu->mvfr2 = 0x00000043;
175 cpu->ctr = 0x84448004; /* L1Ip = VIPT */
176 cpu->reset_sctlr = 0x00c50838;
177 cpu->id_pfr0 = 0x00000131;
178 cpu->id_pfr1 = 0x00011011;
179 cpu->id_dfr0 = 0x03010066;
180 cpu->id_afr0 = 0x00000000;
181 cpu->id_mmfr0 = 0x10101105;
182 cpu->id_mmfr1 = 0x40000000;
183 cpu->id_mmfr2 = 0x01260000;
184 cpu->id_mmfr3 = 0x02102211;
185 cpu->id_isar0 = 0x02101110;
186 cpu->id_isar1 = 0x13112111;
187 cpu->id_isar2 = 0x21232042;
188 cpu->id_isar3 = 0x01112131;
189 cpu->id_isar4 = 0x00011142;
190 cpu->id_isar5 = 0x00011121;
191 cpu->id_aa64pfr0 = 0x00002222;
192 cpu->id_aa64dfr0 = 0x10305106;
193 cpu->id_aa64isar0 = 0x00011120;
194 cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
195 cpu->dbgdidr = 0x3516d000;
196 cpu->clidr = 0x0a200023;
197 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
198 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
199 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
200 cpu->dcz_blocksize = 4; /* 64 bytes */
201 define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
204 #ifdef CONFIG_USER_ONLY
205 static void aarch64_any_initfn(Object *obj)
207 ARMCPU *cpu = ARM_CPU(obj);
209 set_feature(&cpu->env, ARM_FEATURE_V8);
210 set_feature(&cpu->env, ARM_FEATURE_VFP4);
211 set_feature(&cpu->env, ARM_FEATURE_NEON);
212 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
213 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
214 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
215 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
216 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
217 set_feature(&cpu->env, ARM_FEATURE_CRC);
218 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
219 cpu->dcz_blocksize = 7; /* 512 bytes */
221 #endif
223 typedef struct ARMCPUInfo {
224 const char *name;
225 void (*initfn)(Object *obj);
226 void (*class_init)(ObjectClass *oc, void *data);
227 } ARMCPUInfo;
229 static const ARMCPUInfo aarch64_cpus[] = {
230 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
231 { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
232 #ifdef CONFIG_USER_ONLY
233 { .name = "any", .initfn = aarch64_any_initfn },
234 #endif
235 { .name = NULL }
238 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
240 ARMCPU *cpu = ARM_CPU(obj);
242 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
245 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
247 ARMCPU *cpu = ARM_CPU(obj);
249 /* At this time, this property is only allowed if KVM is enabled. This
250 * restriction allows us to avoid fixing up functionality that assumes a
251 * uniform execution state like do_interrupt.
253 if (!kvm_enabled()) {
254 error_setg(errp, "'aarch64' feature cannot be disabled "
255 "unless KVM is enabled");
256 return;
259 if (value == false) {
260 unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
261 } else {
262 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
266 static void aarch64_cpu_initfn(Object *obj)
268 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
269 aarch64_cpu_set_aarch64, NULL);
270 object_property_set_description(obj, "aarch64",
271 "Set on/off to enable/disable aarch64 "
272 "execution state ",
273 NULL);
276 static void aarch64_cpu_finalizefn(Object *obj)
280 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
282 ARMCPU *cpu = ARM_CPU(cs);
283 /* It's OK to look at env for the current mode here, because it's
284 * never possible for an AArch64 TB to chain to an AArch32 TB.
285 * (Otherwise we would need to use synchronize_from_tb instead.)
287 if (is_a64(&cpu->env)) {
288 cpu->env.pc = value;
289 } else {
290 cpu->env.regs[15] = value;
294 static gchar *aarch64_gdb_arch_name(CPUState *cs)
296 return g_strdup("aarch64");
299 static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
301 CPUClass *cc = CPU_CLASS(oc);
303 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
304 cc->set_pc = aarch64_cpu_set_pc;
305 cc->gdb_read_register = aarch64_cpu_gdb_read_register;
306 cc->gdb_write_register = aarch64_cpu_gdb_write_register;
307 cc->gdb_num_core_regs = 34;
308 cc->gdb_core_xml_file = "aarch64-core.xml";
309 cc->gdb_arch_name = aarch64_gdb_arch_name;
312 static void aarch64_cpu_register(const ARMCPUInfo *info)
314 TypeInfo type_info = {
315 .parent = TYPE_AARCH64_CPU,
316 .instance_size = sizeof(ARMCPU),
317 .instance_init = info->initfn,
318 .class_size = sizeof(ARMCPUClass),
319 .class_init = info->class_init,
322 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
323 type_register(&type_info);
324 g_free((void *)type_info.name);
327 static const TypeInfo aarch64_cpu_type_info = {
328 .name = TYPE_AARCH64_CPU,
329 .parent = TYPE_ARM_CPU,
330 .instance_size = sizeof(ARMCPU),
331 .instance_init = aarch64_cpu_initfn,
332 .instance_finalize = aarch64_cpu_finalizefn,
333 .abstract = true,
334 .class_size = sizeof(AArch64CPUClass),
335 .class_init = aarch64_cpu_class_init,
338 static void aarch64_cpu_register_types(void)
340 const ARMCPUInfo *info = aarch64_cpus;
342 type_register_static(&aarch64_cpu_type_info);
344 while (info->name) {
345 aarch64_cpu_register(info);
346 info++;
350 type_init(aarch64_cpu_register_types)