4 * Generate helpers used by TCG for qemu_ld/st ops and code load
7 * Included from target op helpers and exec.c.
9 * Copyright (c) 2003 Fabrice Bellard
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/timer.h"
25 #include "exec/address-spaces.h"
26 #include "exec/memory.h"
28 #define DATA_SIZE (1 << SHIFT)
33 #define SDATA_TYPE int64_t
34 #define DATA_TYPE uint64_t
38 #define SDATA_TYPE int32_t
39 #define DATA_TYPE uint32_t
43 #define SDATA_TYPE int16_t
44 #define DATA_TYPE uint16_t
48 #define SDATA_TYPE int8_t
49 #define DATA_TYPE uint8_t
51 #error unsupported data size
55 /* For the benefit of TCG generated code, we want to avoid the complication
56 of ABI-specific return type promotion and always return a value extended
57 to the register size of the host. This is tcg_target_long, except in the
58 case of a 32-bit host and 64-bit data, and for that we always have
59 uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
60 #if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
61 # define WORD_TYPE DATA_TYPE
62 # define USUFFIX SUFFIX
64 # define WORD_TYPE tcg_target_ulong
65 # define USUFFIX glue(u, SUFFIX)
66 # define SSUFFIX glue(s, SUFFIX)
69 #ifdef SOFTMMU_CODE_ACCESS
70 #define READ_ACCESS_TYPE MMU_INST_FETCH
71 #define ADDR_READ addr_code
73 #define READ_ACCESS_TYPE MMU_DATA_LOAD
74 #define ADDR_READ addr_read
78 # define BSWAP(X) bswap64(X)
80 # define BSWAP(X) bswap32(X)
82 # define BSWAP(X) bswap16(X)
87 #ifdef TARGET_WORDS_BIGENDIAN
88 # define TGT_BE(X) (X)
89 # define TGT_LE(X) BSWAP(X)
91 # define TGT_BE(X) BSWAP(X)
92 # define TGT_LE(X) (X)
96 # define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
97 # define helper_be_ld_name helper_le_ld_name
98 # define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
99 # define helper_be_lds_name helper_le_lds_name
100 # define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
101 # define helper_be_st_name helper_le_st_name
103 # define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
104 # define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
105 # define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
106 # define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
107 # define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
108 # define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
111 #ifdef TARGET_WORDS_BIGENDIAN
112 # define helper_te_ld_name helper_be_ld_name
113 # define helper_te_st_name helper_be_st_name
115 # define helper_te_ld_name helper_le_ld_name
116 # define helper_te_st_name helper_le_st_name
119 #ifndef SOFTMMU_CODE_ACCESS
120 static inline DATA_TYPE
glue(io_read
, SUFFIX
)(CPUArchState
*env
,
121 CPUIOTLBEntry
*iotlbentry
,
126 CPUState
*cpu
= ENV_GET_CPU(env
);
127 hwaddr physaddr
= iotlbentry
->addr
;
128 MemoryRegion
*mr
= iotlb_to_region(cpu
, physaddr
, iotlbentry
->attrs
);
130 physaddr
= (physaddr
& TARGET_PAGE_MASK
) + addr
;
131 cpu
->mem_io_pc
= retaddr
;
132 if (mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !cpu
->can_do_io
) {
133 cpu_io_recompile(cpu
, retaddr
);
136 cpu
->mem_io_vaddr
= addr
;
137 memory_region_dispatch_read(mr
, physaddr
, &val
, 1 << SHIFT
,
143 WORD_TYPE
helper_le_ld_name(CPUArchState
*env
, target_ulong addr
,
144 TCGMemOpIdx oi
, uintptr_t retaddr
)
146 unsigned mmu_idx
= get_mmuidx(oi
);
147 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
148 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
149 int a_bits
= get_alignment_bits(get_memop(oi
));
153 /* Adjust the given return address. */
154 retaddr
-= GETPC_ADJ
;
156 if (a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)) != 0) {
157 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
161 /* If the TLB entry is for a different page, reload and try again. */
162 if ((addr
& TARGET_PAGE_MASK
)
163 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
164 if (!VICTIM_TLB_HIT(ADDR_READ
, addr
)) {
165 tlb_fill(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
168 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
171 /* Handle an IO access. */
172 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
173 CPUIOTLBEntry
*iotlbentry
;
174 if ((addr
& (DATA_SIZE
- 1)) != 0) {
175 goto do_unaligned_access
;
177 iotlbentry
= &env
->iotlb
[mmu_idx
][index
];
179 /* ??? Note that the io helpers always read data in the target
180 byte ordering. We should push the LE/BE request down into io. */
181 res
= glue(io_read
, SUFFIX
)(env
, iotlbentry
, addr
, retaddr
);
186 /* Handle slow unaligned access (it spans two pages or IO). */
188 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
189 >= TARGET_PAGE_SIZE
)) {
190 target_ulong addr1
, addr2
;
191 DATA_TYPE res1
, res2
;
194 addr1
= addr
& ~(DATA_SIZE
- 1);
195 addr2
= addr1
+ DATA_SIZE
;
196 /* Note the adjustment at the beginning of the function.
197 Undo that for the recursion. */
198 res1
= helper_le_ld_name(env
, addr1
, oi
, retaddr
+ GETPC_ADJ
);
199 res2
= helper_le_ld_name(env
, addr2
, oi
, retaddr
+ GETPC_ADJ
);
200 shift
= (addr
& (DATA_SIZE
- 1)) * 8;
202 /* Little-endian combine. */
203 res
= (res1
>> shift
) | (res2
<< ((DATA_SIZE
* 8) - shift
));
207 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
209 res
= glue(glue(ld
, LSUFFIX
), _p
)((uint8_t *)haddr
);
211 res
= glue(glue(ld
, LSUFFIX
), _le_p
)((uint8_t *)haddr
);
217 WORD_TYPE
helper_be_ld_name(CPUArchState
*env
, target_ulong addr
,
218 TCGMemOpIdx oi
, uintptr_t retaddr
)
220 unsigned mmu_idx
= get_mmuidx(oi
);
221 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
222 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
223 int a_bits
= get_alignment_bits(get_memop(oi
));
227 /* Adjust the given return address. */
228 retaddr
-= GETPC_ADJ
;
230 if (a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)) != 0) {
231 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
235 /* If the TLB entry is for a different page, reload and try again. */
236 if ((addr
& TARGET_PAGE_MASK
)
237 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
238 if (!VICTIM_TLB_HIT(ADDR_READ
, addr
)) {
239 tlb_fill(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
242 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
245 /* Handle an IO access. */
246 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
247 CPUIOTLBEntry
*iotlbentry
;
248 if ((addr
& (DATA_SIZE
- 1)) != 0) {
249 goto do_unaligned_access
;
251 iotlbentry
= &env
->iotlb
[mmu_idx
][index
];
253 /* ??? Note that the io helpers always read data in the target
254 byte ordering. We should push the LE/BE request down into io. */
255 res
= glue(io_read
, SUFFIX
)(env
, iotlbentry
, addr
, retaddr
);
260 /* Handle slow unaligned access (it spans two pages or IO). */
262 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
263 >= TARGET_PAGE_SIZE
)) {
264 target_ulong addr1
, addr2
;
265 DATA_TYPE res1
, res2
;
268 addr1
= addr
& ~(DATA_SIZE
- 1);
269 addr2
= addr1
+ DATA_SIZE
;
270 /* Note the adjustment at the beginning of the function.
271 Undo that for the recursion. */
272 res1
= helper_be_ld_name(env
, addr1
, oi
, retaddr
+ GETPC_ADJ
);
273 res2
= helper_be_ld_name(env
, addr2
, oi
, retaddr
+ GETPC_ADJ
);
274 shift
= (addr
& (DATA_SIZE
- 1)) * 8;
276 /* Big-endian combine. */
277 res
= (res1
<< shift
) | (res2
>> ((DATA_SIZE
* 8) - shift
));
281 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
282 res
= glue(glue(ld
, LSUFFIX
), _be_p
)((uint8_t *)haddr
);
285 #endif /* DATA_SIZE > 1 */
287 #ifndef SOFTMMU_CODE_ACCESS
289 /* Provide signed versions of the load routines as well. We can of course
290 avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
291 #if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
292 WORD_TYPE
helper_le_lds_name(CPUArchState
*env
, target_ulong addr
,
293 TCGMemOpIdx oi
, uintptr_t retaddr
)
295 return (SDATA_TYPE
)helper_le_ld_name(env
, addr
, oi
, retaddr
);
299 WORD_TYPE
helper_be_lds_name(CPUArchState
*env
, target_ulong addr
,
300 TCGMemOpIdx oi
, uintptr_t retaddr
)
302 return (SDATA_TYPE
)helper_be_ld_name(env
, addr
, oi
, retaddr
);
307 static inline void glue(io_write
, SUFFIX
)(CPUArchState
*env
,
308 CPUIOTLBEntry
*iotlbentry
,
313 CPUState
*cpu
= ENV_GET_CPU(env
);
314 hwaddr physaddr
= iotlbentry
->addr
;
315 MemoryRegion
*mr
= iotlb_to_region(cpu
, physaddr
, iotlbentry
->attrs
);
317 physaddr
= (physaddr
& TARGET_PAGE_MASK
) + addr
;
318 if (mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !cpu
->can_do_io
) {
319 cpu_io_recompile(cpu
, retaddr
);
322 cpu
->mem_io_vaddr
= addr
;
323 cpu
->mem_io_pc
= retaddr
;
324 memory_region_dispatch_write(mr
, physaddr
, val
, 1 << SHIFT
,
328 void helper_le_st_name(CPUArchState
*env
, target_ulong addr
, DATA_TYPE val
,
329 TCGMemOpIdx oi
, uintptr_t retaddr
)
331 unsigned mmu_idx
= get_mmuidx(oi
);
332 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
333 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
334 int a_bits
= get_alignment_bits(get_memop(oi
));
337 /* Adjust the given return address. */
338 retaddr
-= GETPC_ADJ
;
340 if (a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)) != 0) {
341 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
,
345 /* If the TLB entry is for a different page, reload and try again. */
346 if ((addr
& TARGET_PAGE_MASK
)
347 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
348 if (!VICTIM_TLB_HIT(addr_write
, addr
)) {
349 tlb_fill(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
, mmu_idx
, retaddr
);
351 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
354 /* Handle an IO access. */
355 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
356 CPUIOTLBEntry
*iotlbentry
;
357 if ((addr
& (DATA_SIZE
- 1)) != 0) {
358 goto do_unaligned_access
;
360 iotlbentry
= &env
->iotlb
[mmu_idx
][index
];
362 /* ??? Note that the io helpers always read data in the target
363 byte ordering. We should push the LE/BE request down into io. */
365 glue(io_write
, SUFFIX
)(env
, iotlbentry
, val
, addr
, retaddr
);
369 /* Handle slow unaligned access (it spans two pages or IO). */
371 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
372 >= TARGET_PAGE_SIZE
)) {
374 target_ulong page2
, tlb_addr2
;
376 /* Ensure the second page is in the TLB. Note that the first page
377 is already guaranteed to be filled, and that the second page
378 cannot evict the first. */
379 page2
= (addr
+ DATA_SIZE
) & TARGET_PAGE_MASK
;
380 index2
= (page2
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
381 tlb_addr2
= env
->tlb_table
[mmu_idx
][index2
].addr_write
;
382 if (page2
!= (tlb_addr2
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))
383 && !VICTIM_TLB_HIT(addr_write
, page2
)) {
384 tlb_fill(ENV_GET_CPU(env
), page2
, MMU_DATA_STORE
,
388 /* XXX: not efficient, but simple. */
389 /* This loop must go in the forward direction to avoid issues
390 with self-modifying code in Windows 64-bit. */
391 for (i
= 0; i
< DATA_SIZE
; ++i
) {
392 /* Little-endian extract. */
393 uint8_t val8
= val
>> (i
* 8);
394 /* Note the adjustment at the beginning of the function.
395 Undo that for the recursion. */
396 glue(helper_ret_stb
, MMUSUFFIX
)(env
, addr
+ i
, val8
,
397 oi
, retaddr
+ GETPC_ADJ
);
402 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
404 glue(glue(st
, SUFFIX
), _p
)((uint8_t *)haddr
, val
);
406 glue(glue(st
, SUFFIX
), _le_p
)((uint8_t *)haddr
, val
);
411 void helper_be_st_name(CPUArchState
*env
, target_ulong addr
, DATA_TYPE val
,
412 TCGMemOpIdx oi
, uintptr_t retaddr
)
414 unsigned mmu_idx
= get_mmuidx(oi
);
415 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
416 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
417 int a_bits
= get_alignment_bits(get_memop(oi
));
420 /* Adjust the given return address. */
421 retaddr
-= GETPC_ADJ
;
423 if (a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)) != 0) {
424 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
,
428 /* If the TLB entry is for a different page, reload and try again. */
429 if ((addr
& TARGET_PAGE_MASK
)
430 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
431 if (!VICTIM_TLB_HIT(addr_write
, addr
)) {
432 tlb_fill(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
, mmu_idx
, retaddr
);
434 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
437 /* Handle an IO access. */
438 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
439 CPUIOTLBEntry
*iotlbentry
;
440 if ((addr
& (DATA_SIZE
- 1)) != 0) {
441 goto do_unaligned_access
;
443 iotlbentry
= &env
->iotlb
[mmu_idx
][index
];
445 /* ??? Note that the io helpers always read data in the target
446 byte ordering. We should push the LE/BE request down into io. */
448 glue(io_write
, SUFFIX
)(env
, iotlbentry
, val
, addr
, retaddr
);
452 /* Handle slow unaligned access (it spans two pages or IO). */
454 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
455 >= TARGET_PAGE_SIZE
)) {
457 target_ulong page2
, tlb_addr2
;
459 /* Ensure the second page is in the TLB. Note that the first page
460 is already guaranteed to be filled, and that the second page
461 cannot evict the first. */
462 page2
= (addr
+ DATA_SIZE
) & TARGET_PAGE_MASK
;
463 index2
= (page2
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
464 tlb_addr2
= env
->tlb_table
[mmu_idx
][index2
].addr_write
;
465 if (page2
!= (tlb_addr2
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))
466 && !VICTIM_TLB_HIT(addr_write
, page2
)) {
467 tlb_fill(ENV_GET_CPU(env
), page2
, MMU_DATA_STORE
,
471 /* XXX: not efficient, but simple */
472 /* This loop must go in the forward direction to avoid issues
473 with self-modifying code. */
474 for (i
= 0; i
< DATA_SIZE
; ++i
) {
475 /* Big-endian extract. */
476 uint8_t val8
= val
>> (((DATA_SIZE
- 1) * 8) - (i
* 8));
477 /* Note the adjustment at the beginning of the function.
478 Undo that for the recursion. */
479 glue(helper_ret_stb
, MMUSUFFIX
)(env
, addr
+ i
, val8
,
480 oi
, retaddr
+ GETPC_ADJ
);
485 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
486 glue(glue(st
, SUFFIX
), _be_p
)((uint8_t *)haddr
, val
);
488 #endif /* DATA_SIZE > 1 */
491 /* Probe for whether the specified guest write access is permitted.
492 * If it is not permitted then an exception will be taken in the same
493 * way as if this were a real write access (and we will not return).
494 * Otherwise the function will return, and there will be a valid
495 * entry in the TLB for this access.
497 void probe_write(CPUArchState
*env
, target_ulong addr
, int mmu_idx
,
500 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
501 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
503 if ((addr
& TARGET_PAGE_MASK
)
504 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
505 /* TLB entry is for a different page */
506 if (!VICTIM_TLB_HIT(addr_write
, addr
)) {
507 tlb_fill(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
, mmu_idx
, retaddr
);
512 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
514 #undef READ_ACCESS_TYPE
530 #undef helper_le_ld_name
531 #undef helper_be_ld_name
532 #undef helper_le_lds_name
533 #undef helper_be_lds_name
534 #undef helper_le_st_name
535 #undef helper_be_st_name
536 #undef helper_te_ld_name
537 #undef helper_te_st_name