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aspeed/smc: rework the prototype of the AspeedSMCFlash helper routines
[qemu/ar7.git] / hw / ssi / aspeed_smc.c
blob9b31d5d27012b7d491066c1da5d805d9f3376a56
1 /*
2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "sysemu/sysemu.h"
28 #include "qemu/log.h"
29 #include "include/qemu/error-report.h"
30 #include "exec/address-spaces.h"
31
32 #include "hw/ssi/aspeed_smc.h"
33
34 /* CE Type Setting Register */
35 #define R_CONF (0x00 / 4)
36 #define CONF_LEGACY_DISABLE (1 << 31)
37 #define CONF_ENABLE_W4 20
38 #define CONF_ENABLE_W3 19
39 #define CONF_ENABLE_W2 18
40 #define CONF_ENABLE_W1 17
41 #define CONF_ENABLE_W0 16
42 #define CONF_FLASH_TYPE4 9
43 #define CONF_FLASH_TYPE3 7
44 #define CONF_FLASH_TYPE2 5
45 #define CONF_FLASH_TYPE1 3
46 #define CONF_FLASH_TYPE0 1
47
48 /* CE Control Register */
49 #define R_CE_CTRL (0x04 / 4)
50 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
51 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
52 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
53 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
54 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
55
56 /* Interrupt Control and Status Register */
57 #define R_INTR_CTRL (0x08 / 4)
58 #define INTR_CTRL_DMA_STATUS (1 << 11)
59 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10)
60 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9)
61 #define INTR_CTRL_DMA_EN (1 << 3)
62 #define INTR_CTRL_CMD_ABORT_EN (1 << 2)
63 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
64
65 /* CEx Control Register */
66 #define R_CTRL0 (0x10 / 4)
67 #define CTRL_CMD_SHIFT 16
68 #define CTRL_CMD_MASK 0xff
69 #define CTRL_CE_STOP_ACTIVE (1 << 2)
70 #define CTRL_CMD_MODE_MASK 0x3
71 #define CTRL_READMODE 0x0
72 #define CTRL_FREADMODE 0x1
73 #define CTRL_WRITEMODE 0x2
74 #define CTRL_USERMODE 0x3
75 #define R_CTRL1 (0x14 / 4)
76 #define R_CTRL2 (0x18 / 4)
77 #define R_CTRL3 (0x1C / 4)
78 #define R_CTRL4 (0x20 / 4)
79
80 /* CEx Segment Address Register */
81 #define R_SEG_ADDR0 (0x30 / 4)
82 #define SEG_END_SHIFT 24 /* 8MB units */
83 #define SEG_END_MASK 0xff
84 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
85 #define SEG_START_MASK 0xff
86 #define R_SEG_ADDR1 (0x34 / 4)
87 #define R_SEG_ADDR2 (0x38 / 4)
88 #define R_SEG_ADDR3 (0x3C / 4)
89 #define R_SEG_ADDR4 (0x40 / 4)
90
91 /* Misc Control Register #1 */
92 #define R_MISC_CTRL1 (0x50 / 4)
93
94 /* Misc Control Register #2 */
95 #define R_MISC_CTRL2 (0x54 / 4)
96
97 /* DMA Control/Status Register */
98 #define R_DMA_CTRL (0x80 / 4)
99 #define DMA_CTRL_DELAY_MASK 0xf
100 #define DMA_CTRL_DELAY_SHIFT 8
101 #define DMA_CTRL_FREQ_MASK 0xf
102 #define DMA_CTRL_FREQ_SHIFT 4
103 #define DMA_CTRL_MODE (1 << 3)
104 #define DMA_CTRL_CKSUM (1 << 2)
105 #define DMA_CTRL_DIR (1 << 1)
106 #define DMA_CTRL_EN (1 << 0)
107
108 /* DMA Flash Side Address */
109 #define R_DMA_FLASH_ADDR (0x84 / 4)
110
111 /* DMA DRAM Side Address */
112 #define R_DMA_DRAM_ADDR (0x88 / 4)
113
114 /* DMA Length Register */
115 #define R_DMA_LEN (0x8C / 4)
116
117 /* Checksum Calculation Result */
118 #define R_DMA_CHECKSUM (0x90 / 4)
119
120 /* Misc Control Register #2 */
121 #define R_TIMINGS (0x94 / 4)
122
123 /* SPI controller registers and bits */
124 #define R_SPI_CONF (0x00 / 4)
125 #define SPI_CONF_ENABLE_W0 0
126 #define R_SPI_CTRL0 (0x4 / 4)
127 #define R_SPI_MISC_CTRL (0x10 / 4)
128 #define R_SPI_TIMINGS (0x14 / 4)
129
130 #define ASPEED_SOC_SMC_FLASH_BASE 0x10000000
131 #define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
132 #define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
133 #define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000
134
135 /*
136 * Default segments mapping addresses and size for each slave per
137 * controller. These can be changed when board is initialized with the
138 * Segment Address Registers.
139 */
140 static const AspeedSegments aspeed_segments_legacy[] = {
141 { 0x10000000, 32 * 1024 * 1024 },
142 };
143
144 static const AspeedSegments aspeed_segments_fmc[] = {
145 { 0x20000000, 64 * 1024 * 1024 }, /* start address is readonly */
146 { 0x24000000, 32 * 1024 * 1024 },
147 { 0x26000000, 32 * 1024 * 1024 },
148 { 0x28000000, 32 * 1024 * 1024 },
149 { 0x2A000000, 32 * 1024 * 1024 }
150 };
151
152 static const AspeedSegments aspeed_segments_spi[] = {
153 { 0x30000000, 64 * 1024 * 1024 },
154 };
155
156 static const AspeedSegments aspeed_segments_ast2500_fmc[] = {
157 { 0x20000000, 128 * 1024 * 1024 }, /* start address is readonly */
158 { 0x28000000, 32 * 1024 * 1024 },
159 { 0x2A000000, 32 * 1024 * 1024 },
160 };
161
162 static const AspeedSegments aspeed_segments_ast2500_spi1[] = {
163 { 0x30000000, 32 * 1024 * 1024 }, /* start address is readonly */
164 { 0x32000000, 96 * 1024 * 1024 }, /* end address is readonly */
165 };
166
167 static const AspeedSegments aspeed_segments_ast2500_spi2[] = {
168 { 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */
169 { 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */
170 };
171
172 static const AspeedSMCController controllers[] = {
173 { "aspeed.smc.smc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
174 CONF_ENABLE_W0, 5, aspeed_segments_legacy,
175 ASPEED_SOC_SMC_FLASH_BASE, 0x6000000 },
176 { "aspeed.smc.fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
177 CONF_ENABLE_W0, 5, aspeed_segments_fmc,
178 ASPEED_SOC_FMC_FLASH_BASE, 0x10000000 },
179 { "aspeed.smc.spi", R_SPI_CONF, 0xff, R_SPI_CTRL0, R_SPI_TIMINGS,
180 SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi,
181 ASPEED_SOC_SPI_FLASH_BASE, 0x10000000 },
182 { "aspeed.smc.ast2500-fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
183 CONF_ENABLE_W0, 3, aspeed_segments_ast2500_fmc,
184 ASPEED_SOC_FMC_FLASH_BASE, 0x10000000 },
185 { "aspeed.smc.ast2500-spi1", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
186 CONF_ENABLE_W0, 2, aspeed_segments_ast2500_spi1,
187 ASPEED_SOC_SPI_FLASH_BASE, 0x8000000 },
188 { "aspeed.smc.ast2500-spi2", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
189 CONF_ENABLE_W0, 2, aspeed_segments_ast2500_spi2,
190 ASPEED_SOC_SPI2_FLASH_BASE, 0x8000000 },
191 };
192
193 /*
194 * The Segment Register uses a 8MB unit to encode the start address
195 * and the end address of the mapping window of a flash SPI slave :
196 *
197 * | byte 1 | byte 2 | byte 3 | byte 4 |
198 * +--------+--------+--------+--------+
199 * | end | start | 0 | 0 |
200 *
201 */
202 static inline uint32_t aspeed_smc_segment_to_reg(const AspeedSegments *seg)
203 {
204 uint32_t reg = 0;
205 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT;
206 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT;
207 return reg;
208 }
209
210 static inline void aspeed_smc_reg_to_segment(uint32_t reg, AspeedSegments *seg)
211 {
212 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23;
213 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr;
214 }
215
216 static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
217 const AspeedSegments *new,
218 int cs)
219 {
220 AspeedSegments seg;
221 int i;
222
223 for (i = 0; i < s->ctrl->max_slaves; i++) {
224 if (i == cs) {
225 continue;
226 }
227
228 aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + i], &seg);
229
230 if (new->addr + new->size > seg.addr &&
231 new->addr < seg.addr + seg.size) {
232 qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment CS%d [ 0x%"
233 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with "
234 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
235 s->ctrl->name, cs, new->addr, new->addr + new->size,
236 i, seg.addr, seg.addr + seg.size);
237 return true;
238 }
239 }
240 return false;
241 }
242
243 static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
244 uint64_t new)
245 {
246 AspeedSMCFlash *fl = &s->flashes[cs];
247 AspeedSegments seg;
248
249 aspeed_smc_reg_to_segment(new, &seg);
250
251 /* The start address of CS0 is read-only */
252 if (cs == 0 && seg.addr != s->ctrl->flash_window_base) {
253 qemu_log_mask(LOG_GUEST_ERROR,
254 "%s: Tried to change CS0 start address to 0x%"
255 HWADDR_PRIx "\n", s->ctrl->name, seg.addr);
256 seg.addr = s->ctrl->flash_window_base;
257 new = aspeed_smc_segment_to_reg(&seg);
258 }
259
260 /*
261 * The end address of the AST2500 spi controllers is also
262 * read-only.
263 */
264 if ((s->ctrl->segments == aspeed_segments_ast2500_spi1 ||
265 s->ctrl->segments == aspeed_segments_ast2500_spi2) &&
266 cs == s->ctrl->max_slaves &&
267 seg.addr + seg.size != s->ctrl->segments[cs].addr +
268 s->ctrl->segments[cs].size) {
269 qemu_log_mask(LOG_GUEST_ERROR,
270 "%s: Tried to change CS%d end address to 0x%"
271 HWADDR_PRIx "\n", s->ctrl->name, cs, seg.addr + seg.size);
272 seg.size = s->ctrl->segments[cs].addr + s->ctrl->segments[cs].size -
273 seg.addr;
274 new = aspeed_smc_segment_to_reg(&seg);
275 }
276
277 /* Keep the segment in the overall flash window */
278 if (seg.addr + seg.size <= s->ctrl->flash_window_base ||
279 seg.addr > s->ctrl->flash_window_base + s->ctrl->flash_window_size) {
280 qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is invalid : "
281 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
282 s->ctrl->name, cs, seg.addr, seg.addr + seg.size);
283 return;
284 }
285
286 /* Check start address vs. alignment */
287 if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) {
288 qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is not "
289 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
290 s->ctrl->name, cs, seg.addr, seg.addr + seg.size);
291 }
292
293 /* And segments should not overlap (in the specs) */
294 aspeed_smc_flash_overlap(s, &seg, cs);
295
296 /* All should be fine now to move the region */
297 memory_region_transaction_begin();
298 memory_region_set_size(&fl->mmio, seg.size);
299 memory_region_set_address(&fl->mmio, seg.addr - s->ctrl->flash_window_base);
300 memory_region_set_enabled(&fl->mmio, true);
301 memory_region_transaction_commit();
302
303 s->regs[R_SEG_ADDR0 + cs] = new;
304 }
305
306 static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
307 unsigned size)
308 {
309 qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u"
310 PRIx64 "\n", __func__, addr, size);
311 return 0;
312 }
313
314 static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,
315 uint64_t data, unsigned size)
316 {
317 qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%"
318 PRIx64 "\n", __func__, addr, size, data);
319 }
320
321 static const MemoryRegionOps aspeed_smc_flash_default_ops = {
322 .read = aspeed_smc_flash_default_read,
323 .write = aspeed_smc_flash_default_write,
324 .endianness = DEVICE_LITTLE_ENDIAN,
325 .valid = {
326 .min_access_size = 1,
327 .max_access_size = 4,
328 },
329 };
330
331 static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl)
332 {
333 const AspeedSMCState *s = fl->controller;
334
335 return s->regs[s->r_ctrl0 + fl->id] & CTRL_CMD_MODE_MASK;
336 }
337
338 static inline bool aspeed_smc_is_usermode(const AspeedSMCFlash *fl)
339 {
340 return aspeed_smc_flash_mode(fl) == CTRL_USERMODE;
341 }
342
343 static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl)
344 {
345 const AspeedSMCState *s = fl->controller;
346
347 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->id));
348 }
349
350 static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
351 {
352 AspeedSMCFlash *fl = opaque;
353 const AspeedSMCState *s = fl->controller;
354 uint64_t ret = 0;
355 int i;
356
357 if (aspeed_smc_is_usermode(fl)) {
358 for (i = 0; i < size; i++) {
359 ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
360 }
361 } else {
362 qemu_log_mask(LOG_UNIMP, "%s: usermode not implemented\n",
363 __func__);
364 ret = -1;
365 }
366
367 return ret;
368 }
369
370 static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
371 unsigned size)
372 {
373 AspeedSMCFlash *fl = opaque;
374 const AspeedSMCState *s = fl->controller;
375 int i;
376
377 if (!aspeed_smc_is_writable(fl)) {
378 qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
379 HWADDR_PRIx "\n", __func__, addr);
380 return;
381 }
382
383 if (!aspeed_smc_is_usermode(fl)) {
384 qemu_log_mask(LOG_UNIMP, "%s: usermode not implemented\n",
385 __func__);
386 return;
387 }
388
389 for (i = 0; i < size; i++) {
390 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
391 }
392 }
393
394 static const MemoryRegionOps aspeed_smc_flash_ops = {
395 .read = aspeed_smc_flash_read,
396 .write = aspeed_smc_flash_write,
397 .endianness = DEVICE_LITTLE_ENDIAN,
398 .valid = {
399 .min_access_size = 1,
400 .max_access_size = 4,
401 },
402 };
403
404 static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl)
405 {
406 const AspeedSMCState *s = fl->controller;
407
408 return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE;
409 }
410
411 static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl)
412 {
413 const AspeedSMCState *s = fl->controller;
414
415 qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
416 }
417
418 static void aspeed_smc_reset(DeviceState *d)
419 {
420 AspeedSMCState *s = ASPEED_SMC(d);
421 int i;
422
423 memset(s->regs, 0, sizeof s->regs);
424
425 /* Pretend DMA is done (u-boot initialization) */
426 s->regs[R_INTR_CTRL] = INTR_CTRL_DMA_STATUS;
427
428 /* Unselect all slaves */
429 for (i = 0; i < s->num_cs; ++i) {
430 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
431 qemu_set_irq(s->cs_lines[i], true);
432 }
433
434 /* setup default segment register values for all */
435 for (i = 0; i < s->ctrl->max_slaves; ++i) {
436 s->regs[R_SEG_ADDR0 + i] =
437 aspeed_smc_segment_to_reg(&s->ctrl->segments[i]);
438 }
439 }
440
441 static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
442 {
443 AspeedSMCState *s = ASPEED_SMC(opaque);
444
445 addr >>= 2;
446
447 if (addr >= ARRAY_SIZE(s->regs)) {
448 qemu_log_mask(LOG_GUEST_ERROR,
449 "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n",
450 __func__, addr);
451 return 0;
452 }
453
454 if (addr == s->r_conf ||
455 addr == s->r_timings ||
456 addr == s->r_ce_ctrl ||
457 addr == R_INTR_CTRL ||
458 (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
459 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs)) {
460 return s->regs[addr];
461 } else {
462 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
463 __func__, addr);
464 return 0;
465 }
466 }
467
468 static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
469 unsigned int size)
470 {
471 AspeedSMCState *s = ASPEED_SMC(opaque);
472 uint32_t value = data;
473
474 addr >>= 2;
475
476 if (addr >= ARRAY_SIZE(s->regs)) {
477 qemu_log_mask(LOG_GUEST_ERROR,
478 "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n",
479 __func__, addr);
480 return;
481 }
482
483 if (addr == s->r_conf ||
484 addr == s->r_timings ||
485 addr == s->r_ce_ctrl) {
486 s->regs[addr] = value;
487 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
488 int cs = addr - s->r_ctrl0;
489 s->regs[addr] = value;
490 aspeed_smc_flash_update_cs(&s->flashes[cs]);
491 } else if (addr >= R_SEG_ADDR0 &&
492 addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
493 int cs = addr - R_SEG_ADDR0;
494
495 if (value != s->regs[R_SEG_ADDR0 + cs]) {
496 aspeed_smc_flash_set_segment(s, cs, value);
497 }
498 } else {
499 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
500 __func__, addr);
501 return;
502 }
503 }
504
505 static const MemoryRegionOps aspeed_smc_ops = {
506 .read = aspeed_smc_read,
507 .write = aspeed_smc_write,
508 .endianness = DEVICE_LITTLE_ENDIAN,
509 .valid.unaligned = true,
510 };
511
512 static void aspeed_smc_realize(DeviceState *dev, Error **errp)
513 {
514 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
515 AspeedSMCState *s = ASPEED_SMC(dev);
516 AspeedSMCClass *mc = ASPEED_SMC_GET_CLASS(s);
517 int i;
518 char name[32];
519 hwaddr offset = 0;
520
521 s->ctrl = mc->ctrl;
522
523 /* keep a copy under AspeedSMCState to speed up accesses */
524 s->r_conf = s->ctrl->r_conf;
525 s->r_ce_ctrl = s->ctrl->r_ce_ctrl;
526 s->r_ctrl0 = s->ctrl->r_ctrl0;
527 s->r_timings = s->ctrl->r_timings;
528 s->conf_enable_w0 = s->ctrl->conf_enable_w0;
529
530 /* Enforce some real HW limits */
531 if (s->num_cs > s->ctrl->max_slaves) {
532 qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n",
533 __func__, s->ctrl->max_slaves);
534 s->num_cs = s->ctrl->max_slaves;
535 }
536
537 s->spi = ssi_create_bus(dev, "spi");
538
539 /* Setup cs_lines for slaves */
540 sysbus_init_irq(sbd, &s->irq);
541 s->cs_lines = g_new0(qemu_irq, s->num_cs);
542 ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
543
544 for (i = 0; i < s->num_cs; ++i) {
545 sysbus_init_irq(sbd, &s->cs_lines[i]);
546 }
547
548 /* The memory region for the controller registers */
549 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s,
550 s->ctrl->name, ASPEED_SMC_R_MAX * 4);
551 sysbus_init_mmio(sbd, &s->mmio);
552
553 /*
554 * The container memory region representing the address space
555 * window in which the flash modules are mapped. The size and
556 * address depends on the SoC model and controller type.
557 */
558 snprintf(name, sizeof(name), "%s.flash", s->ctrl->name);
559
560 memory_region_init_io(&s->mmio_flash, OBJECT(s),
561 &aspeed_smc_flash_default_ops, s, name,
562 s->ctrl->flash_window_size);
563 sysbus_init_mmio(sbd, &s->mmio_flash);
564
565 s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_slaves);
566
567 /*
568 * Let's create a sub memory region for each possible slave. All
569 * have a configurable memory segment in the overall flash mapping
570 * window of the controller but, there is not necessarily a flash
571 * module behind to handle the memory accesses. This depends on
572 * the board configuration.
573 */
574 for (i = 0; i < s->ctrl->max_slaves; ++i) {
575 AspeedSMCFlash *fl = &s->flashes[i];
576
577 snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i);
578
579 fl->id = i;
580 fl->controller = s;
581 fl->size = s->ctrl->segments[i].size;
582 memory_region_init_io(&fl->mmio, OBJECT(s), &aspeed_smc_flash_ops,
583 fl, name, fl->size);
584 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
585 offset += fl->size;
586 }
587 }
588
589 static const VMStateDescription vmstate_aspeed_smc = {
590 .name = "aspeed.smc",
591 .version_id = 1,
592 .minimum_version_id = 1,
593 .fields = (VMStateField[]) {
594 VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
595 VMSTATE_END_OF_LIST()
596 }
597 };
598
599 static Property aspeed_smc_properties[] = {
600 DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
601 DEFINE_PROP_END_OF_LIST(),
602 };
603
604 static void aspeed_smc_class_init(ObjectClass *klass, void *data)
605 {
606 DeviceClass *dc = DEVICE_CLASS(klass);
607 AspeedSMCClass *mc = ASPEED_SMC_CLASS(klass);
608
609 dc->realize = aspeed_smc_realize;
610 dc->reset = aspeed_smc_reset;
611 dc->props = aspeed_smc_properties;
612 dc->vmsd = &vmstate_aspeed_smc;
613 mc->ctrl = data;
614 }
615
616 static const TypeInfo aspeed_smc_info = {
617 .name = TYPE_ASPEED_SMC,
618 .parent = TYPE_SYS_BUS_DEVICE,
619 .instance_size = sizeof(AspeedSMCState),
620 .class_size = sizeof(AspeedSMCClass),
621 .abstract = true,
622 };
623
624 static void aspeed_smc_register_types(void)
625 {
626 int i;
627
628 type_register_static(&aspeed_smc_info);
629 for (i = 0; i < ARRAY_SIZE(controllers); ++i) {
630 TypeInfo ti = {
631 .name = controllers[i].name,
632 .parent = TYPE_ASPEED_SMC,
633 .class_init = aspeed_smc_class_init,
634 .class_data = (void *)&controllers[i],
635 };
636 type_register(&ti);
637 }
638 }
639
640 type_init(aspeed_smc_register_types)
AR7 emulation for QEMU