target/sh4/op_helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #ifndef CONFIG_USER_ONLY
  26
  27 void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
  28                                     MMUAccessType access_type,
  29                                     int mmu_idx, uintptr_t retaddr)
  30 {
  31     switch (access_type) {
  32     case MMU_INST_FETCH:
  33     case MMU_DATA_LOAD:
  34         cs->exception_index = 0x0e0;
  35         break;
  36     case MMU_DATA_STORE:
  37         cs->exception_index = 0x100;
  38         break;
  39     }
  40     cpu_loop_exit_restore(cs, retaddr);
  41 }
  42
  43 void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
  44               int mmu_idx, uintptr_t retaddr)
  45 {
  46     int ret;
  47
  48     ret = superh_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
  49     if (ret) {
  50         /* now we have a real cpu fault */
  51         cpu_loop_exit_restore(cs, retaddr);
  52     }
  53 }
  54
  55 #endif
  56
  57 #ifdef CONFIG_USER_ONLY
  58 void QEMU_NORETURN helper_ldtlb(CPUSH4State *env)
  59 #else
  60 void helper_ldtlb(CPUSH4State *env)
  61 #endif
  62 {
  63 #ifdef CONFIG_USER_ONLY
  64     SuperHCPU *cpu = sh_env_get_cpu(env);
  65
  66     /* XXXXX */
  67     cpu_abort(CPU(cpu), "Unhandled ldtlb");
  68 #else
  69     cpu_load_tlb(env);
  70 #endif
  71 }
  72
  73 static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
  74                                                  uintptr_t retaddr)
  75 {
  76     CPUState *cs = CPU(sh_env_get_cpu(env));
  77
  78     cs->exception_index = index;
  79     cpu_loop_exit_restore(cs, retaddr);
  80 }
  81
  82 void QEMU_NORETURN helper_raise_illegal_instruction(CPUSH4State *env)
  83 {
  84     raise_exception(env, 0x180, 0);
  85 }
  86
  87 void QEMU_NORETURN helper_raise_slot_illegal_instruction(CPUSH4State *env)
  88 {
  89     raise_exception(env, 0x1a0, 0);
  90 }
  91
  92 void QEMU_NORETURN helper_raise_fpu_disable(CPUSH4State *env)
  93 {
  94     raise_exception(env, 0x800, 0);
  95 }
  96
  97 void QEMU_NORETURN helper_raise_slot_fpu_disable(CPUSH4State *env)
  98 {
  99     raise_exception(env, 0x820, 0);
 100 }
 101
 102 void QEMU_NORETURN helper_debug(CPUSH4State *env)
 103 {
 104     raise_exception(env, EXCP_DEBUG, 0);
 105 }
 106
 107 void QEMU_NORETURN helper_sleep(CPUSH4State *env)
 108 {
 109     CPUState *cs = CPU(sh_env_get_cpu(env));
 110
 111     cs->halted = 1;
 112     env->in_sleep = 1;
 113     raise_exception(env, EXCP_HLT, 0);
 114 }
 115
 116 void QEMU_NORETURN helper_trapa(CPUSH4State *env, uint32_t tra)
 117 {
 118     env->tra = tra << 2;
 119     raise_exception(env, 0x160, 0);
 120 }
 121
 122 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
 123 {
 124     if (cpu_sh4_is_cached (env, address))
 125     {
 126         memory_content *r = g_new(memory_content, 1);
 127
 128         r->address = address;
 129         r->value = value;
 130         r->next = NULL;
 131
 132         *(env->movcal_backup_tail) = r;
 133         env->movcal_backup_tail = &(r->next);
 134     }
 135 }
 136
 137 void helper_discard_movcal_backup(CPUSH4State *env)
 138 {
 139     memory_content *current = env->movcal_backup;
 140
 141     while(current)
 142     {
 143         memory_content *next = current->next;
 144         g_free(current);
 145         env->movcal_backup = current = next;
 146         if (current == NULL)
 147             env->movcal_backup_tail = &(env->movcal_backup);
 148     }
 149 }
 150
 151 void helper_ocbi(CPUSH4State *env, uint32_t address)
 152 {
 153     memory_content **current = &(env->movcal_backup);
 154     while (*current)
 155     {
 156         uint32_t a = (*current)->address;
 157         if ((a & ~0x1F) == (address & ~0x1F))
 158         {
 159             memory_content *next = (*current)->next;
 160             cpu_stl_data(env, a, (*current)->value);
 161
 162             if (next == NULL)
 163             {
 164                 env->movcal_backup_tail = current;
 165             }
 166
 167             g_free(*current);
 168             *current = next;
 169             break;
 170         }
 171     }
 172 }
 173
 174 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 175 {
 176     int64_t res;
 177
 178     res = ((uint64_t) env->mach << 32) | env->macl;
 179     res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
 180     env->mach = (res >> 32) & 0xffffffff;
 181     env->macl = res & 0xffffffff;
 182     if (env->sr & (1u << SR_S)) {
 183         if (res < 0)
 184             env->mach |= 0xffff0000;
 185         else
 186             env->mach &= 0x00007fff;
 187     }
 188 }
 189
 190 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 191 {
 192     int64_t res;
 193
 194     res = ((uint64_t) env->mach << 32) | env->macl;
 195     res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
 196     env->mach = (res >> 32) & 0xffffffff;
 197     env->macl = res & 0xffffffff;
 198     if (env->sr & (1u << SR_S)) {
 199         if (res < -0x80000000) {
 200             env->mach = 1;
 201             env->macl = 0x80000000;
 202         } else if (res > 0x000000007fffffff) {
 203             env->mach = 1;
 204             env->macl = 0x7fffffff;
 205         }
 206     }
 207 }
 208
 209 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
 210 {
 211     env->fpscr = val & FPSCR_MASK;
 212     if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
 213         set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 214     } else {
 215         set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 216     }
 217     set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 218 }
 219
 220 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
 221 {
 222     int xcpt, cause, enable;
 223
 224     xcpt = get_float_exception_flags(&env->fp_status);
 225
 226     /* Clear the flag entries */
 227     env->fpscr &= ~FPSCR_FLAG_MASK;
 228
 229     if (unlikely(xcpt)) {
 230         if (xcpt & float_flag_invalid) {
 231             env->fpscr |= FPSCR_FLAG_V;
 232         }
 233         if (xcpt & float_flag_divbyzero) {
 234             env->fpscr |= FPSCR_FLAG_Z;
 235         }
 236         if (xcpt & float_flag_overflow) {
 237             env->fpscr |= FPSCR_FLAG_O;
 238         }
 239         if (xcpt & float_flag_underflow) {
 240             env->fpscr |= FPSCR_FLAG_U;
 241         }
 242         if (xcpt & float_flag_inexact) {
 243             env->fpscr |= FPSCR_FLAG_I;
 244         }
 245
 246         /* Accumulate in cause entries */
 247         env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
 248                       << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
 249
 250         /* Generate an exception if enabled */
 251         cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
 252         enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
 253         if (cause & enable) {
 254             raise_exception(env, 0x120, retaddr);
 255         }
 256     }
 257 }
 258
 259 float32 helper_fabs_FT(float32 t0)
 260 {
 261     return float32_abs(t0);
 262 }
 263
 264 float64 helper_fabs_DT(float64 t0)
 265 {
 266     return float64_abs(t0);
 267 }
 268
 269 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
 270 {
 271     set_float_exception_flags(0, &env->fp_status);
 272     t0 = float32_add(t0, t1, &env->fp_status);
 273     update_fpscr(env, GETPC());
 274     return t0;
 275 }
 276
 277 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
 278 {
 279     set_float_exception_flags(0, &env->fp_status);
 280     t0 = float64_add(t0, t1, &env->fp_status);
 281     update_fpscr(env, GETPC());
 282     return t0;
 283 }
 284
 285 void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
 286 {
 287     int relation;
 288
 289     set_float_exception_flags(0, &env->fp_status);
 290     relation = float32_compare(t0, t1, &env->fp_status);
 291     if (unlikely(relation == float_relation_unordered)) {
 292         update_fpscr(env, GETPC());
 293     } else {
 294         env->sr_t = (relation == float_relation_equal);
 295     }
 296 }
 297
 298 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
 299 {
 300     int relation;
 301
 302     set_float_exception_flags(0, &env->fp_status);
 303     relation = float64_compare(t0, t1, &env->fp_status);
 304     if (unlikely(relation == float_relation_unordered)) {
 305         update_fpscr(env, GETPC());
 306     } else {
 307         env->sr_t = (relation == float_relation_equal);
 308     }
 309 }
 310
 311 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
 312 {
 313     int relation;
 314
 315     set_float_exception_flags(0, &env->fp_status);
 316     relation = float32_compare(t0, t1, &env->fp_status);
 317     if (unlikely(relation == float_relation_unordered)) {
 318         update_fpscr(env, GETPC());
 319     } else {
 320         env->sr_t = (relation == float_relation_greater);
 321     }
 322 }
 323
 324 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
 325 {
 326     int relation;
 327
 328     set_float_exception_flags(0, &env->fp_status);
 329     relation = float64_compare(t0, t1, &env->fp_status);
 330     if (unlikely(relation == float_relation_unordered)) {
 331         update_fpscr(env, GETPC());
 332     } else {
 333         env->sr_t = (relation == float_relation_greater);
 334     }
 335 }
 336
 337 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
 338 {
 339     float64 ret;
 340     set_float_exception_flags(0, &env->fp_status);
 341     ret = float32_to_float64(t0, &env->fp_status);
 342     update_fpscr(env, GETPC());
 343     return ret;
 344 }
 345
 346 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
 347 {
 348     float32 ret;
 349     set_float_exception_flags(0, &env->fp_status);
 350     ret = float64_to_float32(t0, &env->fp_status);
 351     update_fpscr(env, GETPC());
 352     return ret;
 353 }
 354
 355 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
 356 {
 357     set_float_exception_flags(0, &env->fp_status);
 358     t0 = float32_div(t0, t1, &env->fp_status);
 359     update_fpscr(env, GETPC());
 360     return t0;
 361 }
 362
 363 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
 364 {
 365     set_float_exception_flags(0, &env->fp_status);
 366     t0 = float64_div(t0, t1, &env->fp_status);
 367     update_fpscr(env, GETPC());
 368     return t0;
 369 }
 370
 371 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
 372 {
 373     float32 ret;
 374     set_float_exception_flags(0, &env->fp_status);
 375     ret = int32_to_float32(t0, &env->fp_status);
 376     update_fpscr(env, GETPC());
 377     return ret;
 378 }
 379
 380 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
 381 {
 382     float64 ret;
 383     set_float_exception_flags(0, &env->fp_status);
 384     ret = int32_to_float64(t0, &env->fp_status);
 385     update_fpscr(env, GETPC());
 386     return ret;
 387 }
 388
 389 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
 390 {
 391     set_float_exception_flags(0, &env->fp_status);
 392     t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
 393     update_fpscr(env, GETPC());
 394     return t0;
 395 }
 396
 397 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
 398 {
 399     set_float_exception_flags(0, &env->fp_status);
 400     t0 = float32_mul(t0, t1, &env->fp_status);
 401     update_fpscr(env, GETPC());
 402     return t0;
 403 }
 404
 405 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
 406 {
 407     set_float_exception_flags(0, &env->fp_status);
 408     t0 = float64_mul(t0, t1, &env->fp_status);
 409     update_fpscr(env, GETPC());
 410     return t0;
 411 }
 412
 413 float32 helper_fneg_T(float32 t0)
 414 {
 415     return float32_chs(t0);
 416 }
 417
 418 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
 419 {
 420     set_float_exception_flags(0, &env->fp_status);
 421     t0 = float32_sqrt(t0, &env->fp_status);
 422     update_fpscr(env, GETPC());
 423     return t0;
 424 }
 425
 426 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
 427 {
 428     set_float_exception_flags(0, &env->fp_status);
 429     t0 = float64_sqrt(t0, &env->fp_status);
 430     update_fpscr(env, GETPC());
 431     return t0;
 432 }
 433
 434 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
 435 {
 436     set_float_exception_flags(0, &env->fp_status);
 437     t0 = float32_sub(t0, t1, &env->fp_status);
 438     update_fpscr(env, GETPC());
 439     return t0;
 440 }
 441
 442 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
 443 {
 444     set_float_exception_flags(0, &env->fp_status);
 445     t0 = float64_sub(t0, t1, &env->fp_status);
 446     update_fpscr(env, GETPC());
 447     return t0;
 448 }
 449
 450 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
 451 {
 452     uint32_t ret;
 453     set_float_exception_flags(0, &env->fp_status);
 454     ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
 455     update_fpscr(env, GETPC());
 456     return ret;
 457 }
 458
 459 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
 460 {
 461     uint32_t ret;
 462     set_float_exception_flags(0, &env->fp_status);
 463     ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
 464     update_fpscr(env, GETPC());
 465     return ret;
 466 }
 467
 468 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
 469 {
 470     int bank, i;
 471     float32 r, p;
 472
 473     bank = (env->sr & FPSCR_FR) ? 16 : 0;
 474     r = float32_zero;
 475     set_float_exception_flags(0, &env->fp_status);
 476
 477     for (i = 0 ; i < 4 ; i++) {
 478         p = float32_mul(env->fregs[bank + m + i],
 479                         env->fregs[bank + n + i],
 480                         &env->fp_status);
 481         r = float32_add(r, p, &env->fp_status);
 482     }
 483     update_fpscr(env, GETPC());
 484
 485     env->fregs[bank + n + 3] = r;
 486 }
 487
 488 void helper_ftrv(CPUSH4State *env, uint32_t n)
 489 {
 490     int bank_matrix, bank_vector;
 491     int i, j;
 492     float32 r[4];
 493     float32 p;
 494
 495     bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
 496     bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
 497     set_float_exception_flags(0, &env->fp_status);
 498     for (i = 0 ; i < 4 ; i++) {
 499         r[i] = float32_zero;
 500         for (j = 0 ; j < 4 ; j++) {
 501             p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
 502                             env->fregs[bank_vector + j],
 503                             &env->fp_status);
 504             r[i] = float32_add(r[i], p, &env->fp_status);
 505         }
 506     }
 507     update_fpscr(env, GETPC());
 508
 509     for (i = 0 ; i < 4 ; i++) {
 510         env->fregs[bank_vector + i] = r[i];
 511     }
 512 }