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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / hw / display / vga.c
blobf33df48b1629265f80f402ce72813e058dcb5b3e
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "hw/hw.h"
27 #include "vga.h"
28 #include "ui/console.h"
29 #include "hw/i386/pc.h"
30 #include "hw/pci/pci.h"
31 #include "vga_int.h"
32 #include "ui/pixel_ops.h"
33 #include "qemu/timer.h"
34 #include "hw/xen/xen.h"
35 #include "trace.h"
36
37 //#define DEBUG_VGA_MEM
38 //#define DEBUG_VGA_REG
39
40 /* 16 state changes per vertical frame @60 Hz */
41 #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
42
43 /*
44 * Video Graphics Array (VGA)
45 *
46 * Chipset docs for original IBM VGA:
47 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
48 *
49 * FreeVGA site:
50 * http://www.osdever.net/FreeVGA/home.htm
51 *
52 * Standard VGA features and Bochs VBE extensions are implemented.
53 */
54
55 /* force some bits to zero */
56 const uint8_t sr_mask[8] = {
57 0x03,
58 0x3d,
59 0x0f,
60 0x3f,
61 0x0e,
62 0x00,
63 0x00,
64 0xff,
65 };
66
67 const uint8_t gr_mask[16] = {
68 0x0f, /* 0x00 */
69 0x0f, /* 0x01 */
70 0x0f, /* 0x02 */
71 0x1f, /* 0x03 */
72 0x03, /* 0x04 */
73 0x7b, /* 0x05 */
74 0x0f, /* 0x06 */
75 0x0f, /* 0x07 */
76 0xff, /* 0x08 */
77 0x00, /* 0x09 */
78 0x00, /* 0x0a */
79 0x00, /* 0x0b */
80 0x00, /* 0x0c */
81 0x00, /* 0x0d */
82 0x00, /* 0x0e */
83 0x00, /* 0x0f */
84 };
85
86 #define cbswap_32(__x) \
87 ((uint32_t)( \
88 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
89 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
90 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
91 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
92
93 #ifdef HOST_WORDS_BIGENDIAN
94 #define PAT(x) cbswap_32(x)
95 #else
96 #define PAT(x) (x)
97 #endif
98
99 #ifdef HOST_WORDS_BIGENDIAN
100 #define BIG 1
101 #else
102 #define BIG 0
103 #endif
104
105 #ifdef HOST_WORDS_BIGENDIAN
106 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
107 #else
108 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
109 #endif
110
111 static const uint32_t mask16[16] = {
112 PAT(0x00000000),
113 PAT(0x000000ff),
114 PAT(0x0000ff00),
115 PAT(0x0000ffff),
116 PAT(0x00ff0000),
117 PAT(0x00ff00ff),
118 PAT(0x00ffff00),
119 PAT(0x00ffffff),
120 PAT(0xff000000),
121 PAT(0xff0000ff),
122 PAT(0xff00ff00),
123 PAT(0xff00ffff),
124 PAT(0xffff0000),
125 PAT(0xffff00ff),
126 PAT(0xffffff00),
127 PAT(0xffffffff),
128 };
129
130 #undef PAT
131
132 #ifdef HOST_WORDS_BIGENDIAN
133 #define PAT(x) (x)
134 #else
135 #define PAT(x) cbswap_32(x)
136 #endif
137
138 static uint32_t expand4[256];
139 static uint16_t expand2[256];
140 static uint8_t expand4to8[16];
141
142 static void vbe_update_vgaregs(VGACommonState *s);
143
144 static inline bool vbe_enabled(VGACommonState *s)
145 {
146 return s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED;
147 }
148
149 static inline uint8_t sr(VGACommonState *s, int idx)
150 {
151 return vbe_enabled(s) ? s->sr_vbe[idx] : s->sr[idx];
152 }
153
154 static void vga_update_memory_access(VGACommonState *s)
155 {
156 hwaddr base, offset, size;
157
158 if (s->legacy_address_space == NULL) {
159 return;
160 }
161
162 if (s->has_chain4_alias) {
163 memory_region_del_subregion(s->legacy_address_space, &s->chain4_alias);
164 object_unparent(OBJECT(&s->chain4_alias));
165 s->has_chain4_alias = false;
166 s->plane_updated = 0xf;
167 }
168 if ((sr(s, VGA_SEQ_PLANE_WRITE) & VGA_SR02_ALL_PLANES) ==
169 VGA_SR02_ALL_PLANES && sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
170 offset = 0;
171 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
172 case 0:
173 base = 0xa0000;
174 size = 0x20000;
175 break;
176 case 1:
177 base = 0xa0000;
178 size = 0x10000;
179 offset = s->bank_offset;
180 break;
181 case 2:
182 base = 0xb0000;
183 size = 0x8000;
184 break;
185 case 3:
186 default:
187 base = 0xb8000;
188 size = 0x8000;
189 break;
190 }
191 assert(offset + size <= s->vram_size);
192 memory_region_init_alias(&s->chain4_alias, memory_region_owner(&s->vram),
193 "vga.chain4", &s->vram, offset, size);
194 memory_region_add_subregion_overlap(s->legacy_address_space, base,
195 &s->chain4_alias, 2);
196 s->has_chain4_alias = true;
197 }
198 }
199
200 static void vga_dumb_update_retrace_info(VGACommonState *s)
201 {
202 (void) s;
203 }
204
205 static void vga_precise_update_retrace_info(VGACommonState *s)
206 {
207 int htotal_chars;
208 int hretr_start_char;
209 int hretr_skew_chars;
210 int hretr_end_char;
211
212 int vtotal_lines;
213 int vretr_start_line;
214 int vretr_end_line;
215
216 int dots;
217 #if 0
218 int div2, sldiv2;
219 #endif
220 int clocking_mode;
221 int clock_sel;
222 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
223 int64_t chars_per_sec;
224 struct vga_precise_retrace *r = &s->retrace_info.precise;
225
226 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
227 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
228 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
229 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
230
231 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
232 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
233 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
234 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
235 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
236 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
237 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
238
239 clocking_mode = (sr(s, VGA_SEQ_CLOCK_MODE) >> 3) & 1;
240 clock_sel = (s->msr >> 2) & 3;
241 dots = (s->msr & 1) ? 8 : 9;
242
243 chars_per_sec = clk_hz[clock_sel] / dots;
244
245 htotal_chars <<= clocking_mode;
246
247 r->total_chars = vtotal_lines * htotal_chars;
248 if (r->freq) {
249 r->ticks_per_char = NANOSECONDS_PER_SECOND / (r->total_chars * r->freq);
250 } else {
251 r->ticks_per_char = NANOSECONDS_PER_SECOND / chars_per_sec;
252 }
253
254 r->vstart = vretr_start_line;
255 r->vend = r->vstart + vretr_end_line + 1;
256
257 r->hstart = hretr_start_char + hretr_skew_chars;
258 r->hend = r->hstart + hretr_end_char + 1;
259 r->htotal = htotal_chars;
260
261 #if 0
262 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
263 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
264 fprintf(stderr,
265 "hz=%f\n"
266 "htotal = %d\n"
267 "hretr_start = %d\n"
268 "hretr_skew = %d\n"
269 "hretr_end = %d\n"
270 "vtotal = %d\n"
271 "vretr_start = %d\n"
272 "vretr_end = %d\n"
273 "div2 = %d sldiv2 = %d\n"
274 "clocking_mode = %d\n"
275 "clock_sel = %d %d\n"
276 "dots = %d\n"
277 "ticks/char = %" PRId64 "\n"
278 "\n",
279 (double) NANOSECONDS_PER_SECOND / (r->ticks_per_char * r->total_chars),
280 htotal_chars,
281 hretr_start_char,
282 hretr_skew_chars,
283 hretr_end_char,
284 vtotal_lines,
285 vretr_start_line,
286 vretr_end_line,
287 div2, sldiv2,
288 clocking_mode,
289 clock_sel,
290 clk_hz[clock_sel],
291 dots,
292 r->ticks_per_char
293 );
294 #endif
295 }
296
297 static uint8_t vga_precise_retrace(VGACommonState *s)
298 {
299 struct vga_precise_retrace *r = &s->retrace_info.precise;
300 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
301
302 if (r->total_chars) {
303 int cur_line, cur_line_char, cur_char;
304 int64_t cur_tick;
305
306 cur_tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
307
308 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
309 cur_line = cur_char / r->htotal;
310
311 if (cur_line >= r->vstart && cur_line <= r->vend) {
312 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
313 } else {
314 cur_line_char = cur_char % r->htotal;
315 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
316 val |= ST01_DISP_ENABLE;
317 }
318 }
319
320 return val;
321 } else {
322 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
323 }
324 }
325
326 static uint8_t vga_dumb_retrace(VGACommonState *s)
327 {
328 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
329 }
330
331 int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
332 {
333 if (s->msr & VGA_MIS_COLOR) {
334 /* Color */
335 return (addr >= 0x3b0 && addr <= 0x3bf);
336 } else {
337 /* Monochrome */
338 return (addr >= 0x3d0 && addr <= 0x3df);
339 }
340 }
341
342 uint32_t vga_ioport_read(void *opaque, uint32_t addr)
343 {
344 VGACommonState *s = opaque;
345 int val, index;
346
347 if (vga_ioport_invalid(s, addr)) {
348 val = 0xff;
349 } else {
350 switch(addr) {
351 case VGA_ATT_W:
352 if (s->ar_flip_flop == 0) {
353 val = s->ar_index;
354 } else {
355 val = 0;
356 }
357 break;
358 case VGA_ATT_R:
359 index = s->ar_index & 0x1f;
360 if (index < VGA_ATT_C) {
361 val = s->ar[index];
362 } else {
363 val = 0;
364 }
365 break;
366 case VGA_MIS_W:
367 val = s->st00;
368 break;
369 case VGA_SEQ_I:
370 val = s->sr_index;
371 break;
372 case VGA_SEQ_D:
373 val = s->sr[s->sr_index];
374 #ifdef DEBUG_VGA_REG
375 fprintf(stderr, "vga: read SR%x = 0x%02x\n", s->sr_index, val);
376 #endif
377 break;
378 case VGA_PEL_IR:
379 val = s->dac_state;
380 break;
381 case VGA_PEL_IW:
382 val = s->dac_write_index;
383 break;
384 case VGA_PEL_D:
385 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
386 if (++s->dac_sub_index == 3) {
387 s->dac_sub_index = 0;
388 s->dac_read_index++;
389 }
390 break;
391 case VGA_FTC_R:
392 val = s->fcr;
393 break;
394 case VGA_MIS_R:
395 val = s->msr;
396 break;
397 case VGA_GFX_I:
398 val = s->gr_index;
399 break;
400 case VGA_GFX_D:
401 val = s->gr[s->gr_index];
402 #ifdef DEBUG_VGA_REG
403 fprintf(stderr, "vga: read GR%x = 0x%02x\n", s->gr_index, val);
404 #endif
405 break;
406 case VGA_CRT_IM:
407 case VGA_CRT_IC:
408 val = s->cr_index;
409 break;
410 case VGA_CRT_DM:
411 case VGA_CRT_DC:
412 val = s->cr[s->cr_index];
413 #ifdef DEBUG_VGA_REG
414 fprintf(stderr, "vga: read CR%x = 0x%02x\n", s->cr_index, val);
415 #endif
416 break;
417 case VGA_IS1_RM:
418 case VGA_IS1_RC:
419 /* just toggle to fool polling */
420 val = s->st01 = s->retrace(s);
421 s->ar_flip_flop = 0;
422 break;
423 default:
424 val = 0x00;
425 break;
426 }
427 }
428 trace_vga_std_read_io(addr, val);
429 return val;
430 }
431
432 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
433 {
434 VGACommonState *s = opaque;
435 int index;
436
437 /* check port range access depending on color/monochrome mode */
438 if (vga_ioport_invalid(s, addr)) {
439 return;
440 }
441 trace_vga_std_write_io(addr, val);
442
443 switch(addr) {
444 case VGA_ATT_W:
445 if (s->ar_flip_flop == 0) {
446 val &= 0x3f;
447 s->ar_index = val;
448 } else {
449 index = s->ar_index & 0x1f;
450 switch(index) {
451 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
452 s->ar[index] = val & 0x3f;
453 break;
454 case VGA_ATC_MODE:
455 s->ar[index] = val & ~0x10;
456 break;
457 case VGA_ATC_OVERSCAN:
458 s->ar[index] = val;
459 break;
460 case VGA_ATC_PLANE_ENABLE:
461 s->ar[index] = val & ~0xc0;
462 break;
463 case VGA_ATC_PEL:
464 s->ar[index] = val & ~0xf0;
465 break;
466 case VGA_ATC_COLOR_PAGE:
467 s->ar[index] = val & ~0xf0;
468 break;
469 default:
470 break;
471 }
472 }
473 s->ar_flip_flop ^= 1;
474 break;
475 case VGA_MIS_W:
476 s->msr = val & ~0x10;
477 s->update_retrace_info(s);
478 break;
479 case VGA_SEQ_I:
480 s->sr_index = val & 7;
481 break;
482 case VGA_SEQ_D:
483 #ifdef DEBUG_VGA_REG
484 fprintf(stderr, "vga: write SR%x = 0x%02x\n", s->sr_index, val);
485 #endif
486 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
487 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
488 s->update_retrace_info(s);
489 }
490 vga_update_memory_access(s);
491 break;
492 case VGA_PEL_IR:
493 s->dac_read_index = val;
494 s->dac_sub_index = 0;
495 s->dac_state = 3;
496 break;
497 case VGA_PEL_IW:
498 s->dac_write_index = val;
499 s->dac_sub_index = 0;
500 s->dac_state = 0;
501 break;
502 case VGA_PEL_D:
503 s->dac_cache[s->dac_sub_index] = val;
504 if (++s->dac_sub_index == 3) {
505 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
506 s->dac_sub_index = 0;
507 s->dac_write_index++;
508 }
509 break;
510 case VGA_GFX_I:
511 s->gr_index = val & 0x0f;
512 break;
513 case VGA_GFX_D:
514 #ifdef DEBUG_VGA_REG
515 fprintf(stderr, "vga: write GR%x = 0x%02x\n", s->gr_index, val);
516 #endif
517 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
518 vbe_update_vgaregs(s);
519 vga_update_memory_access(s);
520 break;
521 case VGA_CRT_IM:
522 case VGA_CRT_IC:
523 s->cr_index = val;
524 break;
525 case VGA_CRT_DM:
526 case VGA_CRT_DC:
527 #ifdef DEBUG_VGA_REG
528 fprintf(stderr, "vga: write CR%x = 0x%02x\n", s->cr_index, val);
529 #endif
530 /* handle CR0-7 protection */
531 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
532 s->cr_index <= VGA_CRTC_OVERFLOW) {
533 /* can always write bit 4 of CR7 */
534 if (s->cr_index == VGA_CRTC_OVERFLOW) {
535 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
536 (val & 0x10);
537 vbe_update_vgaregs(s);
538 }
539 return;
540 }
541 s->cr[s->cr_index] = val;
542 vbe_update_vgaregs(s);
543
544 switch(s->cr_index) {
545 case VGA_CRTC_H_TOTAL:
546 case VGA_CRTC_H_SYNC_START:
547 case VGA_CRTC_H_SYNC_END:
548 case VGA_CRTC_V_TOTAL:
549 case VGA_CRTC_OVERFLOW:
550 case VGA_CRTC_V_SYNC_END:
551 case VGA_CRTC_MODE:
552 s->update_retrace_info(s);
553 break;
554 }
555 break;
556 case VGA_IS1_RM:
557 case VGA_IS1_RC:
558 s->fcr = val & 0x10;
559 break;
560 }
561 }
562
563 /*
564 * Sanity check vbe register writes.
565 *
566 * As we don't have a way to signal errors to the guest in the bochs
567 * dispi interface we'll go adjust the registers to the closest valid
568 * value.
569 */
570 static void vbe_fixup_regs(VGACommonState *s)
571 {
572 uint16_t *r = s->vbe_regs;
573 uint32_t bits, linelength, maxy, offset;
574
575 if (!vbe_enabled(s)) {
576 /* vbe is turned off -- nothing to do */
577 return;
578 }
579
580 /* check depth */
581 switch (r[VBE_DISPI_INDEX_BPP]) {
582 case 4:
583 case 8:
584 case 16:
585 case 24:
586 case 32:
587 bits = r[VBE_DISPI_INDEX_BPP];
588 break;
589 case 15:
590 bits = 16;
591 break;
592 default:
593 bits = r[VBE_DISPI_INDEX_BPP] = 8;
594 break;
595 }
596
597 /* check width */
598 r[VBE_DISPI_INDEX_XRES] &= ~7u;
599 if (r[VBE_DISPI_INDEX_XRES] == 0) {
600 r[VBE_DISPI_INDEX_XRES] = 8;
601 }
602 if (r[VBE_DISPI_INDEX_XRES] > VBE_DISPI_MAX_XRES) {
603 r[VBE_DISPI_INDEX_XRES] = VBE_DISPI_MAX_XRES;
604 }
605 r[VBE_DISPI_INDEX_VIRT_WIDTH] &= ~7u;
606 if (r[VBE_DISPI_INDEX_VIRT_WIDTH] > VBE_DISPI_MAX_XRES) {
607 r[VBE_DISPI_INDEX_VIRT_WIDTH] = VBE_DISPI_MAX_XRES;
608 }
609 if (r[VBE_DISPI_INDEX_VIRT_WIDTH] < r[VBE_DISPI_INDEX_XRES]) {
610 r[VBE_DISPI_INDEX_VIRT_WIDTH] = r[VBE_DISPI_INDEX_XRES];
611 }
612
613 /* check height */
614 linelength = r[VBE_DISPI_INDEX_VIRT_WIDTH] * bits / 8;
615 maxy = s->vbe_size / linelength;
616 if (r[VBE_DISPI_INDEX_YRES] == 0) {
617 r[VBE_DISPI_INDEX_YRES] = 1;
618 }
619 if (r[VBE_DISPI_INDEX_YRES] > VBE_DISPI_MAX_YRES) {
620 r[VBE_DISPI_INDEX_YRES] = VBE_DISPI_MAX_YRES;
621 }
622 if (r[VBE_DISPI_INDEX_YRES] > maxy) {
623 r[VBE_DISPI_INDEX_YRES] = maxy;
624 }
625
626 /* check offset */
627 if (r[VBE_DISPI_INDEX_X_OFFSET] > VBE_DISPI_MAX_XRES) {
628 r[VBE_DISPI_INDEX_X_OFFSET] = VBE_DISPI_MAX_XRES;
629 }
630 if (r[VBE_DISPI_INDEX_Y_OFFSET] > VBE_DISPI_MAX_YRES) {
631 r[VBE_DISPI_INDEX_Y_OFFSET] = VBE_DISPI_MAX_YRES;
632 }
633 offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
634 offset += r[VBE_DISPI_INDEX_Y_OFFSET] * linelength;
635 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
636 r[VBE_DISPI_INDEX_Y_OFFSET] = 0;
637 offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
638 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
639 r[VBE_DISPI_INDEX_X_OFFSET] = 0;
640 offset = 0;
641 }
642 }
643
644 /* update vga state */
645 r[VBE_DISPI_INDEX_VIRT_HEIGHT] = maxy;
646 s->vbe_line_offset = linelength;
647 s->vbe_start_addr = offset / 4;
648 }
649
650 /* we initialize the VGA graphic mode */
651 static void vbe_update_vgaregs(VGACommonState *s)
652 {
653 int h, shift_control;
654
655 if (!vbe_enabled(s)) {
656 /* vbe is turned off -- nothing to do */
657 return;
658 }
659
660 /* graphic mode + memory map 1 */
661 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
662 VGA_GR06_GRAPHICS_MODE;
663 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
664 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
665 /* width */
666 s->cr[VGA_CRTC_H_DISP] =
667 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
668 /* height (only meaningful if < 1024) */
669 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
670 s->cr[VGA_CRTC_V_DISP_END] = h;
671 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
672 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
673 /* line compare to 1023 */
674 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
675 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
676 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
677
678 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
679 shift_control = 0;
680 s->sr_vbe[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
681 } else {
682 shift_control = 2;
683 /* set chain 4 mode */
684 s->sr_vbe[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
685 /* activate all planes */
686 s->sr_vbe[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
687 }
688 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
689 (shift_control << 5);
690 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
691 }
692
693 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
694 {
695 VGACommonState *s = opaque;
696 return s->vbe_index;
697 }
698
699 uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
700 {
701 VGACommonState *s = opaque;
702 uint32_t val;
703
704 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
705 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
706 switch(s->vbe_index) {
707 /* XXX: do not hardcode ? */
708 case VBE_DISPI_INDEX_XRES:
709 val = VBE_DISPI_MAX_XRES;
710 break;
711 case VBE_DISPI_INDEX_YRES:
712 val = VBE_DISPI_MAX_YRES;
713 break;
714 case VBE_DISPI_INDEX_BPP:
715 val = VBE_DISPI_MAX_BPP;
716 break;
717 default:
718 val = s->vbe_regs[s->vbe_index];
719 break;
720 }
721 } else {
722 val = s->vbe_regs[s->vbe_index];
723 }
724 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
725 val = s->vbe_size / (64 * 1024);
726 } else {
727 val = 0;
728 }
729 trace_vga_vbe_read(s->vbe_index, val);
730 return val;
731 }
732
733 void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
734 {
735 VGACommonState *s = opaque;
736 s->vbe_index = val;
737 }
738
739 void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
740 {
741 VGACommonState *s = opaque;
742
743 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
744 trace_vga_vbe_write(s->vbe_index, val);
745 switch(s->vbe_index) {
746 case VBE_DISPI_INDEX_ID:
747 if (val == VBE_DISPI_ID0 ||
748 val == VBE_DISPI_ID1 ||
749 val == VBE_DISPI_ID2 ||
750 val == VBE_DISPI_ID3 ||
751 val == VBE_DISPI_ID4) {
752 s->vbe_regs[s->vbe_index] = val;
753 }
754 break;
755 case VBE_DISPI_INDEX_XRES:
756 case VBE_DISPI_INDEX_YRES:
757 case VBE_DISPI_INDEX_BPP:
758 case VBE_DISPI_INDEX_VIRT_WIDTH:
759 case VBE_DISPI_INDEX_X_OFFSET:
760 case VBE_DISPI_INDEX_Y_OFFSET:
761 s->vbe_regs[s->vbe_index] = val;
762 vbe_fixup_regs(s);
763 vbe_update_vgaregs(s);
764 break;
765 case VBE_DISPI_INDEX_BANK:
766 val &= s->vbe_bank_mask;
767 s->vbe_regs[s->vbe_index] = val;
768 s->bank_offset = (val << 16);
769 vga_update_memory_access(s);
770 break;
771 case VBE_DISPI_INDEX_ENABLE:
772 if ((val & VBE_DISPI_ENABLED) &&
773 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
774
775 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 0;
776 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
777 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
778 s->vbe_regs[VBE_DISPI_INDEX_ENABLE] |= VBE_DISPI_ENABLED;
779 vbe_fixup_regs(s);
780 vbe_update_vgaregs(s);
781
782 /* clear the screen */
783 if (!(val & VBE_DISPI_NOCLEARMEM)) {
784 memset(s->vram_ptr, 0,
785 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
786 }
787 } else {
788 s->bank_offset = 0;
789 }
790 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
791 s->vbe_regs[s->vbe_index] = val;
792 vga_update_memory_access(s);
793 break;
794 default:
795 break;
796 }
797 }
798 }
799
800 /* called for accesses between 0xa0000 and 0xc0000 */
801 uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
802 {
803 int memory_map_mode, plane;
804 uint32_t ret;
805
806 /* convert to VGA memory offset */
807 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
808 addr &= 0x1ffff;
809 switch(memory_map_mode) {
810 case 0:
811 break;
812 case 1:
813 if (addr >= 0x10000)
814 return 0xff;
815 addr += s->bank_offset;
816 break;
817 case 2:
818 addr -= 0x10000;
819 if (addr >= 0x8000)
820 return 0xff;
821 break;
822 default:
823 case 3:
824 addr -= 0x18000;
825 if (addr >= 0x8000)
826 return 0xff;
827 break;
828 }
829
830 if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
831 /* chain 4 mode : simplest access */
832 assert(addr < s->vram_size);
833 ret = s->vram_ptr[addr];
834 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
835 /* odd/even mode (aka text mode mapping) */
836 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
837 addr = ((addr & ~1) << 1) | plane;
838 if (addr >= s->vram_size) {
839 return 0xff;
840 }
841 ret = s->vram_ptr[addr];
842 } else {
843 /* standard VGA latched access */
844 if (addr * sizeof(uint32_t) >= s->vram_size) {
845 return 0xff;
846 }
847 s->latch = ((uint32_t *)s->vram_ptr)[addr];
848
849 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
850 /* read mode 0 */
851 plane = s->gr[VGA_GFX_PLANE_READ];
852 ret = GET_PLANE(s->latch, plane);
853 } else {
854 /* read mode 1 */
855 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
856 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
857 ret |= ret >> 16;
858 ret |= ret >> 8;
859 ret = (~ret) & 0xff;
860 }
861 }
862 return ret;
863 }
864
865 /* called for accesses between 0xa0000 and 0xc0000 */
866 void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
867 {
868 int memory_map_mode, plane, write_mode, b, func_select, mask;
869 uint32_t write_mask, bit_mask, set_mask;
870
871 #ifdef DEBUG_VGA_MEM
872 fprintf(stderr, "vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
873 #endif
874 /* convert to VGA memory offset */
875 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
876 addr &= 0x1ffff;
877 switch(memory_map_mode) {
878 case 0:
879 break;
880 case 1:
881 if (addr >= 0x10000)
882 return;
883 addr += s->bank_offset;
884 break;
885 case 2:
886 addr -= 0x10000;
887 if (addr >= 0x8000)
888 return;
889 break;
890 default:
891 case 3:
892 addr -= 0x18000;
893 if (addr >= 0x8000)
894 return;
895 break;
896 }
897
898 if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
899 /* chain 4 mode : simplest access */
900 plane = addr & 3;
901 mask = (1 << plane);
902 if (sr(s, VGA_SEQ_PLANE_WRITE) & mask) {
903 assert(addr < s->vram_size);
904 s->vram_ptr[addr] = val;
905 #ifdef DEBUG_VGA_MEM
906 fprintf(stderr, "vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
907 #endif
908 s->plane_updated |= mask; /* only used to detect font change */
909 memory_region_set_dirty(&s->vram, addr, 1);
910 }
911 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
912 /* odd/even mode (aka text mode mapping) */
913 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
914 mask = (1 << plane);
915 if (sr(s, VGA_SEQ_PLANE_WRITE) & mask) {
916 addr = ((addr & ~1) << 1) | plane;
917 if (addr >= s->vram_size) {
918 return;
919 }
920 s->vram_ptr[addr] = val;
921 #ifdef DEBUG_VGA_MEM
922 fprintf(stderr, "vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
923 #endif
924 s->plane_updated |= mask; /* only used to detect font change */
925 memory_region_set_dirty(&s->vram, addr, 1);
926 }
927 } else {
928 /* standard VGA latched access */
929 write_mode = s->gr[VGA_GFX_MODE] & 3;
930 switch(write_mode) {
931 default:
932 case 0:
933 /* rotate */
934 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
935 val = ((val >> b) | (val << (8 - b))) & 0xff;
936 val |= val << 8;
937 val |= val << 16;
938
939 /* apply set/reset mask */
940 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
941 val = (val & ~set_mask) |
942 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
943 bit_mask = s->gr[VGA_GFX_BIT_MASK];
944 break;
945 case 1:
946 val = s->latch;
947 goto do_write;
948 case 2:
949 val = mask16[val & 0x0f];
950 bit_mask = s->gr[VGA_GFX_BIT_MASK];
951 break;
952 case 3:
953 /* rotate */
954 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
955 val = (val >> b) | (val << (8 - b));
956
957 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
958 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
959 break;
960 }
961
962 /* apply logical operation */
963 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
964 switch(func_select) {
965 case 0:
966 default:
967 /* nothing to do */
968 break;
969 case 1:
970 /* and */
971 val &= s->latch;
972 break;
973 case 2:
974 /* or */
975 val |= s->latch;
976 break;
977 case 3:
978 /* xor */
979 val ^= s->latch;
980 break;
981 }
982
983 /* apply bit mask */
984 bit_mask |= bit_mask << 8;
985 bit_mask |= bit_mask << 16;
986 val = (val & bit_mask) | (s->latch & ~bit_mask);
987
988 do_write:
989 /* mask data according to sr[2] */
990 mask = sr(s, VGA_SEQ_PLANE_WRITE);
991 s->plane_updated |= mask; /* only used to detect font change */
992 write_mask = mask16[mask];
993 if (addr * sizeof(uint32_t) >= s->vram_size) {
994 return;
995 }
996 ((uint32_t *)s->vram_ptr)[addr] =
997 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
998 (val & write_mask);
999 #ifdef DEBUG_VGA_MEM
1000 fprintf(stderr,
1001 "vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
1002 addr * 4, write_mask, val);
1003 #endif
1004 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
1005 }
1006 }
1007
1008 typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
1009 const uint8_t *s, int width);
1010
1011 #include "vga-helpers.h"
1012
1013 /* return true if the palette was modified */
1014 static int update_palette16(VGACommonState *s)
1015 {
1016 int full_update, i;
1017 uint32_t v, col, *palette;
1018
1019 full_update = 0;
1020 palette = s->last_palette;
1021 for(i = 0; i < 16; i++) {
1022 v = s->ar[i];
1023 if (s->ar[VGA_ATC_MODE] & 0x80) {
1024 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1025 } else {
1026 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1027 }
1028 v = v * 3;
1029 col = rgb_to_pixel32(c6_to_8(s->palette[v]),
1030 c6_to_8(s->palette[v + 1]),
1031 c6_to_8(s->palette[v + 2]));
1032 if (col != palette[i]) {
1033 full_update = 1;
1034 palette[i] = col;
1035 }
1036 }
1037 return full_update;
1038 }
1039
1040 /* return true if the palette was modified */
1041 static int update_palette256(VGACommonState *s)
1042 {
1043 int full_update, i;
1044 uint32_t v, col, *palette;
1045
1046 full_update = 0;
1047 palette = s->last_palette;
1048 v = 0;
1049 for(i = 0; i < 256; i++) {
1050 if (s->dac_8bit) {
1051 col = rgb_to_pixel32(s->palette[v],
1052 s->palette[v + 1],
1053 s->palette[v + 2]);
1054 } else {
1055 col = rgb_to_pixel32(c6_to_8(s->palette[v]),
1056 c6_to_8(s->palette[v + 1]),
1057 c6_to_8(s->palette[v + 2]));
1058 }
1059 if (col != palette[i]) {
1060 full_update = 1;
1061 palette[i] = col;
1062 }
1063 v += 3;
1064 }
1065 return full_update;
1066 }
1067
1068 static void vga_get_offsets(VGACommonState *s,
1069 uint32_t *pline_offset,
1070 uint32_t *pstart_addr,
1071 uint32_t *pline_compare)
1072 {
1073 uint32_t start_addr, line_offset, line_compare;
1074
1075 if (vbe_enabled(s)) {
1076 line_offset = s->vbe_line_offset;
1077 start_addr = s->vbe_start_addr;
1078 line_compare = 65535;
1079 } else {
1080 /* compute line_offset in bytes */
1081 line_offset = s->cr[VGA_CRTC_OFFSET];
1082 line_offset <<= 3;
1083
1084 /* starting address */
1085 start_addr = s->cr[VGA_CRTC_START_LO] |
1086 (s->cr[VGA_CRTC_START_HI] << 8);
1087
1088 /* line compare */
1089 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1090 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1091 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
1092 }
1093 *pline_offset = line_offset;
1094 *pstart_addr = start_addr;
1095 *pline_compare = line_compare;
1096 }
1097
1098 /* update start_addr and line_offset. Return TRUE if modified */
1099 static int update_basic_params(VGACommonState *s)
1100 {
1101 int full_update;
1102 uint32_t start_addr, line_offset, line_compare;
1103
1104 full_update = 0;
1105
1106 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1107
1108 if (line_offset != s->line_offset ||
1109 start_addr != s->start_addr ||
1110 line_compare != s->line_compare) {
1111 s->line_offset = line_offset;
1112 s->start_addr = start_addr;
1113 s->line_compare = line_compare;
1114 full_update = 1;
1115 }
1116 return full_update;
1117 }
1118
1119
1120 static const uint8_t cursor_glyph[32 * 4] = {
1121 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1122 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1123 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1124 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1125 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1126 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1127 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1128 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1129 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1130 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1131 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1132 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1135 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1136 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1137 };
1138
1139 static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
1140 int *pcwidth, int *pcheight)
1141 {
1142 int width, cwidth, height, cheight;
1143
1144 /* total width & height */
1145 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1146 cwidth = 8;
1147 if (!(sr(s, VGA_SEQ_CLOCK_MODE) & VGA_SR01_CHAR_CLK_8DOTS)) {
1148 cwidth = 9;
1149 }
1150 if (sr(s, VGA_SEQ_CLOCK_MODE) & 0x08) {
1151 cwidth = 16; /* NOTE: no 18 pixel wide */
1152 }
1153 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1154 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1155 /* ugly hack for CGA 160x100x16 - explain me the logic */
1156 height = 100;
1157 } else {
1158 height = s->cr[VGA_CRTC_V_DISP_END] |
1159 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1160 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1161 height = (height + 1) / cheight;
1162 }
1163
1164 *pwidth = width;
1165 *pheight = height;
1166 *pcwidth = cwidth;
1167 *pcheight = cheight;
1168 }
1169
1170 /*
1171 * Text mode update
1172 * Missing:
1173 * - double scan
1174 * - double width
1175 * - underline
1176 * - flashing
1177 */
1178 static void vga_draw_text(VGACommonState *s, int full_update)
1179 {
1180 DisplaySurface *surface = qemu_console_surface(s->con);
1181 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1182 int cx_min, cx_max, linesize, x_incr, line, line1;
1183 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1184 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
1185 const uint8_t *font_ptr, *font_base[2];
1186 int dup9, line_offset;
1187 uint32_t *palette;
1188 uint32_t *ch_attr_ptr;
1189 int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1190
1191 /* compute font data address (in plane 2) */
1192 v = sr(s, VGA_SEQ_CHARACTER_MAP);
1193 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1194 if (offset != s->font_offsets[0]) {
1195 s->font_offsets[0] = offset;
1196 full_update = 1;
1197 }
1198 font_base[0] = s->vram_ptr + offset;
1199
1200 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1201 font_base[1] = s->vram_ptr + offset;
1202 if (offset != s->font_offsets[1]) {
1203 s->font_offsets[1] = offset;
1204 full_update = 1;
1205 }
1206 if (s->plane_updated & (1 << 2) || s->has_chain4_alias) {
1207 /* if the plane 2 was modified since the last display, it
1208 indicates the font may have been modified */
1209 s->plane_updated = 0;
1210 full_update = 1;
1211 }
1212 full_update |= update_basic_params(s);
1213
1214 line_offset = s->line_offset;
1215
1216 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1217 if ((height * width) <= 1) {
1218 /* better than nothing: exit if transient size is too small */
1219 return;
1220 }
1221 if ((height * width) > CH_ATTR_SIZE) {
1222 /* better than nothing: exit if transient size is too big */
1223 return;
1224 }
1225
1226 if (width != s->last_width || height != s->last_height ||
1227 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1228 s->last_scr_width = width * cw;
1229 s->last_scr_height = height * cheight;
1230 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1231 surface = qemu_console_surface(s->con);
1232 dpy_text_resize(s->con, width, height);
1233 s->last_depth = 0;
1234 s->last_width = width;
1235 s->last_height = height;
1236 s->last_ch = cheight;
1237 s->last_cw = cw;
1238 full_update = 1;
1239 }
1240 full_update |= update_palette16(s);
1241 palette = s->last_palette;
1242 x_incr = cw * surface_bytes_per_pixel(surface);
1243
1244 if (full_update) {
1245 s->full_update_text = 1;
1246 }
1247 if (s->full_update_gfx) {
1248 s->full_update_gfx = 0;
1249 full_update |= 1;
1250 }
1251
1252 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1253 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1254 if (cursor_offset != s->cursor_offset ||
1255 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1256 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
1257 /* if the cursor position changed, we update the old and new
1258 chars */
1259 if (s->cursor_offset < CH_ATTR_SIZE)
1260 s->last_ch_attr[s->cursor_offset] = -1;
1261 if (cursor_offset < CH_ATTR_SIZE)
1262 s->last_ch_attr[cursor_offset] = -1;
1263 s->cursor_offset = cursor_offset;
1264 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1265 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1266 }
1267 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1268 if (now >= s->cursor_blink_time) {
1269 s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
1270 s->cursor_visible_phase = !s->cursor_visible_phase;
1271 }
1272
1273 dest = surface_data(surface);
1274 linesize = surface_stride(surface);
1275 ch_attr_ptr = s->last_ch_attr;
1276 line = 0;
1277 offset = s->start_addr * 4;
1278 for(cy = 0; cy < height; cy++) {
1279 d1 = dest;
1280 src = s->vram_ptr + offset;
1281 cx_min = width;
1282 cx_max = -1;
1283 for(cx = 0; cx < width; cx++) {
1284 ch_attr = *(uint16_t *)src;
1285 if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
1286 if (cx < cx_min)
1287 cx_min = cx;
1288 if (cx > cx_max)
1289 cx_max = cx;
1290 *ch_attr_ptr = ch_attr;
1291 #ifdef HOST_WORDS_BIGENDIAN
1292 ch = ch_attr >> 8;
1293 cattr = ch_attr & 0xff;
1294 #else
1295 ch = ch_attr & 0xff;
1296 cattr = ch_attr >> 8;
1297 #endif
1298 font_ptr = font_base[(cattr >> 3) & 1];
1299 font_ptr += 32 * 4 * ch;
1300 bgcol = palette[cattr >> 4];
1301 fgcol = palette[cattr & 0x0f];
1302 if (cw == 16) {
1303 vga_draw_glyph16(d1, linesize,
1304 font_ptr, cheight, fgcol, bgcol);
1305 } else if (cw != 9) {
1306 vga_draw_glyph8(d1, linesize,
1307 font_ptr, cheight, fgcol, bgcol);
1308 } else {
1309 dup9 = 0;
1310 if (ch >= 0xb0 && ch <= 0xdf &&
1311 (s->ar[VGA_ATC_MODE] & 0x04)) {
1312 dup9 = 1;
1313 }
1314 vga_draw_glyph9(d1, linesize,
1315 font_ptr, cheight, fgcol, bgcol, dup9);
1316 }
1317 if (src == cursor_ptr &&
1318 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
1319 s->cursor_visible_phase) {
1320 int line_start, line_last, h;
1321 /* draw the cursor */
1322 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1323 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
1324 /* XXX: check that */
1325 if (line_last > cheight - 1)
1326 line_last = cheight - 1;
1327 if (line_last >= line_start && line_start < cheight) {
1328 h = line_last - line_start + 1;
1329 d = d1 + linesize * line_start;
1330 if (cw == 16) {
1331 vga_draw_glyph16(d, linesize,
1332 cursor_glyph, h, fgcol, bgcol);
1333 } else if (cw != 9) {
1334 vga_draw_glyph8(d, linesize,
1335 cursor_glyph, h, fgcol, bgcol);
1336 } else {
1337 vga_draw_glyph9(d, linesize,
1338 cursor_glyph, h, fgcol, bgcol, 1);
1339 }
1340 }
1341 }
1342 }
1343 d1 += x_incr;
1344 src += 4;
1345 ch_attr_ptr++;
1346 }
1347 if (cx_max != -1) {
1348 dpy_gfx_update(s->con, cx_min * cw, cy * cheight,
1349 (cx_max - cx_min + 1) * cw, cheight);
1350 }
1351 dest += linesize * cheight;
1352 line1 = line + cheight;
1353 offset += line_offset;
1354 if (line < s->line_compare && line1 >= s->line_compare) {
1355 offset = 0;
1356 }
1357 line = line1;
1358 }
1359 }
1360
1361 enum {
1362 VGA_DRAW_LINE2,
1363 VGA_DRAW_LINE2D2,
1364 VGA_DRAW_LINE4,
1365 VGA_DRAW_LINE4D2,
1366 VGA_DRAW_LINE8D2,
1367 VGA_DRAW_LINE8,
1368 VGA_DRAW_LINE15_LE,
1369 VGA_DRAW_LINE16_LE,
1370 VGA_DRAW_LINE24_LE,
1371 VGA_DRAW_LINE32_LE,
1372 VGA_DRAW_LINE15_BE,
1373 VGA_DRAW_LINE16_BE,
1374 VGA_DRAW_LINE24_BE,
1375 VGA_DRAW_LINE32_BE,
1376 VGA_DRAW_LINE_NB,
1377 };
1378
1379 static vga_draw_line_func * const vga_draw_line_table[VGA_DRAW_LINE_NB] = {
1380 vga_draw_line2,
1381 vga_draw_line2d2,
1382 vga_draw_line4,
1383 vga_draw_line4d2,
1384 vga_draw_line8d2,
1385 vga_draw_line8,
1386 vga_draw_line15_le,
1387 vga_draw_line16_le,
1388 vga_draw_line24_le,
1389 vga_draw_line32_le,
1390 vga_draw_line15_be,
1391 vga_draw_line16_be,
1392 vga_draw_line24_be,
1393 vga_draw_line32_be,
1394 };
1395
1396 static int vga_get_bpp(VGACommonState *s)
1397 {
1398 int ret;
1399
1400 if (vbe_enabled(s)) {
1401 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1402 } else {
1403 ret = 0;
1404 }
1405 return ret;
1406 }
1407
1408 static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1409 {
1410 int width, height;
1411
1412 if (vbe_enabled(s)) {
1413 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1414 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1415 } else {
1416 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1417 height = s->cr[VGA_CRTC_V_DISP_END] |
1418 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1419 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1420 height = (height + 1);
1421 }
1422 *pwidth = width;
1423 *pheight = height;
1424 }
1425
1426 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
1427 {
1428 int y;
1429 if (y1 >= VGA_MAX_HEIGHT)
1430 return;
1431 if (y2 >= VGA_MAX_HEIGHT)
1432 y2 = VGA_MAX_HEIGHT;
1433 for(y = y1; y < y2; y++) {
1434 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1435 }
1436 }
1437
1438 static bool vga_scanline_invalidated(VGACommonState *s, int y)
1439 {
1440 if (y >= VGA_MAX_HEIGHT) {
1441 return false;
1442 }
1443 return s->invalidated_y_table[y >> 5] & (1 << (y & 0x1f));
1444 }
1445
1446 void vga_sync_dirty_bitmap(VGACommonState *s)
1447 {
1448 memory_region_sync_dirty_bitmap(&s->vram);
1449 }
1450
1451 void vga_dirty_log_start(VGACommonState *s)
1452 {
1453 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
1454 }
1455
1456 void vga_dirty_log_stop(VGACommonState *s)
1457 {
1458 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
1459 }
1460
1461 /*
1462 * graphic modes
1463 */
1464 static void vga_draw_graphic(VGACommonState *s, int full_update)
1465 {
1466 DisplaySurface *surface = qemu_console_surface(s->con);
1467 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1468 int width, height, shift_control, line_offset, bwidth, bits;
1469 ram_addr_t page0, page1;
1470 DirtyBitmapSnapshot *snap = NULL;
1471 int disp_width, multi_scan, multi_run;
1472 uint8_t *d;
1473 uint32_t v, addr1, addr;
1474 vga_draw_line_func *vga_draw_line = NULL;
1475 bool share_surface;
1476 pixman_format_code_t format;
1477 #ifdef HOST_WORDS_BIGENDIAN
1478 bool byteswap = !s->big_endian_fb;
1479 #else
1480 bool byteswap = s->big_endian_fb;
1481 #endif
1482
1483 full_update |= update_basic_params(s);
1484
1485 s->get_resolution(s, &width, &height);
1486 disp_width = width;
1487
1488 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1489 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
1490 if (shift_control != 1) {
1491 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1492 - 1;
1493 } else {
1494 /* in CGA modes, multi_scan is ignored */
1495 /* XXX: is it correct ? */
1496 multi_scan = double_scan;
1497 }
1498 multi_run = multi_scan;
1499 if (shift_control != s->shift_control ||
1500 double_scan != s->double_scan) {
1501 full_update = 1;
1502 s->shift_control = shift_control;
1503 s->double_scan = double_scan;
1504 }
1505
1506 if (shift_control == 0) {
1507 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
1508 disp_width <<= 1;
1509 }
1510 } else if (shift_control == 1) {
1511 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
1512 disp_width <<= 1;
1513 }
1514 }
1515
1516 depth = s->get_bpp(s);
1517
1518 /*
1519 * Check whether we can share the surface with the backend
1520 * or whether we need a shadow surface. We share native
1521 * endian surfaces for 15bpp and above and byteswapped
1522 * surfaces for 24bpp and above.
1523 */
1524 format = qemu_default_pixman_format(depth, !byteswap);
1525 if (format) {
1526 share_surface = dpy_gfx_check_format(s->con, format)
1527 && !s->force_shadow;
1528 } else {
1529 share_surface = false;
1530 }
1531 if (s->line_offset != s->last_line_offset ||
1532 disp_width != s->last_width ||
1533 height != s->last_height ||
1534 s->last_depth != depth ||
1535 s->last_byteswap != byteswap ||
1536 share_surface != is_buffer_shared(surface)) {
1537 if (share_surface) {
1538 surface = qemu_create_displaysurface_from(disp_width,
1539 height, format, s->line_offset,
1540 s->vram_ptr + (s->start_addr * 4));
1541 dpy_gfx_replace_surface(s->con, surface);
1542 } else {
1543 qemu_console_resize(s->con, disp_width, height);
1544 surface = qemu_console_surface(s->con);
1545 }
1546 s->last_scr_width = disp_width;
1547 s->last_scr_height = height;
1548 s->last_width = disp_width;
1549 s->last_height = height;
1550 s->last_line_offset = s->line_offset;
1551 s->last_depth = depth;
1552 s->last_byteswap = byteswap;
1553 full_update = 1;
1554 } else if (is_buffer_shared(surface) &&
1555 (full_update || surface_data(surface) != s->vram_ptr
1556 + (s->start_addr * 4))) {
1557 pixman_format_code_t format =
1558 qemu_default_pixman_format(depth, !byteswap);
1559 surface = qemu_create_displaysurface_from(disp_width,
1560 height, format, s->line_offset,
1561 s->vram_ptr + (s->start_addr * 4));
1562 dpy_gfx_replace_surface(s->con, surface);
1563 }
1564
1565 if (shift_control == 0) {
1566 full_update |= update_palette16(s);
1567 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
1568 v = VGA_DRAW_LINE4D2;
1569 } else {
1570 v = VGA_DRAW_LINE4;
1571 }
1572 bits = 4;
1573 } else if (shift_control == 1) {
1574 full_update |= update_palette16(s);
1575 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
1576 v = VGA_DRAW_LINE2D2;
1577 } else {
1578 v = VGA_DRAW_LINE2;
1579 }
1580 bits = 4;
1581 } else {
1582 switch(s->get_bpp(s)) {
1583 default:
1584 case 0:
1585 full_update |= update_palette256(s);
1586 v = VGA_DRAW_LINE8D2;
1587 bits = 4;
1588 break;
1589 case 8:
1590 full_update |= update_palette256(s);
1591 v = VGA_DRAW_LINE8;
1592 bits = 8;
1593 break;
1594 case 15:
1595 v = s->big_endian_fb ? VGA_DRAW_LINE15_BE : VGA_DRAW_LINE15_LE;
1596 bits = 16;
1597 break;
1598 case 16:
1599 v = s->big_endian_fb ? VGA_DRAW_LINE16_BE : VGA_DRAW_LINE16_LE;
1600 bits = 16;
1601 break;
1602 case 24:
1603 v = s->big_endian_fb ? VGA_DRAW_LINE24_BE : VGA_DRAW_LINE24_LE;
1604 bits = 24;
1605 break;
1606 case 32:
1607 v = s->big_endian_fb ? VGA_DRAW_LINE32_BE : VGA_DRAW_LINE32_LE;
1608 bits = 32;
1609 break;
1610 }
1611 }
1612 vga_draw_line = vga_draw_line_table[v];
1613
1614 if (!is_buffer_shared(surface) && s->cursor_invalidate) {
1615 s->cursor_invalidate(s);
1616 }
1617
1618 line_offset = s->line_offset;
1619 #if 0
1620 fprintf(stderr,
1621 "w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x "
1622 "linecmp=%d sr[0x01]=0x%02x\n",
1623 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1624 s->line_compare, sr(s, VGA_SEQ_CLOCK_MODE));
1625 #endif
1626 addr1 = (s->start_addr * 4);
1627 bwidth = (width * bits + 7) / 8;
1628 y_start = -1;
1629 d = surface_data(surface);
1630 linesize = surface_stride(surface);
1631 y1 = 0;
1632
1633 if (!full_update) {
1634 vga_sync_dirty_bitmap(s);
1635 snap = memory_region_snapshot_and_clear_dirty(&s->vram, addr1,
1636 line_offset * height,
1637 DIRTY_MEMORY_VGA);
1638 }
1639
1640 for(y = 0; y < height; y++) {
1641 addr = addr1;
1642 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
1643 int shift;
1644 /* CGA compatibility handling */
1645 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
1646 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1647 }
1648 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
1649 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1650 }
1651 update = full_update;
1652 page0 = addr;
1653 page1 = addr + bwidth - 1;
1654 if (full_update) {
1655 update = 1;
1656 } else {
1657 update = memory_region_snapshot_get_dirty(&s->vram, snap,
1658 page0, page1 - page0);
1659 }
1660 /* explicit invalidation for the hardware cursor (cirrus only) */
1661 update |= vga_scanline_invalidated(s, y);
1662 if (update) {
1663 if (y_start < 0)
1664 y_start = y;
1665 if (!(is_buffer_shared(surface))) {
1666 vga_draw_line(s, d, s->vram_ptr + addr, width);
1667 if (s->cursor_draw_line)
1668 s->cursor_draw_line(s, d, y);
1669 }
1670 } else {
1671 if (y_start >= 0) {
1672 /* flush to display */
1673 dpy_gfx_update(s->con, 0, y_start,
1674 disp_width, y - y_start);
1675 y_start = -1;
1676 }
1677 }
1678 if (!multi_run) {
1679 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
1680 if ((y1 & mask) == mask)
1681 addr1 += line_offset;
1682 y1++;
1683 multi_run = multi_scan;
1684 } else {
1685 multi_run--;
1686 }
1687 /* line compare acts on the displayed lines */
1688 if (y == s->line_compare)
1689 addr1 = 0;
1690 d += linesize;
1691 }
1692 if (y_start >= 0) {
1693 /* flush to display */
1694 dpy_gfx_update(s->con, 0, y_start,
1695 disp_width, y - y_start);
1696 }
1697 g_free(snap);
1698 memset(s->invalidated_y_table, 0, sizeof(s->invalidated_y_table));
1699 }
1700
1701 static void vga_draw_blank(VGACommonState *s, int full_update)
1702 {
1703 DisplaySurface *surface = qemu_console_surface(s->con);
1704 int i, w;
1705 uint8_t *d;
1706
1707 if (!full_update)
1708 return;
1709 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1710 return;
1711
1712 w = s->last_scr_width * surface_bytes_per_pixel(surface);
1713 d = surface_data(surface);
1714 for(i = 0; i < s->last_scr_height; i++) {
1715 memset(d, 0, w);
1716 d += surface_stride(surface);
1717 }
1718 dpy_gfx_update(s->con, 0, 0,
1719 s->last_scr_width, s->last_scr_height);
1720 }
1721
1722 #define GMODE_TEXT 0
1723 #define GMODE_GRAPH 1
1724 #define GMODE_BLANK 2
1725
1726 static void vga_update_display(void *opaque)
1727 {
1728 VGACommonState *s = opaque;
1729 DisplaySurface *surface = qemu_console_surface(s->con);
1730 int full_update, graphic_mode;
1731
1732 qemu_flush_coalesced_mmio_buffer();
1733
1734 if (surface_bits_per_pixel(surface) == 0) {
1735 /* nothing to do */
1736 } else {
1737 full_update = 0;
1738 if (!(s->ar_index & 0x20)) {
1739 graphic_mode = GMODE_BLANK;
1740 } else {
1741 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1742 }
1743 if (graphic_mode != s->graphic_mode) {
1744 s->graphic_mode = graphic_mode;
1745 s->cursor_blink_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1746 full_update = 1;
1747 }
1748 switch(graphic_mode) {
1749 case GMODE_TEXT:
1750 vga_draw_text(s, full_update);
1751 break;
1752 case GMODE_GRAPH:
1753 vga_draw_graphic(s, full_update);
1754 break;
1755 case GMODE_BLANK:
1756 default:
1757 vga_draw_blank(s, full_update);
1758 break;
1759 }
1760 }
1761 }
1762
1763 /* force a full display refresh */
1764 static void vga_invalidate_display(void *opaque)
1765 {
1766 VGACommonState *s = opaque;
1767
1768 s->last_width = -1;
1769 s->last_height = -1;
1770 }
1771
1772 void vga_common_reset(VGACommonState *s)
1773 {
1774 s->sr_index = 0;
1775 memset(s->sr, '\0', sizeof(s->sr));
1776 memset(s->sr_vbe, '\0', sizeof(s->sr_vbe));
1777 s->gr_index = 0;
1778 memset(s->gr, '\0', sizeof(s->gr));
1779 s->ar_index = 0;
1780 memset(s->ar, '\0', sizeof(s->ar));
1781 s->ar_flip_flop = 0;
1782 s->cr_index = 0;
1783 memset(s->cr, '\0', sizeof(s->cr));
1784 s->msr = 0;
1785 s->fcr = 0;
1786 s->st00 = 0;
1787 s->st01 = 0;
1788 s->dac_state = 0;
1789 s->dac_sub_index = 0;
1790 s->dac_read_index = 0;
1791 s->dac_write_index = 0;
1792 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1793 s->dac_8bit = 0;
1794 memset(s->palette, '\0', sizeof(s->palette));
1795 s->bank_offset = 0;
1796 s->vbe_index = 0;
1797 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1798 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
1799 s->vbe_start_addr = 0;
1800 s->vbe_line_offset = 0;
1801 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1802 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1803 s->graphic_mode = -1; /* force full update */
1804 s->shift_control = 0;
1805 s->double_scan = 0;
1806 s->line_offset = 0;
1807 s->line_compare = 0;
1808 s->start_addr = 0;
1809 s->plane_updated = 0;
1810 s->last_cw = 0;
1811 s->last_ch = 0;
1812 s->last_width = 0;
1813 s->last_height = 0;
1814 s->last_scr_width = 0;
1815 s->last_scr_height = 0;
1816 s->cursor_start = 0;
1817 s->cursor_end = 0;
1818 s->cursor_offset = 0;
1819 s->big_endian_fb = s->default_endian_fb;
1820 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1821 memset(s->last_palette, '\0', sizeof(s->last_palette));
1822 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1823 switch (vga_retrace_method) {
1824 case VGA_RETRACE_DUMB:
1825 break;
1826 case VGA_RETRACE_PRECISE:
1827 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1828 break;
1829 }
1830 vga_update_memory_access(s);
1831 }
1832
1833 static void vga_reset(void *opaque)
1834 {
1835 VGACommonState *s = opaque;
1836 vga_common_reset(s);
1837 }
1838
1839 #define TEXTMODE_X(x) ((x) % width)
1840 #define TEXTMODE_Y(x) ((x) / width)
1841 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1842 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1843 /* relay text rendering to the display driver
1844 * instead of doing a full vga_update_display() */
1845 static void vga_update_text(void *opaque, console_ch_t *chardata)
1846 {
1847 VGACommonState *s = opaque;
1848 int graphic_mode, i, cursor_offset, cursor_visible;
1849 int cw, cheight, width, height, size, c_min, c_max;
1850 uint32_t *src;
1851 console_ch_t *dst, val;
1852 char msg_buffer[80];
1853 int full_update = 0;
1854
1855 qemu_flush_coalesced_mmio_buffer();
1856
1857 if (!(s->ar_index & 0x20)) {
1858 graphic_mode = GMODE_BLANK;
1859 } else {
1860 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1861 }
1862 if (graphic_mode != s->graphic_mode) {
1863 s->graphic_mode = graphic_mode;
1864 full_update = 1;
1865 }
1866 if (s->last_width == -1) {
1867 s->last_width = 0;
1868 full_update = 1;
1869 }
1870
1871 switch (graphic_mode) {
1872 case GMODE_TEXT:
1873 /* TODO: update palette */
1874 full_update |= update_basic_params(s);
1875
1876 /* total width & height */
1877 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1878 cw = 8;
1879 if (!(sr(s, VGA_SEQ_CLOCK_MODE) & VGA_SR01_CHAR_CLK_8DOTS)) {
1880 cw = 9;
1881 }
1882 if (sr(s, VGA_SEQ_CLOCK_MODE) & 0x08) {
1883 cw = 16; /* NOTE: no 18 pixel wide */
1884 }
1885 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1886 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1887 /* ugly hack for CGA 160x100x16 - explain me the logic */
1888 height = 100;
1889 } else {
1890 height = s->cr[VGA_CRTC_V_DISP_END] |
1891 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1892 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1893 height = (height + 1) / cheight;
1894 }
1895
1896 size = (height * width);
1897 if (size > CH_ATTR_SIZE) {
1898 if (!full_update)
1899 return;
1900
1901 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
1902 width, height);
1903 break;
1904 }
1905
1906 if (width != s->last_width || height != s->last_height ||
1907 cw != s->last_cw || cheight != s->last_ch) {
1908 s->last_scr_width = width * cw;
1909 s->last_scr_height = height * cheight;
1910 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1911 dpy_text_resize(s->con, width, height);
1912 s->last_depth = 0;
1913 s->last_width = width;
1914 s->last_height = height;
1915 s->last_ch = cheight;
1916 s->last_cw = cw;
1917 full_update = 1;
1918 }
1919
1920 if (full_update) {
1921 s->full_update_gfx = 1;
1922 }
1923 if (s->full_update_text) {
1924 s->full_update_text = 0;
1925 full_update |= 1;
1926 }
1927
1928 /* Update "hardware" cursor */
1929 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1930 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1931 if (cursor_offset != s->cursor_offset ||
1932 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1933 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
1934 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
1935 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
1936 dpy_text_cursor(s->con,
1937 TEXTMODE_X(cursor_offset),
1938 TEXTMODE_Y(cursor_offset));
1939 else
1940 dpy_text_cursor(s->con, -1, -1);
1941 s->cursor_offset = cursor_offset;
1942 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1943 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1944 }
1945
1946 src = (uint32_t *) s->vram_ptr + s->start_addr;
1947 dst = chardata;
1948
1949 if (full_update) {
1950 for (i = 0; i < size; src ++, dst ++, i ++)
1951 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
1952
1953 dpy_text_update(s->con, 0, 0, width, height);
1954 } else {
1955 c_max = 0;
1956
1957 for (i = 0; i < size; src ++, dst ++, i ++) {
1958 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
1959 if (*dst != val) {
1960 *dst = val;
1961 c_max = i;
1962 break;
1963 }
1964 }
1965 c_min = i;
1966 for (; i < size; src ++, dst ++, i ++) {
1967 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
1968 if (*dst != val) {
1969 *dst = val;
1970 c_max = i;
1971 }
1972 }
1973
1974 if (c_min <= c_max) {
1975 i = TEXTMODE_Y(c_min);
1976 dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
1977 }
1978 }
1979
1980 return;
1981 case GMODE_GRAPH:
1982 if (!full_update)
1983 return;
1984
1985 s->get_resolution(s, &width, &height);
1986 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
1987 width, height);
1988 break;
1989 case GMODE_BLANK:
1990 default:
1991 if (!full_update)
1992 return;
1993
1994 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
1995 break;
1996 }
1997
1998 /* Display a message */
1999 s->last_width = 60;
2000 s->last_height = height = 3;
2001 dpy_text_cursor(s->con, -1, -1);
2002 dpy_text_resize(s->con, s->last_width, height);
2003
2004 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2005 console_write_ch(dst ++, ' ');
2006
2007 size = strlen(msg_buffer);
2008 width = (s->last_width - size) / 2;
2009 dst = chardata + s->last_width + width;
2010 for (i = 0; i < size; i ++)
2011 console_write_ch(dst ++, ATTR2CHTYPE(msg_buffer[i], QEMU_COLOR_BLUE,
2012 QEMU_COLOR_BLACK, 1));
2013
2014 dpy_text_update(s->con, 0, 0, s->last_width, height);
2015 }
2016
2017 static uint64_t vga_mem_read(void *opaque, hwaddr addr,
2018 unsigned size)
2019 {
2020 VGACommonState *s = opaque;
2021
2022 return vga_mem_readb(s, addr);
2023 }
2024
2025 static void vga_mem_write(void *opaque, hwaddr addr,
2026 uint64_t data, unsigned size)
2027 {
2028 VGACommonState *s = opaque;
2029
2030 vga_mem_writeb(s, addr, data);
2031 }
2032
2033 const MemoryRegionOps vga_mem_ops = {
2034 .read = vga_mem_read,
2035 .write = vga_mem_write,
2036 .endianness = DEVICE_LITTLE_ENDIAN,
2037 .impl = {
2038 .min_access_size = 1,
2039 .max_access_size = 1,
2040 },
2041 };
2042
2043 static int vga_common_post_load(void *opaque, int version_id)
2044 {
2045 VGACommonState *s = opaque;
2046
2047 /* force refresh */
2048 s->graphic_mode = -1;
2049 vbe_update_vgaregs(s);
2050 return 0;
2051 }
2052
2053 static bool vga_endian_state_needed(void *opaque)
2054 {
2055 VGACommonState *s = opaque;
2056
2057 /*
2058 * Only send the endian state if it's different from the
2059 * default one, thus ensuring backward compatibility for
2060 * migration of the common case
2061 */
2062 return s->default_endian_fb != s->big_endian_fb;
2063 }
2064
2065 static const VMStateDescription vmstate_vga_endian = {
2066 .name = "vga.endian",
2067 .version_id = 1,
2068 .minimum_version_id = 1,
2069 .needed = vga_endian_state_needed,
2070 .fields = (VMStateField[]) {
2071 VMSTATE_BOOL(big_endian_fb, VGACommonState),
2072 VMSTATE_END_OF_LIST()
2073 }
2074 };
2075
2076 const VMStateDescription vmstate_vga_common = {
2077 .name = "vga",
2078 .version_id = 2,
2079 .minimum_version_id = 2,
2080 .post_load = vga_common_post_load,
2081 .fields = (VMStateField[]) {
2082 VMSTATE_UINT32(latch, VGACommonState),
2083 VMSTATE_UINT8(sr_index, VGACommonState),
2084 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2085 VMSTATE_UINT8(gr_index, VGACommonState),
2086 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2087 VMSTATE_UINT8(ar_index, VGACommonState),
2088 VMSTATE_BUFFER(ar, VGACommonState),
2089 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2090 VMSTATE_UINT8(cr_index, VGACommonState),
2091 VMSTATE_BUFFER(cr, VGACommonState),
2092 VMSTATE_UINT8(msr, VGACommonState),
2093 VMSTATE_UINT8(fcr, VGACommonState),
2094 VMSTATE_UINT8(st00, VGACommonState),
2095 VMSTATE_UINT8(st01, VGACommonState),
2096
2097 VMSTATE_UINT8(dac_state, VGACommonState),
2098 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2099 VMSTATE_UINT8(dac_read_index, VGACommonState),
2100 VMSTATE_UINT8(dac_write_index, VGACommonState),
2101 VMSTATE_BUFFER(dac_cache, VGACommonState),
2102 VMSTATE_BUFFER(palette, VGACommonState),
2103
2104 VMSTATE_INT32(bank_offset, VGACommonState),
2105 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
2106 VMSTATE_UINT16(vbe_index, VGACommonState),
2107 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2108 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2109 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2110 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
2111 VMSTATE_END_OF_LIST()
2112 },
2113 .subsections = (const VMStateDescription*[]) {
2114 &vmstate_vga_endian,
2115 NULL
2116 }
2117 };
2118
2119 static const GraphicHwOps vga_ops = {
2120 .invalidate = vga_invalidate_display,
2121 .gfx_update = vga_update_display,
2122 .text_update = vga_update_text,
2123 };
2124
2125 static inline uint32_t uint_clamp(uint32_t val, uint32_t vmin, uint32_t vmax)
2126 {
2127 if (val < vmin) {
2128 return vmin;
2129 }
2130 if (val > vmax) {
2131 return vmax;
2132 }
2133 return val;
2134 }
2135
2136 void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate)
2137 {
2138 int i, j, v, b;
2139
2140 for(i = 0;i < 256; i++) {
2141 v = 0;
2142 for(j = 0; j < 8; j++) {
2143 v |= ((i >> j) & 1) << (j * 4);
2144 }
2145 expand4[i] = v;
2146
2147 v = 0;
2148 for(j = 0; j < 4; j++) {
2149 v |= ((i >> (2 * j)) & 3) << (j * 4);
2150 }
2151 expand2[i] = v;
2152 }
2153 for(i = 0; i < 16; i++) {
2154 v = 0;
2155 for(j = 0; j < 4; j++) {
2156 b = ((i >> j) & 1);
2157 v |= b << (2 * j);
2158 v |= b << (2 * j + 1);
2159 }
2160 expand4to8[i] = v;
2161 }
2162
2163 s->vram_size_mb = uint_clamp(s->vram_size_mb, 1, 512);
2164 s->vram_size_mb = pow2ceil(s->vram_size_mb);
2165 s->vram_size = s->vram_size_mb << 20;
2166
2167 if (!s->vbe_size) {
2168 s->vbe_size = s->vram_size;
2169 }
2170
2171 s->is_vbe_vmstate = 1;
2172 memory_region_init_ram(&s->vram, obj, "vga.vram", s->vram_size,
2173 &error_fatal);
2174 vmstate_register_ram(&s->vram, global_vmstate ? NULL : DEVICE(obj));
2175 xen_register_framebuffer(&s->vram);
2176 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
2177 s->get_bpp = vga_get_bpp;
2178 s->get_offsets = vga_get_offsets;
2179 s->get_resolution = vga_get_resolution;
2180 s->hw_ops = &vga_ops;
2181 switch (vga_retrace_method) {
2182 case VGA_RETRACE_DUMB:
2183 s->retrace = vga_dumb_retrace;
2184 s->update_retrace_info = vga_dumb_update_retrace_info;
2185 break;
2186
2187 case VGA_RETRACE_PRECISE:
2188 s->retrace = vga_precise_retrace;
2189 s->update_retrace_info = vga_precise_update_retrace_info;
2190 break;
2191 }
2192
2193 /*
2194 * Set default fb endian based on target, could probably be turned
2195 * into a device attribute set by the machine/platform to remove
2196 * all target endian dependencies from this file.
2197 */
2198 #ifdef TARGET_WORDS_BIGENDIAN
2199 s->default_endian_fb = true;
2200 #else
2201 s->default_endian_fb = false;
2202 #endif
2203 vga_dirty_log_start(s);
2204 }
2205
2206 static const MemoryRegionPortio vga_portio_list[] = {
2207 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2208 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2209 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2210 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2211 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2212 PORTIO_END_OF_LIST(),
2213 };
2214
2215 static const MemoryRegionPortio vbe_portio_list[] = {
2216 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2217 # ifdef TARGET_I386
2218 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2219 # endif
2220 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2221 PORTIO_END_OF_LIST(),
2222 };
2223
2224 /* Used by both ISA and PCI */
2225 MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
2226 const MemoryRegionPortio **vga_ports,
2227 const MemoryRegionPortio **vbe_ports)
2228 {
2229 MemoryRegion *vga_mem;
2230
2231 *vga_ports = vga_portio_list;
2232 *vbe_ports = vbe_portio_list;
2233
2234 vga_mem = g_malloc(sizeof(*vga_mem));
2235 memory_region_init_io(vga_mem, obj, &vga_mem_ops, s,
2236 "vga-lowmem", 0x20000);
2237 memory_region_set_flush_coalesced(vga_mem);
2238
2239 return vga_mem;
2240 }
2241
2242 void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
2243 MemoryRegion *address_space_io, bool init_vga_ports)
2244 {
2245 MemoryRegion *vga_io_memory;
2246 const MemoryRegionPortio *vga_ports, *vbe_ports;
2247
2248 qemu_register_reset(vga_reset, s);
2249
2250 s->bank_offset = 0;
2251
2252 s->legacy_address_space = address_space;
2253
2254 vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports);
2255 memory_region_add_subregion_overlap(address_space,
2256 0x000a0000,
2257 vga_io_memory,
2258 1);
2259 memory_region_set_coalescing(vga_io_memory);
2260 if (init_vga_ports) {
2261 portio_list_init(&s->vga_port_list, obj, vga_ports, s, "vga");
2262 portio_list_set_flush_coalesced(&s->vga_port_list);
2263 portio_list_add(&s->vga_port_list, address_space_io, 0x3b0);
2264 }
2265 if (vbe_ports) {
2266 portio_list_init(&s->vbe_port_list, obj, vbe_ports, s, "vbe");
2267 portio_list_add(&s->vbe_port_list, address_space_io, 0x1ce);
2268 }
2269 }
2270
2271 void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *system_memory)
2272 {
2273 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2274 * so use an alias to avoid double-mapping the same region.
2275 */
2276 memory_region_init_alias(&s->vram_vbe, obj, "vram.vbe",
2277 &s->vram, 0, memory_region_size(&s->vram));
2278 /* XXX: use optimized standard vga accesses */
2279 memory_region_add_subregion(system_memory,
2280 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2281 &s->vram_vbe);
2282 s->vbe_mapped = 1;
2283 }
AR7 emulation for QEMU