4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
23 #include "exec/helper-proto.h"
24 #include "internals.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
28 #define SIGNBIT (uint32_t)0x80000000
29 #define SIGNBIT64 ((uint64_t)1 << 63)
31 static void QEMU_NORETURN
32 raise_exception(CPUARMState
*env
, uint32_t excp
,
33 uint32_t syndrome
, uint32_t target_el
)
35 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
37 assert(!excp_is_internal(excp
));
38 cs
->exception_index
= excp
;
39 env
->exception
.syndrome
= syndrome
;
40 env
->exception
.target_el
= target_el
;
44 static int exception_target_el(CPUARMState
*env
)
46 int target_el
= MAX(1, arm_current_el(env
));
48 /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
49 * to EL3 in this case.
51 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3) && target_el
== 1) {
58 uint32_t HELPER(neon_tbl
)(CPUARMState
*env
, uint32_t ireg
, uint32_t def
,
59 uint32_t rn
, uint32_t maxindex
)
66 table
= (uint64_t *)&env
->vfp
.regs
[rn
];
68 for (shift
= 0; shift
< 32; shift
+= 8) {
69 index
= (ireg
>> shift
) & 0xff;
70 if (index
< maxindex
) {
71 tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
74 val
|= def
& (0xff << shift
);
80 #if !defined(CONFIG_USER_ONLY)
82 static inline uint32_t merge_syn_data_abort(uint32_t template_syn
,
83 unsigned int target_el
,
84 bool same_el
, bool ea
,
85 bool s1ptw
, bool is_write
,
90 /* ISV is only set for data aborts routed to EL2 and
91 * never for stage-1 page table walks faulting on stage 2.
93 * Furthermore, ISV is only set for certain kinds of load/stores.
94 * If the template syndrome does not have ISV set, we should leave
97 * See ARMv8 specs, D7-1974:
98 * ISS encoding for an exception from a Data Abort, the
101 if (!(template_syn
& ARM_EL_ISV
) || target_el
!= 2 || s1ptw
) {
102 syn
= syn_data_abort_no_iss(same_el
,
103 ea
, 0, s1ptw
, is_write
, fsc
);
105 /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
106 * syndrome created at translation time.
107 * Now we create the runtime syndrome with the remaining fields.
109 syn
= syn_data_abort_with_iss(same_el
,
111 ea
, 0, s1ptw
, is_write
, fsc
,
113 /* Merge the runtime syndrome with the template syndrome. */
119 static void deliver_fault(ARMCPU
*cpu
, vaddr addr
, MMUAccessType access_type
,
120 int mmu_idx
, ARMMMUFaultInfo
*fi
)
122 CPUARMState
*env
= &cpu
->env
;
125 uint32_t syn
, exc
, fsr
, fsc
;
126 ARMMMUIdx arm_mmu_idx
= core_to_arm_mmu_idx(env
, mmu_idx
);
128 target_el
= exception_target_el(env
);
131 env
->cp15
.hpfar_el2
= extract64(fi
->s2addr
, 12, 47) << 4;
133 same_el
= (arm_current_el(env
) == target_el
);
135 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
136 arm_s1_regime_using_lpae_format(env
, arm_mmu_idx
)) {
137 /* LPAE format fault status register : bottom 6 bits are
138 * status code in the same form as needed for syndrome
140 fsr
= arm_fi_to_lfsc(fi
);
141 fsc
= extract32(fsr
, 0, 6);
143 fsr
= arm_fi_to_sfsc(fi
);
144 /* Short format FSR : this fault will never actually be reported
145 * to an EL that uses a syndrome register. Use a (currently)
146 * reserved FSR code in case the constructed syndrome does leak
147 * into the guest somehow.
152 if (access_type
== MMU_INST_FETCH
) {
153 syn
= syn_insn_abort(same_el
, fi
->ea
, fi
->s1ptw
, fsc
);
154 exc
= EXCP_PREFETCH_ABORT
;
156 syn
= merge_syn_data_abort(env
->exception
.syndrome
, target_el
,
157 same_el
, fi
->ea
, fi
->s1ptw
,
158 access_type
== MMU_DATA_STORE
,
160 if (access_type
== MMU_DATA_STORE
161 && arm_feature(env
, ARM_FEATURE_V6
)) {
164 exc
= EXCP_DATA_ABORT
;
167 env
->exception
.vaddress
= addr
;
168 env
->exception
.fsr
= fsr
;
169 raise_exception(env
, exc
, syn
, target_el
);
172 /* try to fill the TLB and return an exception if error. If retaddr is
173 * NULL, it means that the function was called in C code (i.e. not
174 * from generated code or from helper.c)
176 void tlb_fill(CPUState
*cs
, target_ulong addr
, MMUAccessType access_type
,
177 int mmu_idx
, uintptr_t retaddr
)
180 ARMMMUFaultInfo fi
= {};
182 ret
= arm_tlb_fill(cs
, addr
, access_type
, mmu_idx
, &fi
);
184 ARMCPU
*cpu
= ARM_CPU(cs
);
186 /* now we have a real cpu fault */
187 cpu_restore_state(cs
, retaddr
);
189 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
193 /* Raise a data fault alignment exception for the specified virtual address */
194 void arm_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
195 MMUAccessType access_type
,
196 int mmu_idx
, uintptr_t retaddr
)
198 ARMCPU
*cpu
= ARM_CPU(cs
);
199 ARMMMUFaultInfo fi
= {};
201 /* now we have a real cpu fault */
202 cpu_restore_state(cs
, retaddr
);
204 fi
.type
= ARMFault_Alignment
;
205 deliver_fault(cpu
, vaddr
, access_type
, mmu_idx
, &fi
);
208 /* arm_cpu_do_transaction_failed: handle a memory system error response
209 * (eg "no device/memory present at address") by raising an external abort
212 void arm_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
213 vaddr addr
, unsigned size
,
214 MMUAccessType access_type
,
215 int mmu_idx
, MemTxAttrs attrs
,
216 MemTxResult response
, uintptr_t retaddr
)
218 ARMCPU
*cpu
= ARM_CPU(cs
);
219 ARMMMUFaultInfo fi
= {};
221 /* now we have a real cpu fault */
222 cpu_restore_state(cs
, retaddr
);
224 /* The EA bit in syndromes and fault status registers is an
225 * IMPDEF classification of external aborts. ARM implementations
226 * usually use this to indicate AXI bus Decode error (0) or
227 * Slave error (1); in QEMU we follow that.
229 fi
.ea
= (response
!= MEMTX_DECODE_ERROR
);
230 fi
.type
= ARMFault_SyncExternal
;
231 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
234 #endif /* !defined(CONFIG_USER_ONLY) */
236 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
238 uint32_t res
= a
+ b
;
239 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
244 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
246 uint32_t res
= a
+ b
;
247 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
249 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
254 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
256 uint32_t res
= a
- b
;
257 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
259 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
264 uint32_t HELPER(double_saturate
)(CPUARMState
*env
, int32_t val
)
267 if (val
>= 0x40000000) {
270 } else if (val
<= (int32_t)0xc0000000) {
279 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
281 uint32_t res
= a
+ b
;
289 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
291 uint32_t res
= a
- b
;
299 /* Signed saturation. */
300 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
306 mask
= (1u << shift
) - 1;
310 } else if (top
< -1) {
317 /* Unsigned saturation. */
318 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
322 max
= (1u << shift
) - 1;
326 } else if (val
> max
) {
333 /* Signed saturate. */
334 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
336 return do_ssat(env
, x
, shift
);
339 /* Dual halfword signed saturate. */
340 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
344 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
345 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
349 /* Unsigned saturate. */
350 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
352 return do_usat(env
, x
, shift
);
355 /* Dual halfword unsigned saturate. */
356 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
360 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
361 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
365 void HELPER(setend
)(CPUARMState
*env
)
367 env
->uncached_cpsr
^= CPSR_E
;
370 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
371 * The function returns the target EL (1-3) if the instruction is to be trapped;
372 * otherwise it returns 0 indicating it is not trapped.
374 static inline int check_wfx_trap(CPUARMState
*env
, bool is_wfe
)
376 int cur_el
= arm_current_el(env
);
379 if (arm_feature(env
, ARM_FEATURE_M
)) {
380 /* M profile cores can never trap WFI/WFE. */
384 /* If we are currently in EL0 then we need to check if SCTLR is set up for
385 * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
387 if (cur_el
< 1 && arm_feature(env
, ARM_FEATURE_V8
)) {
390 mask
= is_wfe
? SCTLR_nTWE
: SCTLR_nTWI
;
391 if (arm_is_secure_below_el3(env
) && !arm_el_is_aa64(env
, 3)) {
392 /* Secure EL0 and Secure PL1 is at EL3 */
398 if (!(env
->cp15
.sctlr_el
[target_el
] & mask
)) {
403 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
404 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
405 * bits will be zero indicating no trap.
407 if (cur_el
< 2 && !arm_is_secure(env
)) {
408 mask
= (is_wfe
) ? HCR_TWE
: HCR_TWI
;
409 if (env
->cp15
.hcr_el2
& mask
) {
414 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
416 mask
= (is_wfe
) ? SCR_TWE
: SCR_TWI
;
417 if (env
->cp15
.scr_el3
& mask
) {
425 void HELPER(wfi
)(CPUARMState
*env
, uint32_t insn_len
)
427 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
428 int target_el
= check_wfx_trap(env
, false);
430 if (cpu_has_work(cs
)) {
431 /* Don't bother to go into our "low power state" if
432 * we would just wake up immediately.
439 raise_exception(env
, EXCP_UDEF
, syn_wfx(1, 0xe, 0, insn_len
== 2),
443 cs
->exception_index
= EXCP_HLT
;
448 void QEMU_NORETURN
HELPER(wfe
)(CPUARMState
*env
)
450 /* This is a hint instruction that is semantically different
451 * from YIELD even though we currently implement it identically.
452 * Don't actually halt the CPU, just yield back to top
453 * level loop. This is not going into a "low power state"
454 * (ie halting until some event occurs), so we never take
455 * a configurable trap to a different exception level.
460 void QEMU_NORETURN
HELPER(yield
)(CPUARMState
*env
)
462 ARMCPU
*cpu
= arm_env_get_cpu(env
);
463 CPUState
*cs
= CPU(cpu
);
465 /* This is a non-trappable hint instruction that generally indicates
466 * that the guest is currently busy-looping. Yield control back to the
467 * top level loop so that a more deserving VCPU has a chance to run.
469 cs
->exception_index
= EXCP_YIELD
;
473 /* Raise an internal-to-QEMU exception. This is limited to only
474 * those EXCP values which are special cases for QEMU to interrupt
475 * execution and not to be used for exceptions which are passed to
476 * the guest (those must all have syndrome information and thus should
477 * use exception_with_syndrome).
479 void QEMU_NORETURN
HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
481 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
483 assert(excp_is_internal(excp
));
484 cs
->exception_index
= excp
;
488 /* Raise an exception with the specified syndrome register value */
490 HELPER(exception_with_syndrome
)(CPUARMState
*env
, uint32_t excp
,
491 uint32_t syndrome
, uint32_t target_el
)
493 raise_exception(env
, excp
, syndrome
, target_el
);
496 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
498 return cpsr_read(env
) & ~(CPSR_EXEC
| CPSR_RESERVED
);
501 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
503 cpsr_write(env
, val
, mask
, CPSRWriteByInstr
);
506 /* Write the CPSR for a 32-bit exception return */
507 void HELPER(cpsr_write_eret
)(CPUARMState
*env
, uint32_t val
)
509 cpsr_write(env
, val
, CPSR_ERET_MASK
, CPSRWriteExceptionReturn
);
511 /* Generated code has already stored the new PC value, but
512 * without masking out its low bits, because which bits need
513 * masking depends on whether we're returning to Thumb or ARM
514 * state. Do the masking now.
516 env
->regs
[15] &= (env
->thumb
? ~1 : ~3);
518 qemu_mutex_lock_iothread();
519 arm_call_el_change_hook(arm_env_get_cpu(env
));
520 qemu_mutex_unlock_iothread();
523 /* Access to user mode registers from privileged modes. */
524 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
529 val
= env
->banked_r13
[BANK_USRSYS
];
530 } else if (regno
== 14) {
531 val
= env
->banked_r14
[BANK_USRSYS
];
532 } else if (regno
>= 8
533 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
534 val
= env
->usr_regs
[regno
- 8];
536 val
= env
->regs
[regno
];
541 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
544 env
->banked_r13
[BANK_USRSYS
] = val
;
545 } else if (regno
== 14) {
546 env
->banked_r14
[BANK_USRSYS
] = val
;
547 } else if (regno
>= 8
548 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
549 env
->usr_regs
[regno
- 8] = val
;
551 env
->regs
[regno
] = val
;
555 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
557 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
560 env
->banked_r13
[bank_number(mode
)] = val
;
564 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
566 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_SYS
) {
567 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
568 * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
570 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
571 exception_target_el(env
));
574 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
575 return env
->regs
[13];
577 return env
->banked_r13
[bank_number(mode
)];
581 static void msr_mrs_banked_exc_checks(CPUARMState
*env
, uint32_t tgtmode
,
584 /* Raise an exception if the requested access is one of the UNPREDICTABLE
585 * cases; otherwise return. This broadly corresponds to the pseudocode
586 * BankedRegisterAccessValid() and SPSRAccessValid(),
587 * except that we have already handled some cases at translate time.
589 int curmode
= env
->uncached_cpsr
& CPSR_M
;
591 if (curmode
== tgtmode
) {
595 if (tgtmode
== ARM_CPU_MODE_USR
) {
598 if (curmode
!= ARM_CPU_MODE_FIQ
) {
603 if (curmode
== ARM_CPU_MODE_SYS
) {
608 if (curmode
== ARM_CPU_MODE_HYP
|| curmode
== ARM_CPU_MODE_SYS
) {
617 if (tgtmode
== ARM_CPU_MODE_HYP
) {
619 case 17: /* ELR_Hyp */
620 if (curmode
!= ARM_CPU_MODE_HYP
&& curmode
!= ARM_CPU_MODE_MON
) {
625 if (curmode
!= ARM_CPU_MODE_MON
) {
635 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
636 exception_target_el(env
));
639 void HELPER(msr_banked
)(CPUARMState
*env
, uint32_t value
, uint32_t tgtmode
,
642 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
646 env
->banked_spsr
[bank_number(tgtmode
)] = value
;
648 case 17: /* ELR_Hyp */
649 env
->elr_el
[2] = value
;
652 env
->banked_r13
[bank_number(tgtmode
)] = value
;
655 env
->banked_r14
[bank_number(tgtmode
)] = value
;
659 case ARM_CPU_MODE_USR
:
660 env
->usr_regs
[regno
- 8] = value
;
662 case ARM_CPU_MODE_FIQ
:
663 env
->fiq_regs
[regno
- 8] = value
;
666 g_assert_not_reached();
670 g_assert_not_reached();
674 uint32_t HELPER(mrs_banked
)(CPUARMState
*env
, uint32_t tgtmode
, uint32_t regno
)
676 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
680 return env
->banked_spsr
[bank_number(tgtmode
)];
681 case 17: /* ELR_Hyp */
682 return env
->elr_el
[2];
684 return env
->banked_r13
[bank_number(tgtmode
)];
686 return env
->banked_r14
[bank_number(tgtmode
)];
689 case ARM_CPU_MODE_USR
:
690 return env
->usr_regs
[regno
- 8];
691 case ARM_CPU_MODE_FIQ
:
692 return env
->fiq_regs
[regno
- 8];
694 g_assert_not_reached();
697 g_assert_not_reached();
701 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
,
704 const ARMCPRegInfo
*ri
= rip
;
707 if (arm_feature(env
, ARM_FEATURE_XSCALE
) && ri
->cp
< 14
708 && extract32(env
->cp15
.c15_cpar
, ri
->cp
, 1) == 0) {
709 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
716 switch (ri
->accessfn(env
, ri
, isread
)) {
720 target_el
= exception_target_el(env
);
722 case CP_ACCESS_TRAP_EL2
:
723 /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
724 * a bug in the access function.
726 assert(!arm_is_secure(env
) && arm_current_el(env
) != 3);
729 case CP_ACCESS_TRAP_EL3
:
732 case CP_ACCESS_TRAP_UNCATEGORIZED
:
733 target_el
= exception_target_el(env
);
734 syndrome
= syn_uncategorized();
736 case CP_ACCESS_TRAP_UNCATEGORIZED_EL2
:
738 syndrome
= syn_uncategorized();
740 case CP_ACCESS_TRAP_UNCATEGORIZED_EL3
:
742 syndrome
= syn_uncategorized();
744 case CP_ACCESS_TRAP_FP_EL2
:
746 /* Since we are an implementation that takes exceptions on a trapped
747 * conditional insn only if the insn has passed its condition code
748 * check, we take the IMPDEF choice to always report CV=1 COND=0xe
749 * (which is also the required value for AArch64 traps).
751 syndrome
= syn_fp_access_trap(1, 0xe, false);
753 case CP_ACCESS_TRAP_FP_EL3
:
755 syndrome
= syn_fp_access_trap(1, 0xe, false);
758 g_assert_not_reached();
761 raise_exception(env
, EXCP_UDEF
, syndrome
, target_el
);
764 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
766 const ARMCPRegInfo
*ri
= rip
;
768 if (ri
->type
& ARM_CP_IO
) {
769 qemu_mutex_lock_iothread();
770 ri
->writefn(env
, ri
, value
);
771 qemu_mutex_unlock_iothread();
773 ri
->writefn(env
, ri
, value
);
777 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
779 const ARMCPRegInfo
*ri
= rip
;
782 if (ri
->type
& ARM_CP_IO
) {
783 qemu_mutex_lock_iothread();
784 res
= ri
->readfn(env
, ri
);
785 qemu_mutex_unlock_iothread();
787 res
= ri
->readfn(env
, ri
);
793 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
795 const ARMCPRegInfo
*ri
= rip
;
797 if (ri
->type
& ARM_CP_IO
) {
798 qemu_mutex_lock_iothread();
799 ri
->writefn(env
, ri
, value
);
800 qemu_mutex_unlock_iothread();
802 ri
->writefn(env
, ri
, value
);
806 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
808 const ARMCPRegInfo
*ri
= rip
;
811 if (ri
->type
& ARM_CP_IO
) {
812 qemu_mutex_lock_iothread();
813 res
= ri
->readfn(env
, ri
);
814 qemu_mutex_unlock_iothread();
816 res
= ri
->readfn(env
, ri
);
822 void HELPER(msr_i_pstate
)(CPUARMState
*env
, uint32_t op
, uint32_t imm
)
824 /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
825 * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
826 * to catch that case at translate time.
828 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
829 uint32_t syndrome
= syn_aa64_sysregtrap(0, extract32(op
, 0, 3),
830 extract32(op
, 3, 3), 4,
832 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
836 case 0x05: /* SPSel */
837 update_spsel(env
, imm
);
839 case 0x1e: /* DAIFSet */
840 env
->daif
|= (imm
<< 6) & PSTATE_DAIF
;
842 case 0x1f: /* DAIFClear */
843 env
->daif
&= ~((imm
<< 6) & PSTATE_DAIF
);
846 g_assert_not_reached();
850 void HELPER(clear_pstate_ss
)(CPUARMState
*env
)
852 env
->pstate
&= ~PSTATE_SS
;
855 void HELPER(pre_hvc
)(CPUARMState
*env
)
857 ARMCPU
*cpu
= arm_env_get_cpu(env
);
858 int cur_el
= arm_current_el(env
);
859 /* FIXME: Use actual secure state. */
863 if (arm_is_psci_call(cpu
, EXCP_HVC
)) {
864 /* If PSCI is enabled and this looks like a valid PSCI call then
865 * that overrides the architecturally mandated HVC behaviour.
870 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
871 /* If EL2 doesn't exist, HVC always UNDEFs */
873 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
874 /* EL3.HCE has priority over EL2.HCD. */
875 undef
= !(env
->cp15
.scr_el3
& SCR_HCE
);
877 undef
= env
->cp15
.hcr_el2
& HCR_HCD
;
880 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
881 * For ARMv8/AArch64, HVC is allowed in EL3.
882 * Note that we've already trapped HVC from EL0 at translation
885 if (secure
&& (!is_a64(env
) || cur_el
== 1)) {
890 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
891 exception_target_el(env
));
895 void HELPER(pre_smc
)(CPUARMState
*env
, uint32_t syndrome
)
897 ARMCPU
*cpu
= arm_env_get_cpu(env
);
898 int cur_el
= arm_current_el(env
);
899 bool secure
= arm_is_secure(env
);
900 bool smd
= env
->cp15
.scr_el3
& SCR_SMD
;
901 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
902 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
903 * extensions, SMD only applies to NS state.
904 * On ARMv7 without the Virtualization extensions, the SMD bit
905 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
906 * so we need not special case this here.
908 bool undef
= arm_feature(env
, ARM_FEATURE_AARCH64
) ? smd
: smd
&& !secure
;
910 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
911 cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
912 /* If we have no EL3 then SMC always UNDEFs and can't be
913 * trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3
914 * firmware within QEMU, and we want an EL2 guest to be able
915 * to forbid its EL1 from making PSCI calls into QEMU's
916 * "firmware" via HCR.TSC, so for these purposes treat
917 * PSCI-via-SMC as implying an EL3.
920 } else if (!secure
&& cur_el
== 1 && (env
->cp15
.hcr_el2
& HCR_TSC
)) {
921 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
922 * We also want an EL2 guest to be able to forbid its EL1 from
923 * making PSCI calls into QEMU's "firmware" via HCR.TSC.
925 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);
928 /* If PSCI is enabled and this looks like a valid PSCI call then
929 * suppress the UNDEF -- we'll catch the SMC exception and
930 * implement the PSCI call behaviour there.
932 if (undef
&& !arm_is_psci_call(cpu
, EXCP_SMC
)) {
933 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
934 exception_target_el(env
));
938 static int el_from_spsr(uint32_t spsr
)
940 /* Return the exception level that this SPSR is requesting a return to,
941 * or -1 if it is invalid (an illegal return)
943 if (spsr
& PSTATE_nRW
) {
944 switch (spsr
& CPSR_M
) {
945 case ARM_CPU_MODE_USR
:
947 case ARM_CPU_MODE_HYP
:
949 case ARM_CPU_MODE_FIQ
:
950 case ARM_CPU_MODE_IRQ
:
951 case ARM_CPU_MODE_SVC
:
952 case ARM_CPU_MODE_ABT
:
953 case ARM_CPU_MODE_UND
:
954 case ARM_CPU_MODE_SYS
:
956 case ARM_CPU_MODE_MON
:
957 /* Returning to Mon from AArch64 is never possible,
958 * so this is an illegal return.
964 if (extract32(spsr
, 1, 1)) {
965 /* Return with reserved M[1] bit set */
968 if (extract32(spsr
, 0, 4) == 1) {
969 /* return to EL0 with M[0] bit set */
972 return extract32(spsr
, 2, 2);
976 void HELPER(exception_return
)(CPUARMState
*env
)
978 int cur_el
= arm_current_el(env
);
979 unsigned int spsr_idx
= aarch64_banked_spsr_index(cur_el
);
980 uint32_t spsr
= env
->banked_spsr
[spsr_idx
];
982 bool return_to_aa64
= (spsr
& PSTATE_nRW
) == 0;
984 aarch64_save_sp(env
, cur_el
);
986 arm_clear_exclusive(env
);
988 /* We must squash the PSTATE.SS bit to zero unless both of the
990 * 1. debug exceptions are currently disabled
991 * 2. singlestep will be active in the EL we return to
992 * We check 1 here and 2 after we've done the pstate/cpsr write() to
993 * transition to the EL we're going to.
995 if (arm_generate_debug_exceptions(env
)) {
999 new_el
= el_from_spsr(spsr
);
1001 goto illegal_return
;
1004 || (new_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
))) {
1005 /* Disallow return to an EL which is unimplemented or higher
1006 * than the current one.
1008 goto illegal_return
;
1011 if (new_el
!= 0 && arm_el_is_aa64(env
, new_el
) != return_to_aa64
) {
1012 /* Return to an EL which is configured for a different register width */
1013 goto illegal_return
;
1016 if (new_el
== 2 && arm_is_secure_below_el3(env
)) {
1017 /* Return to the non-existent secure-EL2 */
1018 goto illegal_return
;
1021 if (new_el
== 1 && (env
->cp15
.hcr_el2
& HCR_TGE
)
1022 && !arm_is_secure_below_el3(env
)) {
1023 goto illegal_return
;
1026 if (!return_to_aa64
) {
1028 /* We do a raw CPSR write because aarch64_sync_64_to_32()
1029 * will sort the register banks out for us, and we've already
1030 * caught all the bad-mode cases in el_from_spsr().
1032 cpsr_write(env
, spsr
, ~0, CPSRWriteRaw
);
1033 if (!arm_singlestep_active(env
)) {
1034 env
->uncached_cpsr
&= ~PSTATE_SS
;
1036 aarch64_sync_64_to_32(env
);
1038 if (spsr
& CPSR_T
) {
1039 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x1;
1041 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x3;
1043 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1044 "AArch32 EL%d PC 0x%" PRIx32
"\n",
1045 cur_el
, new_el
, env
->regs
[15]);
1048 pstate_write(env
, spsr
);
1049 if (!arm_singlestep_active(env
)) {
1050 env
->pstate
&= ~PSTATE_SS
;
1052 aarch64_restore_sp(env
, new_el
);
1053 env
->pc
= env
->elr_el
[cur_el
];
1054 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1055 "AArch64 EL%d PC 0x%" PRIx64
"\n",
1056 cur_el
, new_el
, env
->pc
);
1059 qemu_mutex_lock_iothread();
1060 arm_call_el_change_hook(arm_env_get_cpu(env
));
1061 qemu_mutex_unlock_iothread();
1066 /* Illegal return events of various kinds have architecturally
1067 * mandated behaviour:
1068 * restore NZCV and DAIF from SPSR_ELx
1070 * restore PC from ELR_ELx
1071 * no change to exception level, execution state or stack pointer
1073 env
->pstate
|= PSTATE_IL
;
1074 env
->pc
= env
->elr_el
[cur_el
];
1075 spsr
&= PSTATE_NZCV
| PSTATE_DAIF
;
1076 spsr
|= pstate_read(env
) & ~(PSTATE_NZCV
| PSTATE_DAIF
);
1077 pstate_write(env
, spsr
);
1078 if (!arm_singlestep_active(env
)) {
1079 env
->pstate
&= ~PSTATE_SS
;
1081 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal exception return at EL%d: "
1082 "resuming execution at 0x%" PRIx64
"\n", cur_el
, env
->pc
);
1085 /* Return true if the linked breakpoint entry lbn passes its checks */
1086 static bool linked_bp_matches(ARMCPU
*cpu
, int lbn
)
1088 CPUARMState
*env
= &cpu
->env
;
1089 uint64_t bcr
= env
->cp15
.dbgbcr
[lbn
];
1090 int brps
= extract32(cpu
->dbgdidr
, 24, 4);
1091 int ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
1093 uint32_t contextidr
;
1095 /* Links to unimplemented or non-context aware breakpoints are
1096 * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
1097 * as if linked to an UNKNOWN context-aware breakpoint (in which
1098 * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
1099 * We choose the former.
1101 if (lbn
> brps
|| lbn
< (brps
- ctx_cmps
)) {
1105 bcr
= env
->cp15
.dbgbcr
[lbn
];
1107 if (extract64(bcr
, 0, 1) == 0) {
1108 /* Linked breakpoint disabled : generate no events */
1112 bt
= extract64(bcr
, 20, 4);
1114 /* We match the whole register even if this is AArch32 using the
1115 * short descriptor format (in which case it holds both PROCID and ASID),
1116 * since we don't implement the optional v7 context ID masking.
1118 contextidr
= extract64(env
->cp15
.contextidr_el
[1], 0, 32);
1121 case 3: /* linked context ID match */
1122 if (arm_current_el(env
) > 1) {
1123 /* Context matches never fire in EL2 or (AArch64) EL3 */
1126 return (contextidr
== extract64(env
->cp15
.dbgbvr
[lbn
], 0, 32));
1127 case 5: /* linked address mismatch (reserved in AArch64) */
1128 case 9: /* linked VMID match (reserved if no EL2) */
1129 case 11: /* linked context ID and VMID match (reserved if no EL2) */
1131 /* Links to Unlinked context breakpoints must generate no
1132 * events; we choose to do the same for reserved values too.
1140 static bool bp_wp_matches(ARMCPU
*cpu
, int n
, bool is_wp
)
1142 CPUARMState
*env
= &cpu
->env
;
1144 int pac
, hmc
, ssc
, wt
, lbn
;
1145 /* Note that for watchpoints the check is against the CPU security
1146 * state, not the S/NS attribute on the offending data access.
1148 bool is_secure
= arm_is_secure(env
);
1149 int access_el
= arm_current_el(env
);
1152 CPUWatchpoint
*wp
= env
->cpu_watchpoint
[n
];
1154 if (!wp
|| !(wp
->flags
& BP_WATCHPOINT_HIT
)) {
1157 cr
= env
->cp15
.dbgwcr
[n
];
1158 if (wp
->hitattrs
.user
) {
1159 /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
1160 * match watchpoints as if they were accesses done at EL0, even if
1161 * the CPU is at EL1 or higher.
1166 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1168 if (!env
->cpu_breakpoint
[n
] || env
->cpu_breakpoint
[n
]->pc
!= pc
) {
1171 cr
= env
->cp15
.dbgbcr
[n
];
1173 /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
1174 * enabled and that the address and access type match; for breakpoints
1175 * we know the address matched; check the remaining fields, including
1176 * linked breakpoints. We rely on WCR and BCR having the same layout
1177 * for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
1178 * Note that some combinations of {PAC, HMC, SSC} are reserved and
1179 * must act either like some valid combination or as if the watchpoint
1180 * were disabled. We choose the former, and use this together with
1181 * the fact that EL3 must always be Secure and EL2 must always be
1182 * Non-Secure to simplify the code slightly compared to the full
1183 * table in the ARM ARM.
1185 pac
= extract64(cr
, 1, 2);
1186 hmc
= extract64(cr
, 13, 1);
1187 ssc
= extract64(cr
, 14, 2);
1205 switch (access_el
) {
1213 if (extract32(pac
, 0, 1) == 0) {
1218 if (extract32(pac
, 1, 1) == 0) {
1223 g_assert_not_reached();
1226 wt
= extract64(cr
, 20, 1);
1227 lbn
= extract64(cr
, 16, 4);
1229 if (wt
&& !linked_bp_matches(cpu
, lbn
)) {
1236 static bool check_watchpoints(ARMCPU
*cpu
)
1238 CPUARMState
*env
= &cpu
->env
;
1241 /* If watchpoints are disabled globally or we can't take debug
1242 * exceptions here then watchpoint firings are ignored.
1244 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1245 || !arm_generate_debug_exceptions(env
)) {
1249 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_watchpoint
); n
++) {
1250 if (bp_wp_matches(cpu
, n
, true)) {
1257 static bool check_breakpoints(ARMCPU
*cpu
)
1259 CPUARMState
*env
= &cpu
->env
;
1262 /* If breakpoints are disabled globally or we can't take debug
1263 * exceptions here then breakpoint firings are ignored.
1265 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1266 || !arm_generate_debug_exceptions(env
)) {
1270 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_breakpoint
); n
++) {
1271 if (bp_wp_matches(cpu
, n
, false)) {
1278 void HELPER(check_breakpoints
)(CPUARMState
*env
)
1280 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1282 if (check_breakpoints(cpu
)) {
1283 HELPER(exception_internal(env
, EXCP_DEBUG
));
1287 bool arm_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
)
1289 /* Called by core code when a CPU watchpoint fires; need to check if this
1290 * is also an architectural watchpoint match.
1292 ARMCPU
*cpu
= ARM_CPU(cs
);
1294 return check_watchpoints(cpu
);
1297 vaddr
arm_adjust_watchpoint_address(CPUState
*cs
, vaddr addr
, int len
)
1299 ARMCPU
*cpu
= ARM_CPU(cs
);
1300 CPUARMState
*env
= &cpu
->env
;
1302 /* In BE32 system mode, target memory is stored byteswapped (on a
1303 * little-endian host system), and by the time we reach here (via an
1304 * opcode helper) the addresses of subword accesses have been adjusted
1305 * to account for that, which means that watchpoints will not match.
1306 * Undo the adjustment here.
1308 if (arm_sctlr_b(env
)) {
1311 } else if (len
== 2) {
1319 void arm_debug_excp_handler(CPUState
*cs
)
1321 /* Called by core code when a watchpoint or breakpoint fires;
1322 * need to check which one and raise the appropriate exception.
1324 ARMCPU
*cpu
= ARM_CPU(cs
);
1325 CPUARMState
*env
= &cpu
->env
;
1326 CPUWatchpoint
*wp_hit
= cs
->watchpoint_hit
;
1329 if (wp_hit
->flags
& BP_CPU
) {
1330 bool wnr
= (wp_hit
->flags
& BP_WATCHPOINT_HIT_WRITE
) != 0;
1331 bool same_el
= arm_debug_target_el(env
) == arm_current_el(env
);
1333 cs
->watchpoint_hit
= NULL
;
1335 if (extended_addresses_enabled(env
)) {
1336 env
->exception
.fsr
= (1 << 9) | 0x22;
1338 env
->exception
.fsr
= 0x2;
1340 env
->exception
.vaddress
= wp_hit
->hitaddr
;
1341 raise_exception(env
, EXCP_DATA_ABORT
,
1342 syn_watchpoint(same_el
, 0, wnr
),
1343 arm_debug_target_el(env
));
1346 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1347 bool same_el
= (arm_debug_target_el(env
) == arm_current_el(env
));
1349 /* (1) GDB breakpoints should be handled first.
1350 * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
1351 * since singlestep is also done by generating a debug internal
1354 if (cpu_breakpoint_test(cs
, pc
, BP_GDB
)
1355 || !cpu_breakpoint_test(cs
, pc
, BP_CPU
)) {
1359 if (extended_addresses_enabled(env
)) {
1360 env
->exception
.fsr
= (1 << 9) | 0x22;
1362 env
->exception
.fsr
= 0x2;
1364 /* FAR is UNKNOWN, so doesn't need setting */
1365 raise_exception(env
, EXCP_PREFETCH_ABORT
,
1366 syn_breakpoint(same_el
),
1367 arm_debug_target_el(env
));
1371 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
1372 The only way to do that in TCG is a conditional branch, which clobbers
1373 all our temporaries. For now implement these as helper functions. */
1375 /* Similarly for variable shift instructions. */
1377 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1379 int shift
= i
& 0xff;
1386 } else if (shift
!= 0) {
1387 env
->CF
= (x
>> (32 - shift
)) & 1;
1393 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1395 int shift
= i
& 0xff;
1398 env
->CF
= (x
>> 31) & 1;
1402 } else if (shift
!= 0) {
1403 env
->CF
= (x
>> (shift
- 1)) & 1;
1409 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1411 int shift
= i
& 0xff;
1413 env
->CF
= (x
>> 31) & 1;
1414 return (int32_t)x
>> 31;
1415 } else if (shift
!= 0) {
1416 env
->CF
= (x
>> (shift
- 1)) & 1;
1417 return (int32_t)x
>> shift
;
1422 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1426 shift
= shift1
& 0x1f;
1429 env
->CF
= (x
>> 31) & 1;
1432 env
->CF
= (x
>> (shift
- 1)) & 1;
1433 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));