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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / linux-user / main.c
blob1f4027fabc3554bd0bd17db1b57fa3e80e6d011f
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu-version.h"
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qapi/error.h"
25 #include "qemu.h"
26 #include "qemu/path.h"
27 #include "qemu/config-file.h"
28 #include "qemu/cutils.h"
29 #include "qemu/help_option.h"
30 #include "cpu.h"
31 #include "exec/exec-all.h"
32 #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64)
33 #include "vsyscall.h"
34 #endif
35 #include "tcg.h"
36 #include "qemu/timer.h"
37 #include "qemu/envlist.h"
38 #include "elf.h"
39 #include "exec/log.h"
40 #include "trace/control.h"
41
42 char *exec_path;
43
44 int singlestep;
45 static const char *filename;
46 static const char *argv0;
47 static int gdbstub_port;
48 static envlist_t *envlist;
49 static const char *cpu_model;
50 unsigned long mmap_min_addr;
51 uintptr_t guest_base;
52 int have_guest_base;
53
54 #define EXCP_DUMP(env, fmt, ...) \
55 do { \
56 CPUState *cs = ENV_GET_CPU(env); \
57 fprintf(stderr, fmt , ## __VA_ARGS__); \
58 cpu_dump_state(cs, stderr, fprintf, 0); \
59 if (qemu_log_separate()) { \
60 qemu_log(fmt, ## __VA_ARGS__); \
61 log_cpu_state(cs, 0); \
62 } \
63 } while (0)
64
65 /*
66 * When running 32-on-64 we should make sure we can fit all of the possible
67 * guest address space into a contiguous chunk of virtual host memory.
68 *
69 * This way we will never overlap with our own libraries or binaries or stack
70 * or anything else that QEMU maps.
71 *
72 * Many cpus reserve the high bit (or more than one for some 64-bit cpus)
73 * of the address for the kernel. Some cpus rely on this and user space
74 * uses the high bit(s) for pointer tagging and the like. For them, we
75 * must preserve the expected address space.
76 */
77 #ifndef MAX_RESERVED_VA
78 # if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
79 # if TARGET_VIRT_ADDR_SPACE_BITS == 32 && \
80 (TARGET_LONG_BITS == 32 || defined(TARGET_ABI32))
81 /* There are a number of places where we assign reserved_va to a variable
82 of type abi_ulong and expect it to fit. Avoid the last page. */
83 # define MAX_RESERVED_VA (0xfffffffful & TARGET_PAGE_MASK)
84 # else
85 # define MAX_RESERVED_VA (1ul << TARGET_VIRT_ADDR_SPACE_BITS)
86 # endif
87 # else
88 # define MAX_RESERVED_VA 0
89 # endif
90 #endif
91
92 /* That said, reserving *too* much vm space via mmap can run into problems
93 with rlimits, oom due to page table creation, etc. We will still try it,
94 if directed by the command-line option, but not by default. */
95 #if HOST_LONG_BITS == 64 && TARGET_VIRT_ADDR_SPACE_BITS <= 32
96 unsigned long reserved_va = MAX_RESERVED_VA;
97 #else
98 uintptr_t reserved_va;
99 #endif
100
101 static void usage(int exitcode);
102
103 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
104 const char *qemu_uname_release;
105
106 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
107 we allocate a bigger stack. Need a better solution, for example
108 by remapping the process stack directly at the right place */
109 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
110
111 void gemu_log(const char *fmt, ...)
112 {
113 va_list ap;
114
115 va_start(ap, fmt);
116 vfprintf(stderr, fmt, ap);
117 va_end(ap);
118 }
119
120 #if defined(TARGET_I386)
121 int cpu_get_pic_interrupt(CPUX86State *env)
122 {
123 return -1;
124 }
125 #endif
126
127 /***********************************************************/
128 /* Helper routines for implementing atomic operations. */
129
130 /* Make sure everything is in a consistent state for calling fork(). */
131 void fork_start(void)
132 {
133 cpu_list_lock();
134 qemu_mutex_lock(&tb_ctx.tb_lock);
135 mmap_fork_start();
136 }
137
138 void fork_end(int child)
139 {
140 mmap_fork_end(child);
141 if (child) {
142 CPUState *cpu, *next_cpu;
143 /* Child processes created by fork() only have a single thread.
144 Discard information about the parent threads. */
145 CPU_FOREACH_SAFE(cpu, next_cpu) {
146 if (cpu != thread_cpu) {
147 QTAILQ_REMOVE(&cpus, cpu, node);
148 }
149 }
150 qemu_mutex_init(&tb_ctx.tb_lock);
151 qemu_init_cpu_list();
152 gdbserver_fork(thread_cpu);
153 } else {
154 qemu_mutex_unlock(&tb_ctx.tb_lock);
155 cpu_list_unlock();
156 }
157 }
158
159 #ifdef TARGET_I386
160 /***********************************************************/
161 /* CPUX86 core interface */
162
163 uint64_t cpu_get_tsc(CPUX86State *env)
164 {
165 return cpu_get_host_ticks();
166 }
167
168 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
169 int flags)
170 {
171 unsigned int e1, e2;
172 uint32_t *p;
173 e1 = (addr << 16) | (limit & 0xffff);
174 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
175 e2 |= flags;
176 p = ptr;
177 p[0] = tswap32(e1);
178 p[1] = tswap32(e2);
179 }
180
181 static uint64_t *idt_table;
182 #ifdef TARGET_X86_64
183 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
184 uint64_t addr, unsigned int sel)
185 {
186 uint32_t *p, e1, e2;
187 e1 = (addr & 0xffff) | (sel << 16);
188 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
189 p = ptr;
190 p[0] = tswap32(e1);
191 p[1] = tswap32(e2);
192 p[2] = tswap32(addr >> 32);
193 p[3] = 0;
194 }
195 /* only dpl matters as we do only user space emulation */
196 static void set_idt(int n, unsigned int dpl)
197 {
198 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
199 }
200 #else
201 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
202 uint32_t addr, unsigned int sel)
203 {
204 uint32_t *p, e1, e2;
205 e1 = (addr & 0xffff) | (sel << 16);
206 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
207 p = ptr;
208 p[0] = tswap32(e1);
209 p[1] = tswap32(e2);
210 }
211
212 /* only dpl matters as we do only user space emulation */
213 static void set_idt(int n, unsigned int dpl)
214 {
215 set_gate(idt_table + n, 0, dpl, 0, 0);
216 }
217 #endif
218
219 void cpu_loop(CPUX86State *env)
220 {
221 CPUState *cs = CPU(x86_env_get_cpu(env));
222 int trapnr;
223 abi_ulong pc;
224 abi_ulong ret;
225 target_siginfo_t info;
226 #ifdef TARGET_X86_64
227 int syscall_num;
228 uint64_t val;
229 #endif
230
231 for(;;) {
232 cpu_exec_start(cs);
233 trapnr = cpu_exec(cs);
234 cpu_exec_end(cs);
235 process_queued_cpu_work(cs);
236
237 switch(trapnr) {
238 case 0x80:
239 /* linux syscall from int $0x80 */
240 ret = do_syscall(env,
241 env->regs[R_EAX],
242 env->regs[R_EBX],
243 env->regs[R_ECX],
244 env->regs[R_EDX],
245 env->regs[R_ESI],
246 env->regs[R_EDI],
247 env->regs[R_EBP],
248 0, 0);
249 if (ret == -TARGET_ERESTARTSYS) {
250 env->eip -= 2;
251 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
252 env->regs[R_EAX] = ret;
253 }
254 break;
255 #ifndef TARGET_ABI32
256 case EXCP_SYSCALL:
257 /* linux syscall from syscall instruction */
258 ret = do_syscall(env,
259 env->regs[R_EAX],
260 env->regs[R_EDI],
261 env->regs[R_ESI],
262 env->regs[R_EDX],
263 env->regs[10],
264 env->regs[8],
265 env->regs[9],
266 0, 0);
267 if (ret == -TARGET_ERESTARTSYS) {
268 env->eip -= 2;
269 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
270 env->regs[R_EAX] = ret;
271 }
272 break;
273 #endif
274 #ifdef TARGET_X86_64
275 case EXCP_VSYSCALL:
276 switch (env->eip) {
277 case TARGET_VSYSCALL_ADDR(__NR_vgettimeofday):
278 syscall_num = __NR_gettimeofday;
279 break;
280 case TARGET_VSYSCALL_ADDR(__NR_vtime):
281 #ifdef __NR_time
282 syscall_num = __NR_time;
283 #else
284 /* XXX: not yet implemented (arm eabi host) */
285 cpu_abort(cs, "Unimplemented vsyscall vtime");
286 #endif
287 break;
288 case TARGET_VSYSCALL_ADDR(__NR_vgetcpu):
289 /* XXX: not yet implemented */
290 cpu_abort(cs, "Unimplemented vsyscall vgetcpu");
291 break;
292 default:
293 cpu_abort(cs,
294 "Invalid vsyscall to address " TARGET_FMT_lx "\n",
295 env->eip);
296 }
297 env->regs[R_EAX] = do_syscall(env,
298 syscall_num,
299 env->regs[R_EDI],
300 env->regs[R_ESI],
301 env->regs[R_EDX],
302 env->regs[10],
303 env->regs[8],
304 env->regs[9],
305 0, 0);
306 /* simulate a ret */
307 get_user_u64(val, env->regs[R_ESP]);
308 env->eip = val;
309 env->regs[R_ESP] += 8;
310 break;
311 #endif
312 case EXCP0B_NOSEG:
313 case EXCP0C_STACK:
314 info.si_signo = TARGET_SIGBUS;
315 info.si_errno = 0;
316 info.si_code = TARGET_SI_KERNEL;
317 info._sifields._sigfault._addr = 0;
318 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
319 break;
320 case EXCP0D_GPF:
321 /* XXX: potential problem if ABI32 */
322 #ifndef TARGET_X86_64
323 if (env->eflags & VM_MASK) {
324 handle_vm86_fault(env);
325 } else
326 #endif
327 {
328 info.si_signo = TARGET_SIGSEGV;
329 info.si_errno = 0;
330 info.si_code = TARGET_SI_KERNEL;
331 info._sifields._sigfault._addr = 0;
332 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
333 }
334 break;
335 case EXCP0E_PAGE:
336 info.si_signo = TARGET_SIGSEGV;
337 info.si_errno = 0;
338 if (!(env->error_code & 1))
339 info.si_code = TARGET_SEGV_MAPERR;
340 else
341 info.si_code = TARGET_SEGV_ACCERR;
342 info._sifields._sigfault._addr = env->cr[2];
343 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
344 break;
345 case EXCP00_DIVZ:
346 #ifndef TARGET_X86_64
347 if (env->eflags & VM_MASK) {
348 handle_vm86_trap(env, trapnr);
349 } else
350 #endif
351 {
352 /* division by zero */
353 info.si_signo = TARGET_SIGFPE;
354 info.si_errno = 0;
355 info.si_code = TARGET_FPE_INTDIV;
356 info._sifields._sigfault._addr = env->eip;
357 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
358 }
359 break;
360 case EXCP01_DB:
361 case EXCP03_INT3:
362 #ifndef TARGET_X86_64
363 if (env->eflags & VM_MASK) {
364 handle_vm86_trap(env, trapnr);
365 } else
366 #endif
367 {
368 info.si_signo = TARGET_SIGTRAP;
369 info.si_errno = 0;
370 if (trapnr == EXCP01_DB) {
371 info.si_code = TARGET_TRAP_BRKPT;
372 info._sifields._sigfault._addr = env->eip;
373 } else {
374 info.si_code = TARGET_SI_KERNEL;
375 info._sifields._sigfault._addr = 0;
376 }
377 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
378 }
379 break;
380 case EXCP04_INTO:
381 case EXCP05_BOUND:
382 #ifndef TARGET_X86_64
383 if (env->eflags & VM_MASK) {
384 handle_vm86_trap(env, trapnr);
385 } else
386 #endif
387 {
388 info.si_signo = TARGET_SIGSEGV;
389 info.si_errno = 0;
390 info.si_code = TARGET_SI_KERNEL;
391 info._sifields._sigfault._addr = 0;
392 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
393 }
394 break;
395 case EXCP06_ILLOP:
396 info.si_signo = TARGET_SIGILL;
397 info.si_errno = 0;
398 info.si_code = TARGET_ILL_ILLOPN;
399 info._sifields._sigfault._addr = env->eip;
400 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
401 break;
402 case EXCP_INTERRUPT:
403 /* just indicate that signals should be handled asap */
404 break;
405 case EXCP_DEBUG:
406 {
407 int sig;
408
409 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
410 if (sig)
411 {
412 info.si_signo = sig;
413 info.si_errno = 0;
414 info.si_code = TARGET_TRAP_BRKPT;
415 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
416 }
417 }
418 break;
419 case EXCP_ATOMIC:
420 cpu_exec_step_atomic(cs);
421 break;
422 default:
423 pc = env->segs[R_CS].base + env->eip;
424 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
425 (long)pc, trapnr);
426 abort();
427 }
428 process_pending_signals(env);
429 }
430 }
431 #endif
432
433 #ifdef TARGET_ARM
434
435 #define get_user_code_u32(x, gaddr, env) \
436 ({ abi_long __r = get_user_u32((x), (gaddr)); \
437 if (!__r && bswap_code(arm_sctlr_b(env))) { \
438 (x) = bswap32(x); \
439 } \
440 __r; \
441 })
442
443 #define get_user_code_u16(x, gaddr, env) \
444 ({ abi_long __r = get_user_u16((x), (gaddr)); \
445 if (!__r && bswap_code(arm_sctlr_b(env))) { \
446 (x) = bswap16(x); \
447 } \
448 __r; \
449 })
450
451 #define get_user_data_u32(x, gaddr, env) \
452 ({ abi_long __r = get_user_u32((x), (gaddr)); \
453 if (!__r && arm_cpu_bswap_data(env)) { \
454 (x) = bswap32(x); \
455 } \
456 __r; \
457 })
458
459 #define get_user_data_u16(x, gaddr, env) \
460 ({ abi_long __r = get_user_u16((x), (gaddr)); \
461 if (!__r && arm_cpu_bswap_data(env)) { \
462 (x) = bswap16(x); \
463 } \
464 __r; \
465 })
466
467 #define put_user_data_u32(x, gaddr, env) \
468 ({ typeof(x) __x = (x); \
469 if (arm_cpu_bswap_data(env)) { \
470 __x = bswap32(__x); \
471 } \
472 put_user_u32(__x, (gaddr)); \
473 })
474
475 #define put_user_data_u16(x, gaddr, env) \
476 ({ typeof(x) __x = (x); \
477 if (arm_cpu_bswap_data(env)) { \
478 __x = bswap16(__x); \
479 } \
480 put_user_u16(__x, (gaddr)); \
481 })
482
483 #ifdef TARGET_ABI32
484 /* Commpage handling -- there is no commpage for AArch64 */
485
486 /*
487 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
488 * Input:
489 * r0 = pointer to oldval
490 * r1 = pointer to newval
491 * r2 = pointer to target value
492 *
493 * Output:
494 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
495 * C set if *ptr was changed, clear if no exchange happened
496 *
497 * Note segv's in kernel helpers are a bit tricky, we can set the
498 * data address sensibly but the PC address is just the entry point.
499 */
500 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
501 {
502 uint64_t oldval, newval, val;
503 uint32_t addr, cpsr;
504 target_siginfo_t info;
505
506 /* Based on the 32 bit code in do_kernel_trap */
507
508 /* XXX: This only works between threads, not between processes.
509 It's probably possible to implement this with native host
510 operations. However things like ldrex/strex are much harder so
511 there's not much point trying. */
512 start_exclusive();
513 cpsr = cpsr_read(env);
514 addr = env->regs[2];
515
516 if (get_user_u64(oldval, env->regs[0])) {
517 env->exception.vaddress = env->regs[0];
518 goto segv;
519 };
520
521 if (get_user_u64(newval, env->regs[1])) {
522 env->exception.vaddress = env->regs[1];
523 goto segv;
524 };
525
526 if (get_user_u64(val, addr)) {
527 env->exception.vaddress = addr;
528 goto segv;
529 }
530
531 if (val == oldval) {
532 val = newval;
533
534 if (put_user_u64(val, addr)) {
535 env->exception.vaddress = addr;
536 goto segv;
537 };
538
539 env->regs[0] = 0;
540 cpsr |= CPSR_C;
541 } else {
542 env->regs[0] = -1;
543 cpsr &= ~CPSR_C;
544 }
545 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
546 end_exclusive();
547 return;
548
549 segv:
550 end_exclusive();
551 /* We get the PC of the entry address - which is as good as anything,
552 on a real kernel what you get depends on which mode it uses. */
553 info.si_signo = TARGET_SIGSEGV;
554 info.si_errno = 0;
555 /* XXX: check env->error_code */
556 info.si_code = TARGET_SEGV_MAPERR;
557 info._sifields._sigfault._addr = env->exception.vaddress;
558 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
559 }
560
561 /* Handle a jump to the kernel code page. */
562 static int
563 do_kernel_trap(CPUARMState *env)
564 {
565 uint32_t addr;
566 uint32_t cpsr;
567 uint32_t val;
568
569 switch (env->regs[15]) {
570 case 0xffff0fa0: /* __kernel_memory_barrier */
571 /* ??? No-op. Will need to do better for SMP. */
572 break;
573 case 0xffff0fc0: /* __kernel_cmpxchg */
574 /* XXX: This only works between threads, not between processes.
575 It's probably possible to implement this with native host
576 operations. However things like ldrex/strex are much harder so
577 there's not much point trying. */
578 start_exclusive();
579 cpsr = cpsr_read(env);
580 addr = env->regs[2];
581 /* FIXME: This should SEGV if the access fails. */
582 if (get_user_u32(val, addr))
583 val = ~env->regs[0];
584 if (val == env->regs[0]) {
585 val = env->regs[1];
586 /* FIXME: Check for segfaults. */
587 put_user_u32(val, addr);
588 env->regs[0] = 0;
589 cpsr |= CPSR_C;
590 } else {
591 env->regs[0] = -1;
592 cpsr &= ~CPSR_C;
593 }
594 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
595 end_exclusive();
596 break;
597 case 0xffff0fe0: /* __kernel_get_tls */
598 env->regs[0] = cpu_get_tls(env);
599 break;
600 case 0xffff0f60: /* __kernel_cmpxchg64 */
601 arm_kernel_cmpxchg64_helper(env);
602 break;
603
604 default:
605 return 1;
606 }
607 /* Jump back to the caller. */
608 addr = env->regs[14];
609 if (addr & 1) {
610 env->thumb = 1;
611 addr &= ~1;
612 }
613 env->regs[15] = addr;
614
615 return 0;
616 }
617
618 void cpu_loop(CPUARMState *env)
619 {
620 CPUState *cs = CPU(arm_env_get_cpu(env));
621 int trapnr;
622 unsigned int n, insn;
623 target_siginfo_t info;
624 uint32_t addr;
625 abi_ulong ret;
626
627 for(;;) {
628 cpu_exec_start(cs);
629 trapnr = cpu_exec(cs);
630 cpu_exec_end(cs);
631 process_queued_cpu_work(cs);
632
633 switch(trapnr) {
634 case EXCP_UDEF:
635 case EXCP_NOCP:
636 case EXCP_INVSTATE:
637 {
638 TaskState *ts = cs->opaque;
639 uint32_t opcode;
640 int rc;
641
642 /* we handle the FPU emulation here, as Linux */
643 /* we get the opcode */
644 /* FIXME - what to do if get_user() fails? */
645 get_user_code_u32(opcode, env->regs[15], env);
646
647 rc = EmulateAll(opcode, &ts->fpa, env);
648 if (rc == 0) { /* illegal instruction */
649 info.si_signo = TARGET_SIGILL;
650 info.si_errno = 0;
651 info.si_code = TARGET_ILL_ILLOPN;
652 info._sifields._sigfault._addr = env->regs[15];
653 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
654 } else if (rc < 0) { /* FP exception */
655 int arm_fpe=0;
656
657 /* translate softfloat flags to FPSR flags */
658 if (-rc & float_flag_invalid)
659 arm_fpe |= BIT_IOC;
660 if (-rc & float_flag_divbyzero)
661 arm_fpe |= BIT_DZC;
662 if (-rc & float_flag_overflow)
663 arm_fpe |= BIT_OFC;
664 if (-rc & float_flag_underflow)
665 arm_fpe |= BIT_UFC;
666 if (-rc & float_flag_inexact)
667 arm_fpe |= BIT_IXC;
668
669 FPSR fpsr = ts->fpa.fpsr;
670 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
671
672 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
673 info.si_signo = TARGET_SIGFPE;
674 info.si_errno = 0;
675
676 /* ordered by priority, least first */
677 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
678 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
679 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
680 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
681 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
682
683 info._sifields._sigfault._addr = env->regs[15];
684 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
685 } else {
686 env->regs[15] += 4;
687 }
688
689 /* accumulate unenabled exceptions */
690 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
691 fpsr |= BIT_IXC;
692 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
693 fpsr |= BIT_UFC;
694 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
695 fpsr |= BIT_OFC;
696 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
697 fpsr |= BIT_DZC;
698 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
699 fpsr |= BIT_IOC;
700 ts->fpa.fpsr=fpsr;
701 } else { /* everything OK */
702 /* increment PC */
703 env->regs[15] += 4;
704 }
705 }
706 break;
707 case EXCP_SWI:
708 case EXCP_BKPT:
709 {
710 env->eabi = 1;
711 /* system call */
712 if (trapnr == EXCP_BKPT) {
713 if (env->thumb) {
714 /* FIXME - what to do if get_user() fails? */
715 get_user_code_u16(insn, env->regs[15], env);
716 n = insn & 0xff;
717 env->regs[15] += 2;
718 } else {
719 /* FIXME - what to do if get_user() fails? */
720 get_user_code_u32(insn, env->regs[15], env);
721 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
722 env->regs[15] += 4;
723 }
724 } else {
725 if (env->thumb) {
726 /* FIXME - what to do if get_user() fails? */
727 get_user_code_u16(insn, env->regs[15] - 2, env);
728 n = insn & 0xff;
729 } else {
730 /* FIXME - what to do if get_user() fails? */
731 get_user_code_u32(insn, env->regs[15] - 4, env);
732 n = insn & 0xffffff;
733 }
734 }
735
736 if (n == ARM_NR_cacheflush) {
737 /* nop */
738 } else if (n == ARM_NR_semihosting
739 || n == ARM_NR_thumb_semihosting) {
740 env->regs[0] = do_arm_semihosting (env);
741 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
742 /* linux syscall */
743 if (env->thumb || n == 0) {
744 n = env->regs[7];
745 } else {
746 n -= ARM_SYSCALL_BASE;
747 env->eabi = 0;
748 }
749 if ( n > ARM_NR_BASE) {
750 switch (n) {
751 case ARM_NR_cacheflush:
752 /* nop */
753 break;
754 case ARM_NR_set_tls:
755 cpu_set_tls(env, env->regs[0]);
756 env->regs[0] = 0;
757 break;
758 case ARM_NR_breakpoint:
759 env->regs[15] -= env->thumb ? 2 : 4;
760 goto excp_debug;
761 default:
762 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
763 n);
764 env->regs[0] = -TARGET_ENOSYS;
765 break;
766 }
767 } else {
768 ret = do_syscall(env,
769 n,
770 env->regs[0],
771 env->regs[1],
772 env->regs[2],
773 env->regs[3],
774 env->regs[4],
775 env->regs[5],
776 0, 0);
777 if (ret == -TARGET_ERESTARTSYS) {
778 env->regs[15] -= env->thumb ? 2 : 4;
779 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
780 env->regs[0] = ret;
781 }
782 }
783 } else {
784 goto error;
785 }
786 }
787 break;
788 case EXCP_SEMIHOST:
789 env->regs[0] = do_arm_semihosting(env);
790 break;
791 case EXCP_INTERRUPT:
792 /* just indicate that signals should be handled asap */
793 break;
794 case EXCP_PREFETCH_ABORT:
795 case EXCP_DATA_ABORT:
796 addr = env->exception.vaddress;
797 {
798 info.si_signo = TARGET_SIGSEGV;
799 info.si_errno = 0;
800 /* XXX: check env->error_code */
801 info.si_code = TARGET_SEGV_MAPERR;
802 info._sifields._sigfault._addr = addr;
803 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
804 }
805 break;
806 case EXCP_DEBUG:
807 excp_debug:
808 {
809 int sig;
810
811 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
812 if (sig)
813 {
814 info.si_signo = sig;
815 info.si_errno = 0;
816 info.si_code = TARGET_TRAP_BRKPT;
817 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
818 }
819 }
820 break;
821 case EXCP_KERNEL_TRAP:
822 if (do_kernel_trap(env))
823 goto error;
824 break;
825 case EXCP_YIELD:
826 /* nothing to do here for user-mode, just resume guest code */
827 break;
828 case EXCP_ATOMIC:
829 cpu_exec_step_atomic(cs);
830 break;
831 default:
832 error:
833 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
834 abort();
835 }
836 process_pending_signals(env);
837 }
838 }
839
840 #else
841
842 /* AArch64 main loop */
843 void cpu_loop(CPUARMState *env)
844 {
845 CPUState *cs = CPU(arm_env_get_cpu(env));
846 int trapnr, sig;
847 abi_long ret;
848 target_siginfo_t info;
849
850 for (;;) {
851 cpu_exec_start(cs);
852 trapnr = cpu_exec(cs);
853 cpu_exec_end(cs);
854 process_queued_cpu_work(cs);
855
856 switch (trapnr) {
857 case EXCP_SWI:
858 ret = do_syscall(env,
859 env->xregs[8],
860 env->xregs[0],
861 env->xregs[1],
862 env->xregs[2],
863 env->xregs[3],
864 env->xregs[4],
865 env->xregs[5],
866 0, 0);
867 if (ret == -TARGET_ERESTARTSYS) {
868 env->pc -= 4;
869 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
870 env->xregs[0] = ret;
871 }
872 break;
873 case EXCP_INTERRUPT:
874 /* just indicate that signals should be handled asap */
875 break;
876 case EXCP_UDEF:
877 info.si_signo = TARGET_SIGILL;
878 info.si_errno = 0;
879 info.si_code = TARGET_ILL_ILLOPN;
880 info._sifields._sigfault._addr = env->pc;
881 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
882 break;
883 case EXCP_PREFETCH_ABORT:
884 case EXCP_DATA_ABORT:
885 info.si_signo = TARGET_SIGSEGV;
886 info.si_errno = 0;
887 /* XXX: check env->error_code */
888 info.si_code = TARGET_SEGV_MAPERR;
889 info._sifields._sigfault._addr = env->exception.vaddress;
890 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
891 break;
892 case EXCP_DEBUG:
893 case EXCP_BKPT:
894 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
895 if (sig) {
896 info.si_signo = sig;
897 info.si_errno = 0;
898 info.si_code = TARGET_TRAP_BRKPT;
899 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
900 }
901 break;
902 case EXCP_SEMIHOST:
903 env->xregs[0] = do_arm_semihosting(env);
904 break;
905 case EXCP_YIELD:
906 /* nothing to do here for user-mode, just resume guest code */
907 break;
908 case EXCP_ATOMIC:
909 cpu_exec_step_atomic(cs);
910 break;
911 default:
912 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
913 abort();
914 }
915 process_pending_signals(env);
916 /* Exception return on AArch64 always clears the exclusive monitor,
917 * so any return to running guest code implies this.
918 */
919 env->exclusive_addr = -1;
920 }
921 }
922 #endif /* ndef TARGET_ABI32 */
923
924 #endif
925
926 #ifdef TARGET_UNICORE32
927
928 void cpu_loop(CPUUniCore32State *env)
929 {
930 CPUState *cs = CPU(uc32_env_get_cpu(env));
931 int trapnr;
932 unsigned int n, insn;
933 target_siginfo_t info;
934
935 for (;;) {
936 cpu_exec_start(cs);
937 trapnr = cpu_exec(cs);
938 cpu_exec_end(cs);
939 process_queued_cpu_work(cs);
940
941 switch (trapnr) {
942 case UC32_EXCP_PRIV:
943 {
944 /* system call */
945 get_user_u32(insn, env->regs[31] - 4);
946 n = insn & 0xffffff;
947
948 if (n >= UC32_SYSCALL_BASE) {
949 /* linux syscall */
950 n -= UC32_SYSCALL_BASE;
951 if (n == UC32_SYSCALL_NR_set_tls) {
952 cpu_set_tls(env, env->regs[0]);
953 env->regs[0] = 0;
954 } else {
955 abi_long ret = do_syscall(env,
956 n,
957 env->regs[0],
958 env->regs[1],
959 env->regs[2],
960 env->regs[3],
961 env->regs[4],
962 env->regs[5],
963 0, 0);
964 if (ret == -TARGET_ERESTARTSYS) {
965 env->regs[31] -= 4;
966 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
967 env->regs[0] = ret;
968 }
969 }
970 } else {
971 goto error;
972 }
973 }
974 break;
975 case UC32_EXCP_DTRAP:
976 case UC32_EXCP_ITRAP:
977 info.si_signo = TARGET_SIGSEGV;
978 info.si_errno = 0;
979 /* XXX: check env->error_code */
980 info.si_code = TARGET_SEGV_MAPERR;
981 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
982 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
983 break;
984 case EXCP_INTERRUPT:
985 /* just indicate that signals should be handled asap */
986 break;
987 case EXCP_DEBUG:
988 {
989 int sig;
990
991 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
992 if (sig) {
993 info.si_signo = sig;
994 info.si_errno = 0;
995 info.si_code = TARGET_TRAP_BRKPT;
996 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
997 }
998 }
999 break;
1000 case EXCP_ATOMIC:
1001 cpu_exec_step_atomic(cs);
1002 break;
1003 default:
1004 goto error;
1005 }
1006 process_pending_signals(env);
1007 }
1008
1009 error:
1010 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1011 abort();
1012 }
1013 #endif
1014
1015 #ifdef TARGET_SPARC
1016 #define SPARC64_STACK_BIAS 2047
1017
1018 //#define DEBUG_WIN
1019
1020 /* WARNING: dealing with register windows _is_ complicated. More info
1021 can be found at http://www.sics.se/~psm/sparcstack.html */
1022 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1023 {
1024 index = (index + cwp * 16) % (16 * env->nwindows);
1025 /* wrap handling : if cwp is on the last window, then we use the
1026 registers 'after' the end */
1027 if (index < 8 && env->cwp == env->nwindows - 1)
1028 index += 16 * env->nwindows;
1029 return index;
1030 }
1031
1032 /* save the register window 'cwp1' */
1033 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1034 {
1035 unsigned int i;
1036 abi_ulong sp_ptr;
1037
1038 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1039 #ifdef TARGET_SPARC64
1040 if (sp_ptr & 3)
1041 sp_ptr += SPARC64_STACK_BIAS;
1042 #endif
1043 #if defined(DEBUG_WIN)
1044 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1045 sp_ptr, cwp1);
1046 #endif
1047 for(i = 0; i < 16; i++) {
1048 /* FIXME - what to do if put_user() fails? */
1049 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1050 sp_ptr += sizeof(abi_ulong);
1051 }
1052 }
1053
1054 static void save_window(CPUSPARCState *env)
1055 {
1056 #ifndef TARGET_SPARC64
1057 unsigned int new_wim;
1058 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1059 ((1LL << env->nwindows) - 1);
1060 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1061 env->wim = new_wim;
1062 #else
1063 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1064 env->cansave++;
1065 env->canrestore--;
1066 #endif
1067 }
1068
1069 static void restore_window(CPUSPARCState *env)
1070 {
1071 #ifndef TARGET_SPARC64
1072 unsigned int new_wim;
1073 #endif
1074 unsigned int i, cwp1;
1075 abi_ulong sp_ptr;
1076
1077 #ifndef TARGET_SPARC64
1078 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1079 ((1LL << env->nwindows) - 1);
1080 #endif
1081
1082 /* restore the invalid window */
1083 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1084 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1085 #ifdef TARGET_SPARC64
1086 if (sp_ptr & 3)
1087 sp_ptr += SPARC64_STACK_BIAS;
1088 #endif
1089 #if defined(DEBUG_WIN)
1090 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1091 sp_ptr, cwp1);
1092 #endif
1093 for(i = 0; i < 16; i++) {
1094 /* FIXME - what to do if get_user() fails? */
1095 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1096 sp_ptr += sizeof(abi_ulong);
1097 }
1098 #ifdef TARGET_SPARC64
1099 env->canrestore++;
1100 if (env->cleanwin < env->nwindows - 1)
1101 env->cleanwin++;
1102 env->cansave--;
1103 #else
1104 env->wim = new_wim;
1105 #endif
1106 }
1107
1108 static void flush_windows(CPUSPARCState *env)
1109 {
1110 int offset, cwp1;
1111
1112 offset = 1;
1113 for(;;) {
1114 /* if restore would invoke restore_window(), then we can stop */
1115 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1116 #ifndef TARGET_SPARC64
1117 if (env->wim & (1 << cwp1))
1118 break;
1119 #else
1120 if (env->canrestore == 0)
1121 break;
1122 env->cansave++;
1123 env->canrestore--;
1124 #endif
1125 save_window_offset(env, cwp1);
1126 offset++;
1127 }
1128 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1129 #ifndef TARGET_SPARC64
1130 /* set wim so that restore will reload the registers */
1131 env->wim = 1 << cwp1;
1132 #endif
1133 #if defined(DEBUG_WIN)
1134 printf("flush_windows: nb=%d\n", offset - 1);
1135 #endif
1136 }
1137
1138 void cpu_loop (CPUSPARCState *env)
1139 {
1140 CPUState *cs = CPU(sparc_env_get_cpu(env));
1141 int trapnr;
1142 abi_long ret;
1143 target_siginfo_t info;
1144
1145 while (1) {
1146 cpu_exec_start(cs);
1147 trapnr = cpu_exec(cs);
1148 cpu_exec_end(cs);
1149 process_queued_cpu_work(cs);
1150
1151 /* Compute PSR before exposing state. */
1152 if (env->cc_op != CC_OP_FLAGS) {
1153 cpu_get_psr(env);
1154 }
1155
1156 switch (trapnr) {
1157 #ifndef TARGET_SPARC64
1158 case 0x88:
1159 case 0x90:
1160 #else
1161 case 0x110:
1162 case 0x16d:
1163 #endif
1164 ret = do_syscall (env, env->gregs[1],
1165 env->regwptr[0], env->regwptr[1],
1166 env->regwptr[2], env->regwptr[3],
1167 env->regwptr[4], env->regwptr[5],
1168 0, 0);
1169 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1170 break;
1171 }
1172 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1173 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1174 env->xcc |= PSR_CARRY;
1175 #else
1176 env->psr |= PSR_CARRY;
1177 #endif
1178 ret = -ret;
1179 } else {
1180 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1181 env->xcc &= ~PSR_CARRY;
1182 #else
1183 env->psr &= ~PSR_CARRY;
1184 #endif
1185 }
1186 env->regwptr[0] = ret;
1187 /* next instruction */
1188 env->pc = env->npc;
1189 env->npc = env->npc + 4;
1190 break;
1191 case 0x83: /* flush windows */
1192 #ifdef TARGET_ABI32
1193 case 0x103:
1194 #endif
1195 flush_windows(env);
1196 /* next instruction */
1197 env->pc = env->npc;
1198 env->npc = env->npc + 4;
1199 break;
1200 #ifndef TARGET_SPARC64
1201 case TT_WIN_OVF: /* window overflow */
1202 save_window(env);
1203 break;
1204 case TT_WIN_UNF: /* window underflow */
1205 restore_window(env);
1206 break;
1207 case TT_TFAULT:
1208 case TT_DFAULT:
1209 {
1210 info.si_signo = TARGET_SIGSEGV;
1211 info.si_errno = 0;
1212 /* XXX: check env->error_code */
1213 info.si_code = TARGET_SEGV_MAPERR;
1214 info._sifields._sigfault._addr = env->mmuregs[4];
1215 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1216 }
1217 break;
1218 #else
1219 case TT_SPILL: /* window overflow */
1220 save_window(env);
1221 break;
1222 case TT_FILL: /* window underflow */
1223 restore_window(env);
1224 break;
1225 case TT_TFAULT:
1226 case TT_DFAULT:
1227 {
1228 info.si_signo = TARGET_SIGSEGV;
1229 info.si_errno = 0;
1230 /* XXX: check env->error_code */
1231 info.si_code = TARGET_SEGV_MAPERR;
1232 if (trapnr == TT_DFAULT)
1233 info._sifields._sigfault._addr = env->dmmu.mmuregs[4];
1234 else
1235 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1236 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1237 }
1238 break;
1239 #ifndef TARGET_ABI32
1240 case 0x16e:
1241 flush_windows(env);
1242 sparc64_get_context(env);
1243 break;
1244 case 0x16f:
1245 flush_windows(env);
1246 sparc64_set_context(env);
1247 break;
1248 #endif
1249 #endif
1250 case EXCP_INTERRUPT:
1251 /* just indicate that signals should be handled asap */
1252 break;
1253 case TT_ILL_INSN:
1254 {
1255 info.si_signo = TARGET_SIGILL;
1256 info.si_errno = 0;
1257 info.si_code = TARGET_ILL_ILLOPC;
1258 info._sifields._sigfault._addr = env->pc;
1259 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1260 }
1261 break;
1262 case EXCP_DEBUG:
1263 {
1264 int sig;
1265
1266 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1267 if (sig)
1268 {
1269 info.si_signo = sig;
1270 info.si_errno = 0;
1271 info.si_code = TARGET_TRAP_BRKPT;
1272 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1273 }
1274 }
1275 break;
1276 case EXCP_ATOMIC:
1277 cpu_exec_step_atomic(cs);
1278 break;
1279 default:
1280 printf ("Unhandled trap: 0x%x\n", trapnr);
1281 cpu_dump_state(cs, stderr, fprintf, 0);
1282 exit(EXIT_FAILURE);
1283 }
1284 process_pending_signals (env);
1285 }
1286 }
1287
1288 #endif
1289
1290 #ifdef TARGET_PPC
1291 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1292 {
1293 return cpu_get_host_ticks();
1294 }
1295
1296 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1297 {
1298 return cpu_ppc_get_tb(env);
1299 }
1300
1301 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1302 {
1303 return cpu_ppc_get_tb(env) >> 32;
1304 }
1305
1306 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1307 {
1308 return cpu_ppc_get_tb(env);
1309 }
1310
1311 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1312 {
1313 return cpu_ppc_get_tb(env) >> 32;
1314 }
1315
1316 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1317 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1318
1319 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1320 {
1321 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1322 }
1323
1324 /* XXX: to be fixed */
1325 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1326 {
1327 return -1;
1328 }
1329
1330 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1331 {
1332 return -1;
1333 }
1334
1335 static int do_store_exclusive(CPUPPCState *env)
1336 {
1337 target_ulong addr;
1338 target_ulong page_addr;
1339 target_ulong val, val2 __attribute__((unused)) = 0;
1340 int flags;
1341 int segv = 0;
1342
1343 addr = env->reserve_ea;
1344 page_addr = addr & TARGET_PAGE_MASK;
1345 start_exclusive();
1346 mmap_lock();
1347 flags = page_get_flags(page_addr);
1348 if ((flags & PAGE_READ) == 0) {
1349 segv = 1;
1350 } else {
1351 int reg = env->reserve_info & 0x1f;
1352 int size = env->reserve_info >> 5;
1353 int stored = 0;
1354
1355 if (addr == env->reserve_addr) {
1356 switch (size) {
1357 case 1: segv = get_user_u8(val, addr); break;
1358 case 2: segv = get_user_u16(val, addr); break;
1359 case 4: segv = get_user_u32(val, addr); break;
1360 #if defined(TARGET_PPC64)
1361 case 8: segv = get_user_u64(val, addr); break;
1362 case 16: {
1363 segv = get_user_u64(val, addr);
1364 if (!segv) {
1365 segv = get_user_u64(val2, addr + 8);
1366 }
1367 break;
1368 }
1369 #endif
1370 default: abort();
1371 }
1372 if (!segv && val == env->reserve_val) {
1373 val = env->gpr[reg];
1374 switch (size) {
1375 case 1: segv = put_user_u8(val, addr); break;
1376 case 2: segv = put_user_u16(val, addr); break;
1377 case 4: segv = put_user_u32(val, addr); break;
1378 #if defined(TARGET_PPC64)
1379 case 8: segv = put_user_u64(val, addr); break;
1380 case 16: {
1381 if (val2 == env->reserve_val2) {
1382 if (msr_le) {
1383 val2 = val;
1384 val = env->gpr[reg+1];
1385 } else {
1386 val2 = env->gpr[reg+1];
1387 }
1388 segv = put_user_u64(val, addr);
1389 if (!segv) {
1390 segv = put_user_u64(val2, addr + 8);
1391 }
1392 }
1393 break;
1394 }
1395 #endif
1396 default: abort();
1397 }
1398 if (!segv) {
1399 stored = 1;
1400 }
1401 }
1402 }
1403 env->crf[0] = (stored << 1) | xer_so;
1404 env->reserve_addr = (target_ulong)-1;
1405 }
1406 if (!segv) {
1407 env->nip += 4;
1408 }
1409 mmap_unlock();
1410 end_exclusive();
1411 return segv;
1412 }
1413
1414 void cpu_loop(CPUPPCState *env)
1415 {
1416 CPUState *cs = CPU(ppc_env_get_cpu(env));
1417 target_siginfo_t info;
1418 int trapnr;
1419 target_ulong ret;
1420
1421 for(;;) {
1422 cpu_exec_start(cs);
1423 trapnr = cpu_exec(cs);
1424 cpu_exec_end(cs);
1425 process_queued_cpu_work(cs);
1426
1427 switch(trapnr) {
1428 case POWERPC_EXCP_NONE:
1429 /* Just go on */
1430 break;
1431 case POWERPC_EXCP_CRITICAL: /* Critical input */
1432 cpu_abort(cs, "Critical interrupt while in user mode. "
1433 "Aborting\n");
1434 break;
1435 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1436 cpu_abort(cs, "Machine check exception while in user mode. "
1437 "Aborting\n");
1438 break;
1439 case POWERPC_EXCP_DSI: /* Data storage exception */
1440 /* XXX: check this. Seems bugged */
1441 switch (env->error_code & 0xFF000000) {
1442 case 0x40000000:
1443 case 0x42000000:
1444 info.si_signo = TARGET_SIGSEGV;
1445 info.si_errno = 0;
1446 info.si_code = TARGET_SEGV_MAPERR;
1447 break;
1448 case 0x04000000:
1449 info.si_signo = TARGET_SIGILL;
1450 info.si_errno = 0;
1451 info.si_code = TARGET_ILL_ILLADR;
1452 break;
1453 case 0x08000000:
1454 info.si_signo = TARGET_SIGSEGV;
1455 info.si_errno = 0;
1456 info.si_code = TARGET_SEGV_ACCERR;
1457 break;
1458 default:
1459 /* Let's send a regular segfault... */
1460 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1461 env->error_code);
1462 info.si_signo = TARGET_SIGSEGV;
1463 info.si_errno = 0;
1464 info.si_code = TARGET_SEGV_MAPERR;
1465 break;
1466 }
1467 info._sifields._sigfault._addr = env->spr[SPR_DAR];
1468 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1469 break;
1470 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1471 /* XXX: check this */
1472 switch (env->error_code & 0xFF000000) {
1473 case 0x40000000:
1474 info.si_signo = TARGET_SIGSEGV;
1475 info.si_errno = 0;
1476 info.si_code = TARGET_SEGV_MAPERR;
1477 break;
1478 case 0x10000000:
1479 case 0x08000000:
1480 info.si_signo = TARGET_SIGSEGV;
1481 info.si_errno = 0;
1482 info.si_code = TARGET_SEGV_ACCERR;
1483 break;
1484 default:
1485 /* Let's send a regular segfault... */
1486 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1487 env->error_code);
1488 info.si_signo = TARGET_SIGSEGV;
1489 info.si_errno = 0;
1490 info.si_code = TARGET_SEGV_MAPERR;
1491 break;
1492 }
1493 info._sifields._sigfault._addr = env->nip - 4;
1494 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1495 break;
1496 case POWERPC_EXCP_EXTERNAL: /* External input */
1497 cpu_abort(cs, "External interrupt while in user mode. "
1498 "Aborting\n");
1499 break;
1500 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1501 /* XXX: check this */
1502 info.si_signo = TARGET_SIGBUS;
1503 info.si_errno = 0;
1504 info.si_code = TARGET_BUS_ADRALN;
1505 info._sifields._sigfault._addr = env->nip;
1506 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1507 break;
1508 case POWERPC_EXCP_PROGRAM: /* Program exception */
1509 case POWERPC_EXCP_HV_EMU: /* HV emulation */
1510 /* XXX: check this */
1511 switch (env->error_code & ~0xF) {
1512 case POWERPC_EXCP_FP:
1513 info.si_signo = TARGET_SIGFPE;
1514 info.si_errno = 0;
1515 switch (env->error_code & 0xF) {
1516 case POWERPC_EXCP_FP_OX:
1517 info.si_code = TARGET_FPE_FLTOVF;
1518 break;
1519 case POWERPC_EXCP_FP_UX:
1520 info.si_code = TARGET_FPE_FLTUND;
1521 break;
1522 case POWERPC_EXCP_FP_ZX:
1523 case POWERPC_EXCP_FP_VXZDZ:
1524 info.si_code = TARGET_FPE_FLTDIV;
1525 break;
1526 case POWERPC_EXCP_FP_XX:
1527 info.si_code = TARGET_FPE_FLTRES;
1528 break;
1529 case POWERPC_EXCP_FP_VXSOFT:
1530 info.si_code = TARGET_FPE_FLTINV;
1531 break;
1532 case POWERPC_EXCP_FP_VXSNAN:
1533 case POWERPC_EXCP_FP_VXISI:
1534 case POWERPC_EXCP_FP_VXIDI:
1535 case POWERPC_EXCP_FP_VXIMZ:
1536 case POWERPC_EXCP_FP_VXVC:
1537 case POWERPC_EXCP_FP_VXSQRT:
1538 case POWERPC_EXCP_FP_VXCVI:
1539 info.si_code = TARGET_FPE_FLTSUB;
1540 break;
1541 default:
1542 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1543 env->error_code);
1544 break;
1545 }
1546 break;
1547 case POWERPC_EXCP_INVAL:
1548 info.si_signo = TARGET_SIGILL;
1549 info.si_errno = 0;
1550 switch (env->error_code & 0xF) {
1551 case POWERPC_EXCP_INVAL_INVAL:
1552 info.si_code = TARGET_ILL_ILLOPC;
1553 break;
1554 case POWERPC_EXCP_INVAL_LSWX:
1555 info.si_code = TARGET_ILL_ILLOPN;
1556 break;
1557 case POWERPC_EXCP_INVAL_SPR:
1558 info.si_code = TARGET_ILL_PRVREG;
1559 break;
1560 case POWERPC_EXCP_INVAL_FP:
1561 info.si_code = TARGET_ILL_COPROC;
1562 break;
1563 default:
1564 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1565 env->error_code & 0xF);
1566 info.si_code = TARGET_ILL_ILLADR;
1567 break;
1568 }
1569 break;
1570 case POWERPC_EXCP_PRIV:
1571 info.si_signo = TARGET_SIGILL;
1572 info.si_errno = 0;
1573 switch (env->error_code & 0xF) {
1574 case POWERPC_EXCP_PRIV_OPC:
1575 info.si_code = TARGET_ILL_PRVOPC;
1576 break;
1577 case POWERPC_EXCP_PRIV_REG:
1578 info.si_code = TARGET_ILL_PRVREG;
1579 break;
1580 default:
1581 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1582 env->error_code & 0xF);
1583 info.si_code = TARGET_ILL_PRVOPC;
1584 break;
1585 }
1586 break;
1587 case POWERPC_EXCP_TRAP:
1588 cpu_abort(cs, "Tried to call a TRAP\n");
1589 break;
1590 default:
1591 /* Should not happen ! */
1592 cpu_abort(cs, "Unknown program exception (%02x)\n",
1593 env->error_code);
1594 break;
1595 }
1596 info._sifields._sigfault._addr = env->nip;
1597 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1598 break;
1599 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1600 info.si_signo = TARGET_SIGILL;
1601 info.si_errno = 0;
1602 info.si_code = TARGET_ILL_COPROC;
1603 info._sifields._sigfault._addr = env->nip;
1604 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1605 break;
1606 case POWERPC_EXCP_SYSCALL: /* System call exception */
1607 cpu_abort(cs, "Syscall exception while in user mode. "
1608 "Aborting\n");
1609 break;
1610 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1611 info.si_signo = TARGET_SIGILL;
1612 info.si_errno = 0;
1613 info.si_code = TARGET_ILL_COPROC;
1614 info._sifields._sigfault._addr = env->nip;
1615 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1616 break;
1617 case POWERPC_EXCP_DECR: /* Decrementer exception */
1618 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1619 "Aborting\n");
1620 break;
1621 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1622 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1623 "Aborting\n");
1624 break;
1625 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1626 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1627 "Aborting\n");
1628 break;
1629 case POWERPC_EXCP_DTLB: /* Data TLB error */
1630 cpu_abort(cs, "Data TLB exception while in user mode. "
1631 "Aborting\n");
1632 break;
1633 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1634 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1635 "Aborting\n");
1636 break;
1637 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1638 info.si_signo = TARGET_SIGILL;
1639 info.si_errno = 0;
1640 info.si_code = TARGET_ILL_COPROC;
1641 info._sifields._sigfault._addr = env->nip;
1642 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1643 break;
1644 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1645 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1646 break;
1647 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1648 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1649 break;
1650 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1651 cpu_abort(cs, "Performance monitor exception not handled\n");
1652 break;
1653 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1654 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1655 "Aborting\n");
1656 break;
1657 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1658 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1659 "Aborting\n");
1660 break;
1661 case POWERPC_EXCP_RESET: /* System reset exception */
1662 cpu_abort(cs, "Reset interrupt while in user mode. "
1663 "Aborting\n");
1664 break;
1665 case POWERPC_EXCP_DSEG: /* Data segment exception */
1666 cpu_abort(cs, "Data segment exception while in user mode. "
1667 "Aborting\n");
1668 break;
1669 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1670 cpu_abort(cs, "Instruction segment exception "
1671 "while in user mode. Aborting\n");
1672 break;
1673 /* PowerPC 64 with hypervisor mode support */
1674 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1675 cpu_abort(cs, "Hypervisor decrementer interrupt "
1676 "while in user mode. Aborting\n");
1677 break;
1678 case POWERPC_EXCP_TRACE: /* Trace exception */
1679 /* Nothing to do:
1680 * we use this exception to emulate step-by-step execution mode.
1681 */
1682 break;
1683 /* PowerPC 64 with hypervisor mode support */
1684 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1685 cpu_abort(cs, "Hypervisor data storage exception "
1686 "while in user mode. Aborting\n");
1687 break;
1688 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1689 cpu_abort(cs, "Hypervisor instruction storage exception "
1690 "while in user mode. Aborting\n");
1691 break;
1692 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1693 cpu_abort(cs, "Hypervisor data segment exception "
1694 "while in user mode. Aborting\n");
1695 break;
1696 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1697 cpu_abort(cs, "Hypervisor instruction segment exception "
1698 "while in user mode. Aborting\n");
1699 break;
1700 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1701 info.si_signo = TARGET_SIGILL;
1702 info.si_errno = 0;
1703 info.si_code = TARGET_ILL_COPROC;
1704 info._sifields._sigfault._addr = env->nip;
1705 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1706 break;
1707 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1708 cpu_abort(cs, "Programmable interval timer interrupt "
1709 "while in user mode. Aborting\n");
1710 break;
1711 case POWERPC_EXCP_IO: /* IO error exception */
1712 cpu_abort(cs, "IO error exception while in user mode. "
1713 "Aborting\n");
1714 break;
1715 case POWERPC_EXCP_RUNM: /* Run mode exception */
1716 cpu_abort(cs, "Run mode exception while in user mode. "
1717 "Aborting\n");
1718 break;
1719 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1720 cpu_abort(cs, "Emulation trap exception not handled\n");
1721 break;
1722 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1723 cpu_abort(cs, "Instruction fetch TLB exception "
1724 "while in user-mode. Aborting");
1725 break;
1726 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1727 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1728 "Aborting");
1729 break;
1730 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1731 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1732 "Aborting");
1733 break;
1734 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1735 cpu_abort(cs, "Floating-point assist exception not handled\n");
1736 break;
1737 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1738 cpu_abort(cs, "Instruction address breakpoint exception "
1739 "not handled\n");
1740 break;
1741 case POWERPC_EXCP_SMI: /* System management interrupt */
1742 cpu_abort(cs, "System management interrupt while in user mode. "
1743 "Aborting\n");
1744 break;
1745 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1746 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1747 "Aborting\n");
1748 break;
1749 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1750 cpu_abort(cs, "Performance monitor exception not handled\n");
1751 break;
1752 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1753 cpu_abort(cs, "Vector assist exception not handled\n");
1754 break;
1755 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1756 cpu_abort(cs, "Soft patch exception not handled\n");
1757 break;
1758 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1759 cpu_abort(cs, "Maintenance exception while in user mode. "
1760 "Aborting\n");
1761 break;
1762 case POWERPC_EXCP_STOP: /* stop translation */
1763 /* We did invalidate the instruction cache. Go on */
1764 break;
1765 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1766 /* We just stopped because of a branch. Go on */
1767 break;
1768 case POWERPC_EXCP_SYSCALL_USER:
1769 /* system call in user-mode emulation */
1770 /* WARNING:
1771 * PPC ABI uses overflow flag in cr0 to signal an error
1772 * in syscalls.
1773 */
1774 env->crf[0] &= ~0x1;
1775 env->nip += 4;
1776 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1777 env->gpr[5], env->gpr[6], env->gpr[7],
1778 env->gpr[8], 0, 0);
1779 if (ret == -TARGET_ERESTARTSYS) {
1780 env->nip -= 4;
1781 break;
1782 }
1783 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1784 /* Returning from a successful sigreturn syscall.
1785 Avoid corrupting register state. */
1786 break;
1787 }
1788 if (ret > (target_ulong)(-515)) {
1789 env->crf[0] |= 0x1;
1790 ret = -ret;
1791 }
1792 env->gpr[3] = ret;
1793 break;
1794 case POWERPC_EXCP_STCX:
1795 if (do_store_exclusive(env)) {
1796 info.si_signo = TARGET_SIGSEGV;
1797 info.si_errno = 0;
1798 info.si_code = TARGET_SEGV_MAPERR;
1799 info._sifields._sigfault._addr = env->nip;
1800 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1801 }
1802 break;
1803 case EXCP_DEBUG:
1804 {
1805 int sig;
1806
1807 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1808 if (sig) {
1809 info.si_signo = sig;
1810 info.si_errno = 0;
1811 info.si_code = TARGET_TRAP_BRKPT;
1812 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1813 }
1814 }
1815 break;
1816 case EXCP_INTERRUPT:
1817 /* just indicate that signals should be handled asap */
1818 break;
1819 case EXCP_ATOMIC:
1820 cpu_exec_step_atomic(cs);
1821 break;
1822 default:
1823 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
1824 break;
1825 }
1826 process_pending_signals(env);
1827 }
1828 }
1829 #endif
1830
1831 #ifdef TARGET_MIPS
1832
1833 # ifdef TARGET_ABI_MIPSO32
1834 # define MIPS_SYS(name, args) args,
1835 static const uint8_t mips_syscall_args[] = {
1836 MIPS_SYS(sys_syscall , 8) /* 4000 */
1837 MIPS_SYS(sys_exit , 1)
1838 MIPS_SYS(sys_fork , 0)
1839 MIPS_SYS(sys_read , 3)
1840 MIPS_SYS(sys_write , 3)
1841 MIPS_SYS(sys_open , 3) /* 4005 */
1842 MIPS_SYS(sys_close , 1)
1843 MIPS_SYS(sys_waitpid , 3)
1844 MIPS_SYS(sys_creat , 2)
1845 MIPS_SYS(sys_link , 2)
1846 MIPS_SYS(sys_unlink , 1) /* 4010 */
1847 MIPS_SYS(sys_execve , 0)
1848 MIPS_SYS(sys_chdir , 1)
1849 MIPS_SYS(sys_time , 1)
1850 MIPS_SYS(sys_mknod , 3)
1851 MIPS_SYS(sys_chmod , 2) /* 4015 */
1852 MIPS_SYS(sys_lchown , 3)
1853 MIPS_SYS(sys_ni_syscall , 0)
1854 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1855 MIPS_SYS(sys_lseek , 3)
1856 MIPS_SYS(sys_getpid , 0) /* 4020 */
1857 MIPS_SYS(sys_mount , 5)
1858 MIPS_SYS(sys_umount , 1)
1859 MIPS_SYS(sys_setuid , 1)
1860 MIPS_SYS(sys_getuid , 0)
1861 MIPS_SYS(sys_stime , 1) /* 4025 */
1862 MIPS_SYS(sys_ptrace , 4)
1863 MIPS_SYS(sys_alarm , 1)
1864 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1865 MIPS_SYS(sys_pause , 0)
1866 MIPS_SYS(sys_utime , 2) /* 4030 */
1867 MIPS_SYS(sys_ni_syscall , 0)
1868 MIPS_SYS(sys_ni_syscall , 0)
1869 MIPS_SYS(sys_access , 2)
1870 MIPS_SYS(sys_nice , 1)
1871 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1872 MIPS_SYS(sys_sync , 0)
1873 MIPS_SYS(sys_kill , 2)
1874 MIPS_SYS(sys_rename , 2)
1875 MIPS_SYS(sys_mkdir , 2)
1876 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1877 MIPS_SYS(sys_dup , 1)
1878 MIPS_SYS(sys_pipe , 0)
1879 MIPS_SYS(sys_times , 1)
1880 MIPS_SYS(sys_ni_syscall , 0)
1881 MIPS_SYS(sys_brk , 1) /* 4045 */
1882 MIPS_SYS(sys_setgid , 1)
1883 MIPS_SYS(sys_getgid , 0)
1884 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1885 MIPS_SYS(sys_geteuid , 0)
1886 MIPS_SYS(sys_getegid , 0) /* 4050 */
1887 MIPS_SYS(sys_acct , 0)
1888 MIPS_SYS(sys_umount2 , 2)
1889 MIPS_SYS(sys_ni_syscall , 0)
1890 MIPS_SYS(sys_ioctl , 3)
1891 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1892 MIPS_SYS(sys_ni_syscall , 2)
1893 MIPS_SYS(sys_setpgid , 2)
1894 MIPS_SYS(sys_ni_syscall , 0)
1895 MIPS_SYS(sys_olduname , 1)
1896 MIPS_SYS(sys_umask , 1) /* 4060 */
1897 MIPS_SYS(sys_chroot , 1)
1898 MIPS_SYS(sys_ustat , 2)
1899 MIPS_SYS(sys_dup2 , 2)
1900 MIPS_SYS(sys_getppid , 0)
1901 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1902 MIPS_SYS(sys_setsid , 0)
1903 MIPS_SYS(sys_sigaction , 3)
1904 MIPS_SYS(sys_sgetmask , 0)
1905 MIPS_SYS(sys_ssetmask , 1)
1906 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1907 MIPS_SYS(sys_setregid , 2)
1908 MIPS_SYS(sys_sigsuspend , 0)
1909 MIPS_SYS(sys_sigpending , 1)
1910 MIPS_SYS(sys_sethostname , 2)
1911 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1912 MIPS_SYS(sys_getrlimit , 2)
1913 MIPS_SYS(sys_getrusage , 2)
1914 MIPS_SYS(sys_gettimeofday, 2)
1915 MIPS_SYS(sys_settimeofday, 2)
1916 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1917 MIPS_SYS(sys_setgroups , 2)
1918 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1919 MIPS_SYS(sys_symlink , 2)
1920 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1921 MIPS_SYS(sys_readlink , 3) /* 4085 */
1922 MIPS_SYS(sys_uselib , 1)
1923 MIPS_SYS(sys_swapon , 2)
1924 MIPS_SYS(sys_reboot , 3)
1925 MIPS_SYS(old_readdir , 3)
1926 MIPS_SYS(old_mmap , 6) /* 4090 */
1927 MIPS_SYS(sys_munmap , 2)
1928 MIPS_SYS(sys_truncate , 2)
1929 MIPS_SYS(sys_ftruncate , 2)
1930 MIPS_SYS(sys_fchmod , 2)
1931 MIPS_SYS(sys_fchown , 3) /* 4095 */
1932 MIPS_SYS(sys_getpriority , 2)
1933 MIPS_SYS(sys_setpriority , 3)
1934 MIPS_SYS(sys_ni_syscall , 0)
1935 MIPS_SYS(sys_statfs , 2)
1936 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1937 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1938 MIPS_SYS(sys_socketcall , 2)
1939 MIPS_SYS(sys_syslog , 3)
1940 MIPS_SYS(sys_setitimer , 3)
1941 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1942 MIPS_SYS(sys_newstat , 2)
1943 MIPS_SYS(sys_newlstat , 2)
1944 MIPS_SYS(sys_newfstat , 2)
1945 MIPS_SYS(sys_uname , 1)
1946 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1947 MIPS_SYS(sys_vhangup , 0)
1948 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1949 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1950 MIPS_SYS(sys_wait4 , 4)
1951 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1952 MIPS_SYS(sys_sysinfo , 1)
1953 MIPS_SYS(sys_ipc , 6)
1954 MIPS_SYS(sys_fsync , 1)
1955 MIPS_SYS(sys_sigreturn , 0)
1956 MIPS_SYS(sys_clone , 6) /* 4120 */
1957 MIPS_SYS(sys_setdomainname, 2)
1958 MIPS_SYS(sys_newuname , 1)
1959 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1960 MIPS_SYS(sys_adjtimex , 1)
1961 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1962 MIPS_SYS(sys_sigprocmask , 3)
1963 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1964 MIPS_SYS(sys_init_module , 5)
1965 MIPS_SYS(sys_delete_module, 1)
1966 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1967 MIPS_SYS(sys_quotactl , 0)
1968 MIPS_SYS(sys_getpgid , 1)
1969 MIPS_SYS(sys_fchdir , 1)
1970 MIPS_SYS(sys_bdflush , 2)
1971 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1972 MIPS_SYS(sys_personality , 1)
1973 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1974 MIPS_SYS(sys_setfsuid , 1)
1975 MIPS_SYS(sys_setfsgid , 1)
1976 MIPS_SYS(sys_llseek , 5) /* 4140 */
1977 MIPS_SYS(sys_getdents , 3)
1978 MIPS_SYS(sys_select , 5)
1979 MIPS_SYS(sys_flock , 2)
1980 MIPS_SYS(sys_msync , 3)
1981 MIPS_SYS(sys_readv , 3) /* 4145 */
1982 MIPS_SYS(sys_writev , 3)
1983 MIPS_SYS(sys_cacheflush , 3)
1984 MIPS_SYS(sys_cachectl , 3)
1985 MIPS_SYS(sys_sysmips , 4)
1986 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1987 MIPS_SYS(sys_getsid , 1)
1988 MIPS_SYS(sys_fdatasync , 0)
1989 MIPS_SYS(sys_sysctl , 1)
1990 MIPS_SYS(sys_mlock , 2)
1991 MIPS_SYS(sys_munlock , 2) /* 4155 */
1992 MIPS_SYS(sys_mlockall , 1)
1993 MIPS_SYS(sys_munlockall , 0)
1994 MIPS_SYS(sys_sched_setparam, 2)
1995 MIPS_SYS(sys_sched_getparam, 2)
1996 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1997 MIPS_SYS(sys_sched_getscheduler, 1)
1998 MIPS_SYS(sys_sched_yield , 0)
1999 MIPS_SYS(sys_sched_get_priority_max, 1)
2000 MIPS_SYS(sys_sched_get_priority_min, 1)
2001 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2002 MIPS_SYS(sys_nanosleep, 2)
2003 MIPS_SYS(sys_mremap , 5)
2004 MIPS_SYS(sys_accept , 3)
2005 MIPS_SYS(sys_bind , 3)
2006 MIPS_SYS(sys_connect , 3) /* 4170 */
2007 MIPS_SYS(sys_getpeername , 3)
2008 MIPS_SYS(sys_getsockname , 3)
2009 MIPS_SYS(sys_getsockopt , 5)
2010 MIPS_SYS(sys_listen , 2)
2011 MIPS_SYS(sys_recv , 4) /* 4175 */
2012 MIPS_SYS(sys_recvfrom , 6)
2013 MIPS_SYS(sys_recvmsg , 3)
2014 MIPS_SYS(sys_send , 4)
2015 MIPS_SYS(sys_sendmsg , 3)
2016 MIPS_SYS(sys_sendto , 6) /* 4180 */
2017 MIPS_SYS(sys_setsockopt , 5)
2018 MIPS_SYS(sys_shutdown , 2)
2019 MIPS_SYS(sys_socket , 3)
2020 MIPS_SYS(sys_socketpair , 4)
2021 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2022 MIPS_SYS(sys_getresuid , 3)
2023 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2024 MIPS_SYS(sys_poll , 3)
2025 MIPS_SYS(sys_nfsservctl , 3)
2026 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2027 MIPS_SYS(sys_getresgid , 3)
2028 MIPS_SYS(sys_prctl , 5)
2029 MIPS_SYS(sys_rt_sigreturn, 0)
2030 MIPS_SYS(sys_rt_sigaction, 4)
2031 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2032 MIPS_SYS(sys_rt_sigpending, 2)
2033 MIPS_SYS(sys_rt_sigtimedwait, 4)
2034 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2035 MIPS_SYS(sys_rt_sigsuspend, 0)
2036 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2037 MIPS_SYS(sys_pwrite64 , 6)
2038 MIPS_SYS(sys_chown , 3)
2039 MIPS_SYS(sys_getcwd , 2)
2040 MIPS_SYS(sys_capget , 2)
2041 MIPS_SYS(sys_capset , 2) /* 4205 */
2042 MIPS_SYS(sys_sigaltstack , 2)
2043 MIPS_SYS(sys_sendfile , 4)
2044 MIPS_SYS(sys_ni_syscall , 0)
2045 MIPS_SYS(sys_ni_syscall , 0)
2046 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2047 MIPS_SYS(sys_truncate64 , 4)
2048 MIPS_SYS(sys_ftruncate64 , 4)
2049 MIPS_SYS(sys_stat64 , 2)
2050 MIPS_SYS(sys_lstat64 , 2)
2051 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2052 MIPS_SYS(sys_pivot_root , 2)
2053 MIPS_SYS(sys_mincore , 3)
2054 MIPS_SYS(sys_madvise , 3)
2055 MIPS_SYS(sys_getdents64 , 3)
2056 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2057 MIPS_SYS(sys_ni_syscall , 0)
2058 MIPS_SYS(sys_gettid , 0)
2059 MIPS_SYS(sys_readahead , 5)
2060 MIPS_SYS(sys_setxattr , 5)
2061 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2062 MIPS_SYS(sys_fsetxattr , 5)
2063 MIPS_SYS(sys_getxattr , 4)
2064 MIPS_SYS(sys_lgetxattr , 4)
2065 MIPS_SYS(sys_fgetxattr , 4)
2066 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2067 MIPS_SYS(sys_llistxattr , 3)
2068 MIPS_SYS(sys_flistxattr , 3)
2069 MIPS_SYS(sys_removexattr , 2)
2070 MIPS_SYS(sys_lremovexattr, 2)
2071 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2072 MIPS_SYS(sys_tkill , 2)
2073 MIPS_SYS(sys_sendfile64 , 5)
2074 MIPS_SYS(sys_futex , 6)
2075 MIPS_SYS(sys_sched_setaffinity, 3)
2076 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2077 MIPS_SYS(sys_io_setup , 2)
2078 MIPS_SYS(sys_io_destroy , 1)
2079 MIPS_SYS(sys_io_getevents, 5)
2080 MIPS_SYS(sys_io_submit , 3)
2081 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2082 MIPS_SYS(sys_exit_group , 1)
2083 MIPS_SYS(sys_lookup_dcookie, 3)
2084 MIPS_SYS(sys_epoll_create, 1)
2085 MIPS_SYS(sys_epoll_ctl , 4)
2086 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2087 MIPS_SYS(sys_remap_file_pages, 5)
2088 MIPS_SYS(sys_set_tid_address, 1)
2089 MIPS_SYS(sys_restart_syscall, 0)
2090 MIPS_SYS(sys_fadvise64_64, 7)
2091 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2092 MIPS_SYS(sys_fstatfs64 , 2)
2093 MIPS_SYS(sys_timer_create, 3)
2094 MIPS_SYS(sys_timer_settime, 4)
2095 MIPS_SYS(sys_timer_gettime, 2)
2096 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2097 MIPS_SYS(sys_timer_delete, 1)
2098 MIPS_SYS(sys_clock_settime, 2)
2099 MIPS_SYS(sys_clock_gettime, 2)
2100 MIPS_SYS(sys_clock_getres, 2)
2101 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2102 MIPS_SYS(sys_tgkill , 3)
2103 MIPS_SYS(sys_utimes , 2)
2104 MIPS_SYS(sys_mbind , 4)
2105 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2106 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2107 MIPS_SYS(sys_mq_open , 4)
2108 MIPS_SYS(sys_mq_unlink , 1)
2109 MIPS_SYS(sys_mq_timedsend, 5)
2110 MIPS_SYS(sys_mq_timedreceive, 5)
2111 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2112 MIPS_SYS(sys_mq_getsetattr, 3)
2113 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2114 MIPS_SYS(sys_waitid , 4)
2115 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2116 MIPS_SYS(sys_add_key , 5)
2117 MIPS_SYS(sys_request_key, 4)
2118 MIPS_SYS(sys_keyctl , 5)
2119 MIPS_SYS(sys_set_thread_area, 1)
2120 MIPS_SYS(sys_inotify_init, 0)
2121 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2122 MIPS_SYS(sys_inotify_rm_watch, 2)
2123 MIPS_SYS(sys_migrate_pages, 4)
2124 MIPS_SYS(sys_openat, 4)
2125 MIPS_SYS(sys_mkdirat, 3)
2126 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2127 MIPS_SYS(sys_fchownat, 5)
2128 MIPS_SYS(sys_futimesat, 3)
2129 MIPS_SYS(sys_fstatat64, 4)
2130 MIPS_SYS(sys_unlinkat, 3)
2131 MIPS_SYS(sys_renameat, 4) /* 4295 */
2132 MIPS_SYS(sys_linkat, 5)
2133 MIPS_SYS(sys_symlinkat, 3)
2134 MIPS_SYS(sys_readlinkat, 4)
2135 MIPS_SYS(sys_fchmodat, 3)
2136 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2137 MIPS_SYS(sys_pselect6, 6)
2138 MIPS_SYS(sys_ppoll, 5)
2139 MIPS_SYS(sys_unshare, 1)
2140 MIPS_SYS(sys_splice, 6)
2141 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2142 MIPS_SYS(sys_tee, 4)
2143 MIPS_SYS(sys_vmsplice, 4)
2144 MIPS_SYS(sys_move_pages, 6)
2145 MIPS_SYS(sys_set_robust_list, 2)
2146 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2147 MIPS_SYS(sys_kexec_load, 4)
2148 MIPS_SYS(sys_getcpu, 3)
2149 MIPS_SYS(sys_epoll_pwait, 6)
2150 MIPS_SYS(sys_ioprio_set, 3)
2151 MIPS_SYS(sys_ioprio_get, 2)
2152 MIPS_SYS(sys_utimensat, 4)
2153 MIPS_SYS(sys_signalfd, 3)
2154 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2155 MIPS_SYS(sys_eventfd, 1)
2156 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2157 MIPS_SYS(sys_timerfd_create, 2)
2158 MIPS_SYS(sys_timerfd_gettime, 2)
2159 MIPS_SYS(sys_timerfd_settime, 4)
2160 MIPS_SYS(sys_signalfd4, 4)
2161 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2162 MIPS_SYS(sys_epoll_create1, 1)
2163 MIPS_SYS(sys_dup3, 3)
2164 MIPS_SYS(sys_pipe2, 2)
2165 MIPS_SYS(sys_inotify_init1, 1)
2166 MIPS_SYS(sys_preadv, 5) /* 4330 */
2167 MIPS_SYS(sys_pwritev, 5)
2168 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2169 MIPS_SYS(sys_perf_event_open, 5)
2170 MIPS_SYS(sys_accept4, 4)
2171 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2172 MIPS_SYS(sys_fanotify_init, 2)
2173 MIPS_SYS(sys_fanotify_mark, 6)
2174 MIPS_SYS(sys_prlimit64, 4)
2175 MIPS_SYS(sys_name_to_handle_at, 5)
2176 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2177 MIPS_SYS(sys_clock_adjtime, 2)
2178 MIPS_SYS(sys_syncfs, 1)
2179 MIPS_SYS(sys_sendmmsg, 4)
2180 MIPS_SYS(sys_setns, 2)
2181 MIPS_SYS(sys_process_vm_readv, 6) /* 345 */
2182 MIPS_SYS(sys_process_vm_writev, 6)
2183 MIPS_SYS(sys_kcmp, 5)
2184 MIPS_SYS(sys_finit_module, 3)
2185 MIPS_SYS(sys_sched_setattr, 2)
2186 MIPS_SYS(sys_sched_getattr, 3) /* 350 */
2187 MIPS_SYS(sys_renameat2, 5)
2188 MIPS_SYS(sys_seccomp, 3)
2189 MIPS_SYS(sys_getrandom, 3)
2190 MIPS_SYS(sys_memfd_create, 2)
2191 MIPS_SYS(sys_bpf, 3) /* 355 */
2192 MIPS_SYS(sys_execveat, 5)
2193 MIPS_SYS(sys_userfaultfd, 1)
2194 MIPS_SYS(sys_membarrier, 2)
2195 MIPS_SYS(sys_mlock2, 3)
2196 MIPS_SYS(sys_copy_file_range, 6) /* 360 */
2197 MIPS_SYS(sys_preadv2, 6)
2198 MIPS_SYS(sys_pwritev2, 6)
2199 };
2200 # undef MIPS_SYS
2201 # endif /* O32 */
2202
2203 static int do_store_exclusive(CPUMIPSState *env)
2204 {
2205 target_ulong addr;
2206 target_ulong page_addr;
2207 target_ulong val;
2208 int flags;
2209 int segv = 0;
2210 int reg;
2211 int d;
2212
2213 addr = env->lladdr;
2214 page_addr = addr & TARGET_PAGE_MASK;
2215 start_exclusive();
2216 mmap_lock();
2217 flags = page_get_flags(page_addr);
2218 if ((flags & PAGE_READ) == 0) {
2219 segv = 1;
2220 } else {
2221 reg = env->llreg & 0x1f;
2222 d = (env->llreg & 0x20) != 0;
2223 if (d) {
2224 segv = get_user_s64(val, addr);
2225 } else {
2226 segv = get_user_s32(val, addr);
2227 }
2228 if (!segv) {
2229 if (val != env->llval) {
2230 env->active_tc.gpr[reg] = 0;
2231 } else {
2232 if (d) {
2233 segv = put_user_u64(env->llnewval, addr);
2234 } else {
2235 segv = put_user_u32(env->llnewval, addr);
2236 }
2237 if (!segv) {
2238 env->active_tc.gpr[reg] = 1;
2239 }
2240 }
2241 }
2242 }
2243 env->lladdr = -1;
2244 if (!segv) {
2245 env->active_tc.PC += 4;
2246 }
2247 mmap_unlock();
2248 end_exclusive();
2249 return segv;
2250 }
2251
2252 /* Break codes */
2253 enum {
2254 BRK_OVERFLOW = 6,
2255 BRK_DIVZERO = 7
2256 };
2257
2258 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2259 unsigned int code)
2260 {
2261 int ret = -1;
2262
2263 switch (code) {
2264 case BRK_OVERFLOW:
2265 case BRK_DIVZERO:
2266 info->si_signo = TARGET_SIGFPE;
2267 info->si_errno = 0;
2268 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2269 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2270 ret = 0;
2271 break;
2272 default:
2273 info->si_signo = TARGET_SIGTRAP;
2274 info->si_errno = 0;
2275 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2276 ret = 0;
2277 break;
2278 }
2279
2280 return ret;
2281 }
2282
2283 void cpu_loop(CPUMIPSState *env)
2284 {
2285 CPUState *cs = CPU(mips_env_get_cpu(env));
2286 target_siginfo_t info;
2287 int trapnr;
2288 abi_long ret;
2289 # ifdef TARGET_ABI_MIPSO32
2290 unsigned int syscall_num;
2291 # endif
2292
2293 for(;;) {
2294 cpu_exec_start(cs);
2295 trapnr = cpu_exec(cs);
2296 cpu_exec_end(cs);
2297 process_queued_cpu_work(cs);
2298
2299 switch(trapnr) {
2300 case EXCP_SYSCALL:
2301 env->active_tc.PC += 4;
2302 # ifdef TARGET_ABI_MIPSO32
2303 syscall_num = env->active_tc.gpr[2] - 4000;
2304 if (syscall_num >= sizeof(mips_syscall_args)) {
2305 ret = -TARGET_ENOSYS;
2306 } else {
2307 int nb_args;
2308 abi_ulong sp_reg;
2309 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2310
2311 nb_args = mips_syscall_args[syscall_num];
2312 sp_reg = env->active_tc.gpr[29];
2313 switch (nb_args) {
2314 /* these arguments are taken from the stack */
2315 case 8:
2316 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2317 goto done_syscall;
2318 }
2319 case 7:
2320 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2321 goto done_syscall;
2322 }
2323 case 6:
2324 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2325 goto done_syscall;
2326 }
2327 case 5:
2328 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2329 goto done_syscall;
2330 }
2331 default:
2332 break;
2333 }
2334 ret = do_syscall(env, env->active_tc.gpr[2],
2335 env->active_tc.gpr[4],
2336 env->active_tc.gpr[5],
2337 env->active_tc.gpr[6],
2338 env->active_tc.gpr[7],
2339 arg5, arg6, arg7, arg8);
2340 }
2341 done_syscall:
2342 # else
2343 ret = do_syscall(env, env->active_tc.gpr[2],
2344 env->active_tc.gpr[4], env->active_tc.gpr[5],
2345 env->active_tc.gpr[6], env->active_tc.gpr[7],
2346 env->active_tc.gpr[8], env->active_tc.gpr[9],
2347 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2348 # endif /* O32 */
2349 if (ret == -TARGET_ERESTARTSYS) {
2350 env->active_tc.PC -= 4;
2351 break;
2352 }
2353 if (ret == -TARGET_QEMU_ESIGRETURN) {
2354 /* Returning from a successful sigreturn syscall.
2355 Avoid clobbering register state. */
2356 break;
2357 }
2358 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2359 env->active_tc.gpr[7] = 1; /* error flag */
2360 ret = -ret;
2361 } else {
2362 env->active_tc.gpr[7] = 0; /* error flag */
2363 }
2364 env->active_tc.gpr[2] = ret;
2365 break;
2366 case EXCP_TLBL:
2367 case EXCP_TLBS:
2368 case EXCP_AdEL:
2369 case EXCP_AdES:
2370 info.si_signo = TARGET_SIGSEGV;
2371 info.si_errno = 0;
2372 /* XXX: check env->error_code */
2373 info.si_code = TARGET_SEGV_MAPERR;
2374 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2375 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2376 break;
2377 case EXCP_CpU:
2378 case EXCP_RI:
2379 info.si_signo = TARGET_SIGILL;
2380 info.si_errno = 0;
2381 info.si_code = 0;
2382 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2383 break;
2384 case EXCP_INTERRUPT:
2385 /* just indicate that signals should be handled asap */
2386 break;
2387 case EXCP_DEBUG:
2388 {
2389 int sig;
2390
2391 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2392 if (sig)
2393 {
2394 info.si_signo = sig;
2395 info.si_errno = 0;
2396 info.si_code = TARGET_TRAP_BRKPT;
2397 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2398 }
2399 }
2400 break;
2401 case EXCP_SC:
2402 if (do_store_exclusive(env)) {
2403 info.si_signo = TARGET_SIGSEGV;
2404 info.si_errno = 0;
2405 info.si_code = TARGET_SEGV_MAPERR;
2406 info._sifields._sigfault._addr = env->active_tc.PC;
2407 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2408 }
2409 break;
2410 case EXCP_DSPDIS:
2411 info.si_signo = TARGET_SIGILL;
2412 info.si_errno = 0;
2413 info.si_code = TARGET_ILL_ILLOPC;
2414 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2415 break;
2416 /* The code below was inspired by the MIPS Linux kernel trap
2417 * handling code in arch/mips/kernel/traps.c.
2418 */
2419 case EXCP_BREAK:
2420 {
2421 abi_ulong trap_instr;
2422 unsigned int code;
2423
2424 if (env->hflags & MIPS_HFLAG_M16) {
2425 if (env->insn_flags & ASE_MICROMIPS) {
2426 /* microMIPS mode */
2427 ret = get_user_u16(trap_instr, env->active_tc.PC);
2428 if (ret != 0) {
2429 goto error;
2430 }
2431
2432 if ((trap_instr >> 10) == 0x11) {
2433 /* 16-bit instruction */
2434 code = trap_instr & 0xf;
2435 } else {
2436 /* 32-bit instruction */
2437 abi_ulong instr_lo;
2438
2439 ret = get_user_u16(instr_lo,
2440 env->active_tc.PC + 2);
2441 if (ret != 0) {
2442 goto error;
2443 }
2444 trap_instr = (trap_instr << 16) | instr_lo;
2445 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2446 /* Unfortunately, microMIPS also suffers from
2447 the old assembler bug... */
2448 if (code >= (1 << 10)) {
2449 code >>= 10;
2450 }
2451 }
2452 } else {
2453 /* MIPS16e mode */
2454 ret = get_user_u16(trap_instr, env->active_tc.PC);
2455 if (ret != 0) {
2456 goto error;
2457 }
2458 code = (trap_instr >> 6) & 0x3f;
2459 }
2460 } else {
2461 ret = get_user_u32(trap_instr, env->active_tc.PC);
2462 if (ret != 0) {
2463 goto error;
2464 }
2465
2466 /* As described in the original Linux kernel code, the
2467 * below checks on 'code' are to work around an old
2468 * assembly bug.
2469 */
2470 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2471 if (code >= (1 << 10)) {
2472 code >>= 10;
2473 }
2474 }
2475
2476 if (do_break(env, &info, code) != 0) {
2477 goto error;
2478 }
2479 }
2480 break;
2481 case EXCP_TRAP:
2482 {
2483 abi_ulong trap_instr;
2484 unsigned int code = 0;
2485
2486 if (env->hflags & MIPS_HFLAG_M16) {
2487 /* microMIPS mode */
2488 abi_ulong instr[2];
2489
2490 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2491 get_user_u16(instr[1], env->active_tc.PC + 2);
2492
2493 trap_instr = (instr[0] << 16) | instr[1];
2494 } else {
2495 ret = get_user_u32(trap_instr, env->active_tc.PC);
2496 }
2497
2498 if (ret != 0) {
2499 goto error;
2500 }
2501
2502 /* The immediate versions don't provide a code. */
2503 if (!(trap_instr & 0xFC000000)) {
2504 if (env->hflags & MIPS_HFLAG_M16) {
2505 /* microMIPS mode */
2506 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2507 } else {
2508 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2509 }
2510 }
2511
2512 if (do_break(env, &info, code) != 0) {
2513 goto error;
2514 }
2515 }
2516 break;
2517 case EXCP_ATOMIC:
2518 cpu_exec_step_atomic(cs);
2519 break;
2520 default:
2521 error:
2522 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2523 abort();
2524 }
2525 process_pending_signals(env);
2526 }
2527 }
2528 #endif
2529
2530 #ifdef TARGET_NIOS2
2531
2532 void cpu_loop(CPUNios2State *env)
2533 {
2534 CPUState *cs = ENV_GET_CPU(env);
2535 Nios2CPU *cpu = NIOS2_CPU(cs);
2536 target_siginfo_t info;
2537 int trapnr, gdbsig, ret;
2538
2539 for (;;) {
2540 cpu_exec_start(cs);
2541 trapnr = cpu_exec(cs);
2542 cpu_exec_end(cs);
2543 gdbsig = 0;
2544
2545 switch (trapnr) {
2546 case EXCP_INTERRUPT:
2547 /* just indicate that signals should be handled asap */
2548 break;
2549 case EXCP_TRAP:
2550 if (env->regs[R_AT] == 0) {
2551 abi_long ret;
2552 qemu_log_mask(CPU_LOG_INT, "\nSyscall\n");
2553
2554 ret = do_syscall(env, env->regs[2],
2555 env->regs[4], env->regs[5], env->regs[6],
2556 env->regs[7], env->regs[8], env->regs[9],
2557 0, 0);
2558
2559 if (env->regs[2] == 0) { /* FIXME: syscall 0 workaround */
2560 ret = 0;
2561 }
2562
2563 env->regs[2] = abs(ret);
2564 /* Return value is 0..4096 */
2565 env->regs[7] = (ret > 0xfffffffffffff000ULL);
2566 env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
2567 env->regs[CR_STATUS] &= ~0x3;
2568 env->regs[R_EA] = env->regs[R_PC] + 4;
2569 env->regs[R_PC] += 4;
2570 break;
2571 } else {
2572 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2573
2574 env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
2575 env->regs[CR_STATUS] &= ~0x3;
2576 env->regs[R_EA] = env->regs[R_PC] + 4;
2577 env->regs[R_PC] = cpu->exception_addr;
2578
2579 gdbsig = TARGET_SIGTRAP;
2580 break;
2581 }
2582 case 0xaa:
2583 switch (env->regs[R_PC]) {
2584 /*case 0x1000:*/ /* TODO:__kuser_helper_version */
2585 case 0x1004: /* __kuser_cmpxchg */
2586 start_exclusive();
2587 if (env->regs[4] & 0x3) {
2588 goto kuser_fail;
2589 }
2590 ret = get_user_u32(env->regs[2], env->regs[4]);
2591 if (ret) {
2592 end_exclusive();
2593 goto kuser_fail;
2594 }
2595 env->regs[2] -= env->regs[5];
2596 if (env->regs[2] == 0) {
2597 put_user_u32(env->regs[6], env->regs[4]);
2598 }
2599 end_exclusive();
2600 env->regs[R_PC] = env->regs[R_RA];
2601 break;
2602 /*case 0x1040:*/ /* TODO:__kuser_sigtramp */
2603 default:
2604 ;
2605 kuser_fail:
2606 info.si_signo = TARGET_SIGSEGV;
2607 info.si_errno = 0;
2608 /* TODO: check env->error_code */
2609 info.si_code = TARGET_SEGV_MAPERR;
2610 info._sifields._sigfault._addr = env->regs[R_PC];
2611 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2612 }
2613 break;
2614 default:
2615 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2616 trapnr);
2617 gdbsig = TARGET_SIGILL;
2618 break;
2619 }
2620 if (gdbsig) {
2621 gdb_handlesig(cs, gdbsig);
2622 if (gdbsig != TARGET_SIGTRAP) {
2623 exit(EXIT_FAILURE);
2624 }
2625 }
2626
2627 process_pending_signals(env);
2628 }
2629 }
2630
2631 #endif /* TARGET_NIOS2 */
2632
2633 #ifdef TARGET_OPENRISC
2634
2635 void cpu_loop(CPUOpenRISCState *env)
2636 {
2637 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2638 int trapnr;
2639 abi_long ret;
2640 target_siginfo_t info;
2641
2642 for (;;) {
2643 cpu_exec_start(cs);
2644 trapnr = cpu_exec(cs);
2645 cpu_exec_end(cs);
2646 process_queued_cpu_work(cs);
2647
2648 switch (trapnr) {
2649 case EXCP_SYSCALL:
2650 env->pc += 4; /* 0xc00; */
2651 ret = do_syscall(env,
2652 cpu_get_gpr(env, 11), /* return value */
2653 cpu_get_gpr(env, 3), /* r3 - r7 are params */
2654 cpu_get_gpr(env, 4),
2655 cpu_get_gpr(env, 5),
2656 cpu_get_gpr(env, 6),
2657 cpu_get_gpr(env, 7),
2658 cpu_get_gpr(env, 8), 0, 0);
2659 if (ret == -TARGET_ERESTARTSYS) {
2660 env->pc -= 4;
2661 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2662 cpu_set_gpr(env, 11, ret);
2663 }
2664 break;
2665 case EXCP_DPF:
2666 case EXCP_IPF:
2667 case EXCP_RANGE:
2668 info.si_signo = TARGET_SIGSEGV;
2669 info.si_errno = 0;
2670 info.si_code = TARGET_SEGV_MAPERR;
2671 info._sifields._sigfault._addr = env->pc;
2672 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2673 break;
2674 case EXCP_ALIGN:
2675 info.si_signo = TARGET_SIGBUS;
2676 info.si_errno = 0;
2677 info.si_code = TARGET_BUS_ADRALN;
2678 info._sifields._sigfault._addr = env->pc;
2679 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2680 break;
2681 case EXCP_ILLEGAL:
2682 info.si_signo = TARGET_SIGILL;
2683 info.si_errno = 0;
2684 info.si_code = TARGET_ILL_ILLOPC;
2685 info._sifields._sigfault._addr = env->pc;
2686 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2687 break;
2688 case EXCP_FPE:
2689 info.si_signo = TARGET_SIGFPE;
2690 info.si_errno = 0;
2691 info.si_code = 0;
2692 info._sifields._sigfault._addr = env->pc;
2693 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2694 break;
2695 case EXCP_INTERRUPT:
2696 /* We processed the pending cpu work above. */
2697 break;
2698 case EXCP_DEBUG:
2699 trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
2700 if (trapnr) {
2701 info.si_signo = trapnr;
2702 info.si_errno = 0;
2703 info.si_code = TARGET_TRAP_BRKPT;
2704 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2705 }
2706 break;
2707 case EXCP_ATOMIC:
2708 cpu_exec_step_atomic(cs);
2709 break;
2710 default:
2711 g_assert_not_reached();
2712 }
2713 process_pending_signals(env);
2714 }
2715 }
2716
2717 #endif /* TARGET_OPENRISC */
2718
2719 #ifdef TARGET_SH4
2720 void cpu_loop(CPUSH4State *env)
2721 {
2722 CPUState *cs = CPU(sh_env_get_cpu(env));
2723 int trapnr, ret;
2724 target_siginfo_t info;
2725
2726 while (1) {
2727 bool arch_interrupt = true;
2728
2729 cpu_exec_start(cs);
2730 trapnr = cpu_exec(cs);
2731 cpu_exec_end(cs);
2732 process_queued_cpu_work(cs);
2733
2734 switch (trapnr) {
2735 case 0x160:
2736 env->pc += 2;
2737 ret = do_syscall(env,
2738 env->gregs[3],
2739 env->gregs[4],
2740 env->gregs[5],
2741 env->gregs[6],
2742 env->gregs[7],
2743 env->gregs[0],
2744 env->gregs[1],
2745 0, 0);
2746 if (ret == -TARGET_ERESTARTSYS) {
2747 env->pc -= 2;
2748 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2749 env->gregs[0] = ret;
2750 }
2751 break;
2752 case EXCP_INTERRUPT:
2753 /* just indicate that signals should be handled asap */
2754 break;
2755 case EXCP_DEBUG:
2756 {
2757 int sig;
2758
2759 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2760 if (sig) {
2761 info.si_signo = sig;
2762 info.si_errno = 0;
2763 info.si_code = TARGET_TRAP_BRKPT;
2764 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2765 } else {
2766 arch_interrupt = false;
2767 }
2768 }
2769 break;
2770 case 0xa0:
2771 case 0xc0:
2772 info.si_signo = TARGET_SIGSEGV;
2773 info.si_errno = 0;
2774 info.si_code = TARGET_SEGV_MAPERR;
2775 info._sifields._sigfault._addr = env->tea;
2776 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2777 break;
2778 case EXCP_ATOMIC:
2779 cpu_exec_step_atomic(cs);
2780 arch_interrupt = false;
2781 break;
2782 default:
2783 printf ("Unhandled trap: 0x%x\n", trapnr);
2784 cpu_dump_state(cs, stderr, fprintf, 0);
2785 exit(EXIT_FAILURE);
2786 }
2787 process_pending_signals (env);
2788
2789 /* Most of the traps imply an exception or interrupt, which
2790 implies an REI instruction has been executed. Which means
2791 that LDST (aka LOK_ADDR) should be cleared. But there are
2792 a few exceptions for traps internal to QEMU. */
2793 if (arch_interrupt) {
2794 env->lock_addr = -1;
2795 }
2796 }
2797 }
2798 #endif
2799
2800 #ifdef TARGET_CRIS
2801 void cpu_loop(CPUCRISState *env)
2802 {
2803 CPUState *cs = CPU(cris_env_get_cpu(env));
2804 int trapnr, ret;
2805 target_siginfo_t info;
2806
2807 while (1) {
2808 cpu_exec_start(cs);
2809 trapnr = cpu_exec(cs);
2810 cpu_exec_end(cs);
2811 process_queued_cpu_work(cs);
2812
2813 switch (trapnr) {
2814 case 0xaa:
2815 {
2816 info.si_signo = TARGET_SIGSEGV;
2817 info.si_errno = 0;
2818 /* XXX: check env->error_code */
2819 info.si_code = TARGET_SEGV_MAPERR;
2820 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2821 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2822 }
2823 break;
2824 case EXCP_INTERRUPT:
2825 /* just indicate that signals should be handled asap */
2826 break;
2827 case EXCP_BREAK:
2828 ret = do_syscall(env,
2829 env->regs[9],
2830 env->regs[10],
2831 env->regs[11],
2832 env->regs[12],
2833 env->regs[13],
2834 env->pregs[7],
2835 env->pregs[11],
2836 0, 0);
2837 if (ret == -TARGET_ERESTARTSYS) {
2838 env->pc -= 2;
2839 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2840 env->regs[10] = ret;
2841 }
2842 break;
2843 case EXCP_DEBUG:
2844 {
2845 int sig;
2846
2847 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2848 if (sig)
2849 {
2850 info.si_signo = sig;
2851 info.si_errno = 0;
2852 info.si_code = TARGET_TRAP_BRKPT;
2853 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2854 }
2855 }
2856 break;
2857 case EXCP_ATOMIC:
2858 cpu_exec_step_atomic(cs);
2859 break;
2860 default:
2861 printf ("Unhandled trap: 0x%x\n", trapnr);
2862 cpu_dump_state(cs, stderr, fprintf, 0);
2863 exit(EXIT_FAILURE);
2864 }
2865 process_pending_signals (env);
2866 }
2867 }
2868 #endif
2869
2870 #ifdef TARGET_MICROBLAZE
2871 void cpu_loop(CPUMBState *env)
2872 {
2873 CPUState *cs = CPU(mb_env_get_cpu(env));
2874 int trapnr, ret;
2875 target_siginfo_t info;
2876
2877 while (1) {
2878 cpu_exec_start(cs);
2879 trapnr = cpu_exec(cs);
2880 cpu_exec_end(cs);
2881 process_queued_cpu_work(cs);
2882
2883 switch (trapnr) {
2884 case 0xaa:
2885 {
2886 info.si_signo = TARGET_SIGSEGV;
2887 info.si_errno = 0;
2888 /* XXX: check env->error_code */
2889 info.si_code = TARGET_SEGV_MAPERR;
2890 info._sifields._sigfault._addr = 0;
2891 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2892 }
2893 break;
2894 case EXCP_INTERRUPT:
2895 /* just indicate that signals should be handled asap */
2896 break;
2897 case EXCP_BREAK:
2898 /* Return address is 4 bytes after the call. */
2899 env->regs[14] += 4;
2900 env->sregs[SR_PC] = env->regs[14];
2901 ret = do_syscall(env,
2902 env->regs[12],
2903 env->regs[5],
2904 env->regs[6],
2905 env->regs[7],
2906 env->regs[8],
2907 env->regs[9],
2908 env->regs[10],
2909 0, 0);
2910 if (ret == -TARGET_ERESTARTSYS) {
2911 /* Wind back to before the syscall. */
2912 env->sregs[SR_PC] -= 4;
2913 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2914 env->regs[3] = ret;
2915 }
2916 /* All syscall exits result in guest r14 being equal to the
2917 * PC we return to, because the kernel syscall exit "rtbd" does
2918 * this. (This is true even for sigreturn(); note that r14 is
2919 * not a userspace-usable register, as the kernel may clobber it
2920 * at any point.)
2921 */
2922 env->regs[14] = env->sregs[SR_PC];
2923 break;
2924 case EXCP_HW_EXCP:
2925 env->regs[17] = env->sregs[SR_PC] + 4;
2926 if (env->iflags & D_FLAG) {
2927 env->sregs[SR_ESR] |= 1 << 12;
2928 env->sregs[SR_PC] -= 4;
2929 /* FIXME: if branch was immed, replay the imm as well. */
2930 }
2931
2932 env->iflags &= ~(IMM_FLAG | D_FLAG);
2933
2934 switch (env->sregs[SR_ESR] & 31) {
2935 case ESR_EC_DIVZERO:
2936 info.si_signo = TARGET_SIGFPE;
2937 info.si_errno = 0;
2938 info.si_code = TARGET_FPE_FLTDIV;
2939 info._sifields._sigfault._addr = 0;
2940 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2941 break;
2942 case ESR_EC_FPU:
2943 info.si_signo = TARGET_SIGFPE;
2944 info.si_errno = 0;
2945 if (env->sregs[SR_FSR] & FSR_IO) {
2946 info.si_code = TARGET_FPE_FLTINV;
2947 }
2948 if (env->sregs[SR_FSR] & FSR_DZ) {
2949 info.si_code = TARGET_FPE_FLTDIV;
2950 }
2951 info._sifields._sigfault._addr = 0;
2952 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2953 break;
2954 default:
2955 printf ("Unhandled hw-exception: 0x%x\n",
2956 env->sregs[SR_ESR] & ESR_EC_MASK);
2957 cpu_dump_state(cs, stderr, fprintf, 0);
2958 exit(EXIT_FAILURE);
2959 break;
2960 }
2961 break;
2962 case EXCP_DEBUG:
2963 {
2964 int sig;
2965
2966 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2967 if (sig)
2968 {
2969 info.si_signo = sig;
2970 info.si_errno = 0;
2971 info.si_code = TARGET_TRAP_BRKPT;
2972 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2973 }
2974 }
2975 break;
2976 case EXCP_ATOMIC:
2977 cpu_exec_step_atomic(cs);
2978 break;
2979 default:
2980 printf ("Unhandled trap: 0x%x\n", trapnr);
2981 cpu_dump_state(cs, stderr, fprintf, 0);
2982 exit(EXIT_FAILURE);
2983 }
2984 process_pending_signals (env);
2985 }
2986 }
2987 #endif
2988
2989 #ifdef TARGET_M68K
2990
2991 void cpu_loop(CPUM68KState *env)
2992 {
2993 CPUState *cs = CPU(m68k_env_get_cpu(env));
2994 int trapnr;
2995 unsigned int n;
2996 target_siginfo_t info;
2997 TaskState *ts = cs->opaque;
2998
2999 for(;;) {
3000 cpu_exec_start(cs);
3001 trapnr = cpu_exec(cs);
3002 cpu_exec_end(cs);
3003 process_queued_cpu_work(cs);
3004
3005 switch(trapnr) {
3006 case EXCP_ILLEGAL:
3007 {
3008 if (ts->sim_syscalls) {
3009 uint16_t nr;
3010 get_user_u16(nr, env->pc + 2);
3011 env->pc += 4;
3012 do_m68k_simcall(env, nr);
3013 } else {
3014 goto do_sigill;
3015 }
3016 }
3017 break;
3018 case EXCP_HALT_INSN:
3019 /* Semihosing syscall. */
3020 env->pc += 4;
3021 do_m68k_semihosting(env, env->dregs[0]);
3022 break;
3023 case EXCP_LINEA:
3024 case EXCP_LINEF:
3025 case EXCP_UNSUPPORTED:
3026 do_sigill:
3027 info.si_signo = TARGET_SIGILL;
3028 info.si_errno = 0;
3029 info.si_code = TARGET_ILL_ILLOPN;
3030 info._sifields._sigfault._addr = env->pc;
3031 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3032 break;
3033 case EXCP_CHK:
3034 info.si_signo = TARGET_SIGFPE;
3035 info.si_errno = 0;
3036 info.si_code = TARGET_FPE_INTOVF;
3037 info._sifields._sigfault._addr = env->pc;
3038 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3039 break;
3040 case EXCP_DIV0:
3041 info.si_signo = TARGET_SIGFPE;
3042 info.si_errno = 0;
3043 info.si_code = TARGET_FPE_INTDIV;
3044 info._sifields._sigfault._addr = env->pc;
3045 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3046 break;
3047 case EXCP_TRAP0:
3048 {
3049 abi_long ret;
3050 ts->sim_syscalls = 0;
3051 n = env->dregs[0];
3052 env->pc += 2;
3053 ret = do_syscall(env,
3054 n,
3055 env->dregs[1],
3056 env->dregs[2],
3057 env->dregs[3],
3058 env->dregs[4],
3059 env->dregs[5],
3060 env->aregs[0],
3061 0, 0);
3062 if (ret == -TARGET_ERESTARTSYS) {
3063 env->pc -= 2;
3064 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3065 env->dregs[0] = ret;
3066 }
3067 }
3068 break;
3069 case EXCP_INTERRUPT:
3070 /* just indicate that signals should be handled asap */
3071 break;
3072 case EXCP_ACCESS:
3073 {
3074 info.si_signo = TARGET_SIGSEGV;
3075 info.si_errno = 0;
3076 /* XXX: check env->error_code */
3077 info.si_code = TARGET_SEGV_MAPERR;
3078 info._sifields._sigfault._addr = env->mmu.ar;
3079 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3080 }
3081 break;
3082 case EXCP_DEBUG:
3083 {
3084 int sig;
3085
3086 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3087 if (sig)
3088 {
3089 info.si_signo = sig;
3090 info.si_errno = 0;
3091 info.si_code = TARGET_TRAP_BRKPT;
3092 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3093 }
3094 }
3095 break;
3096 case EXCP_ATOMIC:
3097 cpu_exec_step_atomic(cs);
3098 break;
3099 default:
3100 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
3101 abort();
3102 }
3103 process_pending_signals(env);
3104 }
3105 }
3106 #endif /* TARGET_M68K */
3107
3108 #ifdef TARGET_ALPHA
3109 void cpu_loop(CPUAlphaState *env)
3110 {
3111 CPUState *cs = CPU(alpha_env_get_cpu(env));
3112 int trapnr;
3113 target_siginfo_t info;
3114 abi_long sysret;
3115
3116 while (1) {
3117 bool arch_interrupt = true;
3118
3119 cpu_exec_start(cs);
3120 trapnr = cpu_exec(cs);
3121 cpu_exec_end(cs);
3122 process_queued_cpu_work(cs);
3123
3124 switch (trapnr) {
3125 case EXCP_RESET:
3126 fprintf(stderr, "Reset requested. Exit\n");
3127 exit(EXIT_FAILURE);
3128 break;
3129 case EXCP_MCHK:
3130 fprintf(stderr, "Machine check exception. Exit\n");
3131 exit(EXIT_FAILURE);
3132 break;
3133 case EXCP_SMP_INTERRUPT:
3134 case EXCP_CLK_INTERRUPT:
3135 case EXCP_DEV_INTERRUPT:
3136 fprintf(stderr, "External interrupt. Exit\n");
3137 exit(EXIT_FAILURE);
3138 break;
3139 case EXCP_MMFAULT:
3140 info.si_signo = TARGET_SIGSEGV;
3141 info.si_errno = 0;
3142 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3143 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3144 info._sifields._sigfault._addr = env->trap_arg0;
3145 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3146 break;
3147 case EXCP_UNALIGN:
3148 info.si_signo = TARGET_SIGBUS;
3149 info.si_errno = 0;
3150 info.si_code = TARGET_BUS_ADRALN;
3151 info._sifields._sigfault._addr = env->trap_arg0;
3152 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3153 break;
3154 case EXCP_OPCDEC:
3155 do_sigill:
3156 info.si_signo = TARGET_SIGILL;
3157 info.si_errno = 0;
3158 info.si_code = TARGET_ILL_ILLOPC;
3159 info._sifields._sigfault._addr = env->pc;
3160 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3161 break;
3162 case EXCP_ARITH:
3163 info.si_signo = TARGET_SIGFPE;
3164 info.si_errno = 0;
3165 info.si_code = TARGET_FPE_FLTINV;
3166 info._sifields._sigfault._addr = env->pc;
3167 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3168 break;
3169 case EXCP_FEN:
3170 /* No-op. Linux simply re-enables the FPU. */
3171 break;
3172 case EXCP_CALL_PAL:
3173 switch (env->error_code) {
3174 case 0x80:
3175 /* BPT */
3176 info.si_signo = TARGET_SIGTRAP;
3177 info.si_errno = 0;
3178 info.si_code = TARGET_TRAP_BRKPT;
3179 info._sifields._sigfault._addr = env->pc;
3180 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3181 break;
3182 case 0x81:
3183 /* BUGCHK */
3184 info.si_signo = TARGET_SIGTRAP;
3185 info.si_errno = 0;
3186 info.si_code = 0;
3187 info._sifields._sigfault._addr = env->pc;
3188 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3189 break;
3190 case 0x83:
3191 /* CALLSYS */
3192 trapnr = env->ir[IR_V0];
3193 sysret = do_syscall(env, trapnr,
3194 env->ir[IR_A0], env->ir[IR_A1],
3195 env->ir[IR_A2], env->ir[IR_A3],
3196 env->ir[IR_A4], env->ir[IR_A5],
3197 0, 0);
3198 if (sysret == -TARGET_ERESTARTSYS) {
3199 env->pc -= 4;
3200 break;
3201 }
3202 if (sysret == -TARGET_QEMU_ESIGRETURN) {
3203 break;
3204 }
3205 /* Syscall writes 0 to V0 to bypass error check, similar
3206 to how this is handled internal to Linux kernel.
3207 (Ab)use trapnr temporarily as boolean indicating error. */
3208 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3209 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3210 env->ir[IR_A3] = trapnr;
3211 break;
3212 case 0x86:
3213 /* IMB */
3214 /* ??? We can probably elide the code using page_unprotect
3215 that is checking for self-modifying code. Instead we
3216 could simply call tb_flush here. Until we work out the
3217 changes required to turn off the extra write protection,
3218 this can be a no-op. */
3219 break;
3220 case 0x9E:
3221 /* RDUNIQUE */
3222 /* Handled in the translator for usermode. */
3223 abort();
3224 case 0x9F:
3225 /* WRUNIQUE */
3226 /* Handled in the translator for usermode. */
3227 abort();
3228 case 0xAA:
3229 /* GENTRAP */
3230 info.si_signo = TARGET_SIGFPE;
3231 switch (env->ir[IR_A0]) {
3232 case TARGET_GEN_INTOVF:
3233 info.si_code = TARGET_FPE_INTOVF;
3234 break;
3235 case TARGET_GEN_INTDIV:
3236 info.si_code = TARGET_FPE_INTDIV;
3237 break;
3238 case TARGET_GEN_FLTOVF:
3239 info.si_code = TARGET_FPE_FLTOVF;
3240 break;
3241 case TARGET_GEN_FLTUND:
3242 info.si_code = TARGET_FPE_FLTUND;
3243 break;
3244 case TARGET_GEN_FLTINV:
3245 info.si_code = TARGET_FPE_FLTINV;
3246 break;
3247 case TARGET_GEN_FLTINE:
3248 info.si_code = TARGET_FPE_FLTRES;
3249 break;
3250 case TARGET_GEN_ROPRAND:
3251 info.si_code = 0;
3252 break;
3253 default:
3254 info.si_signo = TARGET_SIGTRAP;
3255 info.si_code = 0;
3256 break;
3257 }
3258 info.si_errno = 0;
3259 info._sifields._sigfault._addr = env->pc;
3260 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3261 break;
3262 default:
3263 goto do_sigill;
3264 }
3265 break;
3266 case EXCP_DEBUG:
3267 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3268 if (info.si_signo) {
3269 info.si_errno = 0;
3270 info.si_code = TARGET_TRAP_BRKPT;
3271 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3272 } else {
3273 arch_interrupt = false;
3274 }
3275 break;
3276 case EXCP_INTERRUPT:
3277 /* Just indicate that signals should be handled asap. */
3278 break;
3279 case EXCP_ATOMIC:
3280 cpu_exec_step_atomic(cs);
3281 arch_interrupt = false;
3282 break;
3283 default:
3284 printf ("Unhandled trap: 0x%x\n", trapnr);
3285 cpu_dump_state(cs, stderr, fprintf, 0);
3286 exit(EXIT_FAILURE);
3287 }
3288 process_pending_signals (env);
3289
3290 /* Most of the traps imply a transition through PALcode, which
3291 implies an REI instruction has been executed. Which means
3292 that RX and LOCK_ADDR should be cleared. But there are a
3293 few exceptions for traps internal to QEMU. */
3294 if (arch_interrupt) {
3295 env->flags &= ~ENV_FLAG_RX_FLAG;
3296 env->lock_addr = -1;
3297 }
3298 }
3299 }
3300 #endif /* TARGET_ALPHA */
3301
3302 #ifdef TARGET_S390X
3303
3304 /* s390x masks the fault address it reports in si_addr for SIGSEGV and SIGBUS */
3305 #define S390X_FAIL_ADDR_MASK -4096LL
3306
3307 void cpu_loop(CPUS390XState *env)
3308 {
3309 CPUState *cs = CPU(s390_env_get_cpu(env));
3310 int trapnr, n, sig;
3311 target_siginfo_t info;
3312 target_ulong addr;
3313 abi_long ret;
3314
3315 while (1) {
3316 cpu_exec_start(cs);
3317 trapnr = cpu_exec(cs);
3318 cpu_exec_end(cs);
3319 process_queued_cpu_work(cs);
3320
3321 switch (trapnr) {
3322 case EXCP_INTERRUPT:
3323 /* Just indicate that signals should be handled asap. */
3324 break;
3325
3326 case EXCP_SVC:
3327 n = env->int_svc_code;
3328 if (!n) {
3329 /* syscalls > 255 */
3330 n = env->regs[1];
3331 }
3332 env->psw.addr += env->int_svc_ilen;
3333 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3334 env->regs[4], env->regs[5],
3335 env->regs[6], env->regs[7], 0, 0);
3336 if (ret == -TARGET_ERESTARTSYS) {
3337 env->psw.addr -= env->int_svc_ilen;
3338 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3339 env->regs[2] = ret;
3340 }
3341 break;
3342
3343 case EXCP_DEBUG:
3344 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3345 if (sig) {
3346 n = TARGET_TRAP_BRKPT;
3347 goto do_signal_pc;
3348 }
3349 break;
3350 case EXCP_PGM:
3351 n = env->int_pgm_code;
3352 switch (n) {
3353 case PGM_OPERATION:
3354 case PGM_PRIVILEGED:
3355 sig = TARGET_SIGILL;
3356 n = TARGET_ILL_ILLOPC;
3357 goto do_signal_pc;
3358 case PGM_PROTECTION:
3359 case PGM_ADDRESSING:
3360 sig = TARGET_SIGSEGV;
3361 /* XXX: check env->error_code */
3362 n = TARGET_SEGV_MAPERR;
3363 addr = env->__excp_addr & S390X_FAIL_ADDR_MASK;
3364 goto do_signal;
3365 case PGM_EXECUTE:
3366 case PGM_SPECIFICATION:
3367 case PGM_SPECIAL_OP:
3368 case PGM_OPERAND:
3369 do_sigill_opn:
3370 sig = TARGET_SIGILL;
3371 n = TARGET_ILL_ILLOPN;
3372 goto do_signal_pc;
3373
3374 case PGM_FIXPT_OVERFLOW:
3375 sig = TARGET_SIGFPE;
3376 n = TARGET_FPE_INTOVF;
3377 goto do_signal_pc;
3378 case PGM_FIXPT_DIVIDE:
3379 sig = TARGET_SIGFPE;
3380 n = TARGET_FPE_INTDIV;
3381 goto do_signal_pc;
3382
3383 case PGM_DATA:
3384 n = (env->fpc >> 8) & 0xff;
3385 if (n == 0xff) {
3386 /* compare-and-trap */
3387 goto do_sigill_opn;
3388 } else {
3389 /* An IEEE exception, simulated or otherwise. */
3390 if (n & 0x80) {
3391 n = TARGET_FPE_FLTINV;
3392 } else if (n & 0x40) {
3393 n = TARGET_FPE_FLTDIV;
3394 } else if (n & 0x20) {
3395 n = TARGET_FPE_FLTOVF;
3396 } else if (n & 0x10) {
3397 n = TARGET_FPE_FLTUND;
3398 } else if (n & 0x08) {
3399 n = TARGET_FPE_FLTRES;
3400 } else {
3401 /* ??? Quantum exception; BFP, DFP error. */
3402 goto do_sigill_opn;
3403 }
3404 sig = TARGET_SIGFPE;
3405 goto do_signal_pc;
3406 }
3407
3408 default:
3409 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3410 cpu_dump_state(cs, stderr, fprintf, 0);
3411 exit(EXIT_FAILURE);
3412 }
3413 break;
3414
3415 do_signal_pc:
3416 addr = env->psw.addr;
3417 do_signal:
3418 info.si_signo = sig;
3419 info.si_errno = 0;
3420 info.si_code = n;
3421 info._sifields._sigfault._addr = addr;
3422 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3423 break;
3424
3425 case EXCP_ATOMIC:
3426 cpu_exec_step_atomic(cs);
3427 break;
3428 default:
3429 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3430 cpu_dump_state(cs, stderr, fprintf, 0);
3431 exit(EXIT_FAILURE);
3432 }
3433 process_pending_signals (env);
3434 }
3435 }
3436
3437 #endif /* TARGET_S390X */
3438
3439 #ifdef TARGET_TILEGX
3440
3441 static void gen_sigill_reg(CPUTLGState *env)
3442 {
3443 target_siginfo_t info;
3444
3445 info.si_signo = TARGET_SIGILL;
3446 info.si_errno = 0;
3447 info.si_code = TARGET_ILL_PRVREG;
3448 info._sifields._sigfault._addr = env->pc;
3449 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3450 }
3451
3452 static void do_signal(CPUTLGState *env, int signo, int sigcode)
3453 {
3454 target_siginfo_t info;
3455
3456 info.si_signo = signo;
3457 info.si_errno = 0;
3458 info._sifields._sigfault._addr = env->pc;
3459
3460 if (signo == TARGET_SIGSEGV) {
3461 /* The passed in sigcode is a dummy; check for a page mapping
3462 and pass either MAPERR or ACCERR. */
3463 target_ulong addr = env->excaddr;
3464 info._sifields._sigfault._addr = addr;
3465 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3466 sigcode = TARGET_SEGV_MAPERR;
3467 } else {
3468 sigcode = TARGET_SEGV_ACCERR;
3469 }
3470 }
3471 info.si_code = sigcode;
3472
3473 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3474 }
3475
3476 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3477 {
3478 env->excaddr = addr;
3479 do_signal(env, TARGET_SIGSEGV, 0);
3480 }
3481
3482 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3483 {
3484 if (unlikely(reg >= TILEGX_R_COUNT)) {
3485 switch (reg) {
3486 case TILEGX_R_SN:
3487 case TILEGX_R_ZERO:
3488 return;
3489 case TILEGX_R_IDN0:
3490 case TILEGX_R_IDN1:
3491 case TILEGX_R_UDN0:
3492 case TILEGX_R_UDN1:
3493 case TILEGX_R_UDN2:
3494 case TILEGX_R_UDN3:
3495 gen_sigill_reg(env);
3496 return;
3497 default:
3498 g_assert_not_reached();
3499 }
3500 }
3501 env->regs[reg] = val;
3502 }
3503
3504 /*
3505 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3506 * memory at the address held in the first source register. If the values are
3507 * not equal, then no memory operation is performed. If the values are equal,
3508 * the 8-byte quantity from the second source register is written into memory
3509 * at the address held in the first source register. In either case, the result
3510 * of the instruction is the value read from memory. The compare and write to
3511 * memory are atomic and thus can be used for synchronization purposes. This
3512 * instruction only operates for addresses aligned to a 8-byte boundary.
3513 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3514 *
3515 * Functional Description (64-bit)
3516 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3517 * rf[Dest] = memVal;
3518 * if (memVal == SPR[CmpValueSPR])
3519 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3520 *
3521 * Functional Description (32-bit)
3522 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3523 * rf[Dest] = memVal;
3524 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3525 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3526 *
3527 *
3528 * This function also processes exch and exch4 which need not process SPR.
3529 */
3530 static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3531 {
3532 target_ulong addr;
3533 target_long val, sprval;
3534
3535 start_exclusive();
3536
3537 addr = env->atomic_srca;
3538 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3539 goto sigsegv_maperr;
3540 }
3541
3542 if (cmp) {
3543 if (quad) {
3544 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3545 } else {
3546 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3547 }
3548 }
3549
3550 if (!cmp || val == sprval) {
3551 target_long valb = env->atomic_srcb;
3552 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3553 goto sigsegv_maperr;
3554 }
3555 }
3556
3557 set_regval(env, env->atomic_dstr, val);
3558 end_exclusive();
3559 return;
3560
3561 sigsegv_maperr:
3562 end_exclusive();
3563 gen_sigsegv_maperr(env, addr);
3564 }
3565
3566 static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3567 {
3568 int8_t write = 1;
3569 target_ulong addr;
3570 target_long val, valb;
3571
3572 start_exclusive();
3573
3574 addr = env->atomic_srca;
3575 valb = env->atomic_srcb;
3576 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3577 goto sigsegv_maperr;
3578 }
3579
3580 switch (trapnr) {
3581 case TILEGX_EXCP_OPCODE_FETCHADD:
3582 case TILEGX_EXCP_OPCODE_FETCHADD4:
3583 valb += val;
3584 break;
3585 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3586 valb += val;
3587 if (valb < 0) {
3588 write = 0;
3589 }
3590 break;
3591 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3592 valb += val;
3593 if ((int32_t)valb < 0) {
3594 write = 0;
3595 }
3596 break;
3597 case TILEGX_EXCP_OPCODE_FETCHAND:
3598 case TILEGX_EXCP_OPCODE_FETCHAND4:
3599 valb &= val;
3600 break;
3601 case TILEGX_EXCP_OPCODE_FETCHOR:
3602 case TILEGX_EXCP_OPCODE_FETCHOR4:
3603 valb |= val;
3604 break;
3605 default:
3606 g_assert_not_reached();
3607 }
3608
3609 if (write) {
3610 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3611 goto sigsegv_maperr;
3612 }
3613 }
3614
3615 set_regval(env, env->atomic_dstr, val);
3616 end_exclusive();
3617 return;
3618
3619 sigsegv_maperr:
3620 end_exclusive();
3621 gen_sigsegv_maperr(env, addr);
3622 }
3623
3624 void cpu_loop(CPUTLGState *env)
3625 {
3626 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3627 int trapnr;
3628
3629 while (1) {
3630 cpu_exec_start(cs);
3631 trapnr = cpu_exec(cs);
3632 cpu_exec_end(cs);
3633 process_queued_cpu_work(cs);
3634
3635 switch (trapnr) {
3636 case TILEGX_EXCP_SYSCALL:
3637 {
3638 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3639 env->regs[0], env->regs[1],
3640 env->regs[2], env->regs[3],
3641 env->regs[4], env->regs[5],
3642 env->regs[6], env->regs[7]);
3643 if (ret == -TARGET_ERESTARTSYS) {
3644 env->pc -= 8;
3645 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3646 env->regs[TILEGX_R_RE] = ret;
3647 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3648 }
3649 break;
3650 }
3651 case TILEGX_EXCP_OPCODE_EXCH:
3652 do_exch(env, true, false);
3653 break;
3654 case TILEGX_EXCP_OPCODE_EXCH4:
3655 do_exch(env, false, false);
3656 break;
3657 case TILEGX_EXCP_OPCODE_CMPEXCH:
3658 do_exch(env, true, true);
3659 break;
3660 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3661 do_exch(env, false, true);
3662 break;
3663 case TILEGX_EXCP_OPCODE_FETCHADD:
3664 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3665 case TILEGX_EXCP_OPCODE_FETCHAND:
3666 case TILEGX_EXCP_OPCODE_FETCHOR:
3667 do_fetch(env, trapnr, true);
3668 break;
3669 case TILEGX_EXCP_OPCODE_FETCHADD4:
3670 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3671 case TILEGX_EXCP_OPCODE_FETCHAND4:
3672 case TILEGX_EXCP_OPCODE_FETCHOR4:
3673 do_fetch(env, trapnr, false);
3674 break;
3675 case TILEGX_EXCP_SIGNAL:
3676 do_signal(env, env->signo, env->sigcode);
3677 break;
3678 case TILEGX_EXCP_REG_IDN_ACCESS:
3679 case TILEGX_EXCP_REG_UDN_ACCESS:
3680 gen_sigill_reg(env);
3681 break;
3682 case EXCP_ATOMIC:
3683 cpu_exec_step_atomic(cs);
3684 break;
3685 default:
3686 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3687 g_assert_not_reached();
3688 }
3689 process_pending_signals(env);
3690 }
3691 }
3692
3693 #endif
3694
3695 #ifdef TARGET_HPPA
3696
3697 static abi_ulong hppa_lws(CPUHPPAState *env)
3698 {
3699 uint32_t which = env->gr[20];
3700 abi_ulong addr = env->gr[26];
3701 abi_ulong old = env->gr[25];
3702 abi_ulong new = env->gr[24];
3703 abi_ulong size, ret;
3704
3705 switch (which) {
3706 default:
3707 return -TARGET_ENOSYS;
3708
3709 case 0: /* elf32 atomic 32bit cmpxchg */
3710 if ((addr & 3) || !access_ok(VERIFY_WRITE, addr, 4)) {
3711 return -TARGET_EFAULT;
3712 }
3713 old = tswap32(old);
3714 new = tswap32(new);
3715 ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
3716 ret = tswap32(ret);
3717 break;
3718
3719 case 2: /* elf32 atomic "new" cmpxchg */
3720 size = env->gr[23];
3721 if (size >= 4) {
3722 return -TARGET_ENOSYS;
3723 }
3724 if (((addr | old | new) & ((1 << size) - 1))
3725 || !access_ok(VERIFY_WRITE, addr, 1 << size)
3726 || !access_ok(VERIFY_READ, old, 1 << size)
3727 || !access_ok(VERIFY_READ, new, 1 << size)) {
3728 return -TARGET_EFAULT;
3729 }
3730 /* Note that below we use host-endian loads so that the cmpxchg
3731 can be host-endian as well. */
3732 switch (size) {
3733 case 0:
3734 old = *(uint8_t *)g2h(old);
3735 new = *(uint8_t *)g2h(new);
3736 ret = atomic_cmpxchg((uint8_t *)g2h(addr), old, new);
3737 ret = ret != old;
3738 break;
3739 case 1:
3740 old = *(uint16_t *)g2h(old);
3741 new = *(uint16_t *)g2h(new);
3742 ret = atomic_cmpxchg((uint16_t *)g2h(addr), old, new);
3743 ret = ret != old;
3744 break;
3745 case 2:
3746 old = *(uint32_t *)g2h(old);
3747 new = *(uint32_t *)g2h(new);
3748 ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
3749 ret = ret != old;
3750 break;
3751 case 3:
3752 {
3753 uint64_t o64, n64, r64;
3754 o64 = *(uint64_t *)g2h(old);
3755 n64 = *(uint64_t *)g2h(new);
3756 #ifdef CONFIG_ATOMIC64
3757 r64 = atomic_cmpxchg__nocheck((uint64_t *)g2h(addr), o64, n64);
3758 ret = r64 != o64;
3759 #else
3760 start_exclusive();
3761 r64 = *(uint64_t *)g2h(addr);
3762 ret = 1;
3763 if (r64 == o64) {
3764 *(uint64_t *)g2h(addr) = n64;
3765 ret = 0;
3766 }
3767 end_exclusive();
3768 #endif
3769 }
3770 break;
3771 }
3772 break;
3773 }
3774
3775 env->gr[28] = ret;
3776 return 0;
3777 }
3778
3779 void cpu_loop(CPUHPPAState *env)
3780 {
3781 CPUState *cs = CPU(hppa_env_get_cpu(env));
3782 target_siginfo_t info;
3783 abi_ulong ret;
3784 int trapnr;
3785
3786 while (1) {
3787 cpu_exec_start(cs);
3788 trapnr = cpu_exec(cs);
3789 cpu_exec_end(cs);
3790 process_queued_cpu_work(cs);
3791
3792 switch (trapnr) {
3793 case EXCP_SYSCALL:
3794 ret = do_syscall(env, env->gr[20],
3795 env->gr[26], env->gr[25],
3796 env->gr[24], env->gr[23],
3797 env->gr[22], env->gr[21], 0, 0);
3798 switch (ret) {
3799 default:
3800 env->gr[28] = ret;
3801 /* We arrived here by faking the gateway page. Return. */
3802 env->iaoq_f = env->gr[31];
3803 env->iaoq_b = env->gr[31] + 4;
3804 break;
3805 case -TARGET_ERESTARTSYS:
3806 case -TARGET_QEMU_ESIGRETURN:
3807 break;
3808 }
3809 break;
3810 case EXCP_SYSCALL_LWS:
3811 env->gr[21] = hppa_lws(env);
3812 /* We arrived here by faking the gateway page. Return. */
3813 env->iaoq_f = env->gr[31];
3814 env->iaoq_b = env->gr[31] + 4;
3815 break;
3816 case EXCP_SIGSEGV:
3817 info.si_signo = TARGET_SIGSEGV;
3818 info.si_errno = 0;
3819 info.si_code = TARGET_SEGV_ACCERR;
3820 info._sifields._sigfault._addr = env->ior;
3821 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3822 break;
3823 case EXCP_SIGILL:
3824 info.si_signo = TARGET_SIGILL;
3825 info.si_errno = 0;
3826 info.si_code = TARGET_ILL_ILLOPN;
3827 info._sifields._sigfault._addr = env->iaoq_f;
3828 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3829 break;
3830 case EXCP_SIGFPE:
3831 info.si_signo = TARGET_SIGFPE;
3832 info.si_errno = 0;
3833 info.si_code = 0;
3834 info._sifields._sigfault._addr = env->iaoq_f;
3835 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3836 break;
3837 case EXCP_DEBUG:
3838 trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
3839 if (trapnr) {
3840 info.si_signo = trapnr;
3841 info.si_errno = 0;
3842 info.si_code = TARGET_TRAP_BRKPT;
3843 queue_signal(env, trapnr, QEMU_SI_FAULT, &info);
3844 }
3845 break;
3846 case EXCP_INTERRUPT:
3847 /* just indicate that signals should be handled asap */
3848 break;
3849 default:
3850 g_assert_not_reached();
3851 }
3852 process_pending_signals(env);
3853 }
3854 }
3855
3856 #endif /* TARGET_HPPA */
3857
3858 THREAD CPUState *thread_cpu;
3859
3860 bool qemu_cpu_is_self(CPUState *cpu)
3861 {
3862 return thread_cpu == cpu;
3863 }
3864
3865 void qemu_cpu_kick(CPUState *cpu)
3866 {
3867 cpu_exit(cpu);
3868 }
3869
3870 void task_settid(TaskState *ts)
3871 {
3872 if (ts->ts_tid == 0) {
3873 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3874 }
3875 }
3876
3877 void stop_all_tasks(void)
3878 {
3879 /*
3880 * We trust that when using NPTL, start_exclusive()
3881 * handles thread stopping correctly.
3882 */
3883 start_exclusive();
3884 }
3885
3886 /* Assumes contents are already zeroed. */
3887 void init_task_state(TaskState *ts)
3888 {
3889 ts->used = 1;
3890 }
3891
3892 CPUArchState *cpu_copy(CPUArchState *env)
3893 {
3894 CPUState *cpu = ENV_GET_CPU(env);
3895 CPUState *new_cpu = cpu_init(cpu_model);
3896 CPUArchState *new_env = new_cpu->env_ptr;
3897 CPUBreakpoint *bp;
3898 CPUWatchpoint *wp;
3899
3900 /* Reset non arch specific state */
3901 cpu_reset(new_cpu);
3902
3903 memcpy(new_env, env, sizeof(CPUArchState));
3904
3905 /* Clone all break/watchpoints.
3906 Note: Once we support ptrace with hw-debug register access, make sure
3907 BP_CPU break/watchpoints are handled correctly on clone. */
3908 QTAILQ_INIT(&new_cpu->breakpoints);
3909 QTAILQ_INIT(&new_cpu->watchpoints);
3910 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3911 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3912 }
3913 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3914 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3915 }
3916
3917 return new_env;
3918 }
3919
3920 static void handle_arg_help(const char *arg)
3921 {
3922 usage(EXIT_SUCCESS);
3923 }
3924
3925 static void handle_arg_log(const char *arg)
3926 {
3927 int mask;
3928
3929 mask = qemu_str_to_log_mask(arg);
3930 if (!mask) {
3931 qemu_print_log_usage(stdout);
3932 exit(EXIT_FAILURE);
3933 }
3934 qemu_log_needs_buffers();
3935 qemu_set_log(mask);
3936 }
3937
3938 static void handle_arg_dfilter(const char *arg)
3939 {
3940 qemu_set_dfilter_ranges(arg, NULL);
3941 }
3942
3943 static void handle_arg_log_filename(const char *arg)
3944 {
3945 qemu_set_log_filename(arg, &error_fatal);
3946 }
3947
3948 static void handle_arg_set_env(const char *arg)
3949 {
3950 char *r, *p, *token;
3951 r = p = strdup(arg);
3952 while ((token = strsep(&p, ",")) != NULL) {
3953 if (envlist_setenv(envlist, token) != 0) {
3954 usage(EXIT_FAILURE);
3955 }
3956 }
3957 free(r);
3958 }
3959
3960 static void handle_arg_unset_env(const char *arg)
3961 {
3962 char *r, *p, *token;
3963 r = p = strdup(arg);
3964 while ((token = strsep(&p, ",")) != NULL) {
3965 if (envlist_unsetenv(envlist, token) != 0) {
3966 usage(EXIT_FAILURE);
3967 }
3968 }
3969 free(r);
3970 }
3971
3972 static void handle_arg_argv0(const char *arg)
3973 {
3974 argv0 = strdup(arg);
3975 }
3976
3977 static void handle_arg_stack_size(const char *arg)
3978 {
3979 char *p;
3980 guest_stack_size = strtoul(arg, &p, 0);
3981 if (guest_stack_size == 0) {
3982 usage(EXIT_FAILURE);
3983 }
3984
3985 if (*p == 'M') {
3986 guest_stack_size *= 1024 * 1024;
3987 } else if (*p == 'k' || *p == 'K') {
3988 guest_stack_size *= 1024;
3989 }
3990 }
3991
3992 static void handle_arg_ld_prefix(const char *arg)
3993 {
3994 interp_prefix = strdup(arg);
3995 }
3996
3997 static void handle_arg_pagesize(const char *arg)
3998 {
3999 qemu_host_page_size = atoi(arg);
4000 if (qemu_host_page_size == 0 ||
4001 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
4002 fprintf(stderr, "page size must be a power of two\n");
4003 exit(EXIT_FAILURE);
4004 }
4005 }
4006
4007 static void handle_arg_randseed(const char *arg)
4008 {
4009 unsigned long long seed;
4010
4011 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
4012 fprintf(stderr, "Invalid seed number: %s\n", arg);
4013 exit(EXIT_FAILURE);
4014 }
4015 srand(seed);
4016 }
4017
4018 static void handle_arg_gdb(const char *arg)
4019 {
4020 gdbstub_port = atoi(arg);
4021 }
4022
4023 static void handle_arg_uname(const char *arg)
4024 {
4025 qemu_uname_release = strdup(arg);
4026 }
4027
4028 static void handle_arg_cpu(const char *arg)
4029 {
4030 cpu_model = strdup(arg);
4031 if (cpu_model == NULL || is_help_option(cpu_model)) {
4032 /* XXX: implement xxx_cpu_list for targets that still miss it */
4033 #if defined(cpu_list)
4034 cpu_list(stdout, &fprintf); /* deprecated */
4035 #else
4036 /* TODO: add cpu selection for alpha, microblaze, unicore32, s390x. */
4037 printf("Target ignores cpu selection\n");
4038 #endif
4039 exit(EXIT_FAILURE);
4040 }
4041 }
4042
4043 static void handle_arg_guest_base(const char *arg)
4044 {
4045 guest_base = strtol(arg, NULL, 0);
4046 have_guest_base = 1;
4047 }
4048
4049 static void handle_arg_reserved_va(const char *arg)
4050 {
4051 char *p;
4052 int shift = 0;
4053 reserved_va = strtoul(arg, &p, 0);
4054 switch (*p) {
4055 case 'k':
4056 case 'K':
4057 shift = 10;
4058 break;
4059 case 'M':
4060 shift = 20;
4061 break;
4062 case 'G':
4063 shift = 30;
4064 break;
4065 }
4066 if (shift) {
4067 unsigned long unshifted = reserved_va;
4068 p++;
4069 reserved_va <<= shift;
4070 if (reserved_va >> shift != unshifted
4071 || (MAX_RESERVED_VA && reserved_va > MAX_RESERVED_VA)) {
4072 fprintf(stderr, "Reserved virtual address too big\n");
4073 exit(EXIT_FAILURE);
4074 }
4075 }
4076 if (*p) {
4077 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
4078 exit(EXIT_FAILURE);
4079 }
4080 }
4081
4082 static void handle_arg_singlestep(const char *arg)
4083 {
4084 singlestep = 1;
4085 }
4086
4087 static void handle_arg_strace(const char *arg)
4088 {
4089 do_strace = 1;
4090 }
4091
4092 static void handle_arg_version(const char *arg)
4093 {
4094 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
4095 "\n" QEMU_COPYRIGHT "\n");
4096 exit(EXIT_SUCCESS);
4097 }
4098
4099 static char *trace_file;
4100 static void handle_arg_trace(const char *arg)
4101 {
4102 g_free(trace_file);
4103 trace_file = trace_opt_parse(arg);
4104 }
4105
4106 struct qemu_argument {
4107 const char *argv;
4108 const char *env;
4109 bool has_arg;
4110 void (*handle_opt)(const char *arg);
4111 const char *example;
4112 const char *help;
4113 };
4114
4115 static const struct qemu_argument arg_table[] = {
4116 {"h", "", false, handle_arg_help,
4117 "", "print this help"},
4118 {"help", "", false, handle_arg_help,
4119 "", ""},
4120 {"g", "QEMU_GDB", true, handle_arg_gdb,
4121 "port", "wait gdb connection to 'port'"},
4122 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
4123 "path", "set the elf interpreter prefix to 'path'"},
4124 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
4125 "size", "set the stack size to 'size' bytes"},
4126 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
4127 "model", "select CPU (-cpu help for list)"},
4128 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
4129 "var=value", "sets targets environment variable (see below)"},
4130 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
4131 "var", "unsets targets environment variable (see below)"},
4132 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
4133 "argv0", "forces target process argv[0] to be 'argv0'"},
4134 {"r", "QEMU_UNAME", true, handle_arg_uname,
4135 "uname", "set qemu uname release string to 'uname'"},
4136 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
4137 "address", "set guest_base address to 'address'"},
4138 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
4139 "size", "reserve 'size' bytes for guest virtual address space"},
4140 {"d", "QEMU_LOG", true, handle_arg_log,
4141 "item[,...]", "enable logging of specified items "
4142 "(use '-d help' for a list of items)"},
4143 {"dfilter", "QEMU_DFILTER", true, handle_arg_dfilter,
4144 "range[,...]","filter logging based on address range"},
4145 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
4146 "logfile", "write logs to 'logfile' (default stderr)"},
4147 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4148 "pagesize", "set the host page size to 'pagesize'"},
4149 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4150 "", "run in singlestep mode"},
4151 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4152 "", "log system calls"},
4153 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4154 "", "Seed for pseudo-random number generator"},
4155 {"trace", "QEMU_TRACE", true, handle_arg_trace,
4156 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
4157 {"version", "QEMU_VERSION", false, handle_arg_version,
4158 "", "display version information and exit"},
4159 {NULL, NULL, false, NULL, NULL, NULL}
4160 };
4161
4162 static void QEMU_NORETURN usage(int exitcode)
4163 {
4164 const struct qemu_argument *arginfo;
4165 int maxarglen;
4166 int maxenvlen;
4167
4168 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4169 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
4170 "\n"
4171 "Options and associated environment variables:\n"
4172 "\n");
4173
4174 /* Calculate column widths. We must always have at least enough space
4175 * for the column header.
4176 */
4177 maxarglen = strlen("Argument");
4178 maxenvlen = strlen("Env-variable");
4179
4180 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4181 int arglen = strlen(arginfo->argv);
4182 if (arginfo->has_arg) {
4183 arglen += strlen(arginfo->example) + 1;
4184 }
4185 if (strlen(arginfo->env) > maxenvlen) {
4186 maxenvlen = strlen(arginfo->env);
4187 }
4188 if (arglen > maxarglen) {
4189 maxarglen = arglen;
4190 }
4191 }
4192
4193 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4194 maxenvlen, "Env-variable");
4195
4196 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4197 if (arginfo->has_arg) {
4198 printf("-%s %-*s %-*s %s\n", arginfo->argv,
4199 (int)(maxarglen - strlen(arginfo->argv) - 1),
4200 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
4201 } else {
4202 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
4203 maxenvlen, arginfo->env,
4204 arginfo->help);
4205 }
4206 }
4207
4208 printf("\n"
4209 "Defaults:\n"
4210 "QEMU_LD_PREFIX = %s\n"
4211 "QEMU_STACK_SIZE = %ld byte\n",
4212 interp_prefix,
4213 guest_stack_size);
4214
4215 printf("\n"
4216 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4217 "QEMU_UNSET_ENV environment variables to set and unset\n"
4218 "environment variables for the target process.\n"
4219 "It is possible to provide several variables by separating them\n"
4220 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4221 "provide the -E and -U options multiple times.\n"
4222 "The following lines are equivalent:\n"
4223 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4224 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4225 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4226 "Note that if you provide several changes to a single variable\n"
4227 "the last change will stay in effect.\n"
4228 "\n"
4229 QEMU_HELP_BOTTOM "\n");
4230
4231 exit(exitcode);
4232 }
4233
4234 static int parse_args(int argc, char **argv)
4235 {
4236 const char *r;
4237 int optind;
4238 const struct qemu_argument *arginfo;
4239
4240 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4241 if (arginfo->env == NULL) {
4242 continue;
4243 }
4244
4245 r = getenv(arginfo->env);
4246 if (r != NULL) {
4247 arginfo->handle_opt(r);
4248 }
4249 }
4250
4251 optind = 1;
4252 for (;;) {
4253 if (optind >= argc) {
4254 break;
4255 }
4256 r = argv[optind];
4257 if (r[0] != '-') {
4258 break;
4259 }
4260 optind++;
4261 r++;
4262 if (!strcmp(r, "-")) {
4263 break;
4264 }
4265 /* Treat --foo the same as -foo. */
4266 if (r[0] == '-') {
4267 r++;
4268 }
4269
4270 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4271 if (!strcmp(r, arginfo->argv)) {
4272 if (arginfo->has_arg) {
4273 if (optind >= argc) {
4274 (void) fprintf(stderr,
4275 "qemu: missing argument for option '%s'\n", r);
4276 exit(EXIT_FAILURE);
4277 }
4278 arginfo->handle_opt(argv[optind]);
4279 optind++;
4280 } else {
4281 arginfo->handle_opt(NULL);
4282 }
4283 break;
4284 }
4285 }
4286
4287 /* no option matched the current argv */
4288 if (arginfo->handle_opt == NULL) {
4289 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4290 exit(EXIT_FAILURE);
4291 }
4292 }
4293
4294 if (optind >= argc) {
4295 (void) fprintf(stderr, "qemu: no user program specified\n");
4296 exit(EXIT_FAILURE);
4297 }
4298
4299 filename = argv[optind];
4300 exec_path = argv[optind];
4301
4302 return optind;
4303 }
4304
4305 int main(int argc, char **argv)
4306 {
4307 struct target_pt_regs regs1, *regs = &regs1;
4308 struct image_info info1, *info = &info1;
4309 struct linux_binprm bprm;
4310 TaskState *ts;
4311 CPUArchState *env;
4312 CPUState *cpu;
4313 int optind;
4314 char **target_environ, **wrk;
4315 char **target_argv;
4316 int target_argc;
4317 int i;
4318 int ret;
4319 int execfd;
4320
4321 module_call_init(MODULE_INIT_TRACE);
4322 qemu_init_cpu_list();
4323 module_call_init(MODULE_INIT_QOM);
4324
4325 envlist = envlist_create();
4326
4327 /* add current environment into the list */
4328 for (wrk = environ; *wrk != NULL; wrk++) {
4329 (void) envlist_setenv(envlist, *wrk);
4330 }
4331
4332 /* Read the stack limit from the kernel. If it's "unlimited",
4333 then we can do little else besides use the default. */
4334 {
4335 struct rlimit lim;
4336 if (getrlimit(RLIMIT_STACK, &lim) == 0
4337 && lim.rlim_cur != RLIM_INFINITY
4338 && lim.rlim_cur == (target_long)lim.rlim_cur) {
4339 guest_stack_size = lim.rlim_cur;
4340 }
4341 }
4342
4343 cpu_model = NULL;
4344
4345 srand(time(NULL));
4346
4347 qemu_add_opts(&qemu_trace_opts);
4348
4349 optind = parse_args(argc, argv);
4350
4351 if (!trace_init_backends()) {
4352 exit(1);
4353 }
4354 trace_init_file(trace_file);
4355
4356 /* Zero out regs */
4357 memset(regs, 0, sizeof(struct target_pt_regs));
4358
4359 /* Zero out image_info */
4360 memset(info, 0, sizeof(struct image_info));
4361
4362 memset(&bprm, 0, sizeof (bprm));
4363
4364 /* Scan interp_prefix dir for replacement files. */
4365 init_paths(interp_prefix);
4366
4367 init_qemu_uname_release();
4368
4369 if (cpu_model == NULL) {
4370 #if defined(TARGET_I386)
4371 #ifdef TARGET_X86_64
4372 cpu_model = "qemu64";
4373 #else
4374 cpu_model = "qemu32";
4375 #endif
4376 #elif defined(TARGET_ARM)
4377 cpu_model = "any";
4378 #elif defined(TARGET_UNICORE32)
4379 cpu_model = "any";
4380 #elif defined(TARGET_M68K)
4381 cpu_model = "any";
4382 #elif defined(TARGET_SPARC)
4383 #ifdef TARGET_SPARC64
4384 cpu_model = "TI UltraSparc II";
4385 #else
4386 cpu_model = "Fujitsu MB86904";
4387 #endif
4388 #elif defined(TARGET_MIPS)
4389 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
4390 cpu_model = "5KEf";
4391 #else
4392 cpu_model = "24Kf";
4393 #endif
4394 #elif defined TARGET_OPENRISC
4395 cpu_model = "or1200";
4396 #elif defined(TARGET_PPC)
4397 # ifdef TARGET_PPC64
4398 cpu_model = "POWER8";
4399 # else
4400 cpu_model = "750";
4401 # endif
4402 #elif defined TARGET_SH4
4403 cpu_model = "sh7785";
4404 #elif defined TARGET_S390X
4405 cpu_model = "qemu";
4406 #else
4407 cpu_model = "any";
4408 #endif
4409 }
4410 tcg_exec_init(0);
4411 /* NOTE: we need to init the CPU at this stage to get
4412 qemu_host_page_size */
4413 cpu = cpu_init(cpu_model);
4414 env = cpu->env_ptr;
4415 cpu_reset(cpu);
4416
4417 thread_cpu = cpu;
4418
4419 if (getenv("QEMU_STRACE")) {
4420 do_strace = 1;
4421 }
4422
4423 if (getenv("QEMU_RAND_SEED")) {
4424 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4425 }
4426
4427 target_environ = envlist_to_environ(envlist, NULL);
4428 envlist_free(envlist);
4429
4430 /*
4431 * Now that page sizes are configured in cpu_init() we can do
4432 * proper page alignment for guest_base.
4433 */
4434 guest_base = HOST_PAGE_ALIGN(guest_base);
4435
4436 if (reserved_va || have_guest_base) {
4437 guest_base = init_guest_space(guest_base, reserved_va, 0,
4438 have_guest_base);
4439 if (guest_base == (unsigned long)-1) {
4440 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4441 "space for use as guest address space (check your virtual "
4442 "memory ulimit setting or reserve less using -R option)\n",
4443 reserved_va);
4444 exit(EXIT_FAILURE);
4445 }
4446
4447 if (reserved_va) {
4448 mmap_next_start = reserved_va;
4449 }
4450 }
4451
4452 /*
4453 * Read in mmap_min_addr kernel parameter. This value is used
4454 * When loading the ELF image to determine whether guest_base
4455 * is needed. It is also used in mmap_find_vma.
4456 */
4457 {
4458 FILE *fp;
4459
4460 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4461 unsigned long tmp;
4462 if (fscanf(fp, "%lu", &tmp) == 1) {
4463 mmap_min_addr = tmp;
4464 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
4465 }
4466 fclose(fp);
4467 }
4468 }
4469
4470 /*
4471 * Prepare copy of argv vector for target.
4472 */
4473 target_argc = argc - optind;
4474 target_argv = calloc(target_argc + 1, sizeof (char *));
4475 if (target_argv == NULL) {
4476 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4477 exit(EXIT_FAILURE);
4478 }
4479
4480 /*
4481 * If argv0 is specified (using '-0' switch) we replace
4482 * argv[0] pointer with the given one.
4483 */
4484 i = 0;
4485 if (argv0 != NULL) {
4486 target_argv[i++] = strdup(argv0);
4487 }
4488 for (; i < target_argc; i++) {
4489 target_argv[i] = strdup(argv[optind + i]);
4490 }
4491 target_argv[target_argc] = NULL;
4492
4493 ts = g_new0(TaskState, 1);
4494 init_task_state(ts);
4495 /* build Task State */
4496 ts->info = info;
4497 ts->bprm = &bprm;
4498 cpu->opaque = ts;
4499 task_settid(ts);
4500
4501 execfd = qemu_getauxval(AT_EXECFD);
4502 if (execfd == 0) {
4503 execfd = open(filename, O_RDONLY);
4504 if (execfd < 0) {
4505 printf("Error while loading %s: %s\n", filename, strerror(errno));
4506 _exit(EXIT_FAILURE);
4507 }
4508 }
4509
4510 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4511 info, &bprm);
4512 if (ret != 0) {
4513 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4514 _exit(EXIT_FAILURE);
4515 }
4516
4517 for (wrk = target_environ; *wrk; wrk++) {
4518 g_free(*wrk);
4519 }
4520
4521 g_free(target_environ);
4522
4523 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
4524 qemu_log("guest_base 0x%" PRIxPTR "\n", guest_base);
4525 log_page_dump();
4526
4527 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4528 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4529 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", info->start_code);
4530 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", info->start_data);
4531 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4532 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", info->start_stack);
4533 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4534 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4535 qemu_log("argv_start 0x" TARGET_ABI_FMT_lx "\n", info->arg_start);
4536 qemu_log("env_start 0x" TARGET_ABI_FMT_lx "\n",
4537 info->arg_end + (abi_ulong)sizeof(abi_ulong));
4538 qemu_log("auxv_start 0x" TARGET_ABI_FMT_lx "\n", info->saved_auxv);
4539 }
4540
4541 target_set_brk(info->brk);
4542 syscall_init();
4543 signal_init();
4544
4545 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4546 generating the prologue until now so that the prologue can take
4547 the real value of GUEST_BASE into account. */
4548 tcg_prologue_init(tcg_ctx);
4549 tcg_region_init();
4550
4551 #if defined(TARGET_I386)
4552 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4553 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4554 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4555 env->cr[4] |= CR4_OSFXSR_MASK;
4556 env->hflags |= HF_OSFXSR_MASK;
4557 }
4558 #ifndef TARGET_ABI32
4559 /* enable 64 bit mode if possible */
4560 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4561 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4562 exit(EXIT_FAILURE);
4563 }
4564 env->cr[4] |= CR4_PAE_MASK;
4565 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4566 env->hflags |= HF_LMA_MASK;
4567 #endif
4568
4569 /* flags setup : we activate the IRQs by default as in user mode */
4570 env->eflags |= IF_MASK;
4571
4572 /* linux register setup */
4573 #ifndef TARGET_ABI32
4574 env->regs[R_EAX] = regs->rax;
4575 env->regs[R_EBX] = regs->rbx;
4576 env->regs[R_ECX] = regs->rcx;
4577 env->regs[R_EDX] = regs->rdx;
4578 env->regs[R_ESI] = regs->rsi;
4579 env->regs[R_EDI] = regs->rdi;
4580 env->regs[R_EBP] = regs->rbp;
4581 env->regs[R_ESP] = regs->rsp;
4582 env->eip = regs->rip;
4583 #else
4584 env->regs[R_EAX] = regs->eax;
4585 env->regs[R_EBX] = regs->ebx;
4586 env->regs[R_ECX] = regs->ecx;
4587 env->regs[R_EDX] = regs->edx;
4588 env->regs[R_ESI] = regs->esi;
4589 env->regs[R_EDI] = regs->edi;
4590 env->regs[R_EBP] = regs->ebp;
4591 env->regs[R_ESP] = regs->esp;
4592 env->eip = regs->eip;
4593 #endif
4594
4595 /* linux interrupt setup */
4596 #ifndef TARGET_ABI32
4597 env->idt.limit = 511;
4598 #else
4599 env->idt.limit = 255;
4600 #endif
4601 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4602 PROT_READ|PROT_WRITE,
4603 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4604 idt_table = g2h(env->idt.base);
4605 set_idt(0, 0);
4606 set_idt(1, 0);
4607 set_idt(2, 0);
4608 set_idt(3, 3);
4609 set_idt(4, 3);
4610 set_idt(5, 0);
4611 set_idt(6, 0);
4612 set_idt(7, 0);
4613 set_idt(8, 0);
4614 set_idt(9, 0);
4615 set_idt(10, 0);
4616 set_idt(11, 0);
4617 set_idt(12, 0);
4618 set_idt(13, 0);
4619 set_idt(14, 0);
4620 set_idt(15, 0);
4621 set_idt(16, 0);
4622 set_idt(17, 0);
4623 set_idt(18, 0);
4624 set_idt(19, 0);
4625 set_idt(0x80, 3);
4626
4627 /* linux segment setup */
4628 {
4629 uint64_t *gdt_table;
4630 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4631 PROT_READ|PROT_WRITE,
4632 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4633 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4634 gdt_table = g2h(env->gdt.base);
4635 #ifdef TARGET_ABI32
4636 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4637 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4638 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4639 #else
4640 /* 64 bit code segment */
4641 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4642 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4643 DESC_L_MASK |
4644 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4645 #endif
4646 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4647 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4648 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4649 }
4650 cpu_x86_load_seg(env, R_CS, __USER_CS);
4651 cpu_x86_load_seg(env, R_SS, __USER_DS);
4652 #ifdef TARGET_ABI32
4653 cpu_x86_load_seg(env, R_DS, __USER_DS);
4654 cpu_x86_load_seg(env, R_ES, __USER_DS);
4655 cpu_x86_load_seg(env, R_FS, __USER_DS);
4656 cpu_x86_load_seg(env, R_GS, __USER_DS);
4657 /* This hack makes Wine work... */
4658 env->segs[R_FS].selector = 0;
4659 #else
4660 cpu_x86_load_seg(env, R_DS, 0);
4661 cpu_x86_load_seg(env, R_ES, 0);
4662 cpu_x86_load_seg(env, R_FS, 0);
4663 cpu_x86_load_seg(env, R_GS, 0);
4664 #endif
4665 #elif defined(TARGET_AARCH64)
4666 {
4667 int i;
4668
4669 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4670 fprintf(stderr,
4671 "The selected ARM CPU does not support 64 bit mode\n");
4672 exit(EXIT_FAILURE);
4673 }
4674
4675 for (i = 0; i < 31; i++) {
4676 env->xregs[i] = regs->regs[i];
4677 }
4678 env->pc = regs->pc;
4679 env->xregs[31] = regs->sp;
4680 #ifdef TARGET_WORDS_BIGENDIAN
4681 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4682 for (i = 1; i < 4; ++i) {
4683 env->cp15.sctlr_el[i] |= SCTLR_EE;
4684 }
4685 #endif
4686 }
4687 #elif defined(TARGET_ARM)
4688 {
4689 int i;
4690 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4691 CPSRWriteByInstr);
4692 for(i = 0; i < 16; i++) {
4693 env->regs[i] = regs->uregs[i];
4694 }
4695 #ifdef TARGET_WORDS_BIGENDIAN
4696 /* Enable BE8. */
4697 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4698 && (info->elf_flags & EF_ARM_BE8)) {
4699 env->uncached_cpsr |= CPSR_E;
4700 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4701 } else {
4702 env->cp15.sctlr_el[1] |= SCTLR_B;
4703 }
4704 #endif
4705 }
4706 #elif defined(TARGET_UNICORE32)
4707 {
4708 int i;
4709 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4710 for (i = 0; i < 32; i++) {
4711 env->regs[i] = regs->uregs[i];
4712 }
4713 }
4714 #elif defined(TARGET_SPARC)
4715 {
4716 int i;
4717 env->pc = regs->pc;
4718 env->npc = regs->npc;
4719 env->y = regs->y;
4720 for(i = 0; i < 8; i++)
4721 env->gregs[i] = regs->u_regs[i];
4722 for(i = 0; i < 8; i++)
4723 env->regwptr[i] = regs->u_regs[i + 8];
4724 }
4725 #elif defined(TARGET_PPC)
4726 {
4727 int i;
4728
4729 #if defined(TARGET_PPC64)
4730 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF;
4731 #if defined(TARGET_ABI32)
4732 env->msr &= ~((target_ulong)1 << flag);
4733 #else
4734 env->msr |= (target_ulong)1 << flag;
4735 #endif
4736 #endif
4737 env->nip = regs->nip;
4738 for(i = 0; i < 32; i++) {
4739 env->gpr[i] = regs->gpr[i];
4740 }
4741 }
4742 #elif defined(TARGET_M68K)
4743 {
4744 env->pc = regs->pc;
4745 env->dregs[0] = regs->d0;
4746 env->dregs[1] = regs->d1;
4747 env->dregs[2] = regs->d2;
4748 env->dregs[3] = regs->d3;
4749 env->dregs[4] = regs->d4;
4750 env->dregs[5] = regs->d5;
4751 env->dregs[6] = regs->d6;
4752 env->dregs[7] = regs->d7;
4753 env->aregs[0] = regs->a0;
4754 env->aregs[1] = regs->a1;
4755 env->aregs[2] = regs->a2;
4756 env->aregs[3] = regs->a3;
4757 env->aregs[4] = regs->a4;
4758 env->aregs[5] = regs->a5;
4759 env->aregs[6] = regs->a6;
4760 env->aregs[7] = regs->usp;
4761 env->sr = regs->sr;
4762 ts->sim_syscalls = 1;
4763 }
4764 #elif defined(TARGET_MICROBLAZE)
4765 {
4766 env->regs[0] = regs->r0;
4767 env->regs[1] = regs->r1;
4768 env->regs[2] = regs->r2;
4769 env->regs[3] = regs->r3;
4770 env->regs[4] = regs->r4;
4771 env->regs[5] = regs->r5;
4772 env->regs[6] = regs->r6;
4773 env->regs[7] = regs->r7;
4774 env->regs[8] = regs->r8;
4775 env->regs[9] = regs->r9;
4776 env->regs[10] = regs->r10;
4777 env->regs[11] = regs->r11;
4778 env->regs[12] = regs->r12;
4779 env->regs[13] = regs->r13;
4780 env->regs[14] = regs->r14;
4781 env->regs[15] = regs->r15;
4782 env->regs[16] = regs->r16;
4783 env->regs[17] = regs->r17;
4784 env->regs[18] = regs->r18;
4785 env->regs[19] = regs->r19;
4786 env->regs[20] = regs->r20;
4787 env->regs[21] = regs->r21;
4788 env->regs[22] = regs->r22;
4789 env->regs[23] = regs->r23;
4790 env->regs[24] = regs->r24;
4791 env->regs[25] = regs->r25;
4792 env->regs[26] = regs->r26;
4793 env->regs[27] = regs->r27;
4794 env->regs[28] = regs->r28;
4795 env->regs[29] = regs->r29;
4796 env->regs[30] = regs->r30;
4797 env->regs[31] = regs->r31;
4798 env->sregs[SR_PC] = regs->pc;
4799 }
4800 #elif defined(TARGET_MIPS)
4801 {
4802 int i;
4803
4804 for(i = 0; i < 32; i++) {
4805 env->active_tc.gpr[i] = regs->regs[i];
4806 }
4807 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4808 if (regs->cp0_epc & 1) {
4809 env->hflags |= MIPS_HFLAG_M16;
4810 }
4811 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4812 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4813 if ((env->active_fpu.fcr31_rw_bitmask &
4814 (1 << FCR31_NAN2008)) == 0) {
4815 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4816 exit(1);
4817 }
4818 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4819 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
4820 } else {
4821 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
4822 }
4823 restore_snan_bit_mode(env);
4824 }
4825 }
4826 #elif defined(TARGET_NIOS2)
4827 {
4828 env->regs[0] = 0;
4829 env->regs[1] = regs->r1;
4830 env->regs[2] = regs->r2;
4831 env->regs[3] = regs->r3;
4832 env->regs[4] = regs->r4;
4833 env->regs[5] = regs->r5;
4834 env->regs[6] = regs->r6;
4835 env->regs[7] = regs->r7;
4836 env->regs[8] = regs->r8;
4837 env->regs[9] = regs->r9;
4838 env->regs[10] = regs->r10;
4839 env->regs[11] = regs->r11;
4840 env->regs[12] = regs->r12;
4841 env->regs[13] = regs->r13;
4842 env->regs[14] = regs->r14;
4843 env->regs[15] = regs->r15;
4844 /* TODO: unsigned long orig_r2; */
4845 env->regs[R_RA] = regs->ra;
4846 env->regs[R_FP] = regs->fp;
4847 env->regs[R_SP] = regs->sp;
4848 env->regs[R_GP] = regs->gp;
4849 env->regs[CR_ESTATUS] = regs->estatus;
4850 env->regs[R_EA] = regs->ea;
4851 /* TODO: unsigned long orig_r7; */
4852
4853 /* Emulate eret when starting thread. */
4854 env->regs[R_PC] = regs->ea;
4855 }
4856 #elif defined(TARGET_OPENRISC)
4857 {
4858 int i;
4859
4860 for (i = 0; i < 32; i++) {
4861 cpu_set_gpr(env, i, regs->gpr[i]);
4862 }
4863 env->pc = regs->pc;
4864 cpu_set_sr(env, regs->sr);
4865 }
4866 #elif defined(TARGET_SH4)
4867 {
4868 int i;
4869
4870 for(i = 0; i < 16; i++) {
4871 env->gregs[i] = regs->regs[i];
4872 }
4873 env->pc = regs->pc;
4874 }
4875 #elif defined(TARGET_ALPHA)
4876 {
4877 int i;
4878
4879 for(i = 0; i < 28; i++) {
4880 env->ir[i] = ((abi_ulong *)regs)[i];
4881 }
4882 env->ir[IR_SP] = regs->usp;
4883 env->pc = regs->pc;
4884 }
4885 #elif defined(TARGET_CRIS)
4886 {
4887 env->regs[0] = regs->r0;
4888 env->regs[1] = regs->r1;
4889 env->regs[2] = regs->r2;
4890 env->regs[3] = regs->r3;
4891 env->regs[4] = regs->r4;
4892 env->regs[5] = regs->r5;
4893 env->regs[6] = regs->r6;
4894 env->regs[7] = regs->r7;
4895 env->regs[8] = regs->r8;
4896 env->regs[9] = regs->r9;
4897 env->regs[10] = regs->r10;
4898 env->regs[11] = regs->r11;
4899 env->regs[12] = regs->r12;
4900 env->regs[13] = regs->r13;
4901 env->regs[14] = info->start_stack;
4902 env->regs[15] = regs->acr;
4903 env->pc = regs->erp;
4904 }
4905 #elif defined(TARGET_S390X)
4906 {
4907 int i;
4908 for (i = 0; i < 16; i++) {
4909 env->regs[i] = regs->gprs[i];
4910 }
4911 env->psw.mask = regs->psw.mask;
4912 env->psw.addr = regs->psw.addr;
4913 }
4914 #elif defined(TARGET_TILEGX)
4915 {
4916 int i;
4917 for (i = 0; i < TILEGX_R_COUNT; i++) {
4918 env->regs[i] = regs->regs[i];
4919 }
4920 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4921 env->spregs[i] = 0;
4922 }
4923 env->pc = regs->pc;
4924 }
4925 #elif defined(TARGET_HPPA)
4926 {
4927 int i;
4928 for (i = 1; i < 32; i++) {
4929 env->gr[i] = regs->gr[i];
4930 }
4931 env->iaoq_f = regs->iaoq[0];
4932 env->iaoq_b = regs->iaoq[1];
4933 }
4934 #else
4935 #error unsupported target CPU
4936 #endif
4937
4938 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4939 ts->stack_base = info->start_stack;
4940 ts->heap_base = info->brk;
4941 /* This will be filled in on the first SYS_HEAPINFO call. */
4942 ts->heap_limit = 0;
4943 #endif
4944
4945 if (gdbstub_port) {
4946 if (gdbserver_start(gdbstub_port) < 0) {
4947 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4948 gdbstub_port);
4949 exit(EXIT_FAILURE);
4950 }
4951 gdb_handlesig(cpu, 0);
4952 }
4953 cpu_loop(env);
4954 /* never exits */
4955 return 0;
4956 }
AR7 emulation for QEMU