?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / hw / mips / gt64xxx_pci.c
blob1ce4aef55704cdde467da7774059439f8cbb1716
1 /*
2 * QEMU GT64120 PCI host
3 *
4 * Copyright (c) 2006,2007 Aurelien Jarno
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "hw/mips/mips.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_host.h"
30 #include "hw/i386/pc.h"
31 #include "exec/address-spaces.h"
32
33 //#define DEBUG
34
35 #ifdef DEBUG
36 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
37 #else
38 #define DPRINTF(fmt, ...)
39 #endif
40
41 #define GT_REGS (0x1000 >> 2)
42
43 /* CPU Configuration */
44 #define GT_CPU (0x000 >> 2)
45 #define GT_MULTI (0x120 >> 2)
46
47 /* CPU Address Decode */
48 #define GT_SCS10LD (0x008 >> 2)
49 #define GT_SCS10HD (0x010 >> 2)
50 #define GT_SCS32LD (0x018 >> 2)
51 #define GT_SCS32HD (0x020 >> 2)
52 #define GT_CS20LD (0x028 >> 2)
53 #define GT_CS20HD (0x030 >> 2)
54 #define GT_CS3BOOTLD (0x038 >> 2)
55 #define GT_CS3BOOTHD (0x040 >> 2)
56 #define GT_PCI0IOLD (0x048 >> 2)
57 #define GT_PCI0IOHD (0x050 >> 2)
58 #define GT_PCI0M0LD (0x058 >> 2)
59 #define GT_PCI0M0HD (0x060 >> 2)
60 #define GT_PCI0M1LD (0x080 >> 2)
61 #define GT_PCI0M1HD (0x088 >> 2)
62 #define GT_PCI1IOLD (0x090 >> 2)
63 #define GT_PCI1IOHD (0x098 >> 2)
64 #define GT_PCI1M0LD (0x0a0 >> 2)
65 #define GT_PCI1M0HD (0x0a8 >> 2)
66 #define GT_PCI1M1LD (0x0b0 >> 2)
67 #define GT_PCI1M1HD (0x0b8 >> 2)
68 #define GT_ISD (0x068 >> 2)
69
70 #define GT_SCS10AR (0x0d0 >> 2)
71 #define GT_SCS32AR (0x0d8 >> 2)
72 #define GT_CS20R (0x0e0 >> 2)
73 #define GT_CS3BOOTR (0x0e8 >> 2)
74
75 #define GT_PCI0IOREMAP (0x0f0 >> 2)
76 #define GT_PCI0M0REMAP (0x0f8 >> 2)
77 #define GT_PCI0M1REMAP (0x100 >> 2)
78 #define GT_PCI1IOREMAP (0x108 >> 2)
79 #define GT_PCI1M0REMAP (0x110 >> 2)
80 #define GT_PCI1M1REMAP (0x118 >> 2)
81
82 /* CPU Error Report */
83 #define GT_CPUERR_ADDRLO (0x070 >> 2)
84 #define GT_CPUERR_ADDRHI (0x078 >> 2)
85 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
86 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
87 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
88
89 /* CPU Sync Barrier */
90 #define GT_PCI0SYNC (0x0c0 >> 2)
91 #define GT_PCI1SYNC (0x0c8 >> 2)
92
93 /* SDRAM and Device Address Decode */
94 #define GT_SCS0LD (0x400 >> 2)
95 #define GT_SCS0HD (0x404 >> 2)
96 #define GT_SCS1LD (0x408 >> 2)
97 #define GT_SCS1HD (0x40c >> 2)
98 #define GT_SCS2LD (0x410 >> 2)
99 #define GT_SCS2HD (0x414 >> 2)
100 #define GT_SCS3LD (0x418 >> 2)
101 #define GT_SCS3HD (0x41c >> 2)
102 #define GT_CS0LD (0x420 >> 2)
103 #define GT_CS0HD (0x424 >> 2)
104 #define GT_CS1LD (0x428 >> 2)
105 #define GT_CS1HD (0x42c >> 2)
106 #define GT_CS2LD (0x430 >> 2)
107 #define GT_CS2HD (0x434 >> 2)
108 #define GT_CS3LD (0x438 >> 2)
109 #define GT_CS3HD (0x43c >> 2)
110 #define GT_BOOTLD (0x440 >> 2)
111 #define GT_BOOTHD (0x444 >> 2)
112 #define GT_ADERR (0x470 >> 2)
113
114 /* SDRAM Configuration */
115 #define GT_SDRAM_CFG (0x448 >> 2)
116 #define GT_SDRAM_OPMODE (0x474 >> 2)
117 #define GT_SDRAM_BM (0x478 >> 2)
118 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
119
120 /* SDRAM Parameters */
121 #define GT_SDRAM_B0 (0x44c >> 2)
122 #define GT_SDRAM_B1 (0x450 >> 2)
123 #define GT_SDRAM_B2 (0x454 >> 2)
124 #define GT_SDRAM_B3 (0x458 >> 2)
125
126 /* Device Parameters */
127 #define GT_DEV_B0 (0x45c >> 2)
128 #define GT_DEV_B1 (0x460 >> 2)
129 #define GT_DEV_B2 (0x464 >> 2)
130 #define GT_DEV_B3 (0x468 >> 2)
131 #define GT_DEV_BOOT (0x46c >> 2)
132
133 /* ECC */
134 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
135 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
136 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
137 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
138 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
139
140 /* DMA Record */
141 #define GT_DMA0_CNT (0x800 >> 2)
142 #define GT_DMA1_CNT (0x804 >> 2)
143 #define GT_DMA2_CNT (0x808 >> 2)
144 #define GT_DMA3_CNT (0x80c >> 2)
145 #define GT_DMA0_SA (0x810 >> 2)
146 #define GT_DMA1_SA (0x814 >> 2)
147 #define GT_DMA2_SA (0x818 >> 2)
148 #define GT_DMA3_SA (0x81c >> 2)
149 #define GT_DMA0_DA (0x820 >> 2)
150 #define GT_DMA1_DA (0x824 >> 2)
151 #define GT_DMA2_DA (0x828 >> 2)
152 #define GT_DMA3_DA (0x82c >> 2)
153 #define GT_DMA0_NEXT (0x830 >> 2)
154 #define GT_DMA1_NEXT (0x834 >> 2)
155 #define GT_DMA2_NEXT (0x838 >> 2)
156 #define GT_DMA3_NEXT (0x83c >> 2)
157 #define GT_DMA0_CUR (0x870 >> 2)
158 #define GT_DMA1_CUR (0x874 >> 2)
159 #define GT_DMA2_CUR (0x878 >> 2)
160 #define GT_DMA3_CUR (0x87c >> 2)
161
162 /* DMA Channel Control */
163 #define GT_DMA0_CTRL (0x840 >> 2)
164 #define GT_DMA1_CTRL (0x844 >> 2)
165 #define GT_DMA2_CTRL (0x848 >> 2)
166 #define GT_DMA3_CTRL (0x84c >> 2)
167
168 /* DMA Arbiter */
169 #define GT_DMA_ARB (0x860 >> 2)
170
171 /* Timer/Counter */
172 #define GT_TC0 (0x850 >> 2)
173 #define GT_TC1 (0x854 >> 2)
174 #define GT_TC2 (0x858 >> 2)
175 #define GT_TC3 (0x85c >> 2)
176 #define GT_TC_CONTROL (0x864 >> 2)
177
178 /* PCI Internal */
179 #define GT_PCI0_CMD (0xc00 >> 2)
180 #define GT_PCI0_TOR (0xc04 >> 2)
181 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
182 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
183 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
184 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
185 #define GT_PCI1_IACK (0xc30 >> 2)
186 #define GT_PCI0_IACK (0xc34 >> 2)
187 #define GT_PCI0_BARE (0xc3c >> 2)
188 #define GT_PCI0_PREFMBR (0xc40 >> 2)
189 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
190 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
191 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
192 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
193 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
194 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
195 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
196 #define GT_PCI1_CMD (0xc80 >> 2)
197 #define GT_PCI1_TOR (0xc84 >> 2)
198 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
199 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
200 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
201 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
202 #define GT_PCI1_BARE (0xcbc >> 2)
203 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
204 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
205 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
206 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
207 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
208 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
209 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
210 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
211 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
212 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
213 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
214 #define GT_PCI0_CFGDATA (0xcfc >> 2)
215
216 /* Interrupts */
217 #define GT_INTRCAUSE (0xc18 >> 2)
218 #define GT_INTRMASK (0xc1c >> 2)
219 #define GT_PCI0_ICMASK (0xc24 >> 2)
220 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
221 #define GT_CPU_INTSEL (0xc70 >> 2)
222 #define GT_PCI0_INTSEL (0xc74 >> 2)
223 #define GT_HINTRCAUSE (0xc98 >> 2)
224 #define GT_HINTRMASK (0xc9c >> 2)
225 #define GT_PCI0_HICMASK (0xca4 >> 2)
226 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
227
228 #if 0
229 #define DEBUG
230 #endif
231
232 #if defined(DEBUG)
233 #define logout(fmt, ...) fprintf(stderr, "GT64XXX\t%-24s" fmt, __func__, ##__VA_ARGS__)
234 #else
235 #define logout(fmt, ...) ((void)0)
236 #endif
237
238 #define PCI_MAPPING_ENTRY(regname) \
239 hwaddr regname ##_start; \
240 hwaddr regname ##_length; \
241 MemoryRegion regname ##_mem
242
243 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
244
245 #define GT64120_PCI_HOST_BRIDGE(obj) \
246 OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE)
247
248 typedef struct GT64120State {
249 PCIHostState parent_obj;
250
251 uint32_t regs[GT_REGS];
252 PCI_MAPPING_ENTRY(PCI0IO);
253 PCI_MAPPING_ENTRY(PCI0M0);
254 PCI_MAPPING_ENTRY(PCI0M1);
255 PCI_MAPPING_ENTRY(ISD);
256 MemoryRegion pci0_mem;
257 AddressSpace pci0_mem_as;
258 } GT64120State;
259
260 /* Adjust range to avoid touching space which isn't mappable via PCI */
261 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
262 0x1fc00000 - 0x1fd00000 */
263 static void check_reserved_space (hwaddr *start,
264 hwaddr *length)
265 {
266 hwaddr begin = *start;
267 hwaddr end = *start + *length;
268
269 if (end >= 0x1e000000LL && end < 0x1f100000LL)
270 end = 0x1e000000LL;
271 if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
272 begin = 0x1f100000LL;
273 if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
274 end = 0x1fc00000LL;
275 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
276 begin = 0x1fd00000LL;
277 /* XXX: This is broken when a reserved range splits the requested range */
278 if (end >= 0x1f100000LL && begin < 0x1e000000LL)
279 end = 0x1e000000LL;
280 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
281 end = 0x1fc00000LL;
282
283 *start = begin;
284 *length = end - begin;
285 }
286
287 static void gt64120_isd_mapping(GT64120State *s)
288 {
289 /* Bits 14:0 of ISD map to bits 35:21 of the start address. */
290 hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
291 hwaddr length = 0x1000;
292
293 if (s->ISD_length) {
294 memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
295 }
296 check_reserved_space(&start, &length);
297 length = 0x1000;
298 /* Map new address */
299 DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx
300 " -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n",
301 s->ISD_length, s->ISD_start, length, start);
302 s->ISD_start = start;
303 s->ISD_length = length;
304 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
305 }
306
307 static void gt64120_pci_mapping(GT64120State *s)
308 {
309 /* Update PCI0IO mapping */
310 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
311 /* Unmap old IO address */
312 if (s->PCI0IO_length) {
313 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
314 object_unparent(OBJECT(&s->PCI0IO_mem));
315 }
316 /* Map new IO address */
317 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
318 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
319 (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
320 if (s->PCI0IO_length) {
321 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
322 get_system_io(), 0, s->PCI0IO_length);
323 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
324 &s->PCI0IO_mem);
325 }
326 }
327
328 /* Update PCI0M0 mapping */
329 if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
330 /* Unmap old MEM address */
331 if (s->PCI0M0_length) {
332 memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
333 object_unparent(OBJECT(&s->PCI0M0_mem));
334 }
335 /* Map new mem address */
336 s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
337 s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
338 (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
339 if (s->PCI0M0_length) {
340 memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
341 &s->pci0_mem, s->PCI0M0_start,
342 s->PCI0M0_length);
343 memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
344 &s->PCI0M0_mem);
345 }
346 }
347
348 /* Update PCI0M1 mapping */
349 if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
350 /* Unmap old MEM address */
351 if (s->PCI0M1_length) {
352 memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
353 object_unparent(OBJECT(&s->PCI0M1_mem));
354 }
355 /* Map new mem address */
356 s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
357 s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
358 (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
359 if (s->PCI0M1_length) {
360 memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
361 &s->pci0_mem, s->PCI0M1_start,
362 s->PCI0M1_length);
363 memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
364 &s->PCI0M1_mem);
365 }
366 }
367 }
368
369 static int gt64120_post_load(void *opaque, int version_id)
370 {
371 GT64120State *s = opaque;
372
373 gt64120_isd_mapping(s);
374 gt64120_pci_mapping(s);
375
376 return 0;
377 }
378
379 static const VMStateDescription vmstate_gt64120 = {
380 .name = "gt64120",
381 .version_id = 1,
382 .minimum_version_id = 1,
383 .post_load = gt64120_post_load,
384 .fields = (VMStateField[]) {
385 VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
386 VMSTATE_END_OF_LIST()
387 }
388 };
389
390 static void gt64120_writel (void *opaque, hwaddr addr,
391 uint64_t val, unsigned size)
392 {
393 GT64120State *s = opaque;
394 PCIHostState *phb = PCI_HOST_BRIDGE(s);
395 uint32_t saddr;
396
397 if (!(s->regs[GT_CPU] & 0x00001000))
398 val = bswap32(val);
399
400 saddr = (addr & 0xfff) >> 2;
401 logout("addr = 0x%08x, val = 0x%08x\n", saddr, val);
402
403 switch (saddr) {
404
405 /* CPU Configuration */
406 case GT_CPU:
407 s->regs[GT_CPU] = val;
408 break;
409 case GT_MULTI:
410 /* Read-only register as only one GT64xxx is present on the CPU bus */
411 break;
412
413 /* CPU Address Decode */
414 case GT_PCI0IOLD:
415 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
416 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
417 gt64120_pci_mapping(s);
418 break;
419 case GT_PCI0M0LD:
420 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
421 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
422 gt64120_pci_mapping(s);
423 break;
424 case GT_PCI0M1LD:
425 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
426 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
427 gt64120_pci_mapping(s);
428 break;
429 case GT_PCI1IOLD:
430 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
431 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
432 break;
433 case GT_PCI1M0LD:
434 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
435 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
436 break;
437 case GT_PCI1M1LD:
438 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
439 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
440 break;
441 case GT_PCI0M0HD:
442 case GT_PCI0M1HD:
443 case GT_PCI0IOHD:
444 s->regs[saddr] = val & 0x0000007f;
445 gt64120_pci_mapping(s);
446 break;
447 case GT_PCI1IOHD:
448 case GT_PCI1M0HD:
449 case GT_PCI1M1HD:
450 s->regs[saddr] = val & 0x0000007f;
451 break;
452 case GT_ISD:
453 s->regs[saddr] = val & 0x00007fff;
454 gt64120_isd_mapping(s);
455 break;
456
457 case GT_PCI0IOREMAP:
458 case GT_PCI0M0REMAP:
459 case GT_PCI0M1REMAP:
460 case GT_PCI1IOREMAP:
461 case GT_PCI1M0REMAP:
462 case GT_PCI1M1REMAP:
463 s->regs[saddr] = val & 0x000007ff;
464 break;
465
466 /* CPU Error Report */
467 case GT_CPUERR_ADDRLO:
468 case GT_CPUERR_ADDRHI:
469 case GT_CPUERR_DATALO:
470 case GT_CPUERR_DATAHI:
471 case GT_CPUERR_PARITY:
472 /* Read-only registers, do nothing */
473 break;
474
475 /* CPU Sync Barrier */
476 case GT_PCI0SYNC:
477 case GT_PCI1SYNC:
478 /* Read-only registers, do nothing */
479 break;
480
481 /* SDRAM and Device Address Decode */
482 case GT_SCS0LD:
483 case GT_SCS0HD:
484 case GT_SCS1LD:
485 case GT_SCS1HD:
486 case GT_SCS2LD:
487 case GT_SCS2HD:
488 case GT_SCS3LD:
489 case GT_SCS3HD:
490 case GT_CS0LD:
491 case GT_CS0HD:
492 case GT_CS1LD:
493 case GT_CS1HD:
494 case GT_CS2LD:
495 case GT_CS2HD:
496 case GT_CS3LD:
497 case GT_CS3HD:
498 case GT_BOOTLD:
499 case GT_BOOTHD:
500 case GT_ADERR:
501 /* SDRAM Configuration */
502 case GT_SDRAM_CFG:
503 case GT_SDRAM_OPMODE:
504 case GT_SDRAM_BM:
505 case GT_SDRAM_ADDRDECODE:
506 /* Accept and ignore SDRAM interleave configuration */
507 s->regs[saddr] = val;
508 break;
509
510 /* Device Parameters */
511 case GT_DEV_B0:
512 case GT_DEV_B1:
513 case GT_DEV_B2:
514 case GT_DEV_B3:
515 case GT_DEV_BOOT:
516 /* Not implemented */
517 DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
518 break;
519
520 /* ECC */
521 case GT_ECC_ERRDATALO:
522 case GT_ECC_ERRDATAHI:
523 case GT_ECC_MEM:
524 case GT_ECC_CALC:
525 case GT_ECC_ERRADDR:
526 /* Read-only registers, do nothing */
527 break;
528
529 /* DMA Record */
530 case GT_DMA0_CNT:
531 case GT_DMA1_CNT:
532 case GT_DMA2_CNT:
533 case GT_DMA3_CNT:
534 case GT_DMA0_SA:
535 case GT_DMA1_SA:
536 case GT_DMA2_SA:
537 case GT_DMA3_SA:
538 case GT_DMA0_DA:
539 case GT_DMA1_DA:
540 case GT_DMA2_DA:
541 case GT_DMA3_DA:
542 case GT_DMA0_NEXT:
543 case GT_DMA1_NEXT:
544 case GT_DMA2_NEXT:
545 case GT_DMA3_NEXT:
546 case GT_DMA0_CUR:
547 case GT_DMA1_CUR:
548 case GT_DMA2_CUR:
549 case GT_DMA3_CUR:
550 /* Not implemented */
551 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
552 break;
553
554 /* DMA Channel Control */
555 case GT_DMA0_CTRL:
556 case GT_DMA1_CTRL:
557 case GT_DMA2_CTRL:
558 case GT_DMA3_CTRL:
559 /* Not implemented */
560 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
561 break;
562
563 /* DMA Arbiter */
564 case GT_DMA_ARB:
565 /* Not implemented */
566 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
567 break;
568
569 /* Timer/Counter */
570 case GT_TC0:
571 case GT_TC1:
572 case GT_TC2:
573 case GT_TC3:
574 case GT_TC_CONTROL:
575 /* Not implemented */
576 DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
577 break;
578
579 /* PCI Internal */
580 case GT_PCI0_CMD:
581 case GT_PCI1_CMD:
582 s->regs[saddr] = val & 0x0401fc0f;
583 break;
584 case GT_PCI0_TOR:
585 case GT_PCI0_BS_SCS10:
586 case GT_PCI0_BS_SCS32:
587 case GT_PCI0_BS_CS20:
588 case GT_PCI0_BS_CS3BT:
589 case GT_PCI1_IACK:
590 case GT_PCI0_IACK:
591 case GT_PCI0_BARE:
592 case GT_PCI0_PREFMBR:
593 case GT_PCI0_SCS10_BAR:
594 case GT_PCI0_SCS32_BAR:
595 case GT_PCI0_CS20_BAR:
596 case GT_PCI0_CS3BT_BAR:
597 case GT_PCI0_SSCS10_BAR:
598 case GT_PCI0_SSCS32_BAR:
599 case GT_PCI0_SCS3BT_BAR:
600 case GT_PCI1_TOR:
601 case GT_PCI1_BS_SCS10:
602 case GT_PCI1_BS_SCS32:
603 case GT_PCI1_BS_CS20:
604 case GT_PCI1_BS_CS3BT:
605 case GT_PCI1_BARE:
606 case GT_PCI1_PREFMBR:
607 case GT_PCI1_SCS10_BAR:
608 case GT_PCI1_SCS32_BAR:
609 case GT_PCI1_CS20_BAR:
610 case GT_PCI1_CS3BT_BAR:
611 case GT_PCI1_SSCS10_BAR:
612 case GT_PCI1_SSCS32_BAR:
613 case GT_PCI1_SCS3BT_BAR:
614 case GT_PCI1_CFGADDR:
615 case GT_PCI1_CFGDATA:
616 /* not implemented */
617 break;
618 case GT_PCI0_CFGADDR:
619 phb->config_reg = val & 0x80fffffc;
620 break;
621 case GT_PCI0_CFGDATA:
622 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
623 val = bswap32(val);
624 }
625 if (phb->config_reg & (1u << 31)) {
626 pci_data_write(phb->bus, phb->config_reg, val, 4);
627 }
628 break;
629
630 /* Interrupts */
631 case GT_INTRCAUSE:
632 /* not really implemented */
633 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
634 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
635 DPRINTF("INTRCAUSE %" PRIx64 "\n", val);
636 break;
637 case GT_INTRMASK:
638 s->regs[saddr] = val & 0x3c3ffffe;
639 DPRINTF("INTRMASK %" PRIx64 "\n", val);
640 break;
641 case GT_PCI0_ICMASK:
642 s->regs[saddr] = val & 0x03fffffe;
643 DPRINTF("ICMASK %" PRIx64 "\n", val);
644 break;
645 case GT_PCI0_SERR0MASK:
646 s->regs[saddr] = val & 0x0000003f;
647 DPRINTF("SERR0MASK %" PRIx64 "\n", val);
648 break;
649
650 /* Reserved when only PCI_0 is configured. */
651 case GT_HINTRCAUSE:
652 case GT_CPU_INTSEL:
653 case GT_PCI0_INTSEL:
654 case GT_HINTRMASK:
655 case GT_PCI0_HICMASK:
656 case GT_PCI1_SERR1MASK:
657 /* not implemented */
658 break;
659
660 /* SDRAM Parameters */
661 case GT_SDRAM_B0:
662 case GT_SDRAM_B1:
663 case GT_SDRAM_B2:
664 case GT_SDRAM_B3:
665 /* We don't simulate electrical parameters of the SDRAM.
666 Accept, but ignore the values. */
667 s->regs[saddr] = val;
668 break;
669
670 default:
671 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
672 break;
673 }
674 }
675
676 static uint64_t gt64120_readl (void *opaque,
677 hwaddr addr, unsigned size)
678 {
679 GT64120State *s = opaque;
680 PCIHostState *phb = PCI_HOST_BRIDGE(s);
681 uint32_t val;
682 uint32_t saddr;
683
684 saddr = (addr & 0xfff) >> 2;
685 switch (saddr) {
686
687 /* CPU Configuration */
688 case GT_MULTI:
689 /* Only one GT64xxx is present on the CPU bus, return
690 the initial value */
691 val = s->regs[saddr];
692 break;
693
694 /* CPU Error Report */
695 case GT_CPUERR_ADDRLO:
696 case GT_CPUERR_ADDRHI:
697 case GT_CPUERR_DATALO:
698 case GT_CPUERR_DATAHI:
699 case GT_CPUERR_PARITY:
700 /* Emulated memory has no error, always return the initial
701 values */
702 val = s->regs[saddr];
703 break;
704
705 /* CPU Sync Barrier */
706 case GT_PCI0SYNC:
707 case GT_PCI1SYNC:
708 /* Reading those register should empty all FIFO on the PCI
709 bus, which are not emulated. The return value should be
710 a random value that should be ignored. */
711 val = 0xc000ffee;
712 break;
713
714 /* ECC */
715 case GT_ECC_ERRDATALO:
716 case GT_ECC_ERRDATAHI:
717 case GT_ECC_MEM:
718 case GT_ECC_CALC:
719 case GT_ECC_ERRADDR:
720 /* Emulated memory has no error, always return the initial
721 values */
722 val = s->regs[saddr];
723 break;
724
725 case GT_CPU:
726 case GT_SCS10LD:
727 case GT_SCS10HD:
728 case GT_SCS32LD:
729 case GT_SCS32HD:
730 case GT_CS20LD:
731 case GT_CS20HD:
732 case GT_CS3BOOTLD:
733 case GT_CS3BOOTHD:
734 case GT_SCS10AR:
735 case GT_SCS32AR:
736 case GT_CS20R:
737 case GT_CS3BOOTR:
738 case GT_PCI0IOLD:
739 case GT_PCI0M0LD:
740 case GT_PCI0M1LD:
741 case GT_PCI1IOLD:
742 case GT_PCI1M0LD:
743 case GT_PCI1M1LD:
744 case GT_PCI0IOHD:
745 case GT_PCI0M0HD:
746 case GT_PCI0M1HD:
747 case GT_PCI1IOHD:
748 case GT_PCI1M0HD:
749 case GT_PCI1M1HD:
750 case GT_PCI0IOREMAP:
751 case GT_PCI0M0REMAP:
752 case GT_PCI0M1REMAP:
753 case GT_PCI1IOREMAP:
754 case GT_PCI1M0REMAP:
755 case GT_PCI1M1REMAP:
756 case GT_ISD:
757 val = s->regs[saddr];
758 break;
759 case GT_PCI0_IACK:
760 /* Read the IRQ number */
761 val = pic_read_irq(isa_pic);
762 break;
763
764 /* SDRAM and Device Address Decode */
765 case GT_SCS0LD:
766 case GT_SCS0HD:
767 case GT_SCS1LD:
768 case GT_SCS1HD:
769 case GT_SCS2LD:
770 case GT_SCS2HD:
771 case GT_SCS3LD:
772 case GT_SCS3HD:
773 case GT_CS0LD:
774 case GT_CS0HD:
775 case GT_CS1LD:
776 case GT_CS1HD:
777 case GT_CS2LD:
778 case GT_CS2HD:
779 case GT_CS3LD:
780 case GT_CS3HD:
781 case GT_BOOTLD:
782 case GT_BOOTHD:
783 case GT_ADERR:
784 val = s->regs[saddr];
785 break;
786
787 /* SDRAM Configuration */
788 case GT_SDRAM_CFG:
789 case GT_SDRAM_OPMODE:
790 case GT_SDRAM_BM:
791 case GT_SDRAM_ADDRDECODE:
792 val = s->regs[saddr];
793 break;
794
795 /* SDRAM Parameters */
796 case GT_SDRAM_B0:
797 case GT_SDRAM_B1:
798 case GT_SDRAM_B2:
799 case GT_SDRAM_B3:
800 /* We don't simulate electrical parameters of the SDRAM.
801 Just return the last written value. */
802 val = s->regs[saddr];
803 break;
804
805 /* Device Parameters */
806 case GT_DEV_B0:
807 case GT_DEV_B1:
808 case GT_DEV_B2:
809 case GT_DEV_B3:
810 case GT_DEV_BOOT:
811 val = s->regs[saddr];
812 break;
813
814 /* DMA Record */
815 case GT_DMA0_CNT:
816 case GT_DMA1_CNT:
817 case GT_DMA2_CNT:
818 case GT_DMA3_CNT:
819 case GT_DMA0_SA:
820 case GT_DMA1_SA:
821 case GT_DMA2_SA:
822 case GT_DMA3_SA:
823 case GT_DMA0_DA:
824 case GT_DMA1_DA:
825 case GT_DMA2_DA:
826 case GT_DMA3_DA:
827 case GT_DMA0_NEXT:
828 case GT_DMA1_NEXT:
829 case GT_DMA2_NEXT:
830 case GT_DMA3_NEXT:
831 case GT_DMA0_CUR:
832 case GT_DMA1_CUR:
833 case GT_DMA2_CUR:
834 case GT_DMA3_CUR:
835 val = s->regs[saddr];
836 break;
837
838 /* DMA Channel Control */
839 case GT_DMA0_CTRL:
840 case GT_DMA1_CTRL:
841 case GT_DMA2_CTRL:
842 case GT_DMA3_CTRL:
843 val = s->regs[saddr];
844 break;
845
846 /* DMA Arbiter */
847 case GT_DMA_ARB:
848 val = s->regs[saddr];
849 break;
850
851 /* Timer/Counter */
852 case GT_TC0:
853 case GT_TC1:
854 case GT_TC2:
855 case GT_TC3:
856 case GT_TC_CONTROL:
857 val = s->regs[saddr];
858 break;
859
860 /* PCI Internal */
861 case GT_PCI0_CFGADDR:
862 val = phb->config_reg;
863 break;
864 case GT_PCI0_CFGDATA:
865 if (!(phb->config_reg & (1 << 31))) {
866 val = 0xffffffff;
867 } else {
868 val = pci_data_read(phb->bus, phb->config_reg, 4);
869 }
870 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
871 val = bswap32(val);
872 }
873 break;
874
875 case GT_PCI0_CMD:
876 case GT_PCI0_TOR:
877 case GT_PCI0_BS_SCS10:
878 case GT_PCI0_BS_SCS32:
879 case GT_PCI0_BS_CS20:
880 case GT_PCI0_BS_CS3BT:
881 case GT_PCI1_IACK:
882 case GT_PCI0_BARE:
883 case GT_PCI0_PREFMBR:
884 case GT_PCI0_SCS10_BAR:
885 case GT_PCI0_SCS32_BAR:
886 case GT_PCI0_CS20_BAR:
887 case GT_PCI0_CS3BT_BAR:
888 case GT_PCI0_SSCS10_BAR:
889 case GT_PCI0_SSCS32_BAR:
890 case GT_PCI0_SCS3BT_BAR:
891 case GT_PCI1_CMD:
892 case GT_PCI1_TOR:
893 case GT_PCI1_BS_SCS10:
894 case GT_PCI1_BS_SCS32:
895 case GT_PCI1_BS_CS20:
896 case GT_PCI1_BS_CS3BT:
897 case GT_PCI1_BARE:
898 case GT_PCI1_PREFMBR:
899 case GT_PCI1_SCS10_BAR:
900 case GT_PCI1_SCS32_BAR:
901 case GT_PCI1_CS20_BAR:
902 case GT_PCI1_CS3BT_BAR:
903 case GT_PCI1_SSCS10_BAR:
904 case GT_PCI1_SSCS32_BAR:
905 case GT_PCI1_SCS3BT_BAR:
906 case GT_PCI1_CFGADDR:
907 case GT_PCI1_CFGDATA:
908 val = s->regs[saddr];
909 break;
910
911 /* Interrupts */
912 case GT_INTRCAUSE:
913 val = s->regs[saddr];
914 DPRINTF("INTRCAUSE %x\n", val);
915 break;
916 case GT_INTRMASK:
917 val = s->regs[saddr];
918 DPRINTF("INTRMASK %x\n", val);
919 break;
920 case GT_PCI0_ICMASK:
921 val = s->regs[saddr];
922 DPRINTF("ICMASK %x\n", val);
923 break;
924 case GT_PCI0_SERR0MASK:
925 val = s->regs[saddr];
926 DPRINTF("SERR0MASK %x\n", val);
927 break;
928
929 /* Reserved when only PCI_0 is configured. */
930 case GT_HINTRCAUSE:
931 case GT_CPU_INTSEL:
932 case GT_PCI0_INTSEL:
933 case GT_HINTRMASK:
934 case GT_PCI0_HICMASK:
935 case GT_PCI1_SERR1MASK:
936 val = s->regs[saddr];
937 break;
938
939 default:
940 val = s->regs[saddr];
941 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
942 break;
943 }
944
945 if (!(s->regs[GT_CPU] & 0x00001000))
946 val = bswap32(val);
947
948 return val;
949 }
950
951 static const MemoryRegionOps isd_mem_ops = {
952 .read = gt64120_readl,
953 .write = gt64120_writel,
954 .endianness = DEVICE_NATIVE_ENDIAN,
955 };
956
957 static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
958 {
959 int slot;
960
961 slot = (pci_dev->devfn >> 3);
962
963 switch (slot) {
964 /* PIIX4 USB */
965 case 10:
966 return 3;
967 /* AMD 79C973 Ethernet */
968 case 11:
969 return 1;
970 /* Crystal 4281 Sound */
971 case 12:
972 return 2;
973 /* PCI slot 1 to 4 */
974 case 18 ... 21:
975 return ((slot - 18) + irq_num) & 0x03;
976 /* Unknown device, don't do any translation */
977 default:
978 return irq_num;
979 }
980 }
981
982 static int pci_irq_levels[4];
983
984 static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
985 {
986 int i, pic_irq, pic_level;
987 qemu_irq *pic = opaque;
988
989 pci_irq_levels[irq_num] = level;
990
991 /* now we change the pic irq level according to the piix irq mappings */
992 /* XXX: optimize */
993 pic_irq = piix4_dev->config[0x60 + irq_num];
994 if (pic_irq < 16) {
995 /* The pic level is the logical OR of all the PCI irqs mapped
996 to it */
997 pic_level = 0;
998 for (i = 0; i < 4; i++) {
999 if (pic_irq == piix4_dev->config[0x60 + i])
1000 pic_level |= pci_irq_levels[i];
1001 }
1002 qemu_set_irq(pic[pic_irq], pic_level);
1003 }
1004 }
1005
1006
1007 static void gt64120_reset(void *opaque)
1008 {
1009 GT64120State *s = opaque;
1010
1011 /* FIXME: Malta specific hw assumptions ahead */
1012
1013 /* CPU Configuration */
1014 #ifdef TARGET_WORDS_BIGENDIAN
1015 s->regs[GT_CPU] = 0x00000000;
1016 #else
1017 s->regs[GT_CPU] = 0x00001000;
1018 #endif
1019 s->regs[GT_MULTI] = 0x00000003;
1020
1021 /* CPU Address decode */
1022 s->regs[GT_SCS10LD] = 0x00000000;
1023 s->regs[GT_SCS10HD] = 0x00000007;
1024 s->regs[GT_SCS32LD] = 0x00000008;
1025 s->regs[GT_SCS32HD] = 0x0000000f;
1026 s->regs[GT_CS20LD] = 0x000000e0;
1027 s->regs[GT_CS20HD] = 0x00000070;
1028 s->regs[GT_CS3BOOTLD] = 0x000000f8;
1029 s->regs[GT_CS3BOOTHD] = 0x0000007f;
1030
1031 s->regs[GT_PCI0IOLD] = 0x00000080;
1032 s->regs[GT_PCI0IOHD] = 0x0000000f;
1033 s->regs[GT_PCI0M0LD] = 0x00000090;
1034 s->regs[GT_PCI0M0HD] = 0x0000001f;
1035 s->regs[GT_ISD] = 0x000000a0;
1036 s->regs[GT_PCI0M1LD] = 0x00000790;
1037 s->regs[GT_PCI0M1HD] = 0x0000001f;
1038 s->regs[GT_PCI1IOLD] = 0x00000100;
1039 s->regs[GT_PCI1IOHD] = 0x0000000f;
1040 s->regs[GT_PCI1M0LD] = 0x00000110;
1041 s->regs[GT_PCI1M0HD] = 0x0000001f;
1042 s->regs[GT_PCI1M1LD] = 0x00000120;
1043 s->regs[GT_PCI1M1HD] = 0x0000002f;
1044
1045 s->regs[GT_SCS10AR] = 0x00000000;
1046 s->regs[GT_SCS32AR] = 0x00000008;
1047 s->regs[GT_CS20R] = 0x000000e0;
1048 s->regs[GT_CS3BOOTR] = 0x000000f8;
1049
1050 s->regs[GT_PCI0IOREMAP] = 0x00000080;
1051 s->regs[GT_PCI0M0REMAP] = 0x00000090;
1052 s->regs[GT_PCI0M1REMAP] = 0x00000790;
1053 s->regs[GT_PCI1IOREMAP] = 0x00000100;
1054 s->regs[GT_PCI1M0REMAP] = 0x00000110;
1055 s->regs[GT_PCI1M1REMAP] = 0x00000120;
1056
1057 /* CPU Error Report */
1058 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1059 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1060 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1061 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1062 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1063
1064 /* CPU Sync Barrier */
1065 s->regs[GT_PCI0SYNC] = 0x00000000;
1066 s->regs[GT_PCI1SYNC] = 0x00000000;
1067
1068 /* SDRAM and Device Address Decode */
1069 s->regs[GT_SCS0LD] = 0x00000000;
1070 s->regs[GT_SCS0HD] = 0x00000007;
1071 s->regs[GT_SCS1LD] = 0x00000008;
1072 s->regs[GT_SCS1HD] = 0x0000000f;
1073 s->regs[GT_SCS2LD] = 0x00000010;
1074 s->regs[GT_SCS2HD] = 0x00000017;
1075 s->regs[GT_SCS3LD] = 0x00000018;
1076 s->regs[GT_SCS3HD] = 0x0000001f;
1077 s->regs[GT_CS0LD] = 0x000000c0;
1078 s->regs[GT_CS0HD] = 0x000000c7;
1079 s->regs[GT_CS1LD] = 0x000000c8;
1080 s->regs[GT_CS1HD] = 0x000000cf;
1081 s->regs[GT_CS2LD] = 0x000000d0;
1082 s->regs[GT_CS2HD] = 0x000000df;
1083 s->regs[GT_CS3LD] = 0x000000f0;
1084 s->regs[GT_CS3HD] = 0x000000fb;
1085 s->regs[GT_BOOTLD] = 0x000000fc;
1086 s->regs[GT_BOOTHD] = 0x000000ff;
1087 s->regs[GT_ADERR] = 0xffffffff;
1088
1089 /* SDRAM Configuration */
1090 s->regs[GT_SDRAM_CFG] = 0x00000200;
1091 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1092 s->regs[GT_SDRAM_BM] = 0x00000007;
1093 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1094
1095 /* SDRAM Parameters */
1096 s->regs[GT_SDRAM_B0] = 0x00000005;
1097 s->regs[GT_SDRAM_B1] = 0x00000005;
1098 s->regs[GT_SDRAM_B2] = 0x00000005;
1099 s->regs[GT_SDRAM_B3] = 0x00000005;
1100
1101 /* ECC */
1102 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1103 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1104 s->regs[GT_ECC_MEM] = 0x00000000;
1105 s->regs[GT_ECC_CALC] = 0x00000000;
1106 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1107
1108 /* Device Parameters */
1109 s->regs[GT_DEV_B0] = 0x386fffff;
1110 s->regs[GT_DEV_B1] = 0x386fffff;
1111 s->regs[GT_DEV_B2] = 0x386fffff;
1112 s->regs[GT_DEV_B3] = 0x386fffff;
1113 s->regs[GT_DEV_BOOT] = 0x146fffff;
1114
1115 /* DMA registers are all zeroed at reset */
1116
1117 /* Timer/Counter */
1118 s->regs[GT_TC0] = 0xffffffff;
1119 s->regs[GT_TC1] = 0x00ffffff;
1120 s->regs[GT_TC2] = 0x00ffffff;
1121 s->regs[GT_TC3] = 0x00ffffff;
1122 s->regs[GT_TC_CONTROL] = 0x00000000;
1123
1124 /* PCI Internal */
1125 s->regs[GT_PCI0_CMD] = 0;
1126 if (s->regs[GT_CPU] & (1 << 12)) {
1127 s->regs[GT_PCI0_CMD] = 0x00010001;
1128 }
1129 s->regs[GT_PCI0_TOR] = 0x0000070f;
1130 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1131 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1132 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1133 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1134 s->regs[GT_PCI1_IACK] = 0x00000000;
1135 s->regs[GT_PCI0_IACK] = 0x00000000;
1136 s->regs[GT_PCI0_BARE] = 0x0000000f;
1137 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1138 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1139 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1140 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1141 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1142 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1143 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1144 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1145 s->regs[GT_PCI1_CMD] = 0;
1146 if (s->regs[GT_CPU] & (1 << 12)) {
1147 s->regs[GT_PCI1_CMD] = 0x00010001;
1148 }
1149 s->regs[GT_PCI1_TOR] = 0x0000070f;
1150 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1151 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1152 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1153 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1154 s->regs[GT_PCI1_BARE] = 0x0000000f;
1155 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1156 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1157 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1158 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1159 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1160 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1161 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1162 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1163 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1164 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1165 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1166
1167 /* Interrupt registers are all zeroed at reset */
1168
1169 gt64120_isd_mapping(s);
1170 gt64120_pci_mapping(s);
1171 }
1172
1173 PCIBus *gt64120_register(qemu_irq *pic)
1174 {
1175 GT64120State *d;
1176 PCIHostState *phb;
1177 DeviceState *dev;
1178
1179 dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
1180 d = GT64120_PCI_HOST_BRIDGE(dev);
1181 phb = PCI_HOST_BRIDGE(dev);
1182 memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX);
1183 address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
1184 phb->bus = pci_register_root_bus(dev, "pci",
1185 gt64120_pci_set_irq, gt64120_pci_map_irq,
1186 pic,
1187 &d->pci0_mem,
1188 get_system_io(),
1189 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
1190 qdev_init_nofail(dev);
1191 memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000);
1192
1193 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1194 return phb->bus;
1195 }
1196
1197 static int gt64120_init(SysBusDevice *dev)
1198 {
1199 GT64120State *s;
1200
1201 s = GT64120_PCI_HOST_BRIDGE(dev);
1202
1203 qemu_register_reset(gt64120_reset, s);
1204 return 0;
1205 }
1206
1207 static void gt64120_pci_realize(PCIDevice *d, Error **errp)
1208 {
1209 /* FIXME: Malta specific hw assumptions ahead */
1210 //~ pci_set_word(d->config + PCI_COMMAND, 0);
1211 pci_set_word(d->config + PCI_STATUS,
1212 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1213 pci_config_set_prog_interface(d->config, 0);
1214 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1215 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1216 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1217 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1218 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1219 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1220 pci_set_byte(d->config + 0x3d, 0x01);
1221 }
1222
1223 static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1224 {
1225 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1226 DeviceClass *dc = DEVICE_CLASS(klass);
1227
1228 k->realize = gt64120_pci_realize;
1229 k->vendor_id = PCI_VENDOR_ID_MARVELL;
1230 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1231 k->revision = 0x10;
1232 k->class_id = PCI_CLASS_BRIDGE_HOST;
1233 /*
1234 * PCI-facing part of the host bridge, not usable without the
1235 * host-facing part, which can't be device_add'ed, yet.
1236 */
1237 dc->user_creatable = false;
1238 }
1239
1240 static const TypeInfo gt64120_pci_info = {
1241 .name = "gt64120_pci",
1242 .parent = TYPE_PCI_DEVICE,
1243 .instance_size = sizeof(PCIDevice),
1244 .class_init = gt64120_pci_class_init,
1245 .interfaces = (InterfaceInfo[]) {
1246 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1247 { },
1248 },
1249 };
1250
1251 static void gt64120_class_init(ObjectClass *klass, void *data)
1252 {
1253 DeviceClass *dc = DEVICE_CLASS(klass);
1254 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1255
1256 sdc->init = gt64120_init;
1257 dc->vmsd = &vmstate_gt64120;
1258 }
1259
1260 static const TypeInfo gt64120_info = {
1261 .name = TYPE_GT64120_PCI_HOST_BRIDGE,
1262 .parent = TYPE_PCI_HOST_BRIDGE,
1263 .instance_size = sizeof(GT64120State),
1264 .class_init = gt64120_class_init,
1265 };
1266
1267 static void gt64120_pci_register_types(void)
1268 {
1269 type_register_static(&gt64120_info);
1270 type_register_static(&gt64120_pci_info);
1271 }
1272
1273 type_init(gt64120_pci_register_types)
AR7 emulation for QEMU