2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "hw/sysbus.h"
34 #include "hw/arm/arm.h"
35 #include "hw/arm/primecell.h"
36 #include "hw/arm/virt.h"
37 #include "hw/devices.h"
39 #include "sysemu/block-backend.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/numa.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/kvm.h"
44 #include "hw/boards.h"
45 #include "hw/compat.h"
46 #include "hw/loader.h"
47 #include "exec/address-spaces.h"
48 #include "qemu/bitops.h"
49 #include "qemu/error-report.h"
50 #include "hw/pci-host/gpex.h"
51 #include "hw/arm/sysbus-fdt.h"
52 #include "hw/platform-bus.h"
53 #include "hw/arm/fdt.h"
54 #include "hw/intc/arm_gic.h"
55 #include "hw/intc/arm_gicv3_common.h"
57 #include "hw/smbios/smbios.h"
58 #include "qapi/visitor.h"
59 #include "standard-headers/linux/input.h"
61 /* Number of external interrupt lines to configure the GIC with */
64 #define PLATFORM_BUS_NUM_IRQS 64
66 static ARMPlatformBusSystemParams platform_bus_params
;
70 bool disallow_affinity_adjustment
;
73 bool claim_edge_triggered_timers
;
78 VirtGuestInfo acpi_guest_info
;
79 Notifier machine_done
;
83 struct arm_boot_info bootinfo
;
84 const MemMapEntry
*memmap
;
89 uint32_t clock_phandle
;
95 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
96 #define VIRT_MACHINE(obj) \
97 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
98 #define VIRT_MACHINE_GET_CLASS(obj) \
99 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
100 #define VIRT_MACHINE_CLASS(klass) \
101 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
104 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
105 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
108 MachineClass *mc = MACHINE_CLASS(oc); \
109 virt_machine_##major##_##minor##_options(mc); \
110 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
112 mc->alias = "virt"; \
115 static const TypeInfo machvirt_##major##_##minor##_info = { \
116 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
117 .parent = TYPE_VIRT_MACHINE, \
118 .instance_init = virt_##major##_##minor##_instance_init, \
119 .class_init = virt_##major##_##minor##_class_init, \
121 static void machvirt_machine_##major##_##minor##_init(void) \
123 type_register_static(&machvirt_##major##_##minor##_info); \
125 type_init(machvirt_machine_##major##_##minor##_init);
127 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
128 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
129 #define DEFINE_VIRT_MACHINE(major, minor) \
130 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
133 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
134 * RAM can go up to the 256GB mark, leaving 256GB of the physical
135 * address space unallocated and free for future use between 256G and 512G.
136 * If we need to provide more RAM to VMs in the future then we need to:
137 * * allocate a second bank of RAM starting at 2TB and working up
138 * * fix the DT and ACPI table generation code in QEMU to correctly
139 * report two split lumps of RAM to the guest
140 * * fix KVM in the host kernel to allow guests with >40 bit address spaces
141 * (We don't want to fill all the way up to 512GB with RAM because
142 * we might want it for non-RAM purposes later. Conversely it seems
143 * reasonable to assume that anybody configuring a VM with a quarter
144 * of a terabyte of RAM will be doing it on a host with more than a
145 * terabyte of physical address space.)
147 #define RAMLIMIT_GB 255
148 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
150 /* Addresses and sizes of our components.
151 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
152 * 128MB..256MB is used for miscellaneous device I/O.
153 * 256MB..1GB is reserved for possible future PCI support (ie where the
154 * PCI memory window will go if we add a PCI host controller).
155 * 1GB and up is RAM (which may happily spill over into the
156 * high memory region beyond 4GB).
157 * This represents a compromise between how much RAM can be given to
158 * a 32 bit VM and leaving space for expansion and in particular for PCI.
159 * Note that devices should generally be placed at multiples of 0x10000,
160 * to accommodate guests using 64K pages.
162 static const MemMapEntry a15memmap
[] = {
163 /* Space up to 0x8000000 is reserved for a boot ROM */
164 [VIRT_FLASH
] = { 0, 0x08000000 },
165 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
166 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
167 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
168 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
169 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
170 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
171 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
172 /* This redistributor space allows up to 2*64kB*123 CPUs */
173 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
174 [VIRT_UART
] = { 0x09000000, 0x00001000 },
175 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
176 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
177 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
178 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
179 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
180 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
181 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
182 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
183 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
184 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
185 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
186 [VIRT_MEM
] = { 0x40000000, RAMLIMIT_BYTES
},
187 /* Second PCIe window, 512GB wide at the 512GB boundary */
188 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
191 static const int a15irqmap
[] = {
194 [VIRT_PCIE
] = 3, /* ... to 6 */
196 [VIRT_SECURE_UART
] = 8,
197 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
198 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
199 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
202 static const char *valid_cpus
[] = {
210 static bool cpuname_valid(const char *cpu
)
214 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
215 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
222 static void create_fdt(VirtMachineState
*vms
)
224 void *fdt
= create_device_tree(&vms
->fdt_size
);
227 error_report("create_device_tree() failed");
234 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
235 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
236 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
239 * /chosen and /memory nodes must exist for load_dtb
240 * to fill in necessary properties later
242 qemu_fdt_add_subnode(fdt
, "/chosen");
243 qemu_fdt_add_subnode(fdt
, "/memory");
244 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
246 /* Clock node, for the benefit of the UART. The kernel device tree
247 * binding documentation claims the PL011 node clock properties are
248 * optional but in practice if you omit them the kernel refuses to
249 * probe for the device.
251 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
252 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
253 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
254 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
255 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
256 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
258 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
262 static void fdt_add_psci_node(const VirtMachineState
*vms
)
264 uint32_t cpu_suspend_fn
;
268 void *fdt
= vms
->fdt
;
269 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
271 if (!vms
->using_psci
) {
275 qemu_fdt_add_subnode(fdt
, "/psci");
276 if (armcpu
->psci_version
== 2) {
277 const char comp
[] = "arm,psci-0.2\0arm,psci";
278 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
280 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
281 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
282 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
283 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
284 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
286 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
287 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
288 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
291 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
293 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
294 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
295 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
296 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
299 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
300 * to the instruction that should be used to invoke PSCI functions.
301 * However, the device tree binding uses 'method' instead, so that is
302 * what we should use here.
304 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
306 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
307 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
308 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
309 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
312 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
314 /* On real hardware these interrupts are level-triggered.
315 * On KVM they were edge-triggered before host kernel version 4.4,
316 * and level-triggered afterwards.
317 * On emulated QEMU they are level-triggered.
319 * Getting the DTB info about them wrong is awkward for some
321 * pre-4.8 ignore the DT and leave the interrupt configured
322 * with whatever the GIC reset value (or the bootloader) left it at
323 * 4.8 before rc6 honour the incorrect data by programming it back
324 * into the GIC, causing problems
325 * 4.8rc6 and later ignore the DT and always write "level triggered"
328 * For backwards-compatibility, virt-2.8 and earlier will continue
329 * to say these are edge-triggered, but later machines will report
330 * the correct information.
333 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
334 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
336 if (vmc
->claim_edge_triggered_timers
) {
337 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
340 if (vms
->gic_version
== 2) {
341 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
342 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
343 (1 << vms
->smp_cpus
) - 1);
346 qemu_fdt_add_subnode(vms
->fdt
, "/timer");
348 armcpu
= ARM_CPU(qemu_get_cpu(0));
349 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
350 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
351 qemu_fdt_setprop(vms
->fdt
, "/timer", "compatible",
352 compat
, sizeof(compat
));
354 qemu_fdt_setprop_string(vms
->fdt
, "/timer", "compatible",
357 qemu_fdt_setprop(vms
->fdt
, "/timer", "always-on", NULL
, 0);
358 qemu_fdt_setprop_cells(vms
->fdt
, "/timer", "interrupts",
359 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
360 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
361 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
362 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
365 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
372 * From Documentation/devicetree/bindings/arm/cpus.txt
373 * On ARM v8 64-bit systems value should be set to 2,
374 * that corresponds to the MPIDR_EL1 register size.
375 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
376 * in the system, #address-cells can be set to 1, since
377 * MPIDR_EL1[63:32] bits are not used for CPUs
380 * Here we actually don't know whether our system is 32- or 64-bit one.
381 * The simplest way to go is to examine affinity IDs of all our CPUs. If
382 * at least one of them has Aff3 populated, we set #address-cells to 2.
384 for (cpu
= 0; cpu
< vms
->smp_cpus
; cpu
++) {
385 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
387 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
393 qemu_fdt_add_subnode(vms
->fdt
, "/cpus");
394 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#address-cells", addr_cells
);
395 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#size-cells", 0x0);
397 for (cpu
= vms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
398 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
399 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
401 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
402 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "cpu");
403 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
404 armcpu
->dtb_compatible
);
406 if (vms
->using_psci
&& vms
->smp_cpus
> 1) {
407 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
408 "enable-method", "psci");
411 if (addr_cells
== 2) {
412 qemu_fdt_setprop_u64(vms
->fdt
, nodename
, "reg",
413 armcpu
->mp_affinity
);
415 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "reg",
416 armcpu
->mp_affinity
);
419 i
= numa_get_node_for_cpu(cpu
);
420 if (i
< nb_numa_nodes
) {
421 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "numa-node-id", i
);
428 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
430 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
431 qemu_fdt_add_subnode(vms
->fdt
, "/intc/its");
432 qemu_fdt_setprop_string(vms
->fdt
, "/intc/its", "compatible",
434 qemu_fdt_setprop(vms
->fdt
, "/intc/its", "msi-controller", NULL
, 0);
435 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/its", "reg",
436 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
437 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
438 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/its", "phandle", vms
->msi_phandle
);
441 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
443 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
444 qemu_fdt_add_subnode(vms
->fdt
, "/intc/v2m");
445 qemu_fdt_setprop_string(vms
->fdt
, "/intc/v2m", "compatible",
446 "arm,gic-v2m-frame");
447 qemu_fdt_setprop(vms
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
448 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/v2m", "reg",
449 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
450 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
451 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/v2m", "phandle", vms
->msi_phandle
);
454 static void fdt_add_gic_node(VirtMachineState
*vms
)
456 vms
->gic_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
457 qemu_fdt_setprop_cell(vms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
459 qemu_fdt_add_subnode(vms
->fdt
, "/intc");
460 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#interrupt-cells", 3);
461 qemu_fdt_setprop(vms
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
462 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#address-cells", 0x2);
463 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#size-cells", 0x2);
464 qemu_fdt_setprop(vms
->fdt
, "/intc", "ranges", NULL
, 0);
465 if (vms
->gic_version
== 3) {
466 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
468 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
469 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
470 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
471 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
472 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
474 /* 'cortex-a15-gic' means 'GIC v2' */
475 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
476 "arm,cortex-a15-gic");
477 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
478 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
479 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
480 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
481 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
484 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "phandle", vms
->gic_phandle
);
487 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
491 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
494 armcpu
= ARM_CPU(cpu
);
495 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
) ||
496 !kvm_arm_pmu_create(cpu
, PPI(VIRTUAL_PMU_IRQ
))) {
501 if (vms
->gic_version
== 2) {
502 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
503 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
504 (1 << vms
->smp_cpus
) - 1);
507 armcpu
= ARM_CPU(qemu_get_cpu(0));
508 qemu_fdt_add_subnode(vms
->fdt
, "/pmu");
509 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
510 const char compat
[] = "arm,armv8-pmuv3";
511 qemu_fdt_setprop(vms
->fdt
, "/pmu", "compatible",
512 compat
, sizeof(compat
));
513 qemu_fdt_setprop_cells(vms
->fdt
, "/pmu", "interrupts",
514 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
518 static void create_its(VirtMachineState
*vms
, DeviceState
*gicdev
)
520 const char *itsclass
= its_class_name();
524 /* Do nothing if not supported */
528 dev
= qdev_create(NULL
, itsclass
);
530 object_property_set_link(OBJECT(dev
), OBJECT(gicdev
), "parent-gicv3",
532 qdev_init_nofail(dev
);
533 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
535 fdt_add_its_gic_node(vms
);
538 static void create_v2m(VirtMachineState
*vms
, qemu_irq
*pic
)
541 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
544 dev
= qdev_create(NULL
, "arm-gicv2m");
545 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
546 qdev_prop_set_uint32(dev
, "base-spi", irq
);
547 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
548 qdev_init_nofail(dev
);
550 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
551 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
554 fdt_add_v2m_gic_node(vms
);
557 static void create_gic(VirtMachineState
*vms
, qemu_irq
*pic
)
559 /* We create a standalone GIC */
560 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
562 SysBusDevice
*gicbusdev
;
564 int type
= vms
->gic_version
, i
;
566 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
568 gicdev
= qdev_create(NULL
, gictype
);
569 qdev_prop_set_uint32(gicdev
, "revision", type
);
570 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
571 /* Note that the num-irq property counts both internal and external
572 * interrupts; there are always 32 of the former (mandated by GIC spec).
574 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
575 if (!kvm_irqchip_in_kernel()) {
576 qdev_prop_set_bit(gicdev
, "has-security-extensions", vms
->secure
);
578 qdev_init_nofail(gicdev
);
579 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
580 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
582 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
584 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
587 /* Wire the outputs from each CPU's generic timer to the
588 * appropriate GIC PPI inputs, and the GIC's IRQ output to
589 * the CPU's IRQ input.
591 for (i
= 0; i
< smp_cpus
; i
++) {
592 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
593 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
595 /* Mapping from the output timer irq lines from the CPU to the
596 * GIC PPI inputs we use for the virt board.
598 const int timer_irq
[] = {
599 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
600 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
601 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
602 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
605 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
606 qdev_connect_gpio_out(cpudev
, irq
,
607 qdev_get_gpio_in(gicdev
,
608 ppibase
+ timer_irq
[irq
]));
611 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
612 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
613 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
616 for (i
= 0; i
< NUM_IRQS
; i
++) {
617 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
620 fdt_add_gic_node(vms
);
622 if (type
== 3 && !vmc
->no_its
) {
623 create_its(vms
, gicdev
);
624 } else if (type
== 2) {
625 create_v2m(vms
, pic
);
629 static void create_uart(const VirtMachineState
*vms
, qemu_irq
*pic
, int uart
,
630 MemoryRegion
*mem
, CharDriverState
*chr
)
633 hwaddr base
= vms
->memmap
[uart
].base
;
634 hwaddr size
= vms
->memmap
[uart
].size
;
635 int irq
= vms
->irqmap
[uart
];
636 const char compat
[] = "arm,pl011\0arm,primecell";
637 const char clocknames
[] = "uartclk\0apb_pclk";
638 DeviceState
*dev
= qdev_create(NULL
, "pl011");
639 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
641 qdev_prop_set_chr(dev
, "chardev", chr
);
642 qdev_init_nofail(dev
);
643 memory_region_add_subregion(mem
, base
,
644 sysbus_mmio_get_region(s
, 0));
645 sysbus_connect_irq(s
, 0, pic
[irq
]);
647 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
648 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
649 /* Note that we can't use setprop_string because of the embedded NUL */
650 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible",
651 compat
, sizeof(compat
));
652 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
654 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
655 GIC_FDT_IRQ_TYPE_SPI
, irq
,
656 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
657 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "clocks",
658 vms
->clock_phandle
, vms
->clock_phandle
);
659 qemu_fdt_setprop(vms
->fdt
, nodename
, "clock-names",
660 clocknames
, sizeof(clocknames
));
662 if (uart
== VIRT_UART
) {
663 qemu_fdt_setprop_string(vms
->fdt
, "/chosen", "stdout-path", nodename
);
665 /* Mark as not usable by the normal world */
666 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
667 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
673 static void create_rtc(const VirtMachineState
*vms
, qemu_irq
*pic
)
676 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
677 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
678 int irq
= vms
->irqmap
[VIRT_RTC
];
679 const char compat
[] = "arm,pl031\0arm,primecell";
681 sysbus_create_simple("pl031", base
, pic
[irq
]);
683 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
684 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
685 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
686 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
688 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
689 GIC_FDT_IRQ_TYPE_SPI
, irq
,
690 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
691 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
692 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
696 static DeviceState
*gpio_key_dev
;
697 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
699 /* use gpio Pin 3 for power button event */
700 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
703 static Notifier virt_system_powerdown_notifier
= {
704 .notify
= virt_powerdown_req
707 static void create_gpio(const VirtMachineState
*vms
, qemu_irq
*pic
)
710 DeviceState
*pl061_dev
;
711 hwaddr base
= vms
->memmap
[VIRT_GPIO
].base
;
712 hwaddr size
= vms
->memmap
[VIRT_GPIO
].size
;
713 int irq
= vms
->irqmap
[VIRT_GPIO
];
714 const char compat
[] = "arm,pl061\0arm,primecell";
716 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
718 uint32_t phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
719 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
720 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
721 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
723 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
724 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#gpio-cells", 2);
725 qemu_fdt_setprop(vms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
726 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
727 GIC_FDT_IRQ_TYPE_SPI
, irq
,
728 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
729 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
730 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
731 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", phandle
);
733 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
734 qdev_get_gpio_in(pl061_dev
, 3));
735 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys");
736 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
737 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#size-cells", 0);
738 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#address-cells", 1);
740 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys/poweroff");
741 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys/poweroff",
742 "label", "GPIO Key Poweroff");
743 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys/poweroff", "linux,code",
745 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-keys/poweroff",
746 "gpios", phandle
, 3, 0);
748 /* connect powerdown request */
749 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
754 static void create_virtio_devices(const VirtMachineState
*vms
, qemu_irq
*pic
)
757 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
759 /* We create the transports in forwards order. Since qbus_realize()
760 * prepends (not appends) new child buses, the incrementing loop below will
761 * create a list of virtio-mmio buses with decreasing base addresses.
763 * When a -device option is processed from the command line,
764 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
765 * order. The upshot is that -device options in increasing command line
766 * order are mapped to virtio-mmio buses with decreasing base addresses.
768 * When this code was originally written, that arrangement ensured that the
769 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
770 * the first -device on the command line. (The end-to-end order is a
771 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
772 * guest kernel's name-to-address assignment strategy.)
774 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
775 * the message, if not necessarily the code, of commit 70161ff336.
776 * Therefore the loop now establishes the inverse of the original intent.
778 * Unfortunately, we can't counteract the kernel change by reversing the
779 * loop; it would break existing command lines.
781 * In any case, the kernel makes no guarantee about the stability of
782 * enumeration order of virtio devices (as demonstrated by it changing
783 * between kernel versions). For reliable and stable identification
784 * of disks users must use UUIDs or similar mechanisms.
786 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
787 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
788 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
790 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
793 /* We add dtb nodes in reverse order so that they appear in the finished
794 * device tree lowest address first.
796 * Note that this mapping is independent of the loop above. The previous
797 * loop influences virtio device to virtio transport assignment, whereas
798 * this loop controls how virtio transports are laid out in the dtb.
800 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
802 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
803 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
805 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
806 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
807 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
808 "compatible", "virtio,mmio");
809 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
811 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
812 GIC_FDT_IRQ_TYPE_SPI
, irq
,
813 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
818 static void create_one_flash(const char *name
, hwaddr flashbase
,
819 hwaddr flashsize
, const char *file
,
820 MemoryRegion
*sysmem
)
822 /* Create and map a single flash device. We use the same
823 * parameters as the flash devices on the Versatile Express board.
825 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
826 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
827 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
828 const uint64_t sectorlength
= 256 * 1024;
831 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
835 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
836 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
837 qdev_prop_set_uint8(dev
, "width", 4);
838 qdev_prop_set_uint8(dev
, "device-width", 2);
839 qdev_prop_set_bit(dev
, "big-endian", false);
840 qdev_prop_set_uint16(dev
, "id0", 0x89);
841 qdev_prop_set_uint16(dev
, "id1", 0x18);
842 qdev_prop_set_uint16(dev
, "id2", 0x00);
843 qdev_prop_set_uint16(dev
, "id3", 0x00);
844 qdev_prop_set_string(dev
, "name", name
);
845 qdev_init_nofail(dev
);
847 memory_region_add_subregion(sysmem
, flashbase
,
848 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0));
854 if (drive_get(IF_PFLASH
, 0, 0)) {
855 error_report("The contents of the first flash device may be "
856 "specified with -bios or with -drive if=pflash... "
857 "but you cannot use both options at once");
860 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
862 error_report("Could not find ROM image '%s'", file
);
865 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
867 if (image_size
< 0) {
868 error_report("Could not load ROM image '%s'", file
);
874 static void create_flash(const VirtMachineState
*vms
,
875 MemoryRegion
*sysmem
,
876 MemoryRegion
*secure_sysmem
)
878 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
879 * Any file passed via -bios goes in the first of these.
880 * sysmem is the system memory space. secure_sysmem is the secure view
881 * of the system, and the first flash device should be made visible only
882 * there. The second flash device is visible to both secure and nonsecure.
883 * If sysmem == secure_sysmem this means there is no separate Secure
884 * address space and both flash devices are generally visible.
886 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
887 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
890 create_one_flash("virt.flash0", flashbase
, flashsize
,
891 bios_name
, secure_sysmem
);
892 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
,
895 if (sysmem
== secure_sysmem
) {
896 /* Report both flash devices as a single node in the DT */
897 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
898 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
899 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
900 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
901 2, flashbase
, 2, flashsize
,
902 2, flashbase
+ flashsize
, 2, flashsize
);
903 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
906 /* Report the devices as separate nodes so we can mark one as
907 * only visible to the secure world.
909 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
910 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
911 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
912 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
913 2, flashbase
, 2, flashsize
);
914 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
915 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
916 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
919 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
920 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
921 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
922 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
923 2, flashbase
+ flashsize
, 2, flashsize
);
924 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
929 static void create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
931 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
932 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
936 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
937 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
939 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
940 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
941 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
942 "compatible", "qemu,fw-cfg-mmio");
943 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
948 static void create_pcie_irq_map(const VirtMachineState
*vms
,
949 uint32_t gic_phandle
,
950 int first_irq
, const char *nodename
)
953 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
954 uint32_t *irq_map
= full_irq_map
;
956 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
957 for (pin
= 0; pin
< 4; pin
++) {
958 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
959 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
960 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
964 devfn
<< 8, 0, 0, /* devfn */
965 pin
+ 1, /* PCI pin */
966 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
968 /* Convert map to big endian */
969 for (i
= 0; i
< 10; i
++) {
970 irq_map
[i
] = cpu_to_be32(map
[i
]);
976 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-map",
977 full_irq_map
, sizeof(full_irq_map
));
979 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupt-map-mask",
980 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
984 static void create_pcie(const VirtMachineState
*vms
, qemu_irq
*pic
)
986 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
987 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
988 hwaddr base_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
989 hwaddr size_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
990 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
991 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
992 hwaddr base_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].base
;
993 hwaddr size_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].size
;
994 hwaddr base
= base_mmio
;
995 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
996 int irq
= vms
->irqmap
[VIRT_PCIE
];
997 MemoryRegion
*mmio_alias
;
998 MemoryRegion
*mmio_reg
;
999 MemoryRegion
*ecam_alias
;
1000 MemoryRegion
*ecam_reg
;
1006 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
1007 qdev_init_nofail(dev
);
1009 /* Map only the first size_ecam bytes of ECAM space */
1010 ecam_alias
= g_new0(MemoryRegion
, 1);
1011 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1012 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1013 ecam_reg
, 0, size_ecam
);
1014 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1016 /* Map the MMIO window into system address space so as to expose
1017 * the section of PCI MMIO space which starts at the same base address
1018 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1021 mmio_alias
= g_new0(MemoryRegion
, 1);
1022 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1023 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1024 mmio_reg
, base_mmio
, size_mmio
);
1025 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1028 /* Map high MMIO space */
1029 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1031 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1032 mmio_reg
, base_mmio_high
, size_mmio_high
);
1033 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1037 /* Map IO port space */
1038 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1040 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1041 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1044 pci
= PCI_HOST_BRIDGE(dev
);
1046 for (i
= 0; i
< nb_nics
; i
++) {
1047 NICInfo
*nd
= &nd_table
[i
];
1050 nd
->model
= g_strdup("virtio");
1053 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1057 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1058 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1059 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1060 "compatible", "pci-host-ecam-generic");
1061 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "pci");
1062 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 3);
1063 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 2);
1064 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "bus-range", 0,
1066 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1068 if (vms
->msi_phandle
) {
1069 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "msi-parent",
1073 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1074 2, base_ecam
, 2, size_ecam
);
1077 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1078 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1079 2, base_pio
, 2, size_pio
,
1080 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1081 2, base_mmio
, 2, size_mmio
,
1082 1, FDT_PCI_RANGE_MMIO_64BIT
,
1084 2, base_mmio_high
, 2, size_mmio_high
);
1086 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1087 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1088 2, base_pio
, 2, size_pio
,
1089 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1090 2, base_mmio
, 2, size_mmio
);
1093 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 1);
1094 create_pcie_irq_map(vms
, vms
->gic_phandle
, irq
, nodename
);
1099 static void create_platform_bus(VirtMachineState
*vms
, qemu_irq
*pic
)
1104 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
1105 MemoryRegion
*sysmem
= get_system_memory();
1107 platform_bus_params
.platform_bus_base
= vms
->memmap
[VIRT_PLATFORM_BUS
].base
;
1108 platform_bus_params
.platform_bus_size
= vms
->memmap
[VIRT_PLATFORM_BUS
].size
;
1109 platform_bus_params
.platform_bus_first_irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
];
1110 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
1112 fdt_params
->system_params
= &platform_bus_params
;
1113 fdt_params
->binfo
= &vms
->bootinfo
;
1114 fdt_params
->intc
= "/intc";
1116 * register a machine init done notifier that creates the device tree
1117 * nodes of the platform bus and its children dynamic sysbus devices
1119 arm_register_platform_bus_fdt_creator(fdt_params
);
1121 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1122 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1123 qdev_prop_set_uint32(dev
, "num_irqs",
1124 platform_bus_params
.platform_bus_num_irqs
);
1125 qdev_prop_set_uint32(dev
, "mmio_size",
1126 platform_bus_params
.platform_bus_size
);
1127 qdev_init_nofail(dev
);
1128 s
= SYS_BUS_DEVICE(dev
);
1130 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
1131 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
1132 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1135 memory_region_add_subregion(sysmem
,
1136 platform_bus_params
.platform_bus_base
,
1137 sysbus_mmio_get_region(s
, 0));
1140 static void create_secure_ram(VirtMachineState
*vms
,
1141 MemoryRegion
*secure_sysmem
)
1143 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1145 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1146 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1148 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
, &error_fatal
);
1149 vmstate_register_ram_global(secram
);
1150 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1152 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1153 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1154 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "memory");
1155 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1156 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1157 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1162 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1164 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1167 *fdt_size
= board
->fdt_size
;
1171 static void virt_build_smbios(VirtGuestInfo
*guest_info
)
1173 FWCfgState
*fw_cfg
= guest_info
->fw_cfg
;
1174 uint8_t *smbios_tables
, *smbios_anchor
;
1175 size_t smbios_tables_len
, smbios_anchor_len
;
1176 const char *product
= "QEMU Virtual Machine";
1182 if (kvm_enabled()) {
1183 product
= "KVM Virtual Machine";
1186 smbios_set_defaults("QEMU", product
,
1187 "1.0", false, true, SMBIOS_ENTRY_POINT_30
);
1189 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1190 &smbios_anchor
, &smbios_anchor_len
);
1192 if (smbios_anchor
) {
1193 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-tables",
1194 smbios_tables
, smbios_tables_len
);
1195 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-anchor",
1196 smbios_anchor
, smbios_anchor_len
);
1201 void virt_machine_done(Notifier
*notifier
, void *data
)
1203 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1206 virt_acpi_setup(&vms
->acpi_guest_info
);
1207 virt_build_smbios(&vms
->acpi_guest_info
);
1210 static void machvirt_init(MachineState
*machine
)
1212 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1213 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1214 qemu_irq pic
[NUM_IRQS
];
1215 MemoryRegion
*sysmem
= get_system_memory();
1216 MemoryRegion
*secure_sysmem
= NULL
;
1217 int n
, virt_max_cpus
;
1218 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1219 const char *cpu_model
= machine
->cpu_model
;
1220 VirtGuestInfo
*guest_info
= &vms
->acpi_guest_info
;
1223 const char *typename
;
1226 bool firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1230 cpu_model
= "cortex-a15";
1233 /* We can probe only here because during property set
1234 * KVM is not available yet
1236 if (!vms
->gic_version
) {
1237 if (!kvm_enabled()) {
1238 error_report("gic-version=host requires KVM");
1242 vms
->gic_version
= kvm_arm_vgic_probe();
1243 if (!vms
->gic_version
) {
1244 error_report("Unable to determine GIC version supported by host");
1249 /* Separate the actual CPU model name from any appended features */
1250 cpustr
= g_strsplit(cpu_model
, ",", 2);
1252 if (!cpuname_valid(cpustr
[0])) {
1253 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
1257 /* If we have an EL3 boot ROM then the assumption is that it will
1258 * implement PSCI itself, so disable QEMU's internal implementation
1259 * so it doesn't get in the way. Instead of starting secondary
1260 * CPUs in PSCI powerdown state we will start them all running and
1261 * let the boot ROM sort them out.
1262 * The usual case is that we do use QEMU's PSCI implementation.
1264 vms
->using_psci
= !(vms
->secure
&& firmware_loaded
);
1266 /* The maximum number of CPUs depends on the GIC version, or on how
1267 * many redistributors we can fit into the memory map.
1269 if (vms
->gic_version
== 3) {
1270 virt_max_cpus
= vms
->memmap
[VIRT_GIC_REDIST
].size
/ 0x20000;
1271 clustersz
= GICV3_TARGETLIST_BITS
;
1273 virt_max_cpus
= GIC_NCPU
;
1274 clustersz
= GIC_TARGETLIST_BITS
;
1277 if (max_cpus
> virt_max_cpus
) {
1278 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1279 "supported by machine 'mach-virt' (%d)",
1280 max_cpus
, virt_max_cpus
);
1284 vms
->smp_cpus
= smp_cpus
;
1286 if (machine
->ram_size
> vms
->memmap
[VIRT_MEM
].size
) {
1287 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB
);
1292 if (kvm_enabled()) {
1293 error_report("mach-virt: KVM does not support Security extensions");
1297 /* The Secure view of the world is the same as the NonSecure,
1298 * but with a few extra devices. Create it as a container region
1299 * containing the system memory at low priority; any secure-only
1300 * devices go in at higher priority and take precedence.
1302 secure_sysmem
= g_new(MemoryRegion
, 1);
1303 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1305 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1310 oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
1312 error_report("Unable to find CPU definition");
1315 typename
= object_class_get_name(oc
);
1317 /* convert -smp CPU options specified by the user into global props */
1319 cc
->parse_features(typename
, cpustr
[1], &err
);
1322 error_report_err(err
);
1326 for (n
= 0; n
< smp_cpus
; n
++) {
1327 Object
*cpuobj
= object_new(typename
);
1328 if (!vmc
->disallow_affinity_adjustment
) {
1329 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1330 * GIC's target-list limitations. 32-bit KVM hosts currently
1331 * always create clusters of 4 CPUs, but that is expected to
1332 * change when they gain support for gicv3. When KVM is enabled
1333 * it will override the changes we make here, therefore our
1334 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1335 * and to improve SGI efficiency.
1337 uint8_t aff1
= n
/ clustersz
;
1338 uint8_t aff0
= n
% clustersz
;
1339 object_property_set_int(cpuobj
, (aff1
<< ARM_AFF1_SHIFT
) | aff0
,
1340 "mp-affinity", NULL
);
1344 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1347 if (vms
->using_psci
) {
1348 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
,
1349 "psci-conduit", NULL
);
1351 /* Secondary CPUs start in PSCI powered-down state */
1353 object_property_set_bool(cpuobj
, true,
1354 "start-powered-off", NULL
);
1358 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu", NULL
)) {
1359 object_property_set_bool(cpuobj
, false, "pmu", NULL
);
1362 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1363 object_property_set_int(cpuobj
, vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1364 "reset-cbar", &error_abort
);
1367 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1370 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1371 "secure-memory", &error_abort
);
1374 object_property_set_bool(cpuobj
, true, "realized", NULL
);
1376 fdt_add_timer_nodes(vms
);
1377 fdt_add_cpu_nodes(vms
);
1378 fdt_add_psci_node(vms
);
1380 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1382 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
, ram
);
1384 create_flash(vms
, sysmem
, secure_sysmem
? secure_sysmem
: sysmem
);
1386 create_gic(vms
, pic
);
1388 fdt_add_pmu_nodes(vms
);
1390 create_uart(vms
, pic
, VIRT_UART
, sysmem
, serial_hds
[0]);
1393 create_secure_ram(vms
, secure_sysmem
);
1394 create_uart(vms
, pic
, VIRT_SECURE_UART
, secure_sysmem
, serial_hds
[1]);
1397 create_rtc(vms
, pic
);
1399 create_pcie(vms
, pic
);
1401 create_gpio(vms
, pic
);
1403 /* Create mmio transports, so the user can create virtio backends
1404 * (which will be automatically plugged in to the transports). If
1405 * no backend is created the transport will just sit harmlessly idle.
1407 create_virtio_devices(vms
, pic
);
1409 create_fw_cfg(vms
, &address_space_memory
);
1410 rom_set_fw(fw_cfg_find());
1412 guest_info
->smp_cpus
= smp_cpus
;
1413 guest_info
->fw_cfg
= fw_cfg_find();
1414 guest_info
->memmap
= vms
->memmap
;
1415 guest_info
->irqmap
= vms
->irqmap
;
1416 guest_info
->use_highmem
= vms
->highmem
;
1417 guest_info
->gic_version
= vms
->gic_version
;
1418 guest_info
->no_its
= vmc
->no_its
;
1419 vms
->machine_done
.notify
= virt_machine_done
;
1420 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
1422 vms
->bootinfo
.ram_size
= machine
->ram_size
;
1423 vms
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1424 vms
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1425 vms
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1426 vms
->bootinfo
.nb_cpus
= smp_cpus
;
1427 vms
->bootinfo
.board_id
= -1;
1428 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
1429 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
1430 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
1431 arm_load_kernel(ARM_CPU(first_cpu
), &vms
->bootinfo
);
1434 * arm_load_kernel machine init done notifier registration must
1435 * happen before the platform_bus_create call. In this latter,
1436 * another notifier is registered which adds platform bus nodes.
1437 * Notifiers are executed in registration reverse order.
1439 create_platform_bus(vms
, pic
);
1442 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1444 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1449 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1451 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1453 vms
->secure
= value
;
1456 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1458 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1460 return vms
->highmem
;
1463 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1465 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1467 vms
->highmem
= value
;
1470 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1472 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1473 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1475 return g_strdup(val
);
1478 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1480 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1482 if (!strcmp(value
, "3")) {
1483 vms
->gic_version
= 3;
1484 } else if (!strcmp(value
, "2")) {
1485 vms
->gic_version
= 2;
1486 } else if (!strcmp(value
, "host")) {
1487 vms
->gic_version
= 0; /* Will probe later */
1489 error_setg(errp
, "Invalid gic-version value");
1490 error_append_hint(errp
, "Valid values are 3, 2, host.\n");
1494 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1496 MachineClass
*mc
= MACHINE_CLASS(oc
);
1498 mc
->init
= machvirt_init
;
1499 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1500 * it later in machvirt_init, where we have more information about the
1501 * configuration of the particular instance.
1504 mc
->has_dynamic_sysbus
= true;
1505 mc
->block_default_type
= IF_VIRTIO
;
1507 mc
->pci_allow_0_address
= true;
1508 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1509 mc
->minimum_page_bits
= 12;
1512 static const TypeInfo virt_machine_info
= {
1513 .name
= TYPE_VIRT_MACHINE
,
1514 .parent
= TYPE_MACHINE
,
1516 .instance_size
= sizeof(VirtMachineState
),
1517 .class_size
= sizeof(VirtMachineClass
),
1518 .class_init
= virt_machine_class_init
,
1521 static void machvirt_machine_init(void)
1523 type_register_static(&virt_machine_info
);
1525 type_init(machvirt_machine_init
);
1527 static void virt_2_9_instance_init(Object
*obj
)
1529 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1531 /* EL3 is disabled by default on virt: this makes us consistent
1532 * between KVM and TCG for this board, and it also allows us to
1533 * boot UEFI blobs which assume no TrustZone support.
1535 vms
->secure
= false;
1536 object_property_add_bool(obj
, "secure", virt_get_secure
,
1537 virt_set_secure
, NULL
);
1538 object_property_set_description(obj
, "secure",
1539 "Set on/off to enable/disable the ARM "
1540 "Security Extensions (TrustZone)",
1543 /* High memory is enabled by default */
1544 vms
->highmem
= true;
1545 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1546 virt_set_highmem
, NULL
);
1547 object_property_set_description(obj
, "highmem",
1548 "Set on/off to enable/disable using "
1549 "physical address space above 32 bits",
1551 /* Default GIC type is v2 */
1552 vms
->gic_version
= 2;
1553 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1554 virt_set_gic_version
, NULL
);
1555 object_property_set_description(obj
, "gic-version",
1557 "Valid values are 2, 3 and host", NULL
);
1559 vms
->memmap
= a15memmap
;
1560 vms
->irqmap
= a15irqmap
;
1563 static void virt_machine_2_9_options(MachineClass
*mc
)
1566 DEFINE_VIRT_MACHINE_AS_LATEST(2, 9)
1568 #define VIRT_COMPAT_2_8 \
1571 static void virt_2_8_instance_init(Object
*obj
)
1573 virt_2_9_instance_init(obj
);
1576 static void virt_machine_2_8_options(MachineClass
*mc
)
1578 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1580 virt_machine_2_9_options(mc
);
1581 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_8
);
1582 /* For 2.8 and earlier we falsely claimed in the DT that
1583 * our timers were edge-triggered, not level-triggered.
1585 vmc
->claim_edge_triggered_timers
= true;
1587 DEFINE_VIRT_MACHINE(2, 8)
1589 #define VIRT_COMPAT_2_7 \
1592 static void virt_2_7_instance_init(Object
*obj
)
1594 virt_2_8_instance_init(obj
);
1597 static void virt_machine_2_7_options(MachineClass
*mc
)
1599 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1601 virt_machine_2_8_options(mc
);
1602 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_7
);
1603 /* ITS was introduced with 2.8 */
1605 /* Stick with 1K pages for migration compatibility */
1606 mc
->minimum_page_bits
= 0;
1608 DEFINE_VIRT_MACHINE(2, 7)
1610 #define VIRT_COMPAT_2_6 \
1613 static void virt_2_6_instance_init(Object
*obj
)
1615 virt_2_7_instance_init(obj
);
1618 static void virt_machine_2_6_options(MachineClass
*mc
)
1620 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1622 virt_machine_2_7_options(mc
);
1623 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_6
);
1624 vmc
->disallow_affinity_adjustment
= true;
1625 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
1628 DEFINE_VIRT_MACHINE(2, 6)