?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'v3.0.0-rc4'
[qemu/ar7.git] / memory.c
blobd1cf938feea0a3ac9ca77ca629e4c13919581fce
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "qemu-common.h"
19 #include "cpu.h"
20 #include "exec/exec-all.h" /* qemu_sprint_backtrace */
21 #include "exec/memory.h"
22 #include "exec/address-spaces.h"
23 #include "qapi/visitor.h"
24 #include "qemu/bitops.h"
25 #include "qemu/error-report.h"
26 #include "qom/object.h"
27 #include "trace-root.h"
28
29 #include "exec/memory-internal.h"
30 #include "exec/ram_addr.h"
31 #include "sysemu/kvm.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/misc/mmio_interface.h"
34 #include "hw/qdev-properties.h"
35 #include "migration/vmstate.h"
36
37 //#define DEBUG_UNASSIGNED
38
39 static unsigned memory_region_transaction_depth;
40 static bool memory_region_update_pending;
41 static bool ioeventfd_update_pending;
42 static bool global_dirty_log = false;
43
44 static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
46
47 static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
50 static GHashTable *flat_views;
51
52 typedef struct AddrRange AddrRange;
53
54 /*
55 * Note that signed integers are needed for negative offsetting in aliases
56 * (large MemoryRegion::alias_offset).
57 */
58 struct AddrRange {
59 Int128 start;
60 Int128 size;
61 };
62
63 static AddrRange addrrange_make(Int128 start, Int128 size)
64 {
65 return (AddrRange) { start, size };
66 }
67
68 static bool addrrange_equal(AddrRange r1, AddrRange r2)
69 {
70 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
71 }
72
73 static Int128 addrrange_end(AddrRange r)
74 {
75 return int128_add(r.start, r.size);
76 }
77
78 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
79 {
80 int128_addto(&range.start, delta);
81 return range;
82 }
83
84 static bool addrrange_contains(AddrRange range, Int128 addr)
85 {
86 return int128_ge(addr, range.start)
87 && int128_lt(addr, addrrange_end(range));
88 }
89
90 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
91 {
92 return addrrange_contains(r1, r2.start)
93 || addrrange_contains(r2, r1.start);
94 }
95
96 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
97 {
98 Int128 start = int128_max(r1.start, r2.start);
99 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
100 return addrrange_make(start, int128_sub(end, start));
101 }
102
103 enum ListenerDirection { Forward, Reverse };
104
105 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
106 do { \
107 MemoryListener *_listener; \
108 \
109 switch (_direction) { \
110 case Forward: \
111 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
112 if (_listener->_callback) { \
113 _listener->_callback(_listener, ##_args); \
114 } \
115 } \
116 break; \
117 case Reverse: \
118 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
119 memory_listeners, link) { \
120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
130 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
131 do { \
132 MemoryListener *_listener; \
133 struct memory_listeners_as *list = &(_as)->listeners; \
134 \
135 switch (_direction) { \
136 case Forward: \
137 QTAILQ_FOREACH(_listener, list, link_as) { \
138 if (_listener->_callback) { \
139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 case Reverse: \
144 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
145 link_as) { \
146 if (_listener->_callback) { \
147 _listener->_callback(_listener, _section, ##_args); \
148 } \
149 } \
150 break; \
151 default: \
152 abort(); \
153 } \
154 } while (0)
155
156 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
157 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
158 do { \
159 MemoryRegionSection mrs = section_from_flat_range(fr, \
160 address_space_to_flatview(as)); \
161 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
162 } while(0)
163
164 struct CoalescedMemoryRange {
165 AddrRange addr;
166 QTAILQ_ENTRY(CoalescedMemoryRange) link;
167 };
168
169 struct MemoryRegionIoeventfd {
170 AddrRange addr;
171 bool match_data;
172 uint64_t data;
173 EventNotifier *e;
174 };
175
176 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
177 MemoryRegionIoeventfd *b)
178 {
179 if (int128_lt(a->addr.start, b->addr.start)) {
180 return true;
181 } else if (int128_gt(a->addr.start, b->addr.start)) {
182 return false;
183 } else if (int128_lt(a->addr.size, b->addr.size)) {
184 return true;
185 } else if (int128_gt(a->addr.size, b->addr.size)) {
186 return false;
187 } else if (a->match_data < b->match_data) {
188 return true;
189 } else if (a->match_data > b->match_data) {
190 return false;
191 } else if (a->match_data) {
192 if (a->data < b->data) {
193 return true;
194 } else if (a->data > b->data) {
195 return false;
196 }
197 }
198 if (a->e < b->e) {
199 return true;
200 } else if (a->e > b->e) {
201 return false;
202 }
203 return false;
204 }
205
206 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
207 MemoryRegionIoeventfd *b)
208 {
209 return !memory_region_ioeventfd_before(a, b)
210 && !memory_region_ioeventfd_before(b, a);
211 }
212
213 /* Range of memory in the global map. Addresses are absolute. */
214 struct FlatRange {
215 MemoryRegion *mr;
216 hwaddr offset_in_region;
217 AddrRange addr;
218 uint8_t dirty_log_mask;
219 bool romd_mode;
220 bool readonly;
221 };
222
223 #define FOR_EACH_FLAT_RANGE(var, view) \
224 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
225
226 static inline MemoryRegionSection
227 section_from_flat_range(FlatRange *fr, FlatView *fv)
228 {
229 return (MemoryRegionSection) {
230 .mr = fr->mr,
231 .fv = fv,
232 .offset_within_region = fr->offset_in_region,
233 .size = fr->addr.size,
234 .offset_within_address_space = int128_get64(fr->addr.start),
235 .readonly = fr->readonly,
236 };
237 }
238
239 static bool flatrange_equal(FlatRange *a, FlatRange *b)
240 {
241 return a->mr == b->mr
242 && addrrange_equal(a->addr, b->addr)
243 && a->offset_in_region == b->offset_in_region
244 && a->romd_mode == b->romd_mode
245 && a->readonly == b->readonly;
246 }
247
248 static FlatView *flatview_new(MemoryRegion *mr_root)
249 {
250 FlatView *view;
251
252 view = g_new0(FlatView, 1);
253 view->ref = 1;
254 view->root = mr_root;
255 memory_region_ref(mr_root);
256 trace_flatview_new(view, mr_root);
257
258 return view;
259 }
260
261 /* Insert a range into a given position. Caller is responsible for maintaining
262 * sorting order.
263 */
264 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
265 {
266 if (view->nr == view->nr_allocated) {
267 view->nr_allocated = MAX(2 * view->nr, 10);
268 view->ranges = g_realloc(view->ranges,
269 view->nr_allocated * sizeof(*view->ranges));
270 }
271 memmove(view->ranges + pos + 1, view->ranges + pos,
272 (view->nr - pos) * sizeof(FlatRange));
273 view->ranges[pos] = *range;
274 memory_region_ref(range->mr);
275 ++view->nr;
276 }
277
278 static void flatview_destroy(FlatView *view)
279 {
280 int i;
281
282 trace_flatview_destroy(view, view->root);
283 if (view->dispatch) {
284 address_space_dispatch_free(view->dispatch);
285 }
286 for (i = 0; i < view->nr; i++) {
287 memory_region_unref(view->ranges[i].mr);
288 }
289 g_free(view->ranges);
290 memory_region_unref(view->root);
291 g_free(view);
292 }
293
294 static bool flatview_ref(FlatView *view)
295 {
296 return atomic_fetch_inc_nonzero(&view->ref) > 0;
297 }
298
299 void flatview_unref(FlatView *view)
300 {
301 if (atomic_fetch_dec(&view->ref) == 1) {
302 trace_flatview_destroy_rcu(view, view->root);
303 assert(view->root);
304 call_rcu(view, flatview_destroy, rcu);
305 }
306 }
307
308 static bool can_merge(FlatRange *r1, FlatRange *r2)
309 {
310 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
311 && r1->mr == r2->mr
312 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
313 r1->addr.size),
314 int128_make64(r2->offset_in_region))
315 && r1->dirty_log_mask == r2->dirty_log_mask
316 && r1->romd_mode == r2->romd_mode
317 && r1->readonly == r2->readonly;
318 }
319
320 /* Attempt to simplify a view by merging adjacent ranges */
321 static void flatview_simplify(FlatView *view)
322 {
323 unsigned i, j;
324
325 i = 0;
326 while (i < view->nr) {
327 j = i + 1;
328 while (j < view->nr
329 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
330 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
331 ++j;
332 }
333 ++i;
334 memmove(&view->ranges[i], &view->ranges[j],
335 (view->nr - j) * sizeof(view->ranges[j]));
336 view->nr -= j - i;
337 }
338 }
339
340 static bool memory_region_big_endian(MemoryRegion *mr)
341 {
342 #ifdef TARGET_WORDS_BIGENDIAN
343 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
344 #else
345 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
346 #endif
347 }
348
349 static bool memory_region_wrong_endianness(MemoryRegion *mr)
350 {
351 #ifdef TARGET_WORDS_BIGENDIAN
352 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
353 #else
354 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
355 #endif
356 }
357
358 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
359 {
360 if (memory_region_wrong_endianness(mr)) {
361 switch (size) {
362 case 1:
363 break;
364 case 2:
365 *data = bswap16(*data);
366 break;
367 case 4:
368 *data = bswap32(*data);
369 break;
370 case 8:
371 *data = bswap64(*data);
372 break;
373 default:
374 abort();
375 }
376 }
377 }
378
379 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
380 {
381 MemoryRegion *root;
382 hwaddr abs_addr = offset;
383
384 abs_addr += mr->addr;
385 for (root = mr; root->container; ) {
386 root = root->container;
387 abs_addr += root->addr;
388 }
389
390 return abs_addr;
391 }
392
393 static int get_cpu_index(void)
394 {
395 if (current_cpu) {
396 return current_cpu->cpu_index;
397 }
398 return -1;
399 }
400
401 static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
402 hwaddr addr,
403 uint64_t *value,
404 unsigned size,
405 unsigned shift,
406 uint64_t mask,
407 MemTxAttrs attrs)
408 {
409 uint64_t tmp;
410
411 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
412 if (mr->subpage) {
413 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
414 } else if (mr == &io_mem_notdirty) {
415 /* Accesses to code which has previously been translated into a TB show
416 * up in the MMIO path, as accesses to the io_mem_notdirty
417 * MemoryRegion. */
418 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
419 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
420 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
421 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
422 }
423 *value |= (tmp & mask) << shift;
424 return MEMTX_OK;
425 }
426
427 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
428 hwaddr addr,
429 uint64_t *value,
430 unsigned size,
431 unsigned shift,
432 uint64_t mask,
433 MemTxAttrs attrs)
434 {
435 uint64_t tmp;
436
437 tmp = mr->ops->read(mr->opaque, addr, size);
438 if (mr->subpage) {
439 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
440 } else if (mr == &io_mem_notdirty) {
441 /* Accesses to code which has previously been translated into a TB show
442 * up in the MMIO path, as accesses to the io_mem_notdirty
443 * MemoryRegion. */
444 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
445 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
446 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
447 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
448 }
449 *value |= (tmp & mask) << shift;
450 return MEMTX_OK;
451 }
452
453 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
454 hwaddr addr,
455 uint64_t *value,
456 unsigned size,
457 unsigned shift,
458 uint64_t mask,
459 MemTxAttrs attrs)
460 {
461 uint64_t tmp = 0;
462 MemTxResult r;
463
464 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
465 if (mr->subpage) {
466 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
467 } else if (mr == &io_mem_notdirty) {
468 /* Accesses to code which has previously been translated into a TB show
469 * up in the MMIO path, as accesses to the io_mem_notdirty
470 * MemoryRegion. */
471 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
472 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
473 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
474 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
475 }
476 *value |= (tmp & mask) << shift;
477 return r;
478 }
479
480 static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
481 hwaddr addr,
482 uint64_t *value,
483 unsigned size,
484 unsigned shift,
485 uint64_t mask,
486 MemTxAttrs attrs)
487 {
488 uint64_t tmp;
489
490 tmp = (*value >> shift) & mask;
491 if (mr->subpage) {
492 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
493 } else if (mr == &io_mem_notdirty) {
494 /* Accesses to code which has previously been translated into a TB show
495 * up in the MMIO path, as accesses to the io_mem_notdirty
496 * MemoryRegion. */
497 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
498 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
499 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
500 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
501 }
502 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
503 return MEMTX_OK;
504 }
505
506 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
507 hwaddr addr,
508 uint64_t *value,
509 unsigned size,
510 unsigned shift,
511 uint64_t mask,
512 MemTxAttrs attrs)
513 {
514 uint64_t tmp;
515
516 tmp = (*value >> shift) & mask;
517 if (mr->subpage) {
518 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
519 } else if (mr == &io_mem_notdirty) {
520 /* Accesses to code which has previously been translated into a TB show
521 * up in the MMIO path, as accesses to the io_mem_notdirty
522 * MemoryRegion. */
523 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
524 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
525 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
526 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
527 }
528 mr->ops->write(mr->opaque, addr, tmp, size);
529 return MEMTX_OK;
530 }
531
532 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
533 hwaddr addr,
534 uint64_t *value,
535 unsigned size,
536 unsigned shift,
537 uint64_t mask,
538 MemTxAttrs attrs)
539 {
540 uint64_t tmp;
541
542 tmp = (*value >> shift) & mask;
543 if (mr->subpage) {
544 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
545 } else if (mr == &io_mem_notdirty) {
546 /* Accesses to code which has previously been translated into a TB show
547 * up in the MMIO path, as accesses to the io_mem_notdirty
548 * MemoryRegion. */
549 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
550 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
551 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
552 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
553 }
554 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
555 }
556
557 static MemTxResult access_with_adjusted_size(hwaddr addr,
558 uint64_t *value,
559 unsigned size,
560 unsigned access_size_min,
561 unsigned access_size_max,
562 MemTxResult (*access_fn)
563 (MemoryRegion *mr,
564 hwaddr addr,
565 uint64_t *value,
566 unsigned size,
567 unsigned shift,
568 uint64_t mask,
569 MemTxAttrs attrs),
570 MemoryRegion *mr,
571 MemTxAttrs attrs)
572 {
573 uint64_t access_mask;
574 unsigned access_size;
575 unsigned i;
576 MemTxResult r = MEMTX_OK;
577
578 if (!access_size_min) {
579 access_size_min = 1;
580 }
581 if (!access_size_max) {
582 access_size_max = 4;
583 }
584
585 /* FIXME: support unaligned access? */
586 access_size = MAX(MIN(size, access_size_max), access_size_min);
587 access_mask = -1ULL >> (64 - access_size * 8);
588 if (memory_region_big_endian(mr)) {
589 for (i = 0; i < size; i += access_size) {
590 r |= access_fn(mr, addr + i, value, access_size,
591 (size - access_size - i) * 8, access_mask, attrs);
592 }
593 } else {
594 for (i = 0; i < size; i += access_size) {
595 r |= access_fn(mr, addr + i, value, access_size, i * 8,
596 access_mask, attrs);
597 }
598 }
599 return r;
600 }
601
602 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
603 {
604 AddressSpace *as;
605
606 while (mr->container) {
607 mr = mr->container;
608 }
609 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
610 if (mr == as->root) {
611 return as;
612 }
613 }
614 return NULL;
615 }
616
617 /* Render a memory region into the global view. Ranges in @view obscure
618 * ranges in @mr.
619 */
620 static void render_memory_region(FlatView *view,
621 MemoryRegion *mr,
622 Int128 base,
623 AddrRange clip,
624 bool readonly)
625 {
626 MemoryRegion *subregion;
627 unsigned i;
628 hwaddr offset_in_region;
629 Int128 remain;
630 Int128 now;
631 FlatRange fr;
632 AddrRange tmp;
633
634 if (!mr->enabled) {
635 return;
636 }
637
638 int128_addto(&base, int128_make64(mr->addr));
639 readonly |= mr->readonly;
640
641 tmp = addrrange_make(base, mr->size);
642
643 if (!addrrange_intersects(tmp, clip)) {
644 return;
645 }
646
647 clip = addrrange_intersection(tmp, clip);
648
649 if (mr->alias) {
650 int128_subfrom(&base, int128_make64(mr->alias->addr));
651 int128_subfrom(&base, int128_make64(mr->alias_offset));
652 render_memory_region(view, mr->alias, base, clip, readonly);
653 return;
654 }
655
656 /* Render subregions in priority order. */
657 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
658 render_memory_region(view, subregion, base, clip, readonly);
659 }
660
661 if (!mr->terminates) {
662 return;
663 }
664
665 offset_in_region = int128_get64(int128_sub(clip.start, base));
666 base = clip.start;
667 remain = clip.size;
668
669 fr.mr = mr;
670 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
671 fr.romd_mode = mr->romd_mode;
672 fr.readonly = readonly;
673
674 /* Render the region itself into any gaps left by the current view. */
675 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
676 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
677 continue;
678 }
679 if (int128_lt(base, view->ranges[i].addr.start)) {
680 now = int128_min(remain,
681 int128_sub(view->ranges[i].addr.start, base));
682 fr.offset_in_region = offset_in_region;
683 fr.addr = addrrange_make(base, now);
684 flatview_insert(view, i, &fr);
685 ++i;
686 int128_addto(&base, now);
687 offset_in_region += int128_get64(now);
688 int128_subfrom(&remain, now);
689 }
690 now = int128_sub(int128_min(int128_add(base, remain),
691 addrrange_end(view->ranges[i].addr)),
692 base);
693 int128_addto(&base, now);
694 offset_in_region += int128_get64(now);
695 int128_subfrom(&remain, now);
696 }
697 if (int128_nz(remain)) {
698 fr.offset_in_region = offset_in_region;
699 fr.addr = addrrange_make(base, remain);
700 flatview_insert(view, i, &fr);
701 }
702 }
703
704 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
705 {
706 while (mr->enabled) {
707 if (mr->alias) {
708 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
709 /* The alias is included in its entirety. Use it as
710 * the "real" root, so that we can share more FlatViews.
711 */
712 mr = mr->alias;
713 continue;
714 }
715 } else if (!mr->terminates) {
716 unsigned int found = 0;
717 MemoryRegion *child, *next = NULL;
718 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
719 if (child->enabled) {
720 if (++found > 1) {
721 next = NULL;
722 break;
723 }
724 if (!child->addr && int128_ge(mr->size, child->size)) {
725 /* A child is included in its entirety. If it's the only
726 * enabled one, use it in the hope of finding an alias down the
727 * way. This will also let us share FlatViews.
728 */
729 next = child;
730 }
731 }
732 }
733 if (found == 0) {
734 return NULL;
735 }
736 if (next) {
737 mr = next;
738 continue;
739 }
740 }
741
742 return mr;
743 }
744
745 return NULL;
746 }
747
748 /* Render a memory topology into a list of disjoint absolute ranges. */
749 static FlatView *generate_memory_topology(MemoryRegion *mr)
750 {
751 int i;
752 FlatView *view;
753
754 view = flatview_new(mr);
755
756 if (mr) {
757 render_memory_region(view, mr, int128_zero(),
758 addrrange_make(int128_zero(), int128_2_64()), false);
759 }
760 flatview_simplify(view);
761
762 view->dispatch = address_space_dispatch_new(view);
763 for (i = 0; i < view->nr; i++) {
764 MemoryRegionSection mrs =
765 section_from_flat_range(&view->ranges[i], view);
766 flatview_add_to_dispatch(view, &mrs);
767 }
768 address_space_dispatch_compact(view->dispatch);
769 g_hash_table_replace(flat_views, mr, view);
770
771 return view;
772 }
773
774 static void address_space_add_del_ioeventfds(AddressSpace *as,
775 MemoryRegionIoeventfd *fds_new,
776 unsigned fds_new_nb,
777 MemoryRegionIoeventfd *fds_old,
778 unsigned fds_old_nb)
779 {
780 unsigned iold, inew;
781 MemoryRegionIoeventfd *fd;
782 MemoryRegionSection section;
783
784 /* Generate a symmetric difference of the old and new fd sets, adding
785 * and deleting as necessary.
786 */
787
788 iold = inew = 0;
789 while (iold < fds_old_nb || inew < fds_new_nb) {
790 if (iold < fds_old_nb
791 && (inew == fds_new_nb
792 || memory_region_ioeventfd_before(&fds_old[iold],
793 &fds_new[inew]))) {
794 fd = &fds_old[iold];
795 section = (MemoryRegionSection) {
796 .fv = address_space_to_flatview(as),
797 .offset_within_address_space = int128_get64(fd->addr.start),
798 .size = fd->addr.size,
799 };
800 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
801 fd->match_data, fd->data, fd->e);
802 ++iold;
803 } else if (inew < fds_new_nb
804 && (iold == fds_old_nb
805 || memory_region_ioeventfd_before(&fds_new[inew],
806 &fds_old[iold]))) {
807 fd = &fds_new[inew];
808 section = (MemoryRegionSection) {
809 .fv = address_space_to_flatview(as),
810 .offset_within_address_space = int128_get64(fd->addr.start),
811 .size = fd->addr.size,
812 };
813 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
814 fd->match_data, fd->data, fd->e);
815 ++inew;
816 } else {
817 ++iold;
818 ++inew;
819 }
820 }
821 }
822
823 FlatView *address_space_get_flatview(AddressSpace *as)
824 {
825 FlatView *view;
826
827 rcu_read_lock();
828 do {
829 view = address_space_to_flatview(as);
830 /* If somebody has replaced as->current_map concurrently,
831 * flatview_ref returns false.
832 */
833 } while (!flatview_ref(view));
834 rcu_read_unlock();
835 return view;
836 }
837
838 static void address_space_update_ioeventfds(AddressSpace *as)
839 {
840 FlatView *view;
841 FlatRange *fr;
842 unsigned ioeventfd_nb = 0;
843 MemoryRegionIoeventfd *ioeventfds = NULL;
844 AddrRange tmp;
845 unsigned i;
846
847 view = address_space_get_flatview(as);
848 FOR_EACH_FLAT_RANGE(fr, view) {
849 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
850 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
851 int128_sub(fr->addr.start,
852 int128_make64(fr->offset_in_region)));
853 if (addrrange_intersects(fr->addr, tmp)) {
854 ++ioeventfd_nb;
855 ioeventfds = g_realloc(ioeventfds,
856 ioeventfd_nb * sizeof(*ioeventfds));
857 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
858 ioeventfds[ioeventfd_nb-1].addr = tmp;
859 }
860 }
861 }
862
863 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
864 as->ioeventfds, as->ioeventfd_nb);
865
866 g_free(as->ioeventfds);
867 as->ioeventfds = ioeventfds;
868 as->ioeventfd_nb = ioeventfd_nb;
869 flatview_unref(view);
870 }
871
872 static void address_space_update_topology_pass(AddressSpace *as,
873 const FlatView *old_view,
874 const FlatView *new_view,
875 bool adding)
876 {
877 unsigned iold, inew;
878 FlatRange *frold, *frnew;
879
880 /* Generate a symmetric difference of the old and new memory maps.
881 * Kill ranges in the old map, and instantiate ranges in the new map.
882 */
883 iold = inew = 0;
884 while (iold < old_view->nr || inew < new_view->nr) {
885 if (iold < old_view->nr) {
886 frold = &old_view->ranges[iold];
887 } else {
888 frold = NULL;
889 }
890 if (inew < new_view->nr) {
891 frnew = &new_view->ranges[inew];
892 } else {
893 frnew = NULL;
894 }
895
896 if (frold
897 && (!frnew
898 || int128_lt(frold->addr.start, frnew->addr.start)
899 || (int128_eq(frold->addr.start, frnew->addr.start)
900 && !flatrange_equal(frold, frnew)))) {
901 /* In old but not in new, or in both but attributes changed. */
902
903 if (!adding) {
904 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
905 }
906
907 ++iold;
908 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
909 /* In both and unchanged (except logging may have changed) */
910
911 if (adding) {
912 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
913 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
914 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
915 frold->dirty_log_mask,
916 frnew->dirty_log_mask);
917 }
918 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
919 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
920 frold->dirty_log_mask,
921 frnew->dirty_log_mask);
922 }
923 }
924
925 ++iold;
926 ++inew;
927 } else {
928 /* In new */
929
930 if (adding) {
931 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
932 }
933
934 ++inew;
935 }
936 }
937 }
938
939 static void flatviews_init(void)
940 {
941 static FlatView *empty_view;
942
943 if (flat_views) {
944 return;
945 }
946
947 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
948 (GDestroyNotify) flatview_unref);
949 if (!empty_view) {
950 empty_view = generate_memory_topology(NULL);
951 /* We keep it alive forever in the global variable. */
952 flatview_ref(empty_view);
953 } else {
954 g_hash_table_replace(flat_views, NULL, empty_view);
955 flatview_ref(empty_view);
956 }
957 }
958
959 static void flatviews_reset(void)
960 {
961 AddressSpace *as;
962
963 if (flat_views) {
964 g_hash_table_unref(flat_views);
965 flat_views = NULL;
966 }
967 flatviews_init();
968
969 /* Render unique FVs */
970 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
971 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
972
973 if (g_hash_table_lookup(flat_views, physmr)) {
974 continue;
975 }
976
977 generate_memory_topology(physmr);
978 }
979 }
980
981 static void address_space_set_flatview(AddressSpace *as)
982 {
983 FlatView *old_view = address_space_to_flatview(as);
984 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
985 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
986
987 assert(new_view);
988
989 if (old_view == new_view) {
990 return;
991 }
992
993 if (old_view) {
994 flatview_ref(old_view);
995 }
996
997 flatview_ref(new_view);
998
999 if (!QTAILQ_EMPTY(&as->listeners)) {
1000 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1001
1002 if (!old_view2) {
1003 old_view2 = &tmpview;
1004 }
1005 address_space_update_topology_pass(as, old_view2, new_view, false);
1006 address_space_update_topology_pass(as, old_view2, new_view, true);
1007 }
1008
1009 /* Writes are protected by the BQL. */
1010 atomic_rcu_set(&as->current_map, new_view);
1011 if (old_view) {
1012 flatview_unref(old_view);
1013 }
1014
1015 /* Note that all the old MemoryRegions are still alive up to this
1016 * point. This relieves most MemoryListeners from the need to
1017 * ref/unref the MemoryRegions they get---unless they use them
1018 * outside the iothread mutex, in which case precise reference
1019 * counting is necessary.
1020 */
1021 if (old_view) {
1022 flatview_unref(old_view);
1023 }
1024 }
1025
1026 static void address_space_update_topology(AddressSpace *as)
1027 {
1028 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1029
1030 flatviews_init();
1031 if (!g_hash_table_lookup(flat_views, physmr)) {
1032 generate_memory_topology(physmr);
1033 }
1034 address_space_set_flatview(as);
1035 }
1036
1037 void memory_region_transaction_begin(void)
1038 {
1039 qemu_flush_coalesced_mmio_buffer();
1040 ++memory_region_transaction_depth;
1041 }
1042
1043 void memory_region_transaction_commit(void)
1044 {
1045 AddressSpace *as;
1046
1047 assert(memory_region_transaction_depth);
1048 assert(qemu_mutex_iothread_locked());
1049
1050 --memory_region_transaction_depth;
1051 if (!memory_region_transaction_depth) {
1052 if (memory_region_update_pending) {
1053 flatviews_reset();
1054
1055 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1056
1057 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1058 address_space_set_flatview(as);
1059 address_space_update_ioeventfds(as);
1060 }
1061 memory_region_update_pending = false;
1062 ioeventfd_update_pending = false;
1063 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1064 } else if (ioeventfd_update_pending) {
1065 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1066 address_space_update_ioeventfds(as);
1067 }
1068 ioeventfd_update_pending = false;
1069 }
1070 }
1071 }
1072
1073 static void memory_region_destructor_none(MemoryRegion *mr)
1074 {
1075 }
1076
1077 static void memory_region_destructor_ram(MemoryRegion *mr)
1078 {
1079 qemu_ram_free(mr->ram_block);
1080 }
1081
1082 static bool memory_region_need_escape(char c)
1083 {
1084 return c == '/' || c == '[' || c == '\\' || c == ']';
1085 }
1086
1087 static char *memory_region_escape_name(const char *name)
1088 {
1089 const char *p;
1090 char *escaped, *q;
1091 uint8_t c;
1092 size_t bytes = 0;
1093
1094 for (p = name; *p; p++) {
1095 bytes += memory_region_need_escape(*p) ? 4 : 1;
1096 }
1097 if (bytes == p - name) {
1098 return g_memdup(name, bytes + 1);
1099 }
1100
1101 escaped = g_malloc(bytes + 1);
1102 for (p = name, q = escaped; *p; p++) {
1103 c = *p;
1104 if (unlikely(memory_region_need_escape(c))) {
1105 *q++ = '\\';
1106 *q++ = 'x';
1107 *q++ = "0123456789abcdef"[c >> 4];
1108 c = "0123456789abcdef"[c & 15];
1109 }
1110 *q++ = c;
1111 }
1112 *q = 0;
1113 return escaped;
1114 }
1115
1116 static void memory_region_do_init(MemoryRegion *mr,
1117 Object *owner,
1118 const char *name,
1119 uint64_t size)
1120 {
1121 mr->size = int128_make64(size);
1122 if (size == UINT64_MAX) {
1123 mr->size = int128_2_64();
1124 }
1125 mr->name = g_strdup(name);
1126 mr->owner = owner;
1127 mr->ram_block = NULL;
1128
1129 if (name) {
1130 char *escaped_name = memory_region_escape_name(name);
1131 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1132
1133 if (!owner) {
1134 owner = container_get(qdev_get_machine(), "/unattached");
1135 }
1136
1137 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1138 object_unref(OBJECT(mr));
1139 g_free(name_array);
1140 g_free(escaped_name);
1141 }
1142 }
1143
1144 void memory_region_init(MemoryRegion *mr,
1145 Object *owner,
1146 const char *name,
1147 uint64_t size)
1148 {
1149 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1150 memory_region_do_init(mr, owner, name, size);
1151 }
1152
1153 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1154 void *opaque, Error **errp)
1155 {
1156 MemoryRegion *mr = MEMORY_REGION(obj);
1157 uint64_t value = mr->addr;
1158
1159 visit_type_uint64(v, name, &value, errp);
1160 }
1161
1162 static void memory_region_get_container(Object *obj, Visitor *v,
1163 const char *name, void *opaque,
1164 Error **errp)
1165 {
1166 MemoryRegion *mr = MEMORY_REGION(obj);
1167 gchar *path = (gchar *)"";
1168
1169 if (mr->container) {
1170 path = object_get_canonical_path(OBJECT(mr->container));
1171 }
1172 visit_type_str(v, name, &path, errp);
1173 if (mr->container) {
1174 g_free(path);
1175 }
1176 }
1177
1178 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1179 const char *part)
1180 {
1181 MemoryRegion *mr = MEMORY_REGION(obj);
1182
1183 return OBJECT(mr->container);
1184 }
1185
1186 static void memory_region_get_priority(Object *obj, Visitor *v,
1187 const char *name, void *opaque,
1188 Error **errp)
1189 {
1190 MemoryRegion *mr = MEMORY_REGION(obj);
1191 int32_t value = mr->priority;
1192
1193 visit_type_int32(v, name, &value, errp);
1194 }
1195
1196 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1197 void *opaque, Error **errp)
1198 {
1199 MemoryRegion *mr = MEMORY_REGION(obj);
1200 uint64_t value = memory_region_size(mr);
1201
1202 visit_type_uint64(v, name, &value, errp);
1203 }
1204
1205 static void memory_region_initfn(Object *obj)
1206 {
1207 MemoryRegion *mr = MEMORY_REGION(obj);
1208 ObjectProperty *op;
1209
1210 mr->ops = &unassigned_mem_ops;
1211 mr->enabled = true;
1212 mr->romd_mode = true;
1213 mr->global_locking = true;
1214 mr->destructor = memory_region_destructor_none;
1215 QTAILQ_INIT(&mr->subregions);
1216 QTAILQ_INIT(&mr->coalesced);
1217
1218 op = object_property_add(OBJECT(mr), "container",
1219 "link<" TYPE_MEMORY_REGION ">",
1220 memory_region_get_container,
1221 NULL, /* memory_region_set_container */
1222 NULL, NULL, &error_abort);
1223 op->resolve = memory_region_resolve_container;
1224
1225 object_property_add(OBJECT(mr), "addr", "uint64",
1226 memory_region_get_addr,
1227 NULL, /* memory_region_set_addr */
1228 NULL, NULL, &error_abort);
1229 object_property_add(OBJECT(mr), "priority", "uint32",
1230 memory_region_get_priority,
1231 NULL, /* memory_region_set_priority */
1232 NULL, NULL, &error_abort);
1233 object_property_add(OBJECT(mr), "size", "uint64",
1234 memory_region_get_size,
1235 NULL, /* memory_region_set_size, */
1236 NULL, NULL, &error_abort);
1237 }
1238
1239 static int qemu_target_backtrace(target_ulong *array, size_t size)
1240 {
1241 int n = 0;
1242 if (size >= 2) {
1243 #if defined(TARGET_ARM)
1244 CPUArchState *env = current_cpu->env_ptr;
1245 array[0] = env->regs[15];
1246 array[1] = env->regs[14];
1247 #elif defined(TARGET_MIPS)
1248 CPUArchState *env = current_cpu->env_ptr;
1249 array[0] = env->active_tc.PC;
1250 array[1] = env->active_tc.gpr[31];
1251 #else
1252 array[0] = 0;
1253 array[1] = 0;
1254 #endif
1255 n = 2;
1256 }
1257 return n;
1258 }
1259
1260 #include "disas/disas.h"
1261 const char *qemu_sprint_backtrace(char *buffer, size_t length)
1262 {
1263 char *p = buffer;
1264 if (current_cpu) {
1265 target_ulong caller[2];
1266 const char *symbol;
1267 qemu_target_backtrace(caller, 2);
1268 symbol = lookup_symbol(caller[0]);
1269 p += sprintf(p, "[%s]", symbol);
1270 symbol = lookup_symbol(caller[1]);
1271 p += sprintf(p, "[%s]", symbol);
1272 } else {
1273 p += sprintf(p, "[cpu not running]");
1274 }
1275 assert((p - buffer) < length);
1276 return buffer;
1277 }
1278
1279 static void iommu_memory_region_initfn(Object *obj)
1280 {
1281 MemoryRegion *mr = MEMORY_REGION(obj);
1282
1283 mr->is_iommu = true;
1284 }
1285
1286 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1287 unsigned size)
1288 {
1289 if (trace_unassigned) {
1290 char buffer[256];
1291 fprintf(stderr, "Unassigned mem read " TARGET_FMT_plx " %s\n",
1292 addr, qemu_sprint_backtrace(buffer, sizeof(buffer)));
1293 }
1294 //~ vm_stop(0);
1295 if (current_cpu != NULL) {
1296 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
1297 }
1298 return 0;
1299 }
1300
1301 static void unassigned_mem_write(void *opaque, hwaddr addr,
1302 uint64_t val, unsigned size)
1303 {
1304 if (trace_unassigned) {
1305 char buffer[256];
1306 fprintf(stderr, "Unassigned mem write " TARGET_FMT_plx
1307 " = 0x%" PRIx64 " %s\n",
1308 addr, val, qemu_sprint_backtrace(buffer, sizeof(buffer)));
1309 }
1310 if (current_cpu != NULL) {
1311 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1312 }
1313 }
1314
1315 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1316 unsigned size, bool is_write,
1317 MemTxAttrs attrs)
1318 {
1319 return false;
1320 }
1321
1322 const MemoryRegionOps unassigned_mem_ops = {
1323 .valid.accepts = unassigned_mem_accepts,
1324 .endianness = DEVICE_NATIVE_ENDIAN,
1325 };
1326
1327 static uint64_t memory_region_ram_device_read(void *opaque,
1328 hwaddr addr, unsigned size)
1329 {
1330 MemoryRegion *mr = opaque;
1331 uint64_t data = (uint64_t)~0;
1332
1333 switch (size) {
1334 case 1:
1335 data = *(uint8_t *)(mr->ram_block->host + addr);
1336 break;
1337 case 2:
1338 data = *(uint16_t *)(mr->ram_block->host + addr);
1339 break;
1340 case 4:
1341 data = *(uint32_t *)(mr->ram_block->host + addr);
1342 break;
1343 case 8:
1344 data = *(uint64_t *)(mr->ram_block->host + addr);
1345 break;
1346 }
1347
1348 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1349
1350 return data;
1351 }
1352
1353 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1354 uint64_t data, unsigned size)
1355 {
1356 MemoryRegion *mr = opaque;
1357
1358 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1359
1360 switch (size) {
1361 case 1:
1362 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1363 break;
1364 case 2:
1365 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1366 break;
1367 case 4:
1368 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1369 break;
1370 case 8:
1371 *(uint64_t *)(mr->ram_block->host + addr) = data;
1372 break;
1373 }
1374 }
1375
1376 static const MemoryRegionOps ram_device_mem_ops = {
1377 .read = memory_region_ram_device_read,
1378 .write = memory_region_ram_device_write,
1379 .endianness = DEVICE_HOST_ENDIAN,
1380 .valid = {
1381 .min_access_size = 1,
1382 .max_access_size = 8,
1383 .unaligned = true,
1384 },
1385 .impl = {
1386 .min_access_size = 1,
1387 .max_access_size = 8,
1388 .unaligned = true,
1389 },
1390 };
1391
1392 bool memory_region_access_valid(MemoryRegion *mr,
1393 hwaddr addr,
1394 unsigned size,
1395 bool is_write,
1396 MemTxAttrs attrs)
1397 {
1398 int access_size_min, access_size_max;
1399 int access_size, i;
1400
1401 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1402 fprintf(stderr, "Misaligned i/o to address %08" HWADDR_PRIx
1403 " with size %u for memory region %s\n",
1404 addr, size, mr->name);
1405 return false;
1406 }
1407
1408 if (!mr->ops->valid.accepts) {
1409 return true;
1410 }
1411
1412 access_size_min = mr->ops->valid.min_access_size;
1413 if (!mr->ops->valid.min_access_size) {
1414 access_size_min = 1;
1415 }
1416
1417 access_size_max = mr->ops->valid.max_access_size;
1418 if (!mr->ops->valid.max_access_size) {
1419 access_size_max = 4;
1420 }
1421
1422 access_size = MAX(MIN(size, access_size_max), access_size_min);
1423 for (i = 0; i < size; i += access_size) {
1424 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1425 is_write, attrs)) {
1426 return false;
1427 }
1428 }
1429
1430 return true;
1431 }
1432
1433 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1434 hwaddr addr,
1435 uint64_t *pval,
1436 unsigned size,
1437 MemTxAttrs attrs)
1438 {
1439 *pval = 0;
1440
1441 if (mr->ops->read) {
1442 return access_with_adjusted_size(addr, pval, size,
1443 mr->ops->impl.min_access_size,
1444 mr->ops->impl.max_access_size,
1445 memory_region_read_accessor,
1446 mr, attrs);
1447 } else if (mr->ops->read_with_attrs) {
1448 return access_with_adjusted_size(addr, pval, size,
1449 mr->ops->impl.min_access_size,
1450 mr->ops->impl.max_access_size,
1451 memory_region_read_with_attrs_accessor,
1452 mr, attrs);
1453 } else {
1454 return access_with_adjusted_size(addr, pval, size, 1, 4,
1455 memory_region_oldmmio_read_accessor,
1456 mr, attrs);
1457 }
1458 }
1459
1460 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1461 hwaddr addr,
1462 uint64_t *pval,
1463 unsigned size,
1464 MemTxAttrs attrs)
1465 {
1466 MemTxResult r;
1467
1468 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1469 *pval = unassigned_mem_read(mr, addr, size);
1470 return MEMTX_DECODE_ERROR;
1471 }
1472
1473 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1474 adjust_endianness(mr, pval, size);
1475 return r;
1476 }
1477
1478 /* Return true if an eventfd was signalled */
1479 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1480 hwaddr addr,
1481 uint64_t data,
1482 unsigned size,
1483 MemTxAttrs attrs)
1484 {
1485 MemoryRegionIoeventfd ioeventfd = {
1486 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1487 .data = data,
1488 };
1489 unsigned i;
1490
1491 for (i = 0; i < mr->ioeventfd_nb; i++) {
1492 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1493 ioeventfd.e = mr->ioeventfds[i].e;
1494
1495 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1496 event_notifier_set(ioeventfd.e);
1497 return true;
1498 }
1499 }
1500
1501 return false;
1502 }
1503
1504 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1505 hwaddr addr,
1506 uint64_t data,
1507 unsigned size,
1508 MemTxAttrs attrs)
1509 {
1510 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1511 unassigned_mem_write(mr, addr, data, size);
1512 return MEMTX_DECODE_ERROR;
1513 }
1514
1515 adjust_endianness(mr, &data, size);
1516
1517 if ((!kvm_eventfds_enabled()) &&
1518 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1519 return MEMTX_OK;
1520 }
1521
1522 if (mr->ops->write) {
1523 return access_with_adjusted_size(addr, &data, size,
1524 mr->ops->impl.min_access_size,
1525 mr->ops->impl.max_access_size,
1526 memory_region_write_accessor, mr,
1527 attrs);
1528 } else if (mr->ops->write_with_attrs) {
1529 return
1530 access_with_adjusted_size(addr, &data, size,
1531 mr->ops->impl.min_access_size,
1532 mr->ops->impl.max_access_size,
1533 memory_region_write_with_attrs_accessor,
1534 mr, attrs);
1535 } else {
1536 return access_with_adjusted_size(addr, &data, size, 1, 4,
1537 memory_region_oldmmio_write_accessor,
1538 mr, attrs);
1539 }
1540 }
1541
1542 void memory_region_init_io(MemoryRegion *mr,
1543 Object *owner,
1544 const MemoryRegionOps *ops,
1545 void *opaque,
1546 const char *name,
1547 uint64_t size)
1548 {
1549 memory_region_init(mr, owner, name, size);
1550 mr->ops = ops ? ops : &unassigned_mem_ops;
1551 mr->opaque = opaque;
1552 mr->terminates = true;
1553 }
1554
1555 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1556 Object *owner,
1557 const char *name,
1558 uint64_t size,
1559 Error **errp)
1560 {
1561 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1562 }
1563
1564 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1565 Object *owner,
1566 const char *name,
1567 uint64_t size,
1568 bool share,
1569 Error **errp)
1570 {
1571 memory_region_init(mr, owner, name, size);
1572 mr->ram = true;
1573 mr->terminates = true;
1574 mr->destructor = memory_region_destructor_ram;
1575 mr->ram_block = qemu_ram_alloc(size, share, mr, errp);
1576 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1577 }
1578
1579 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1580 Object *owner,
1581 const char *name,
1582 uint64_t size,
1583 uint64_t max_size,
1584 void (*resized)(const char*,
1585 uint64_t length,
1586 void *host),
1587 Error **errp)
1588 {
1589 memory_region_init(mr, owner, name, size);
1590 mr->ram = true;
1591 mr->terminates = true;
1592 mr->destructor = memory_region_destructor_ram;
1593 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1594 mr, errp);
1595 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1596 }
1597
1598 #ifdef __linux__
1599 void memory_region_init_ram_from_file(MemoryRegion *mr,
1600 struct Object *owner,
1601 const char *name,
1602 uint64_t size,
1603 uint64_t align,
1604 bool share,
1605 const char *path,
1606 Error **errp)
1607 {
1608 memory_region_init(mr, owner, name, size);
1609 mr->ram = true;
1610 mr->terminates = true;
1611 mr->destructor = memory_region_destructor_ram;
1612 mr->align = align;
1613 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
1614 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1615 }
1616
1617 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1618 struct Object *owner,
1619 const char *name,
1620 uint64_t size,
1621 bool share,
1622 int fd,
1623 Error **errp)
1624 {
1625 memory_region_init(mr, owner, name, size);
1626 mr->ram = true;
1627 mr->terminates = true;
1628 mr->destructor = memory_region_destructor_ram;
1629 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1630 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1631 }
1632 #endif
1633
1634 void memory_region_init_ram_ptr(MemoryRegion *mr,
1635 Object *owner,
1636 const char *name,
1637 uint64_t size,
1638 void *ptr)
1639 {
1640 memory_region_init(mr, owner, name, size);
1641 mr->ram = true;
1642 mr->terminates = true;
1643 mr->destructor = memory_region_destructor_ram;
1644 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1645
1646 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1647 assert(ptr != NULL);
1648 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1649 }
1650
1651 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1652 Object *owner,
1653 const char *name,
1654 uint64_t size,
1655 void *ptr)
1656 {
1657 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1658 mr->ram_device = true;
1659 mr->ops = &ram_device_mem_ops;
1660 mr->opaque = mr;
1661 }
1662
1663 void memory_region_init_alias(MemoryRegion *mr,
1664 Object *owner,
1665 const char *name,
1666 MemoryRegion *orig,
1667 hwaddr offset,
1668 uint64_t size)
1669 {
1670 memory_region_init(mr, owner, name, size);
1671 mr->alias = orig;
1672 mr->alias_offset = offset;
1673 }
1674
1675 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1676 struct Object *owner,
1677 const char *name,
1678 uint64_t size,
1679 Error **errp)
1680 {
1681 memory_region_init(mr, owner, name, size);
1682 mr->ram = true;
1683 mr->readonly = true;
1684 mr->terminates = true;
1685 mr->destructor = memory_region_destructor_ram;
1686 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
1687 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1688 }
1689
1690 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1691 Object *owner,
1692 const MemoryRegionOps *ops,
1693 void *opaque,
1694 const char *name,
1695 uint64_t size,
1696 Error **errp)
1697 {
1698 assert(ops);
1699 memory_region_init(mr, owner, name, size);
1700 mr->ops = ops;
1701 mr->opaque = opaque;
1702 mr->terminates = true;
1703 mr->rom_device = true;
1704 mr->destructor = memory_region_destructor_ram;
1705 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
1706 }
1707
1708 void memory_region_init_iommu(void *_iommu_mr,
1709 size_t instance_size,
1710 const char *mrtypename,
1711 Object *owner,
1712 const char *name,
1713 uint64_t size)
1714 {
1715 struct IOMMUMemoryRegion *iommu_mr;
1716 struct MemoryRegion *mr;
1717
1718 object_initialize(_iommu_mr, instance_size, mrtypename);
1719 mr = MEMORY_REGION(_iommu_mr);
1720 memory_region_do_init(mr, owner, name, size);
1721 iommu_mr = IOMMU_MEMORY_REGION(mr);
1722 mr->terminates = true; /* then re-forwards */
1723 QLIST_INIT(&iommu_mr->iommu_notify);
1724 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1725 }
1726
1727 static void memory_region_finalize(Object *obj)
1728 {
1729 MemoryRegion *mr = MEMORY_REGION(obj);
1730
1731 assert(!mr->container);
1732
1733 /* We know the region is not visible in any address space (it
1734 * does not have a container and cannot be a root either because
1735 * it has no references, so we can blindly clear mr->enabled.
1736 * memory_region_set_enabled instead could trigger a transaction
1737 * and cause an infinite loop.
1738 */
1739 mr->enabled = false;
1740 memory_region_transaction_begin();
1741 while (!QTAILQ_EMPTY(&mr->subregions)) {
1742 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1743 memory_region_del_subregion(mr, subregion);
1744 }
1745 memory_region_transaction_commit();
1746
1747 mr->destructor(mr);
1748 memory_region_clear_coalescing(mr);
1749 g_free((char *)mr->name);
1750 g_free(mr->ioeventfds);
1751 }
1752
1753 Object *memory_region_owner(MemoryRegion *mr)
1754 {
1755 Object *obj = OBJECT(mr);
1756 return obj->parent;
1757 }
1758
1759 void memory_region_ref(MemoryRegion *mr)
1760 {
1761 /* MMIO callbacks most likely will access data that belongs
1762 * to the owner, hence the need to ref/unref the owner whenever
1763 * the memory region is in use.
1764 *
1765 * The memory region is a child of its owner. As long as the
1766 * owner doesn't call unparent itself on the memory region,
1767 * ref-ing the owner will also keep the memory region alive.
1768 * Memory regions without an owner are supposed to never go away;
1769 * we do not ref/unref them because it slows down DMA sensibly.
1770 */
1771 if (mr && mr->owner) {
1772 object_ref(mr->owner);
1773 }
1774 }
1775
1776 void memory_region_unref(MemoryRegion *mr)
1777 {
1778 if (mr && mr->owner) {
1779 object_unref(mr->owner);
1780 }
1781 }
1782
1783 uint64_t memory_region_size(MemoryRegion *mr)
1784 {
1785 if (int128_eq(mr->size, int128_2_64())) {
1786 return UINT64_MAX;
1787 }
1788 return int128_get64(mr->size);
1789 }
1790
1791 const char *memory_region_name(const MemoryRegion *mr)
1792 {
1793 if (!mr->name) {
1794 ((MemoryRegion *)mr)->name =
1795 object_get_canonical_path_component(OBJECT(mr));
1796 }
1797 return mr->name;
1798 }
1799
1800 bool memory_region_is_ram_device(MemoryRegion *mr)
1801 {
1802 return mr->ram_device;
1803 }
1804
1805 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1806 {
1807 uint8_t mask = mr->dirty_log_mask;
1808 if (global_dirty_log && mr->ram_block) {
1809 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1810 }
1811 return mask;
1812 }
1813
1814 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1815 {
1816 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1817 }
1818
1819 static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
1820 {
1821 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1822 IOMMUNotifier *iommu_notifier;
1823 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1824
1825 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1826 flags |= iommu_notifier->notifier_flags;
1827 }
1828
1829 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1830 imrc->notify_flag_changed(iommu_mr,
1831 iommu_mr->iommu_notify_flags,
1832 flags);
1833 }
1834
1835 iommu_mr->iommu_notify_flags = flags;
1836 }
1837
1838 void memory_region_register_iommu_notifier(MemoryRegion *mr,
1839 IOMMUNotifier *n)
1840 {
1841 IOMMUMemoryRegion *iommu_mr;
1842
1843 if (mr->alias) {
1844 memory_region_register_iommu_notifier(mr->alias, n);
1845 return;
1846 }
1847
1848 /* We need to register for at least one bitfield */
1849 iommu_mr = IOMMU_MEMORY_REGION(mr);
1850 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1851 assert(n->start <= n->end);
1852 assert(n->iommu_idx >= 0 &&
1853 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1854
1855 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1856 memory_region_update_iommu_notify_flags(iommu_mr);
1857 }
1858
1859 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1860 {
1861 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1862
1863 if (imrc->get_min_page_size) {
1864 return imrc->get_min_page_size(iommu_mr);
1865 }
1866 return TARGET_PAGE_SIZE;
1867 }
1868
1869 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1870 {
1871 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1872 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1873 hwaddr addr, granularity;
1874 IOMMUTLBEntry iotlb;
1875
1876 /* If the IOMMU has its own replay callback, override */
1877 if (imrc->replay) {
1878 imrc->replay(iommu_mr, n);
1879 return;
1880 }
1881
1882 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1883
1884 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1885 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1886 if (iotlb.perm != IOMMU_NONE) {
1887 n->notify(n, &iotlb);
1888 }
1889
1890 /* if (2^64 - MR size) < granularity, it's possible to get an
1891 * infinite loop here. This should catch such a wraparound */
1892 if ((addr + granularity) < addr) {
1893 break;
1894 }
1895 }
1896 }
1897
1898 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
1899 {
1900 IOMMUNotifier *notifier;
1901
1902 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1903 memory_region_iommu_replay(iommu_mr, notifier);
1904 }
1905 }
1906
1907 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1908 IOMMUNotifier *n)
1909 {
1910 IOMMUMemoryRegion *iommu_mr;
1911
1912 if (mr->alias) {
1913 memory_region_unregister_iommu_notifier(mr->alias, n);
1914 return;
1915 }
1916 QLIST_REMOVE(n, node);
1917 iommu_mr = IOMMU_MEMORY_REGION(mr);
1918 memory_region_update_iommu_notify_flags(iommu_mr);
1919 }
1920
1921 void memory_region_notify_one(IOMMUNotifier *notifier,
1922 IOMMUTLBEntry *entry)
1923 {
1924 IOMMUNotifierFlag request_flags;
1925
1926 /*
1927 * Skip the notification if the notification does not overlap
1928 * with registered range.
1929 */
1930 if (notifier->start > entry->iova + entry->addr_mask ||
1931 notifier->end < entry->iova) {
1932 return;
1933 }
1934
1935 if (entry->perm & IOMMU_RW) {
1936 request_flags = IOMMU_NOTIFIER_MAP;
1937 } else {
1938 request_flags = IOMMU_NOTIFIER_UNMAP;
1939 }
1940
1941 if (notifier->notifier_flags & request_flags) {
1942 notifier->notify(notifier, entry);
1943 }
1944 }
1945
1946 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1947 int iommu_idx,
1948 IOMMUTLBEntry entry)
1949 {
1950 IOMMUNotifier *iommu_notifier;
1951
1952 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1953
1954 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1955 if (iommu_notifier->iommu_idx == iommu_idx) {
1956 memory_region_notify_one(iommu_notifier, &entry);
1957 }
1958 }
1959 }
1960
1961 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1962 enum IOMMUMemoryRegionAttr attr,
1963 void *data)
1964 {
1965 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1966
1967 if (!imrc->get_attr) {
1968 return -EINVAL;
1969 }
1970
1971 return imrc->get_attr(iommu_mr, attr, data);
1972 }
1973
1974 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1975 MemTxAttrs attrs)
1976 {
1977 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1978
1979 if (!imrc->attrs_to_index) {
1980 return 0;
1981 }
1982
1983 return imrc->attrs_to_index(iommu_mr, attrs);
1984 }
1985
1986 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
1987 {
1988 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1989
1990 if (!imrc->num_indexes) {
1991 return 1;
1992 }
1993
1994 return imrc->num_indexes(iommu_mr);
1995 }
1996
1997 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1998 {
1999 uint8_t mask = 1 << client;
2000 uint8_t old_logging;
2001
2002 assert(client == DIRTY_MEMORY_VGA);
2003 old_logging = mr->vga_logging_count;
2004 mr->vga_logging_count += log ? 1 : -1;
2005 if (!!old_logging == !!mr->vga_logging_count) {
2006 return;
2007 }
2008
2009 memory_region_transaction_begin();
2010 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2011 memory_region_update_pending |= mr->enabled;
2012 memory_region_transaction_commit();
2013 }
2014
2015 bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
2016 hwaddr size, unsigned client)
2017 {
2018 assert(mr->ram_block);
2019 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
2020 size, client);
2021 }
2022
2023 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2024 hwaddr size)
2025 {
2026 assert(mr->ram_block);
2027 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2028 size,
2029 memory_region_get_dirty_log_mask(mr));
2030 }
2031
2032 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2033 {
2034 MemoryListener *listener;
2035 AddressSpace *as;
2036 FlatView *view;
2037 FlatRange *fr;
2038
2039 /* If the same address space has multiple log_sync listeners, we
2040 * visit that address space's FlatView multiple times. But because
2041 * log_sync listeners are rare, it's still cheaper than walking each
2042 * address space once.
2043 */
2044 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2045 if (!listener->log_sync) {
2046 continue;
2047 }
2048 as = listener->address_space;
2049 view = address_space_get_flatview(as);
2050 FOR_EACH_FLAT_RANGE(fr, view) {
2051 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2052 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2053 listener->log_sync(listener, &mrs);
2054 }
2055 }
2056 flatview_unref(view);
2057 }
2058 }
2059
2060 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2061 hwaddr addr,
2062 hwaddr size,
2063 unsigned client)
2064 {
2065 assert(mr->ram_block);
2066 memory_region_sync_dirty_bitmap(mr);
2067 return cpu_physical_memory_snapshot_and_clear_dirty(
2068 memory_region_get_ram_addr(mr) + addr, size, client);
2069 }
2070
2071 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2072 hwaddr addr, hwaddr size)
2073 {
2074 assert(mr->ram_block);
2075 return cpu_physical_memory_snapshot_get_dirty(snap,
2076 memory_region_get_ram_addr(mr) + addr, size);
2077 }
2078
2079 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2080 {
2081 if (mr->readonly != readonly) {
2082 memory_region_transaction_begin();
2083 mr->readonly = readonly;
2084 memory_region_update_pending |= mr->enabled;
2085 memory_region_transaction_commit();
2086 }
2087 }
2088
2089 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2090 {
2091 if (mr->romd_mode != romd_mode) {
2092 memory_region_transaction_begin();
2093 mr->romd_mode = romd_mode;
2094 memory_region_update_pending |= mr->enabled;
2095 memory_region_transaction_commit();
2096 }
2097 }
2098
2099 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2100 hwaddr size, unsigned client)
2101 {
2102 assert(mr->ram_block);
2103 cpu_physical_memory_test_and_clear_dirty(
2104 memory_region_get_ram_addr(mr) + addr, size, client);
2105 }
2106
2107 int memory_region_get_fd(MemoryRegion *mr)
2108 {
2109 int fd;
2110
2111 rcu_read_lock();
2112 while (mr->alias) {
2113 mr = mr->alias;
2114 }
2115 fd = mr->ram_block->fd;
2116 rcu_read_unlock();
2117
2118 return fd;
2119 }
2120
2121 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2122 {
2123 void *ptr;
2124 uint64_t offset = 0;
2125
2126 rcu_read_lock();
2127 while (mr->alias) {
2128 offset += mr->alias_offset;
2129 mr = mr->alias;
2130 }
2131 assert(mr->ram_block);
2132 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2133 rcu_read_unlock();
2134
2135 return ptr;
2136 }
2137
2138 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2139 {
2140 RAMBlock *block;
2141
2142 block = qemu_ram_block_from_host(ptr, false, offset);
2143 if (!block) {
2144 return NULL;
2145 }
2146
2147 return block->mr;
2148 }
2149
2150 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2151 {
2152 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2153 }
2154
2155 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2156 {
2157 assert(mr->ram_block);
2158
2159 qemu_ram_resize(mr->ram_block, newsize, errp);
2160 }
2161
2162 static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
2163 {
2164 FlatView *view;
2165 FlatRange *fr;
2166 CoalescedMemoryRange *cmr;
2167 AddrRange tmp;
2168 MemoryRegionSection section;
2169
2170 view = address_space_get_flatview(as);
2171 FOR_EACH_FLAT_RANGE(fr, view) {
2172 if (fr->mr == mr) {
2173 section = (MemoryRegionSection) {
2174 .fv = view,
2175 .offset_within_address_space = int128_get64(fr->addr.start),
2176 .size = fr->addr.size,
2177 };
2178
2179 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
2180 int128_get64(fr->addr.start),
2181 int128_get64(fr->addr.size));
2182 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2183 tmp = addrrange_shift(cmr->addr,
2184 int128_sub(fr->addr.start,
2185 int128_make64(fr->offset_in_region)));
2186 if (!addrrange_intersects(tmp, fr->addr)) {
2187 continue;
2188 }
2189 tmp = addrrange_intersection(tmp, fr->addr);
2190 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
2191 int128_get64(tmp.start),
2192 int128_get64(tmp.size));
2193 }
2194 }
2195 }
2196 flatview_unref(view);
2197 }
2198
2199 static void memory_region_update_coalesced_range(MemoryRegion *mr)
2200 {
2201 AddressSpace *as;
2202
2203 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2204 memory_region_update_coalesced_range_as(mr, as);
2205 }
2206 }
2207
2208 void memory_region_set_coalescing(MemoryRegion *mr)
2209 {
2210 memory_region_clear_coalescing(mr);
2211 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2212 }
2213
2214 void memory_region_add_coalescing(MemoryRegion *mr,
2215 hwaddr offset,
2216 uint64_t size)
2217 {
2218 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2219
2220 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2221 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2222 memory_region_update_coalesced_range(mr);
2223 memory_region_set_flush_coalesced(mr);
2224 }
2225
2226 void memory_region_clear_coalescing(MemoryRegion *mr)
2227 {
2228 CoalescedMemoryRange *cmr;
2229 bool updated = false;
2230
2231 qemu_flush_coalesced_mmio_buffer();
2232 mr->flush_coalesced_mmio = false;
2233
2234 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2235 cmr = QTAILQ_FIRST(&mr->coalesced);
2236 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2237 g_free(cmr);
2238 updated = true;
2239 }
2240
2241 if (updated) {
2242 memory_region_update_coalesced_range(mr);
2243 }
2244 }
2245
2246 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2247 {
2248 mr->flush_coalesced_mmio = true;
2249 }
2250
2251 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2252 {
2253 qemu_flush_coalesced_mmio_buffer();
2254 if (QTAILQ_EMPTY(&mr->coalesced)) {
2255 mr->flush_coalesced_mmio = false;
2256 }
2257 }
2258
2259 void memory_region_clear_global_locking(MemoryRegion *mr)
2260 {
2261 mr->global_locking = false;
2262 }
2263
2264 static bool userspace_eventfd_warning;
2265
2266 void memory_region_add_eventfd(MemoryRegion *mr,
2267 hwaddr addr,
2268 unsigned size,
2269 bool match_data,
2270 uint64_t data,
2271 EventNotifier *e)
2272 {
2273 MemoryRegionIoeventfd mrfd = {
2274 .addr.start = int128_make64(addr),
2275 .addr.size = int128_make64(size),
2276 .match_data = match_data,
2277 .data = data,
2278 .e = e,
2279 };
2280 unsigned i;
2281
2282 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2283 userspace_eventfd_warning))) {
2284 userspace_eventfd_warning = true;
2285 error_report("Using eventfd without MMIO binding in KVM. "
2286 "Suboptimal performance expected");
2287 }
2288
2289 if (size) {
2290 adjust_endianness(mr, &mrfd.data, size);
2291 }
2292 memory_region_transaction_begin();
2293 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2294 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2295 break;
2296 }
2297 }
2298 ++mr->ioeventfd_nb;
2299 mr->ioeventfds = g_realloc(mr->ioeventfds,
2300 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2301 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2302 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2303 mr->ioeventfds[i] = mrfd;
2304 ioeventfd_update_pending |= mr->enabled;
2305 memory_region_transaction_commit();
2306 }
2307
2308 void memory_region_del_eventfd(MemoryRegion *mr,
2309 hwaddr addr,
2310 unsigned size,
2311 bool match_data,
2312 uint64_t data,
2313 EventNotifier *e)
2314 {
2315 MemoryRegionIoeventfd mrfd = {
2316 .addr.start = int128_make64(addr),
2317 .addr.size = int128_make64(size),
2318 .match_data = match_data,
2319 .data = data,
2320 .e = e,
2321 };
2322 unsigned i;
2323
2324 if (size) {
2325 adjust_endianness(mr, &mrfd.data, size);
2326 }
2327 memory_region_transaction_begin();
2328 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2329 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2330 break;
2331 }
2332 }
2333 assert(i != mr->ioeventfd_nb);
2334 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2335 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2336 --mr->ioeventfd_nb;
2337 mr->ioeventfds = g_realloc(mr->ioeventfds,
2338 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2339 ioeventfd_update_pending |= mr->enabled;
2340 memory_region_transaction_commit();
2341 }
2342
2343 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2344 {
2345 MemoryRegion *mr = subregion->container;
2346 MemoryRegion *other;
2347
2348 memory_region_transaction_begin();
2349
2350 memory_region_ref(subregion);
2351 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2352 if (subregion->priority >= other->priority) {
2353 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2354 goto done;
2355 }
2356 }
2357 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2358 done:
2359 memory_region_update_pending |= mr->enabled && subregion->enabled;
2360 memory_region_transaction_commit();
2361 }
2362
2363 static void memory_region_add_subregion_common(MemoryRegion *mr,
2364 hwaddr offset,
2365 MemoryRegion *subregion)
2366 {
2367 assert(!subregion->container);
2368 subregion->container = mr;
2369 subregion->addr = offset;
2370 memory_region_update_container_subregions(subregion);
2371 }
2372
2373 void memory_region_add_subregion(MemoryRegion *mr,
2374 hwaddr offset,
2375 MemoryRegion *subregion)
2376 {
2377 subregion->priority = 0;
2378 memory_region_add_subregion_common(mr, offset, subregion);
2379 }
2380
2381 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2382 hwaddr offset,
2383 MemoryRegion *subregion,
2384 int priority)
2385 {
2386 subregion->priority = priority;
2387 memory_region_add_subregion_common(mr, offset, subregion);
2388 }
2389
2390 void memory_region_del_subregion(MemoryRegion *mr,
2391 MemoryRegion *subregion)
2392 {
2393 memory_region_transaction_begin();
2394 assert(subregion->container == mr);
2395 subregion->container = NULL;
2396 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2397 memory_region_unref(subregion);
2398 memory_region_update_pending |= mr->enabled && subregion->enabled;
2399 memory_region_transaction_commit();
2400 }
2401
2402 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2403 {
2404 if (enabled == mr->enabled) {
2405 return;
2406 }
2407 memory_region_transaction_begin();
2408 mr->enabled = enabled;
2409 memory_region_update_pending = true;
2410 memory_region_transaction_commit();
2411 }
2412
2413 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2414 {
2415 Int128 s = int128_make64(size);
2416
2417 if (size == UINT64_MAX) {
2418 s = int128_2_64();
2419 }
2420 if (int128_eq(s, mr->size)) {
2421 return;
2422 }
2423 memory_region_transaction_begin();
2424 mr->size = s;
2425 memory_region_update_pending = true;
2426 memory_region_transaction_commit();
2427 }
2428
2429 static void memory_region_readd_subregion(MemoryRegion *mr)
2430 {
2431 MemoryRegion *container = mr->container;
2432
2433 if (container) {
2434 memory_region_transaction_begin();
2435 memory_region_ref(mr);
2436 memory_region_del_subregion(container, mr);
2437 mr->container = container;
2438 memory_region_update_container_subregions(mr);
2439 memory_region_unref(mr);
2440 memory_region_transaction_commit();
2441 }
2442 }
2443
2444 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2445 {
2446 if (addr != mr->addr) {
2447 mr->addr = addr;
2448 memory_region_readd_subregion(mr);
2449 }
2450 }
2451
2452 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2453 {
2454 assert(mr->alias);
2455
2456 if (offset == mr->alias_offset) {
2457 return;
2458 }
2459
2460 memory_region_transaction_begin();
2461 mr->alias_offset = offset;
2462 memory_region_update_pending |= mr->enabled;
2463 memory_region_transaction_commit();
2464 }
2465
2466 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2467 {
2468 return mr->align;
2469 }
2470
2471 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2472 {
2473 const AddrRange *addr = addr_;
2474 const FlatRange *fr = fr_;
2475
2476 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2477 return -1;
2478 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2479 return 1;
2480 }
2481 return 0;
2482 }
2483
2484 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2485 {
2486 return bsearch(&addr, view->ranges, view->nr,
2487 sizeof(FlatRange), cmp_flatrange_addr);
2488 }
2489
2490 bool memory_region_is_mapped(MemoryRegion *mr)
2491 {
2492 return mr->container ? true : false;
2493 }
2494
2495 /* Same as memory_region_find, but it does not add a reference to the
2496 * returned region. It must be called from an RCU critical section.
2497 */
2498 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2499 hwaddr addr, uint64_t size)
2500 {
2501 MemoryRegionSection ret = { .mr = NULL };
2502 MemoryRegion *root;
2503 AddressSpace *as;
2504 AddrRange range;
2505 FlatView *view;
2506 FlatRange *fr;
2507
2508 addr += mr->addr;
2509 for (root = mr; root->container; ) {
2510 root = root->container;
2511 addr += root->addr;
2512 }
2513
2514 as = memory_region_to_address_space(root);
2515 if (!as) {
2516 return ret;
2517 }
2518 range = addrrange_make(int128_make64(addr), int128_make64(size));
2519
2520 view = address_space_to_flatview(as);
2521 fr = flatview_lookup(view, range);
2522 if (!fr) {
2523 return ret;
2524 }
2525
2526 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2527 --fr;
2528 }
2529
2530 ret.mr = fr->mr;
2531 ret.fv = view;
2532 range = addrrange_intersection(range, fr->addr);
2533 ret.offset_within_region = fr->offset_in_region;
2534 ret.offset_within_region += int128_get64(int128_sub(range.start,
2535 fr->addr.start));
2536 ret.size = range.size;
2537 ret.offset_within_address_space = int128_get64(range.start);
2538 ret.readonly = fr->readonly;
2539 return ret;
2540 }
2541
2542 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2543 hwaddr addr, uint64_t size)
2544 {
2545 MemoryRegionSection ret;
2546 rcu_read_lock();
2547 ret = memory_region_find_rcu(mr, addr, size);
2548 if (ret.mr) {
2549 memory_region_ref(ret.mr);
2550 }
2551 rcu_read_unlock();
2552 return ret;
2553 }
2554
2555 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2556 {
2557 MemoryRegion *mr;
2558
2559 rcu_read_lock();
2560 mr = memory_region_find_rcu(container, addr, 1).mr;
2561 rcu_read_unlock();
2562 return mr && mr != container;
2563 }
2564
2565 void memory_global_dirty_log_sync(void)
2566 {
2567 memory_region_sync_dirty_bitmap(NULL);
2568 }
2569
2570 static VMChangeStateEntry *vmstate_change;
2571
2572 void memory_global_dirty_log_start(void)
2573 {
2574 if (vmstate_change) {
2575 qemu_del_vm_change_state_handler(vmstate_change);
2576 vmstate_change = NULL;
2577 }
2578
2579 global_dirty_log = true;
2580
2581 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2582
2583 /* Refresh DIRTY_LOG_MIGRATION bit. */
2584 memory_region_transaction_begin();
2585 memory_region_update_pending = true;
2586 memory_region_transaction_commit();
2587 }
2588
2589 static void memory_global_dirty_log_do_stop(void)
2590 {
2591 global_dirty_log = false;
2592
2593 /* Refresh DIRTY_LOG_MIGRATION bit. */
2594 memory_region_transaction_begin();
2595 memory_region_update_pending = true;
2596 memory_region_transaction_commit();
2597
2598 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2599 }
2600
2601 static void memory_vm_change_state_handler(void *opaque, int running,
2602 RunState state)
2603 {
2604 if (running) {
2605 memory_global_dirty_log_do_stop();
2606
2607 if (vmstate_change) {
2608 qemu_del_vm_change_state_handler(vmstate_change);
2609 vmstate_change = NULL;
2610 }
2611 }
2612 }
2613
2614 void memory_global_dirty_log_stop(void)
2615 {
2616 if (!runstate_is_running()) {
2617 if (vmstate_change) {
2618 return;
2619 }
2620 vmstate_change = qemu_add_vm_change_state_handler(
2621 memory_vm_change_state_handler, NULL);
2622 return;
2623 }
2624
2625 memory_global_dirty_log_do_stop();
2626 }
2627
2628 static void listener_add_address_space(MemoryListener *listener,
2629 AddressSpace *as)
2630 {
2631 FlatView *view;
2632 FlatRange *fr;
2633
2634 if (listener->begin) {
2635 listener->begin(listener);
2636 }
2637 if (global_dirty_log) {
2638 if (listener->log_global_start) {
2639 listener->log_global_start(listener);
2640 }
2641 }
2642
2643 view = address_space_get_flatview(as);
2644 FOR_EACH_FLAT_RANGE(fr, view) {
2645 MemoryRegionSection section = section_from_flat_range(fr, view);
2646
2647 if (listener->region_add) {
2648 listener->region_add(listener, &section);
2649 }
2650 if (fr->dirty_log_mask && listener->log_start) {
2651 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2652 }
2653 }
2654 if (listener->commit) {
2655 listener->commit(listener);
2656 }
2657 flatview_unref(view);
2658 }
2659
2660 static void listener_del_address_space(MemoryListener *listener,
2661 AddressSpace *as)
2662 {
2663 FlatView *view;
2664 FlatRange *fr;
2665
2666 if (listener->begin) {
2667 listener->begin(listener);
2668 }
2669 view = address_space_get_flatview(as);
2670 FOR_EACH_FLAT_RANGE(fr, view) {
2671 MemoryRegionSection section = section_from_flat_range(fr, view);
2672
2673 if (fr->dirty_log_mask && listener->log_stop) {
2674 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2675 }
2676 if (listener->region_del) {
2677 listener->region_del(listener, &section);
2678 }
2679 }
2680 if (listener->commit) {
2681 listener->commit(listener);
2682 }
2683 flatview_unref(view);
2684 }
2685
2686 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2687 {
2688 MemoryListener *other = NULL;
2689
2690 listener->address_space = as;
2691 if (QTAILQ_EMPTY(&memory_listeners)
2692 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2693 memory_listeners)->priority) {
2694 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2695 } else {
2696 QTAILQ_FOREACH(other, &memory_listeners, link) {
2697 if (listener->priority < other->priority) {
2698 break;
2699 }
2700 }
2701 QTAILQ_INSERT_BEFORE(other, listener, link);
2702 }
2703
2704 if (QTAILQ_EMPTY(&as->listeners)
2705 || listener->priority >= QTAILQ_LAST(&as->listeners,
2706 memory_listeners)->priority) {
2707 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2708 } else {
2709 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2710 if (listener->priority < other->priority) {
2711 break;
2712 }
2713 }
2714 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2715 }
2716
2717 listener_add_address_space(listener, as);
2718 }
2719
2720 void memory_listener_unregister(MemoryListener *listener)
2721 {
2722 if (!listener->address_space) {
2723 return;
2724 }
2725
2726 listener_del_address_space(listener, listener->address_space);
2727 QTAILQ_REMOVE(&memory_listeners, listener, link);
2728 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2729 listener->address_space = NULL;
2730 }
2731
2732 bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2733 {
2734 void *host;
2735 unsigned size = 0;
2736 unsigned offset = 0;
2737 Object *new_interface;
2738
2739 if (!mr || !mr->ops->request_ptr) {
2740 return false;
2741 }
2742
2743 /*
2744 * Avoid an update if the request_ptr call
2745 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2746 * a cache.
2747 */
2748 memory_region_transaction_begin();
2749
2750 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2751
2752 if (!host || !size) {
2753 memory_region_transaction_commit();
2754 return false;
2755 }
2756
2757 new_interface = object_new("mmio_interface");
2758 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2759 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2760 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2761 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2762 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2763 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2764
2765 memory_region_transaction_commit();
2766 return true;
2767 }
2768
2769 typedef struct MMIOPtrInvalidate {
2770 MemoryRegion *mr;
2771 hwaddr offset;
2772 unsigned size;
2773 int busy;
2774 int allocated;
2775 } MMIOPtrInvalidate;
2776
2777 #define MAX_MMIO_INVALIDATE 10
2778 static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2779
2780 static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2781 run_on_cpu_data data)
2782 {
2783 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2784 MemoryRegion *mr = invalidate_data->mr;
2785 hwaddr offset = invalidate_data->offset;
2786 unsigned size = invalidate_data->size;
2787 MemoryRegionSection section = memory_region_find(mr, offset, size);
2788
2789 qemu_mutex_lock_iothread();
2790
2791 /* Reset dirty so this doesn't happen later. */
2792 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2793
2794 if (section.mr != mr) {
2795 /* memory_region_find add a ref on section.mr */
2796 memory_region_unref(section.mr);
2797 if (MMIO_INTERFACE(section.mr->owner)) {
2798 /* We found the interface just drop it. */
2799 object_property_set_bool(section.mr->owner, false, "realized",
2800 NULL);
2801 object_unref(section.mr->owner);
2802 object_unparent(section.mr->owner);
2803 }
2804 }
2805
2806 qemu_mutex_unlock_iothread();
2807
2808 if (invalidate_data->allocated) {
2809 g_free(invalidate_data);
2810 } else {
2811 invalidate_data->busy = 0;
2812 }
2813 }
2814
2815 void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2816 unsigned size)
2817 {
2818 size_t i;
2819 MMIOPtrInvalidate *invalidate_data = NULL;
2820
2821 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2822 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2823 invalidate_data = &mmio_ptr_invalidate_list[i];
2824 break;
2825 }
2826 }
2827
2828 if (!invalidate_data) {
2829 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2830 invalidate_data->allocated = 1;
2831 }
2832
2833 invalidate_data->mr = mr;
2834 invalidate_data->offset = offset;
2835 invalidate_data->size = size;
2836
2837 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2838 RUN_ON_CPU_HOST_PTR(invalidate_data));
2839 }
2840
2841 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2842 {
2843 memory_region_ref(root);
2844 as->root = root;
2845 as->current_map = NULL;
2846 as->ioeventfd_nb = 0;
2847 as->ioeventfds = NULL;
2848 QTAILQ_INIT(&as->listeners);
2849 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2850 as->name = g_strdup(name ? name : "anonymous");
2851 address_space_update_topology(as);
2852 address_space_update_ioeventfds(as);
2853 }
2854
2855 static void do_address_space_destroy(AddressSpace *as)
2856 {
2857 assert(QTAILQ_EMPTY(&as->listeners));
2858
2859 flatview_unref(as->current_map);
2860 g_free(as->name);
2861 g_free(as->ioeventfds);
2862 memory_region_unref(as->root);
2863 }
2864
2865 void address_space_destroy(AddressSpace *as)
2866 {
2867 MemoryRegion *root = as->root;
2868
2869 /* Flush out anything from MemoryListeners listening in on this */
2870 memory_region_transaction_begin();
2871 as->root = NULL;
2872 memory_region_transaction_commit();
2873 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2874
2875 /* At this point, as->dispatch and as->current_map are dummy
2876 * entries that the guest should never use. Wait for the old
2877 * values to expire before freeing the data.
2878 */
2879 as->root = root;
2880 call_rcu(as, do_address_space_destroy, rcu);
2881 }
2882
2883 static const char *memory_region_type(MemoryRegion *mr)
2884 {
2885 if (memory_region_is_ram_device(mr)) {
2886 return "ramd";
2887 } else if (memory_region_is_romd(mr)) {
2888 return "romd";
2889 } else if (memory_region_is_rom(mr)) {
2890 return "rom";
2891 } else if (memory_region_is_ram(mr)) {
2892 return "ram";
2893 } else {
2894 return "i/o";
2895 }
2896 }
2897
2898 typedef struct MemoryRegionList MemoryRegionList;
2899
2900 struct MemoryRegionList {
2901 const MemoryRegion *mr;
2902 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2903 };
2904
2905 typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
2906
2907 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2908 int128_sub((size), int128_one())) : 0)
2909 #define MTREE_INDENT " "
2910
2911 static void mtree_expand_owner(fprintf_function mon_printf, void *f,
2912 const char *label, Object *obj)
2913 {
2914 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2915
2916 mon_printf(f, " %s:{%s", label, dev ? "dev" : "obj");
2917 if (dev && dev->id) {
2918 mon_printf(f, " id=%s", dev->id);
2919 } else {
2920 gchar *canonical_path = object_get_canonical_path(obj);
2921 if (canonical_path) {
2922 mon_printf(f, " path=%s", canonical_path);
2923 g_free(canonical_path);
2924 } else {
2925 mon_printf(f, " type=%s", object_get_typename(obj));
2926 }
2927 }
2928 mon_printf(f, "}");
2929 }
2930
2931 static void mtree_print_mr_owner(fprintf_function mon_printf, void *f,
2932 const MemoryRegion *mr)
2933 {
2934 Object *owner = mr->owner;
2935 Object *parent = memory_region_owner((MemoryRegion *)mr);
2936
2937 if (!owner && !parent) {
2938 mon_printf(f, " orphan");
2939 return;
2940 }
2941 if (owner) {
2942 mtree_expand_owner(mon_printf, f, "owner", owner);
2943 }
2944 if (parent && parent != owner) {
2945 mtree_expand_owner(mon_printf, f, "parent", parent);
2946 }
2947 }
2948
2949 static void mtree_print_mr(fprintf_function mon_printf, void *f,
2950 const MemoryRegion *mr, unsigned int level,
2951 hwaddr base,
2952 MemoryRegionListHead *alias_print_queue,
2953 bool owner)
2954 {
2955 MemoryRegionList *new_ml, *ml, *next_ml;
2956 MemoryRegionListHead submr_print_queue;
2957 const MemoryRegion *submr;
2958 unsigned int i;
2959 hwaddr cur_start, cur_end;
2960
2961 if (!mr) {
2962 return;
2963 }
2964
2965 for (i = 0; i < level; i++) {
2966 mon_printf(f, MTREE_INDENT);
2967 }
2968
2969 cur_start = base + mr->addr;
2970 cur_end = cur_start + MR_SIZE(mr->size);
2971
2972 /*
2973 * Try to detect overflow of memory region. This should never
2974 * happen normally. When it happens, we dump something to warn the
2975 * user who is observing this.
2976 */
2977 if (cur_start < base || cur_end < cur_start) {
2978 mon_printf(f, "[DETECTED OVERFLOW!] ");
2979 }
2980
2981 if (mr->alias) {
2982 MemoryRegionList *ml;
2983 bool found = false;
2984
2985 /* check if the alias is already in the queue */
2986 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2987 if (ml->mr == mr->alias) {
2988 found = true;
2989 }
2990 }
2991
2992 if (!found) {
2993 ml = g_new(MemoryRegionList, 1);
2994 ml->mr = mr->alias;
2995 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2996 }
2997 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
2998 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
2999 "-" TARGET_FMT_plx "%s",
3000 cur_start, cur_end,
3001 mr->priority,
3002 memory_region_type((MemoryRegion *)mr),
3003 memory_region_name(mr),
3004 memory_region_name(mr->alias),
3005 mr->alias_offset,
3006 mr->alias_offset + MR_SIZE(mr->size),
3007 mr->enabled ? "" : " [disabled]");
3008 if (owner) {
3009 mtree_print_mr_owner(mon_printf, f, mr);
3010 }
3011 } else {
3012 mon_printf(f,
3013 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s",
3014 cur_start, cur_end,
3015 mr->priority,
3016 memory_region_type((MemoryRegion *)mr),
3017 memory_region_name(mr),
3018 mr->enabled ? "" : " [disabled]");
3019 if (owner) {
3020 mtree_print_mr_owner(mon_printf, f, mr);
3021 }
3022 }
3023 mon_printf(f, "\n");
3024
3025 QTAILQ_INIT(&submr_print_queue);
3026
3027 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
3028 new_ml = g_new(MemoryRegionList, 1);
3029 new_ml->mr = submr;
3030 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3031 if (new_ml->mr->addr < ml->mr->addr ||
3032 (new_ml->mr->addr == ml->mr->addr &&
3033 new_ml->mr->priority > ml->mr->priority)) {
3034 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
3035 new_ml = NULL;
3036 break;
3037 }
3038 }
3039 if (new_ml) {
3040 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
3041 }
3042 }
3043
3044 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3045 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
3046 alias_print_queue, owner);
3047 }
3048
3049 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
3050 g_free(ml);
3051 }
3052 }
3053
3054 struct FlatViewInfo {
3055 fprintf_function mon_printf;
3056 void *f;
3057 int counter;
3058 bool dispatch_tree;
3059 bool owner;
3060 };
3061
3062 static void mtree_print_flatview(gpointer key, gpointer value,
3063 gpointer user_data)
3064 {
3065 FlatView *view = key;
3066 GArray *fv_address_spaces = value;
3067 struct FlatViewInfo *fvi = user_data;
3068 fprintf_function p = fvi->mon_printf;
3069 void *f = fvi->f;
3070 FlatRange *range = &view->ranges[0];
3071 MemoryRegion *mr;
3072 int n = view->nr;
3073 int i;
3074 AddressSpace *as;
3075
3076 p(f, "FlatView #%d\n", fvi->counter);
3077 ++fvi->counter;
3078
3079 for (i = 0; i < fv_address_spaces->len; ++i) {
3080 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3081 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
3082 if (as->root->alias) {
3083 p(f, ", alias %s", memory_region_name(as->root->alias));
3084 }
3085 p(f, "\n");
3086 }
3087
3088 p(f, " Root memory region: %s\n",
3089 view->root ? memory_region_name(view->root) : "(none)");
3090
3091 if (n <= 0) {
3092 p(f, MTREE_INDENT "No rendered FlatView\n\n");
3093 return;
3094 }
3095
3096 while (n--) {
3097 mr = range->mr;
3098 if (range->offset_in_region) {
3099 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3100 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx,
3101 int128_get64(range->addr.start),
3102 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3103 mr->priority,
3104 range->readonly ? "rom" : memory_region_type(mr),
3105 memory_region_name(mr),
3106 range->offset_in_region);
3107 } else {
3108 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3109 TARGET_FMT_plx " (prio %d, %s): %s",
3110 int128_get64(range->addr.start),
3111 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3112 mr->priority,
3113 range->readonly ? "rom" : memory_region_type(mr),
3114 memory_region_name(mr));
3115 }
3116 if (fvi->owner) {
3117 mtree_print_mr_owner(p, f, mr);
3118 }
3119 p(f, "\n");
3120 range++;
3121 }
3122
3123 #if !defined(CONFIG_USER_ONLY)
3124 if (fvi->dispatch_tree && view->root) {
3125 mtree_print_dispatch(p, f, view->dispatch, view->root);
3126 }
3127 #endif
3128
3129 p(f, "\n");
3130 }
3131
3132 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3133 gpointer user_data)
3134 {
3135 FlatView *view = key;
3136 GArray *fv_address_spaces = value;
3137
3138 g_array_unref(fv_address_spaces);
3139 flatview_unref(view);
3140
3141 return true;
3142 }
3143
3144 void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3145 bool dispatch_tree, bool owner)
3146 {
3147 MemoryRegionListHead ml_head;
3148 MemoryRegionList *ml, *ml2;
3149 AddressSpace *as;
3150
3151 if (flatview) {
3152 FlatView *view;
3153 struct FlatViewInfo fvi = {
3154 .mon_printf = mon_printf,
3155 .f = f,
3156 .counter = 0,
3157 .dispatch_tree = dispatch_tree,
3158 .owner = owner,
3159 };
3160 GArray *fv_address_spaces;
3161 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3162
3163 /* Gather all FVs in one table */
3164 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3165 view = address_space_get_flatview(as);
3166
3167 fv_address_spaces = g_hash_table_lookup(views, view);
3168 if (!fv_address_spaces) {
3169 fv_address_spaces = g_array_new(false, false, sizeof(as));
3170 g_hash_table_insert(views, view, fv_address_spaces);
3171 }
3172
3173 g_array_append_val(fv_address_spaces, as);
3174 }
3175
3176 /* Print */
3177 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3178
3179 /* Free */
3180 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3181 g_hash_table_unref(views);
3182
3183 return;
3184 }
3185
3186 QTAILQ_INIT(&ml_head);
3187
3188 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3189 mon_printf(f, "address-space: %s\n", as->name);
3190 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head, owner);
3191 mon_printf(f, "\n");
3192 }
3193
3194 /* print aliased regions */
3195 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3196 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3197 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head, owner);
3198 mon_printf(f, "\n");
3199 }
3200
3201 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3202 g_free(ml);
3203 }
3204 }
3205
3206 void memory_region_init_ram(MemoryRegion *mr,
3207 struct Object *owner,
3208 const char *name,
3209 uint64_t size,
3210 Error **errp)
3211 {
3212 DeviceState *owner_dev;
3213 Error *err = NULL;
3214
3215 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3216 if (err) {
3217 error_propagate(errp, err);
3218 return;
3219 }
3220 /* This will assert if owner is neither NULL nor a DeviceState.
3221 * We only want the owner here for the purposes of defining a
3222 * unique name for migration. TODO: Ideally we should implement
3223 * a naming scheme for Objects which are not DeviceStates, in
3224 * which case we can relax this restriction.
3225 */
3226 owner_dev = DEVICE(owner);
3227 vmstate_register_ram(mr, owner_dev);
3228 }
3229
3230 void memory_region_init_rom(MemoryRegion *mr,
3231 struct Object *owner,
3232 const char *name,
3233 uint64_t size,
3234 Error **errp)
3235 {
3236 DeviceState *owner_dev;
3237 Error *err = NULL;
3238
3239 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3240 if (err) {
3241 error_propagate(errp, err);
3242 return;
3243 }
3244 /* This will assert if owner is neither NULL nor a DeviceState.
3245 * We only want the owner here for the purposes of defining a
3246 * unique name for migration. TODO: Ideally we should implement
3247 * a naming scheme for Objects which are not DeviceStates, in
3248 * which case we can relax this restriction.
3249 */
3250 owner_dev = DEVICE(owner);
3251 vmstate_register_ram(mr, owner_dev);
3252 }
3253
3254 void memory_region_init_rom_device(MemoryRegion *mr,
3255 struct Object *owner,
3256 const MemoryRegionOps *ops,
3257 void *opaque,
3258 const char *name,
3259 uint64_t size,
3260 Error **errp)
3261 {
3262 DeviceState *owner_dev;
3263 Error *err = NULL;
3264
3265 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3266 name, size, &err);
3267 if (err) {
3268 error_propagate(errp, err);
3269 return;
3270 }
3271 /* This will assert if owner is neither NULL nor a DeviceState.
3272 * We only want the owner here for the purposes of defining a
3273 * unique name for migration. TODO: Ideally we should implement
3274 * a naming scheme for Objects which are not DeviceStates, in
3275 * which case we can relax this restriction.
3276 */
3277 owner_dev = DEVICE(owner);
3278 vmstate_register_ram(mr, owner_dev);
3279 }
3280
3281 static const TypeInfo memory_region_info = {
3282 .parent = TYPE_OBJECT,
3283 .name = TYPE_MEMORY_REGION,
3284 .instance_size = sizeof(MemoryRegion),
3285 .instance_init = memory_region_initfn,
3286 .instance_finalize = memory_region_finalize,
3287 };
3288
3289 static const TypeInfo iommu_memory_region_info = {
3290 .parent = TYPE_MEMORY_REGION,
3291 .name = TYPE_IOMMU_MEMORY_REGION,
3292 .class_size = sizeof(IOMMUMemoryRegionClass),
3293 .instance_size = sizeof(IOMMUMemoryRegion),
3294 .instance_init = iommu_memory_region_initfn,
3295 .abstract = true,
3296 };
3297
3298 static void memory_register_types(void)
3299 {
3300 type_register_static(&memory_region_info);
3301 type_register_static(&iommu_memory_region_info);
3302 }
3303
3304 type_init(memory_register_types)
AR7 emulation for QEMU